Facilitating RFID tag assembly using integrated circuits with chamfered corners

Abstract

Trenching scribe lanes and widened regions on a wafer cause some corners of RFID ICs on the wafer to be chamfered. The widened regions increase a distance between adjacent ICs at their intersections, thereby reducing the likelihood that a tilted or rotated IC will collide with an adjacent IC. In addition, the widened regions allow vision-based alignment systems operating from a dicing tape backside to more accurately singulate ICs, reducing the likelihood of causing an IC to be tilted or rotated during ejection of the RFID IC. The chamfered corners of ICs also reduce the stress and fragility of the ICs at those areas, thereby reducing the likelihood of damage in the event of a collision.

Description

EAaLITATING RHD TAG ASSEMBLY USING INTEGRATED CIRCUITSW ITH CHAMFERED CORNERSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] 1 lis application claim.-, priority to I .S. 1’rov Fiona! Patent Application Ser. No. <> ' 5X E5O5 riled on September |0. 202 ’. 1 he disclosures til the Prov isional \pplicalion arc hereby incorporated by reference in their entirety .BACKGROUND|0t02| Radio-Frequency Identificati on (RFID)^systems typically include RFID readers, also know n as RFI D reader. w riters or Ri I D interrogators, and Rl ID tags.Rl ID sy stems can be used in many w ays ibr locating and identify ing objects to w hich the tags are attached. RFID systems are useful in product-related and service-related industries Ibr tracking objects being processed, inv entoried, or handled. In such cases, an RFID tag is usually attached to an individual item, or to its package. ’lire RFID tag typically includes, or is. a radio-frequency ■ Rl ) integrated circuit ( K t.

[0003] Semiconductor processing generally includes multiple photolithographic, etching, plating and doping operations to form an array of indiv idtial integrated circuit dies on the surface of a semiconductor substrate, such as a w afer. For application of RFID lag chips, integrated circuit die densities frequently range in the tens of thousands of dies per w afer. Each die is separated from the others by a narrow inaciiv e boundary referred to as a scribe lane (the space between adjacent die on a wafer). Once integrated circuit die fabrication and testing at the wafer level are completed, the individual die is “singulated".

[0004] Singulation may be accomplished by cutting along the scribe lanes using a sawing process, w in more modern approaches rising plasma dicing. While scribe fanes for mechanical sawing techniques may be tensiof micrometers wide (e.g.. 60 micrometers). w afers lor plasma dicing may have much narrow er scribe kmc,, in the order of single-digit micrometers or smaller. As the die sizes decrease, the use of plasma etching orsimilar techniquesand narrower scribedanes allows for a substantial increase of total die area (e.g., by 20% or more).some Ki ll) ICs may be pla<ma diced while their wafers are mounted on a dicing tape. After the ICs are singulated, a direct-die-attach machine can be used to mount individual ICs directly from the dicing tape to tag inlays. Some direct-die* attach machines operate by using an ejector needle to ■’eject" indiv ideal it s for mounting. In these si tuations, the ejector needle, which is positioned on the backside of the dicing tape, is aligned with a desired individual IC. The' ejector needle then presses against the dicing tape, deforming the tape to “eject" the desired IC by moving or pushing it with respect to other ICs on the wafer. The “ejected” IC is then directly attached to a tag inlay or intermediate te.g.. strap), for example by using an adhesive.|()(»06| If the ejector needle is not precisely aligned w ith the center of an IC t tat is to be ejected, the ejector needle may cause the IC to tilt during the ejection process. However, because direct-die-attach processes generally perform needle-IC alignment from the backside of the dicing tape, it may be difficult to “see” through the dicing tape well enough to perform accurate alignment.

[0007] When scribe lanes are very narrow, as can be the case when plasma dicing is used, diced IC s are very close to each other During the ejection process, an ejected IC may be tilted because of misalignment of the ejector needle, as described above, or may be rotated or shifted due to uneven forces, uneven release from the tape, or for other reasons. A tilted or rotated IC may collide with adjacent ICs. causing damage to the ti Ited'rotated IC and'or the adjacent ICs. The damage may be particularly pronounced at the IC corners, in part due to the fragility of square comers. BRIEF SUMMARY(00fl8| This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended as an aid in determining the scope of the claimed subject matter.|0i09| Examples are directed to a method to reduce integrated circuit (IC) damage during an IC ejection process. The method may include receiving a wafer comprising undiced ICs mounted on a dicing tape, fo-hc-etched regions of the wafer may be defined for a first plurality of parallel scribe lanes between the ICs on the wafer, asecond plurality of parallel scribe lanes between the ICs on the wafer, the second plurality being perpendicular to the first plurality, and a plurality of widened regions at intersections of the first and second plurality of scribe lanes, bach widened region m.i\ be configured io cause at least one K ' corner on al each ol the intersections to be chamlered during a w afer dicing process in order to reduce an incidence of IC-to-IC corner contact and damage during the ejection process. The method may also include trenching the first and second plurality of scribe lanes. The method may further include trenching the widened regions to form a plurality of chamfered IC comers.I ach w idened region may be al least partialis bounded b> one or more of the chamfered IC corners. The method may then include ejecting a plurality of K's from the dicing tape.

[0010] Ir other examples, an arrangement of integrated circuils ( ICs ) is configured to reduce IC damage during an IC ejection process. The arrangement can include a plurality of ICs mounted bn a dicing tape. The arrangement can further include a first plurality ol parallel trenches between the ICs and a second plurality of parallel trenches betw een the ICs. the second plurality perpendicular to the first plurality, the arrangement can also include a plurality of opened widened regions at intersections of the first and second plurality of trenches, wherein each opened widened region is at least partially hounded by one or more chamfered IC corners and is configured to reduce an incidence of IC-to-IC corner contact and damage during the ejection process.[001 11 Ir. yet other examples, a w afer conf gured to reduce damage during an integrated circuit ( IC) ejection process is provided. The wafer can comprise a plurality of ICs. 1 he wafer can also include a first plurality of parallel scribe lanes between the ICs and a second plurality of parallel scribe lanes between the ICs, the second plurality perpendicular to the first plurality. The wafer can further include a plurality of widened regions at intersections of the first and second plurality of scribe lanes configured to increase an edge-to-edge spacing between ICs at the intersections by causing at least one IC corner al each of the intersections to be chamfered during a wafer dicing process, thereby reducing an incidence of K -to-IC corner contact at the intersections and resulting damage during the IC ejection process.[0012| These and other features and advantages will be apparent from a reading of the following detailed description and a review of the associated drawings. It is to beunderstood that both the foregoing general description and the following detailed description are explanatory only and are not restrictive of aspects as claimed.BRIEF DESCRIPTION OF HIE DRAW INGS

[0013] T ic following Detailed Description proceeds w ith reference to the accompanying drawings, in which:|0014| I ;< J. 1 Lx a block diagram of components of an KI ID sx stem.

[0000] 5| I I( i. 2 is a diagram show ing components of a passix e R I H) lag. such as a lag dial can be used in die system ot I Ki. I .|0016| I K i. 3 is a conceptual diagram for explaining a half-dupie.x mode of communication betw een the components o the R I H ) system of I K i. 1.

[0017] l it I. 4 is a block diagram show ing a detail oi'an RI H) tag. such as the one shown in FIG. 2.[0018| MG. 5 A and 5B illustrate signal paths during lag-lo-reader and reader-to-lag communications in the block diagram of FIG. 4.|00I9] I i( i. 6 illustrates processing of a waler starling w ith a blank (starting) waler and ■ ending with singulated ICs,

[0120] - FIG. 7A illustrates- an example of how a direct-die-attach machine uses an ejector needle to eject a specific IC onto a tag inlay or intermediate.

[0021] FIG. 7B illustrates an example of how an ejector needle that is misaligned with a selected IC’ can cause the IC to collide with adjacent ICs during ejection, potentially resulting in IC damage.

[0022] FIG. 8 illustrates an intersection of two scribe lanes and four ICs on a wafer.|0023|: FIG. 9 illustrates various combinations of IC comer chamfering to form:w idened regions at the intersection of four ICs on a wafer, according to examples.

[0024] FIG. 10 illustrates various corner chamfering configurations for an K , according to examples.

[0025] FIG. 1 1 illustrates a flow diagram of a method to singulate and attach RFID ICs oilm an KI ID tag or an Rl- ID tag precursor w hile reducing IC-lo-K collision damage using chamfered corners, according to embodiments.DETAIHED DESCRDPTION

[0026] In the following detailed description, references are made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments or examples. These embodiments or examples may be combined, other aspects may be utilized, and structural changes may be made without departing from the spirit orscope of the present disclosure. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims and their equivalents.[OO27| As used herein, "memory is one of ROM. RAM. SRA M. DR \M. \V M.ITPROM. IT. AS 1 1, I’use. MRAM. 1’RAM. and other similar volatile and nonvolatile infotnation*storage technologies. Some portions of memory may be'writeable and some not. “Instruction" refers to a request to a tag to perform a single explicit action (e.g.(write data into memory). “Command” refers to a reader .request for one or more tags to perform one or more actions and includes one or more lag instructions preceded by a command identifier or command code that identifies the command and / or the tag instructions. “Program" refers to a request to a tag to perform a set or sequence of instructions (e.g.. read a x alue from memory and. if the read x alue is less than a threshold then lock a memory word). “Protocol” refers to an industry standard for communications between a reader and a tag (and vice versa). One such protocol is the Class- 1 (ieneration-2 CHI' Ri ll) Protocol for Communications at 860 Ml Iz • 960MHz by ( IS I l- PC global. Inc. (’’the Gen2 Protocol"). xersions 1.2.0. 2.0. and 3.0 of which are hereby incorporated by reference. Another protocol is thelSO / IEC 18000- 63 Information technology Radio frequency identification for item management • Part 63: Parameters for air interface communications at 860 MHz to 960 MHz Type C ("ISO II A I XOOO-o.V’i. also hereby incorporated by reference.

[0028] In situations where scribe lanes on a wafer are very narrow such as wafers for plasma d oing. diced ICs are x cry close to each other. 1 hiring the ejection process, an ejected IC may be lilted, rotated, and / or shifted, for example due to misalignment of the ejector needle, uneven forces on the KTand / or uneven J C release from the dicing tape. Such an IC’ may collide with adjacent K’s. causing damage to the ICs. The damage may be particularly pronounced al the It corners. in part due io the fragility of the corners.There are numerous technical advantages of the example implementations. Manufacturing y ields may increase due to decreased damage to ICs during singulation. In addition, costly ejector needle alignment systems with high accuracy may not he needed, and further decreases in IC sizes max be tolerated without increased It* damage during singulation.[0030} i id. 1 is a diagram ol [he components of a ty pical RFID sy stem I W. incorporating embodiments. An RFID reader 110 and a nearby RFID tag 120 communicate via RF signals 1 12 and 126. When sending data to lag 120. reader 1 10 may generate RF signall lZ by encoding the data, modulating:an RF wavefornrwith the encoc.ed data, and transmitting the modulated Ri w aveform as Rl signal I 12. In turn, tag 120 may receiv e Rl signa! I 12. demodulate encoded data horn Rl- signal 1 12. and decode the encoded data. Similarly, w hen sending data to reader 1 10 tag 120 may generate RF signal 126 by encoding the data, modulating an RF waveform with ’die encoc.vd data, and causing the modulated RF wax dorm to be sent as Ri signal 126. The data sent between reader 1 10 and tag 120 may be represented by symbols, also known as RFID symbols. A symbol may be a delimiter, acalibration value, or implemented to represent binary data, such as “0” and “1 ”, if desired. Upon processing by reader 1 10 and tag 12<k symbols may be treated as values, numbers, or any other suitable data rcpresenialion.s.

[0031] I ic RF waveforms transmitted by reader I I t) and or tag 120 may be in a suitable range of frequencies, such as those near 900 M Hz. 13.56 MHz. or similar. In some embodiments, RF signals 112 and / or 116 may include non-propagating RF signals, such « reactive near-field signals or similar. RFID tag 120 may be activwor battery-assisted (i.e., possessing its own power source), or passive. In the latter case. RFID tag 120 may harvest power from Rl signal 1 12.[0032| FIG. 2 is a diagram Of an RFI D tag 220, which may function as tag 120 of FIG. I . Tag 220 may be formed on a substantially planar inlay or substrate 222. which can be made in any suitable way, 'Fag 220 includes a circuit which may be implemented as an IC 224. In some embodiments IC 224 is fabricated in > complementary metal-oxide semiconductor (CMOS) technology. In other embodiments R 22 4 may be lubricated in other technologies such bipolar junction transistor i B.l 1 1 technology, metal-semicordtictor field-effect transistor i Ml SI- !•. I )technology, and others as will be well known to those skilled in the art. IC 224 is arranged on inlay 222.

[0033] l ag 220 also includes an antenna for transmitting and'or interacting with RF signals. Jn some embodiments the antenna can be etched, deposited, and / or printed metal on inlay 222: conductive thread formed with or without substrate 222: nonmviallie conductiv e (such as graphene) patterning on substrate 222; a l ir-l antenna coupled inductively, capacitively, or galvanically to a second antenna: or can he fabricated in myriad other ways that exist for forming antennas to receive RI’ waves. In some embodiments the antenna may even be formed in 1C 224. Regardless of the antenna type. It’ 224 is electrically coupled to the antenna via suitable IC contacts (not show n in 1- It >. 2). I he term '•electrically coupled” as used herein may mean a direct electrical connection, or it may mean a connection that includes one or more intervening circuit blocks, elements, or devices. The "electrical" part of the term "electrically coupled" as used in this document shall mean a coupling that is one or more of ohmic / galvanic. capacitive, and / or inductive. Similarly, the terms “electrically isolated" or "electrically decoupled” as used herein mean that electrical coupling of one or more types (e.g., galvanic^ capacitive, and / or inductive) is not present, at least to the extent possible. For example, elements that are electrically isolated from each other are galv anically isolated from each other, capacitively isolated from each other, and 'or inductively isolated from each other. Of course, electrically isolated components will generally have some unavoidable stray capacitive or inductive coupling between them, but the intent of the isolation is to minimize this stray coupling when compared with an electrically coupled path.|0034] IC 224 is shown with a single antenna port, comprising two IC contacts electrically coupled to two antenna segments 226 and 228 which are shown here forming a dipole. Many other embodiments are possible using any number of ports, contacts, antennas, and / or antenna segments. Antenna segments 226 and 228 arc depicted as separate from IC 224. but in other embodiments the antenna segments may alternatively be formed on K 224. l ag antennas according to embodiment-, may be designed in any form and are not limited to dipoles. For example, the tag antenna may be a patch, a slot, a loop, a eoil. a horn, a spiral, a monopole, microstrip, stripline, or any other suitable antenna.(0I35J Diagrani250 depicts top and side views of tag 252, formed using a strap. Tag 252 differs from tag 220 in that it includes a substantially planar strap substrate 254 having strap contacts 256 and 258. IC 224 is mounted on strap substrate 254 such that the IC contacts on IC 224 electrically coupie to strap contacts 256 and 258 via suitable connections ( not show n ). Strap substrate 254 is then placed on inlay 222 such that strap contacts 256 and 258 electrically couple to antenna segments 226 and 228. Strap substrate 254 may be affixed to inlay 222 via pressing, an interface layer, one or more adhesives, or any other suitable means.(0(1361 ^Diagram 260 depicts a side view of an alternative way to place strap substrate 254 onto inlay 222. Instead of strap substrate 254's surface, including strap contacts 256 25S. lacing the surface of inlay 222. strap substrate 254 is placed w ith its strap contacts 256 / 258 facing away from the surface of inlay 222. Strap contacts 256 / 258 can then be cither capacitively coupled to antenna segments 226 228 through strap substrate 254, or eonductively coupled using a through-via w hich mac he formed by crimping strap contacts 256 / 258 to antenna segments 226 / 228. In some embodiments, the positions of strap substrate 254 and inlay 222 may be reversed, with strap substrate 254 mounted beneath inlay 222 and strap contacts 256 258 electrically coupled to antenna segments 226 / 228 through inlay 222. Of course, in yet other embodiments -map coniacts 256 / 25S ma} electrically couple to anienna segments 226'228 through both inlay 222 and strap substrate 254.[0037| In operation, the antenna touples w ilh R1 signals in lhe environment and propagates the signals to 10 224. which may both harvest power and respond if appropriate, / based on the incoming signals and the IC’s internal state. If IC 224 -uses backscatter modulation then it may generate a response signal fe.g„ signal 126) / from / an RF signal in the environment (e.g., signal 1 12) by modulating the antenna’s reflectance. Electrically coupling and uncoupling the IC contacts of IC 224 can modulate the antenna's rellectanee, as can varying the admittance or impedance of a shunt-connected or series-connected circuit element which is coupled to the IC contacts. If IC 224 is capable of transmitting signals (e.g., has its ow n power source. is coupled to an external pow er source, and or can harv est MI I Ik ienl pow er to iransiiiii signals), then IC 224 may respond by transmitting response signal 126. In the embodiments of I •!( i. 2, antenna segments 226 and 228 are separate from IC 224. In other embodiments, the antenna segments may alternatively be- termed on / IC 224.[0038| \n Ri ll) lag such as lag 220 is oticn allached to or associated w ilh an individual item or the item packaging. An RFID tag may be fabricated and then atached to the item or packaging* may be partly fabricated before attachment to the item or packaging and then completely fabricated upon ullaclimenl io the item or packaging, or the manufacturing process of the item or packaging max include the fabrication of the RFID tag. In some embodiments, the RFI D tag may be integrated into the item or packaging. In this case, portions of the item or packaging may serve as tag components. For example, conductive item or packaging portions may serve as tag antenna segments or contacts. Nonconduciive item or packaging portions may serve as tag substrates or inlays. If the item or packaging includes integrated circuits or other circuitry, some portion of the circuitry may be configured to operate as part or all of an RF ID tag IC. Thus, an “RFID IC" need not be distinct from an item, but more generally refers to the item containing an RFI D l(’ and antenna capable of interacting with RF wax es and receiving aril responding to Rl ID signals. Because the boundaries between It', tag. and item are thus often blurred, the terms "RFID It’". "RFID tag", “lag", or “tag IC" as used herein may refer to the IC. the tag. or even to the item as long as the referenced clement is capable of Rl ID functionality .

[0039] l ire components of the RFID system oiTIG. 1 may communicate with each other in any number of modes. One such mode is called lull duplex, w here both reader 1 10 and lag 120 can transmit al the same time. In some embodiments, RFID system 100 may be capable of full duplex communication. Another such mode, which may be more suitable for passive tags, is called half-duplex, and is described below.|0040| MG. 3 is a conceptual diagram 300 for explaining half-duplex communications between the components of the RFID system of FIG. I , in this case w ith tag 120 implemented as a passive tag. I he explanation is made w ith reference to a TIME axis, and also to a human metaphor of “talking” and “listening”. The actual technical implementations for "talking" and “listening" are now described.[00411 In a half-duplex communication mode. R I I I ) reader I I O and R! I D tag I 2t) talk and listen to each other by taking turns. As seen on axis TIME, reader 110 talks to lag 120 during intervals designated “R-AT", and tag 120 talks to reader 1 10 during interv als designated ” I -A R". I or example, a sample R-A I interv al occurs during lime interval 312. during which reader 1 10 talks (block 332) and tag 120 listens (block 342). A following sample I -AR interval occurs during time interval 326. duringwhich reader 1 10 listens (block 336) and tag 120 talks (Mock 346). Interval 312 may be of a different duration than interval 326 - here the durations are shown approximately equal only Cor purposes of illustration.

[0042] During interval 312. reader 1 10 transmits a signal such as signal 1 12 described in FIG. I (block 352). while tag 120 receives the reader signal (block 362). processes the reader signal to extract data, and harvests / power from the reader signal. While receiving the reader signal, tag 120 does not backscatter (block 372). and therefore reader 1 10 does not receive a signal from tag 120 (block 382).[IMf43| During intenal 326. also know n as a backscatter lime interval or backscatter interval, reader 1 10 does not transmit a data-bearjng signal. Instead, reader 110 transmits a continuous wave (CW) signal, which is -a earner that generally does not encode irformation. 1 he C\\ signal pro\ ides energy tor lag 120 to harvest a- well as a waveform that tag 120 can modulate to form a backscatter response signal.Accordingly, during interval 326 tag 120 is not receiv ing a signal with encoded information (block 366) and instead modulates the CW signal (block 376) to generate a backscatter Mgiutl such as signal 126 described in I K i. 2. l ag 1 20 may modulate the CW signal to generate a backscatter signal by adjusting its antenna reflectance, as described above. Reader 110 then receives andprocesses the<backscater signal (block 386).

[0044] 1 K i. 4 is a block diagram show ing a detail of an Ri ll ) IC, such as IC 224 in FIG. 2. I . lectrical circuit 424 may be implemented in an IC. such as IC 224. Circuit 424 implements at least two IC contacts 432 and 433, suitable for coupling to antenna segments such as antenna segments 226 / 228 in FIG. 2. When two IC contacts form the signa: input from and signal return to an antenna they1arc often referred-to as an antenna port. IC contacts 432 and 433 may be made in any suitable way. such as from electrically conductive pads, bumps, or similar. In some embodiments circuit 424 implements more than two IC contacts, especially when eonligured w ith multiple antenna ports and / or to couple to multiple antennas.

[0045] Circuit 424 includes signal-routing section 435 w hich may include signal wiringj signal-routing busses, receive / transmit switches, andaimilar that can route signals betw een the components of circuit 424. IC contacts 432433 may couple galvanically, capacitively , andtor inductively to signal-routing section 435. Forexample, optional capacitors 436 and / or 438 may capacitively couple IC contacts 432 / 433 to signal-routing section 435. thereby galvanically decoupling IC contacts 432 '433 from signal-routing section 435 and other components of circuit 424.

[0046] Capacitive coupling (and the resultant galvanic decoupling) betw een IC contacts 432 and / or 433 and components of circuit 424 is desirable in certain situations. I or example, in some Ri ll ) tag embodiments l< contacts 432 and 433 max galvanically connect to terminals of a tuning loop on the tag. In these embodiments, galvanically decoupling IC contact 432 from IC contact 433 may prevent the formation of a DC short circuit between the Iff contacts through the tuning loop.

[0047] Capacitors 436 / 438 may be implemented within circuit 424 andfor partly or completely external to circuit 424. For example, a dielectric or insulating layer on the surface of the It containing circuit 424 may serv e as the dielectric in capacitor 43o and / or capacitor 438. As another example, a dielectric or insulating layer on the surface of a tag substrate (e.g.. inlay 222 or strap substrate 254) may serv e as the dielectric in capacitors 436'438. Metallic or conductive layers positioned on both sides of the dielectric layer (i.e., between the dielectric layer and the IC and between the dielectric layer and the tag substrate) may then serve as terminals of the capacitors 436 438. The conductive layers may include IC’ contacts (e.g.. IC contacts 432'433 ). antenna segments (e.g.. antenna segments 226 / 228). or any other suitable conductive layers.

[0048] Circuit 424 includes a rectifier and PMU (Power Management Unit) 441 that harvests energy from the RF signal incident on antenna segments 226 / 228 to power the circuits of IC 424 during either or both reader-to-tag (R->T) and tag-to-reader ('I ->R) intervals. Rectifier and PMl I 441 may be implemented in any way known in the art. and may include one or more components configured to convert an alternating-current (AC) or time-varying signal into a direct-current (DC) or sub^taniially time-invariant signal.[0049| Circuit 424 also includes a demodu ator 442. a processing block 444. a memory 450. and a modulator 446. Demodulator 442 demodulates the Rl- signal received v ia IC contacts 432'433, and may be implemented in any' suitable way. for example using a slicer, an amplifier, and other similar components. Processing block 444 receives the output from demodulator 442, performs operations ' such as commanddecoding, memory interfacing, and other related operations, and may generate an output signal for transmission. Processing block 444 may be implemented in any suitable way, for example by combinations of one or more of a processor, memory, decoder, encoder, and other similar components. Memory 450 store- data 452. and Bitty, be at least partly implemented as pennanent or semi-permanent memory such as nonvolatile memory (NVM ). l il l’ROM. ROM, or other memory types configured to retain data 452 even when circuit 424 does not lun e power. Processing block 444 may be configured to read data from and / or write data to memory 450.|0050| Modulator 446 generates a modulated signal from the output signal generated by processing block 444. In one embodiment, modulator 446 generates the modulated signal by driving the load presented by antenna -egmenti s) coupled to It contacts 432 / 433 to form a backscatter signal as described above. In another embodiment, modulator 446 includes and-'or uses a transmitter to generate and transmit the modulated signal via antenna segment(s) coupled to IC contacts 432'433. Modulator 446 may be implemented in any suitable way. for example using a switch, driver, amplifier, and other similar components. Demodulator 442 and modulator 446 may be separate components, combined in a single transceiver circuit, and / or part of processing block 444.

[0051] In some embodiments, particularly in those with more than one antenna port, circuit 424 may contain multiple demodulators, rectifiers, PMOs, modulators, processing blocks, and-or memoric-.[OO52] l it i. 5 \ show s v ersion 524- / X of components of circuit 424 of ] Io. 4. forllicr modified io emphasize a signa) operation during a R-> I interv al (e.g.. lime interval 312 of H( ,i. 3). During the R->T interval, demodulator 442 demodulates an RF signal received from IC contacts 432 / 433. The demodulated signal is provided to processing block 444 as CJN. which in some embodiments may include a received stream of symbols. Rectifier and PMD 441 may he active, for example harvesting power from an incident Rl waveform and providing power to demodulator 442. processing block 444, and other circuit components. During the R*>T interval, modulator 446 is not actively modulating a signal, and in fact may he decoupled from the Rl signal. For example, signal routing section 435 may be configured to decouple modulator 446 from the RF signal, or an impedance of modulator 446 may be adjusted to decouple it from the RF signal.

[0053] i. 5B show s v ersion 524-B of components oi circtiit 424 of I’K i. 4. further modified to emphasize a signal operation during a T~>R interval (e.g.. time interval 326 of' HG. 3). During the T~>R interval, processing block 444 outputs a signal (’ OUT. which may include a stream of symbols for transmission. Modulator 446 then generates a modulated signal f rom ( OU I and sends the modulated signal via antenna segment! s) coupled to 1C contacts 432 '433. as described above. During the T->R interval, rectiller and PMl I 441 may be active, while demodulator 442 may not be actively demodulating a signal. In some embodiments, demodulator 442 may be decoupled from the Rl- signal during the I -» R interv al, for example, signal routing section 435 may be configured to decouple demodulator 442 from the RE signal, or an impedance of demodulator 442 may be adjusted to decouple it from the Rl ‘ signal.

[0054] In typical embodiments, demodulator 442 and modulator 446 are operable to demodulate and modulate signals according to a protocol, such as the Gen2 Protocol mentioned above. In embodiments where circuit 424 includes multiple demodulators modulators, and / or processing blocks, each may he configured to support different protocols or dif ferent sets of protocols. A protocol specifies, m pan. sy mbol encodings, and may include a se t o f modulations, rates, timings, or any other parameter / associated with data communications. A / protocol can be a variant trf am internationally ratified protocol such as the t ier,? Protocol, for example including fewer or additional commands than the ratified protocol calls for. and so on. In some instances, additional commands may sometimes be called custom commands.[0055j I Ki. 6 illustrates processing of a wafer starting w ith a blank (starling; wafer and ending with singulated K’s.

[0056] Diagram 610 shows a starting wafer 612. Starting wafer 612 may he of semiconductor material, such as silicon. Silicon is sometimes doped / with p-type or n- type impurities, to improve its electronic properties, as desired for it to operate as a substrate. Starting w ater 612 has a top side 614 and a bottom side o l O opposite the top side 614. Typically, circuits for tile RHDTCmay be fabricated on / the top side 614, as described below.

[0057] Diagram 620 shows a processed wafer 622 including integrated circuits (ICs) 624 separated from each other by scribe lanes 626. The processed wafer 622 may result 'from the febrication of ICs 624 cm the starting wafer 612. ICs 624 are / febricaiedby semiconductor manufacturing machines, often operated by foundries. K 's 624 are formed al the original surface of lop side 614. both beneath and above the level of the original surface. In addition, other materials are also deposited on the top side 614, for example gale slacks for CMOS dev ices, interconnect layers (racial w ires). dev ices above the silicon surface such as M iM ( nietal-i mulaior-mctai i capacitors ami a circuit passivation layer, which is sometimes also called a dielectric, and many others potential structures and layers. Accordingly, the processed w afer 622 acquires a new top surface 628, which is elevated from the original surface.[0058| In diagram 620, only a few such ICs 624 are depicted, for illustrative purposes. In actual practice, IC manufacturers attempt to fabricate as many such ICs o24 as possible on a processed wafer, to increase the y ield of it s per wafer and thereby reduce the cost of each individual IC. The number of ICs on a wafer may he increased by (a) decreasing IC size and or (b) decreasing scribe lane width between Il s.

[0059] ;Diagram 630 is a representation of how ICs 624 on wafer 622 may be separated from each other, in a process known as “singulation". Singulation may be performed by dicing lhe processed wafer 622 along lhe scribe lanes 62b to form scribe lanelrendies 632. Scribe lane trendies 632 may extend partially or entirely through the whole height of the processed wafer. In general, scribe lane trench formation (or “trenching”) occurs after IC fabrication, although in some circumstances trenches may be formed before or along w ith IC iabricalioii. I he size ol a trench may depend on the specific technology or singulation technique used. In some cases, the side walls of the scribe lane trenches may be coated with a passivation layer. Singulation may be done through mechanical sawing, laser dicing, or plasma dicing, among other approaches. Heli ol the resulting singulated ICs 634 ly pically contams one ol lhe indiv idual ICs 624. I he size of each singulated II (e.g.. 6 U) is thus determined in part by the size of the individual IC (c.g., 624). Singulated R1 I 1) ICs may then be attached to RFID tags or RFID tag precursors (e.g., a tag inlay or intermediate).

[0060] As mentioned herein, RFID ICs on wafers may be singulated to separate, indiv idual ICs from each other. Prior to singulation, wafers may be mounted to dicing tape, usually on lhe w afer backside, such that singulated Il s slick to lhe dicing tape. / \lter singulation, the dicing tape-mounted waler may he provided to a direct-die-attach machine configured to attach specific RFID ICs, on the wafer to tag inlays or intermediates.

[0061] MG. 7 A illustrates an example of how a direcl-die-attach machine uses an ejector needle to eject a specific IC onto a tag inlay or intermediate.[00621;Diagram 700A shows a simplified diagram of a ^direct-die-attach machine. The direct-die-attach machine holds a singulaled waler, represented by singulatcd It’s 708A. 70811, and 708C, mounted on the front side of a dicing tape 706. Specifically, the direct-die-attach machine may hold the back side of the dicing (ape 'T'O using vacuum caps 704. I o attach a selected Ri l l) IC. such as RI H) IC 7O8B. to a tag inlay or intermediate 712. the direct-die-attach machine first aligns an ejector needle 702. positioned on thefiack side of the dicing tape 706, with the center of the selected IC 708B. Once aligned, the direct-die-attach machine presses the ejector needle against the back side of the dicing tape 706, deforming the tape to eject IC 708B by moving orpushing it with respect to adjacent lCs (e.g.,4C 7O8A and;708C) on the tape 706. The ejected IC 708B may then be attached to the lag inlay intermediate 712, for example using adhesiv e 710. I llis process is called a direct-die-attach Ri ll) tag assembly process. 1 he tag inlay or intermediate ~ I 2 may also be referred to as R| II ) tag or RFID tag precursor. Although the process Is described wi th reference to ejecting the selected RFID IC 708B. multiple ICs may be ejected at once.

[0063] As described above, increasing IC yield from a wafer can involv e decreasing [C size and / or decreasing scribe lane width between ICs. In some situations, this leads io scribe lane trendies that arc v ery narrow , resulting in v ery little clearance between an IC being ejected in a direct-die-attach process and adjacent ICs. If precise al ignment between an ejector needle and a selected;IC is not achieved, then the resulting tilt of the IC will cause the IC to collide with adjacent ICs, potentially damaging the ICs involved in the collision.

[0064] FIG. 7B illustrates an example of how an ejector needle that is misaligned w ith a selected IC can cause the K io collide w iih adjacent ICs during ejection, potentially resulting in IC damage.

[0065] Diagram 700B show s a selected IC 724 being ejected from among ICs 7()<s during a direct-die-attach process. The ejector needle 702 is not correctly aligned with the center of IC 724. causing IC 724 to tilt during ejection. As a result, the selected IC724 collides (at collision points 722) with adjacent ICs, potentially damaging the selected IC 724 and the adjacent ICs.[0066j I ven in situations w here an ejector needle is correctly aligned w ith an It to be ejected, narrow scribe lane trenches may cause any rotation or shilling of the IC (for example due to unevenly applied forces, uneven adhesive release, or similar reasons) to result in collisions w ith adjacent It s and subsequent damage.|®W7| Purtherm ore, harrow scribe lane tenches may make precise needle alignment even more difficult. Direcl-dic-altach processes generally perform needlc-IC alignment from the hack side of the dicing tape. It can be difficult for an alignment system to see through the dicing tape well enough to perform accurate alignment, and if the alignment system uses scribe lanes or scribe lane tenches to / guide alignment, narrow scribe lanes may exacerbate alignment difficulties. In addition, w hereas larger ICs may tolerate a larger degree of ejector needle-to-IC center misalignment before lilting sufficiently to cause IC damage, smaller RFID ICs cannot tolerate as much misalignment before tilting enough to cause IC damage.|0®68| As mentioned above, IC yield from a wafer depends partly oft IC size and scribe lane width. As IC size or scribe lane width decreases, IC yield increases.How ever, such M / e and w ickh reductions may lead to increased IC damage potential and therefore reduce It y ield. I or example, in direct-die-attach processes as described above, reduced IC size and scribe lane widths increase the probability of collisions and JCdamage during ICejectton^causing a reduction inHC yield. Collision-based IC damage may be especially pronounced at the corners of the ICs.(0069J FIG, 8 illustrates an intersection of two scribe lanes and four ICs on a wafer. Diagram 8(H) show s an intersection of tw o scribe lanes 804 and 8(.)o. between lour It s 802 -\-D. When scribe lanes 801 and 806 are narrow , adjacent ICs 802 VI) arc also very narrowly spaced from each other. In this situation, if an ejected IC is lilted or rotated, i ts edges and corners may col lide with edges and comers of adjacent ICsc( potential corner collisions 80S). Damage to the IC may be particularly pronounced at the IC corners as compared to the IC edges, in part due to the increased fragility of comers te compared to straigh t edges. In some / scenarios, one til ted or rotated I C may damage multiple adjacent ICs.{0070] According to some examples, IC corners at scribe lane intersections may be chamfered to create widened (as compared to scribe lane widths) regions at the intersections alter trenching. The widened regions increase edge-to-edge spacing betw een adjacent It's at the intersections, reducing the probability of corner collisions and damage and potentially increasing visibility to vision-based alignment systems. In this disclosure, a chamfered comer refers to a comer or corner region that is rounder or more obtuse than a right angle. Similarly, chamfering a corner means to reduce the acuteness of the corner. For example, chamfering an IC corner may involve converting a corner of an IC into two or more v ertices. For a rectangular It ', chamfering an IC corner may convert the right-angle IC comer to form two or more obtuse-angle corners, thereby converting the rectangular IC into a polygonal IC with more than four sides. A chamfered corner w ith two obtuse angles of 135 degrees may be referred to as a Battened corner. Chamfering may also involve rounding one or more IC comers, which may involve eliminating one or more vertices and forming a curve or an arc. In some examples, IC corner chamfering may be done using an etching process such as plasma dicing, which may allow the formation of arbitrarily shaped edges and comers.

[0071] Chamfering IC comers to create widened regions at scribe lane intersections may provide several advantages. First, it may increase the distance between the edges of adjacent ICs at the scribe lane intersections, thereby reducing the likelihood that a tilted or rotated IC will collide with an adjacent IC. Scribe lanes may have a width on the scale of 100pm. lOpm. 5pni. or any suitable width, Embodiments arc particularly adv antageous at these scales. Second, chamfering IC corners may reduce IC stress and fragility of the Id at those corners, thereby decretning the likelihood of damage in the event of a collision. For example, in an IC-to-IC comer collision the force experienced by each Ids concentrated at the corner point. Chamfering the corner by converting it into two or more vertices, or even by rounding the corner, distributes the force experienced over a larger area, decreasing the likelihood of damage. I hid. chamfering IC corners to create widened regions at scribe lane intersections w ill result in larger open areas or openings al those intersections, which may improve the visibility of those intersections to vision-based alignment sy stems operating from the dicing tape backside, thereby assisting in ncedlc-IC alignment.[0072| FIG. 9 illustrates various combinations of IC comer chamfering to form widened regions at the intersection of two scribe lanes (and four ICs) on a wafer, according to examples. Diagrams 900A-D show examples of corner chamfering at scribe hire intersections on a wafer. 1 or example, diagram 9o() A depicts It '> 902A-I). w ith only l( ' 902D having a chamfered corner al scribe lane intersection 904. Diagram 900B depicts two K's. K's 902C-D, with chamfered comers al scribe lane intersection 904. Diagram 900C depicts ICs 902A. 902C, and 9021) with chamfered comers at scribe lane intersection 904. Diagram 900D depicts all of ICs 902A-D with chamfered corner- at scribe lane intersection 904. Note that in some situations w here only two K corners at a scribe lane intersection are chamfered, the two chamfered corners may be diagonally opposite each other.|00 73] I ic increase in distance betw een adjacent l( ’< is dependent on the chamfering applied to the comers. Referring to diagram 90(H), presume a scribe lane width of .v and (hat the corners of the K's 902A-I) are chamfered al a depth equal to the width .v to create a flattened corner with two identical obtuse angles of 135 degrees. Looking at IC 90?. \. the ehamlering prov ides for an increase in the edge-to-edge spacing between the adjacent ICs 902B-D at all points on the chamfered edge, except at exactly the endpoints of the edge. In one example, the edge-to-edge spacing cart be delined using the midpoint of the chamfered edge. I sing this dellnition. the midpoint of the chamfered edge of 902 A provides an increase of.v 2 relative to the nonchamfered comer, i.e. — the corner of 902A in diagram;900A. The increased edge-to- edge spacing between the midpoint of the chamfered edge of 9112A and the midpoint ul an\ of the adjacent ICs 9U2B-C is then al least equal to the w idth o! lite scribe lane x Edge-to-edge spacing can be defined in other manners, such as by the smallest distance between edges of two adjacent K's. the largest distance between edges of two adjacent ICs, the average distance between edges of two ICs, or any other suitable manner.

[0074] As suggested in diagrams 900A-D, in some examples a rectangular IC may have one. two. three, or all four of its right-angle corners chamfered or rounded. FIG.10 illustrates various corner chamfering configurations for an IC. according to examples. Diagram 1000 shows IC 1002 with a single chamfered comer. IC 1004 with two chamfered corners. IC 1006 with three chamfered corners, and IC 1008 with four chamfered corners.

[0075] I ic specific IC comers that are chamfered may be selected based on any suitable>scheine. In some cases, the IC corners to be chamfered maybe selected to provide a widened region having an orientation-dependent shape at a scribe lane' intersection. For example, when fewer than four IC corners present al a particular scribe lane intersection are cham fered, as in diagrams 900A-C, the 'resulting widened region al the intersection, when trenched, has a shape that provides information about how the w afer is oriented. This orientation-dependent shape may serve as a way tor vision-based alignnientsystems to determihelC and / or wafer orientation.[0076| Note that while FIGs. 9and 10 depict IC corners being chamfered in th ©same way (i.e.. a right-angle corner being chamfered Io create two vertices of equal angle), in some situations the different corners present on a single IC or at a certain scribe lane intersection may be chamfered in different ways. For example, one corner may be chamfered as depicted in 1 IGs. 9 and 10, whereas another corner may be chamfered to create three or more vertfees, or to form an arc.

[0077] ;Chamfering one or more comers ©fan IC involves sacrificing some IC area, which otherwise may be used for additional circuitry or supporting structures. In general, circuitry or structures nearest the IC edges or corners will he most impacted by corner chamfering. In these situations, the relevant circuitry or structures may he designed to accommodate potential corner chamfering. l or example, some ICs include an IC seal ring that helps to physical ly reinforce the IC and isolate ' leiectrically and or physically ) circuitry within the k . In this case, portions of the It' seal ring that could be affected by IC corner chamfering, such as the external corners of the IC seal ring may be designed to accommodate the chamfered IC corner without damaging or otherwise compromising the functionality of the IC seal ring. More explicitly, the geometry of IC chamfering can act as a boundary for IC seal rings to be completely contained within such they are not damaged when the IC comer is chamfered.

[0078] I K i. I I illustrates a flow diagram of a method I 100 to smgulate and attachRFID ICs onto an RFID tag or an RFID tag precursor while reducing IC-to-IC collision using chamfered corners, according to embodiments. The method 1 100 may begin at block 1 102, where a singulation system receives a wafer mounted on dicing tape and including undiced RI H) Il X.

[0079] At block 1104, the singulation system may define to-be-etched regions of th e wafer for IC singulation. The regions may include, ibut are not limited to, a fist plurality of parallel scribe lanes between the ICs on the wafer, a second plurality of parallel scribe lanes between the ICs on the wafer and perpendicular to the first plurality of scribe lanes, and a plurality of widened regions at intersections of the first and second plurality of scribe lanes. Lach widened region may be at least partially bounded by one or more IC comers at the respective intersections and ma) be configured to cause the IC corner(s) to be chamfered during a subsequent wafer dicing process in order to reduce an incidence of K -lo-l( ' comer contact and damage during a direct-die-attach process. The incidence of IC-to-IC corner contact can be defined in any suitable manner, such as a measure of IC-to-IC corner collisions per unit time, an amount or percentage of IC-to-IC collisions occurring during the ejection process, a percentage of K -lo-IC col I isii >ns occurring per w aler, or otherw ise. In addition, the incidence can also he associated w ith a level of damage to the IC incurred in a collision. Embodiments may reduce the incidence of high levels of damage significantly (e.g; , doe to increased edge»to-edge spacing, spreading of force from a point to an edge, or otherwise).

[0080] At block 1 106. the singulation system may dice the wafer by trenching the w afer al the first and second plurality ol scribe lanes and the w idened regions, to form scribe kmc trenches and pits or openings at the w idened regions. I he openings at the widened .regions may be at least partially bounded by one or more chamfered IC comers. The singulation process can be performed through mechanical sawing, laser dicing, plasma dicing, among other approaches.

[0081] At block 1 108, a direct-die-attach machine may align an ejector needle to a selected IC on the diced wafer from a second surface of the dicing tape opposite the first surface to which the wafer is attached. A vision-based alignment sy stem max be employed to align the ejector needle with tlwselected 1(1 The openings attlie; •widened regions created at block I 106 may be used to increase amaccuracy of tlfe V ision-based alignment system. In some examples, orieniation-depciident openings at the w idened regions formed using three or fewer channeled corners, or different types of chamfering applied to two or more IC corners (e.g.. flattened corner, rounding, a combination of obtuse angles, or any other suitable arbitrary shape), may be used bythe vision-based alignment system to determine IC and / or wafer orientation and increase;an accuracy of ejector needle alignment.

[0082] \l block I I Kt the direct-die-atlach machine may use the ejector needle to eject the selected IC from a plane of the diced wafer. The widened regions around the selected IC may reduce the incidence of an IC-to-lC collision and damage during the ejection process. I he selected IC may be ejected onto an adhesive on an R I l i > tag or an RMI) tag precursor, or onto antenna terminals on an Rl II ) lag or an Ri ll) tag precursor« The4irect-die-attach machine may proceeds eject a plurality of ICs from ' the dicing tape using. In some embodiments, the ICs may be ejected from the dicing tape one at a time as described above. As such, the alignment and ejection process described by blocks 1 I OX and 1 1 10 may be repeated for all ICs on the wafer. In other embodiments, the dircct-dic-attaeh machine may be configured to eject multiple ICs atetime. A reduction no the incidence of IC-to-IC cornercontact and damage can be determined with respect to the probability of occurrence during a plurality of single ejections, a single ejection of multiple ICs. or a plurality of ejections of multiple ICs.|00 83| A number and order of the steps of the method I 100 are not intended to present limitations on embodiments. The processes of the method 1 100 at various blocks described above may be performed in a different order and fewer or additional blocks may be used, employing the principles described herein.

[0084] According to some examples, a method to reduce integrated circuit (IC) damage during an IC ejection / process may include receiving a wafereomprising undiced It s mounted on a dicing tape and defining to-be-etched regions on die wulei. I he wafer may include a first plurality of parallel scribe lanes between the ICs on the wafer, a second plurality of parallel scribe lanes betw een the ICs on the wafer, the second plurality perpendicular to the first plurality, and a plurality of w idened regions at intersections of the first and second plural ity of scribe lanes, each widened region configured io cause at least one IC corner al each of ihe intersections to be chamfered during a wafer dicing process in order to reduce an incidence of IC-to-IC corner contact and damage during art ejection process. The method may further include dicing the wafer by trenching the first and second plurality of scribe lanes: and trenching the widened regions io form a plurality ot chamfered IC corners, wherein each widened region is at least partially bounded by one or more of the chamfered IC corners. The method may also include ejecting a plurality of ICs from the dicing tape.(0185) According® other examples, the plurality of chamfered IC corners may include one or more of a flattened corner, a rounded corner, ora combination of two or more obtuse angles. At least one of the plurality of ICs may include an IC seal ring designed to accommodate the chamfered comers of the IC. I: jeering the plurality of K > from the dicing tape max include employ ing a vision-based alignment system to align an ejector needle with a selected IC in the plurality of ICs, wherein the vision- based alignment system is configured to align the ejector needle using one or more of the plurality of trenched widened regions around the selected IC: and ejecting the '•elected IC onto an KI I I ) tag or an KM !) tag precursor. At least one of the w idened regions around the selected IC can be trenched such that at least one but not all IC corners bounding the widened region are chamfered to form an orientation-dependent trenched widened region, and the orientation-dependent trenched w idened region is used by the vision-based alignment system to determine IC and'or wafer orientation and increase an accuracy of the alignment of the ejector needle.[0(186] According to further examples, al least one of the w idened regions is trenched such that different types of chamfering are applied to two or more IC corners bounding the widened region to form an orientation-dependent trenched widened region, and the orientation-dependent trenched widened region is used by the vision- based alignment system to determine IC and or w afer orientation and increase an accuracy of the alignment of the ejector needle. Ejecting the plurality of ICs from the dicing tape may include ejecting one IC at a time, wherein the incidence of IC-to-IC corner contact and damage is determined with respect to the plurality of ejections, or ejecting multiple ICs at a time, where the incidence of IC-to-IC corner contact and damage i> determined w ith respect to a single ejection of multiple ICs. or the incidence of IC-to-IC corner contact and damage is determined with respect to a plurality of ejections of multiple ICs.(0087|:According to some examples, :an arrangement ofintegrated circuits (ICs) is configured to reduce IC damage during an IC ejection process may include a plurality of ICs mounted on a dicing tape; a first plurality of parallel trenches between the ICs; a second plurality of parallel trenches betw een the ICs. the second plurality perpendicular to the first plurality; and a plurality of opened widened regions at intersections of the first and second plurality of trenches, wherein each opened wtdened region is at least partially bounded by one or more chamfered IC corners andis configured to reduce an incidence of IC-to-lC comer contact and damage during the ejection process.

[0088] According to other examples, al least one of the opened widened regions is al least partially bounded by three or fewer IC corners, forming an orientation-dependent opened w idened region. In j et other examples, al least one of the opened w idened regions is at least partially bounded by tw o or more IC corners w ith different types of chamfering, forming an orientation-dependent opened widened region. The first and second plurality of parallel trenches and the plurality of opened widened regions can be trenched msing plasma dicing. For each IC of the plurality of ICs, a vision-based alignment system can be used to align an ejector needle with the IC. and the visionbased alignment system is configured to align the ejector needle using the opened widened regions around the IC. At least one of the plurality of K's can comprise an IC seal ring designed to accommodate the chamfered corners of the IC. The width of each trench of the first and second plurality of trenches can be less than 10pm.|00891 According to further examples, a wafer is configured to reduce damage during an integrated circuit (IC ) ejection process may include a plurality of ICs: a first plurality of parallel scribe lanes between the ICs: a second plurality of parallel scribe lanes between the ICs, the second plurality perpendicular to the first plurality; and a plurality of widened regions al intersections of the first and second plurality of scribe lanes configured to increase an edge-to-edge spacing between ICs at the intersections by causing al least one IC corner al each of the intersections to be chamfered during a wafer dicing process, thereby reducing an incidence of IC-to-IC corner contact at the intersections and resulting damage during the IC ejection process.

[0090] According to some examples, the plurality of w idened regions are orientationdependent widened regions that are at least partially bounded by three or fewer IC corners al the intersection to be chamfered, or by causing different types of chamfering to be applied to two or more It corners al the intersection bach IC ol the plurality of ICs is ejected from the dicing tape after forming the widened regions. I he widened regions can be formed through plasma dicing. The width of each scribe lane of the first and second plurality of scribe lanes can be less than I (fem. The IC comers can be chamfered into a llatlened corner, and the edge-lo-cdge spacing is measured betw een midpoints of the chamfered corner of adjacent ICs and is al least twice (he width oFthe scribe lanes.10091J As mentioned previously, embodiments are directed to facilitating RFID tag assembly using integrated circuits with chamfered corners. Embodiments additionally include programs, and methods ofopcration of the programs for manufacturing of R1 ID It s. A program is generally defined as a group of steps or operations leading to a desired result, due to the nature of the elements in the steps and their sequence. A program is usually advantageously implemented as a sequence of steps or operations for a processor but may be implemented in other processing elements such as FP( iAs. DSPs, or other devices as described above.|W92| Performing the steps, instructions, or operations of a program requires manipulating physical quantities. I sually . though not necessarily . these quantities may be transferred, combined, compared, and otherw ise manipulated or processed according t& the steps or instructions, and they may also be stored in acomputer*^ readable medium. These quantities include, for example, electrical, magnetic, and electromagnetic charges or particles, states of matter, and in the more genera! case can inchide the states of any physical dev ices or elements. Information represented by the slates of these quantities may be referred-to as bits, data bits, samples, values, symbols, characters, terms, numbers, or the like. I lovvev-er. these and similar terms are associated with, and merely convenient labels applied to the appropriate phy sical quantities, individually or in groups.

[11093] Embodiments furthermore include storage media. Such media, individually or in combination with others, hav e stored thereon instructions, data. keys, signatures, and other data of A program made according to the embodiments. A storage medium according to embodiments is a computer-readable medium, such as a memory, and can be read by a processor of the type mentioned above. If a memory, it can be implemented in any of the ways and using any of the technologies described above.|0094| Even though it is said that a program may be stored in a computer-readable medium, it docs not need to be a single memory, or even a single machine. V arious portions,. modules^or features of it may reside in separate memories, !or even separate machines. The separate machines may be connected directly, or through a network such as a local access network ( LAN ) or a global network such as the Internet.often, for the sake of convenience only, it is desirable to implement and describe a program as software. The software can be unitary or thought of in terms of various interconnected distinct software modules.

[0096] The foregoing detailed description has set forth various embodiments of the devices and / or processes via the use of block diagrams and or examples. Insofar as such block diagrams and or examples contain one or more functions and or aspects, each function and 'or aspect within such block diagrams or examples may be implemented individually and'or collectively, by a wide range of hardware, software, firmware, or virtually any combination thereof.' Some aspects Of the embodiments disclosed herein, in w hole or in part, max be cquivalentiy implemented employ ing integrated circuits, as one or more computer programs runnihg on one / or more computers (c.g., as one or more programs running on one or more computer systems), as one or more programs running on one or more processors (e.g. as one or more programs running on one or more microprocessors), as firmware, or as virtually any combination thereof, and that designing the circuitry and or writing the code for the software and / or firmware would be well within the skill of one of skill in the art in light of this disclosure.[0097J The present disclosure is not to be limited in terms of the particular embodiments described in this application, which are intended as illustrations of various aspects. Many modifications and variations can be made w ithout departing from iis spirit and scope, l unclionalh cquixalem methods and apparatuses w ithin the scope of the disclosure, in addition to those enumerated herein, will be apparent to those skilled in the art from the foregoing descriptions. Such modifications and variations arc intended to fall within the scope of the appended claims. The present disclosure is to be limited only by the terms of the appended claims, along with the full scope of equivalents to which such claims are entitled. It is to he understood that this disclosure is not limited to particular methods, configurations, tags. RI'ICs. readers, systems, and the like, which can, of course, vary. I t is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, arid is not intended to be titrating.|0098| With respect to the use of substantially any plural and 'or singular terms herein, those having skill in the art can translate from the plural to the singular and / or from the singular to the plural as is appropriate to the context and / or application. Thevarious singular / plural permutations may be expressly set forth herein for sake of clarity.

[0099] h’ general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as “open” terms (e.g.. the term "including” should be interpreted as “including but not limited to.” the term "having” should be interpreted as “having at least.’1the term “includes” should be interpreted as “includes but is not limited to.” etc.). If a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases "at least one" and "one or more" to introduce claim recitations. Howev er, the use of such phrases should not he construed to imply that the introduction of a claim recitation by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim recitation to embodiments containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g., “a” and or “an" should be interpreted to mean “at least one” or “one or more’*); the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, such recitation should be interpreted to mean al least the recited number (e.g.. the bare recitation of "two recitations," without other modifiers, means at least tw o recitations, or two or more recitations).(0i00| Furthermore, in those instances where a convention analogous to ‘‘at least one of A, B, and C, etc.” is used, in general such a construction is intended in the sense one hav ing skill in the art w ould understand the conv ention te.g.. ”a system having at least one of A. B. and ( ” would include but not be limited to systems ihal have A alone, B alone. C alone, A and B together. and C together. B and C together, and'or A,, B, and C together, etc.). Any disjunctive word and / or phrase presenting two or more alternative terms, w hether in the description, claims, or draw ings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase "A or B” will be understood to include the possibilities of “A” or “B" or "A and B.”[0101J For any and all purposes, such as in terms of providing a written description, all ranges disclosed herein also encompass any and all possible subranges and combinations of subranges thereof Any listed range can be easily recognized as sufficiently describing and enabling the same range being broken down into al least equal halves, thirds, quarters, fifths. tenths, etc. As a non-limiting example, each range discussed herein can be readily broken down into a lower third, middle third and upper third, etc. All language such as "up to." "at least." "greater than." "less than,” and the like include the number recited and refer to ranges which can be siihsequcntlx broken dow n into subranges as discussed abov e. I inally . a range includes each individual member. Thus, for example, a group having 1 -3 cells refers to groups having 1 , 2. or 3 cells. Similarly, a group having 1 -5 cells refers to groups having I , 2. 3, 4, or 5 cells, and so forth.

Claims

CLAIMSI / WE CLAW:

1. A method to reduce integrated circuit (IC) damage during an K ejection process, the method comprising: receiving a waler comprising undiced ICs mounted on a dicing tape; defining to-be-etched regions on the wafer, including: a first plurality of parallel scribe lanes between the K’s on the wafer. a second plurality of parallel scribe lanes between the K's on the wafer, the second plurality perpendicular to the first plurality, and a plurality of widened regions to intersections of the first and second plurality of scribe lanes, each w idened region configured to cause at least one IC corner ateach of the intersections to fie chamfered during a yvafer dicing process in order to reduce an incidence of IC-to-IC corner contact and damage during an ejection process; dicing the wafer by: trenching the first and second plurality' of scribe lanes; and trenching the widened regions to forma plurality of chamfered IC corners, wherein each widened region is at least partially bounded by one or more of the chamfered IC corners; and’ ejecting a plurality of ICs from the dicing tape.

2. Tie method of claim I , wherein the plurality of chamfered IC corners comprises one or more of a flattened corner, a rounded comer, or a combihatipn of ; tw o or more obtuse angle-..

3. The method of claim I . wherein at least one of the plurality of ICs comprise an IG seal ring designed to accommodate the chamfered corners of the IC,4. The method of claim I , wherein ejecting the plurality of ICs from the dicing tape comprises: employing a vision-based alignment system to align an ejector needle with a selected IC in the ^plurality of ICs, wherein the wision-based alignment system isconfigured to align the ejector needle using one or more of the plurality of trenched widened regions around the selected IC’ and ejecting the selected IC onto an RFID tag or an RFID lag precursor.

5. The method of claim 4. wherein at least one of the widened regions around the selected IC is trenched such that al least one hut not all IC corners hounding the w idened region are chamfered to form an orientation-dependent trenched widened region, and the orientation-dependent trenched w idened region is used by the vision-based alignment system lo determine IC and / or wafer orientation and increase an accuracy of the alignment of the ejector needle.

6. The method of claim 4, wherein at least one of the widened regions is trenched such that different types of chamfering arc applied lo two or more IC comers hounding the widened region lo form an orientation-dependent trenched widened region, and the orientation-dependent trenched widened region is used by the vision-based alignment system to determine IC and / or wafer orientation and increase an accuracy of the alignment of the ejector needle.

7. An arrangement of integrated circuits ( ICs) configured to reduce IC damage during an IC ejection process, the arrangement comprising: a plurality of ICs mounted on a dicing tape; a first plurality of parallel trenches between the / lCs; a second plurality of parallel trenches between the ICs. the second plurality perpendicular to the first plurality: and a plurality of opened widened region'- at intersections of die first and second plurality of trenches, wherein each opened widened region is at least partially bounded by one or more chamfered IC corners and is configured to reduce an incidence of IC-to-IC corner contact and damage during the ejection process.

8. The arrangement of ICs of claim 7. wherein the first and second plurality of parallel trenches and the plurality of opened widened regions are trenched using plasma dicing.

9. The arrangement of ICs of claim 7, wherein, for each IC of the plurality of ICs. a vision-based alignment system is used to align an ejector needle with the IC. and the vision-based alignment system is configured to align the ejector needle using the opened widened regions around the IC.

10. The arrangement of ICs of claim 7, wherein the width of each trench of the first and second plurality of trenches is less than l ()gm.

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