Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns. The circuit units each comprise a pixel driving circuit and a control line, and the pixel driving circuit comprises a driving transistor (T3), a first light-emitting control transistor (T5), and a second light-emitting control transistor (T6), a second electrode of the first light-emitting control transistor (T5) being connected to a first electrode of the driving transistor (T3), and a first electrode of the second light-emitting control transistor (T6) being connected to a second electrode of the driving transistor (T3). The first light-emitting control transistor (T5) and the second light-emitting control transistor (T6) are connected to different control lines. The first light-emitting control transistor (T5) and the second light-emitting control transistor (T6) are separately arranged on two sides in the unit column direction of the driving transistor (T3).

Description

Display substrate and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit and at least one control line, wherein the control line is configured to provide a light-emitting control signal to the pixel driving circuit; in at least one circuit unit, the pixel driving circuit comprises at least a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor, wherein the first electrode of the first light-emitting control transistor is connected to a first power line, the second electrode of the first light-emitting control transistor is connected to the first electrode of the driving transistor, and the first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor; the first light-emitting control transistor and the second light-emitting control transistor are connected to different control lines, and the first light-emitting control transistor and the second light-emitting control transistor are respectively arranged on both sides of the driving transistor unit column direction.

[0006] In an exemplary embodiment, at least one control line includes a first signal line and a second signal line, the first light emission control transistor is connected to the first signal line, the second light emission control transistor is connected to the second signal line, and the first signal line and the second signal line are respectively arranged on both sides of the column direction of the driving transistor unit.

[0007] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes a plurality of conductive layers, and the first signal line and the second signal line are provided in different conductive layers.

[0008] In an exemplary embodiment, the second light emission control transistor includes at least a second gate, the second gate and the first signal line are provided in the same conductive layer, and the second gate and the second signal line are provided in different conductive layers.

[0009] In an exemplary embodiment, the pixel driving circuit further includes a compensation transistor, a gate electrode of the compensation transistor being connected to a first scanning signal line, a first electrode of the compensation transistor being connected to the gate electrode of the driving transistor via a first connecting electrode, and a second electrode of the compensation transistor being connected to the second electrode of the driving transistor and the first electrode of the second light-emitting control transistor, respectively; an orthographic projection of the first connecting electrode on a display substrate plane at least partially overlaps with an orthographic projection of the first signal line on a display substrate plane, and an orthographic projection of the first connecting electrode on a display substrate plane at least partially overlaps with an orthographic projection of the first scanning signal line on a display substrate plane.

[0010] In an exemplary embodiment, the compensation transistor includes at least a compensation active layer, the second light-emitting control transistor includes at least a second light-emitting control active layer, and the second region of the compensation active layer is connected to the first region of the second light-emitting control active layer through a fifth connecting electrode; in a direction perpendicular to the display substrate, the display substrate includes at least at least one semiconductor layer and at least one conductive layer, the compensation active layer and the second light-emitting control active layer are arranged in the semiconductor layer, and the fifth connecting electrode is arranged in the conductive layer.

[0011] In an exemplary embodiment, the pixel driving circuit further includes a data writing transistor, a first electrode of the data writing transistor being connected to a data signal line, a second electrode of the data writing transistor being connected to a first electrode of the driving transistor, and the data writing transistor and the compensation transistor being respectively arranged on both sides of the driving transistor unit column direction.

[0012] In an exemplary embodiment, at least one control line includes a light emission signal line connected to the second light emission control transistor in a current cell row, and the light emission signal line is connected to the first light emission control transistor in a next cell row.

[0013] In an exemplary embodiment, the first light emission control transistor includes at least a first gate, the second light emission control transistor includes at least a second gate, the light emission signal line is connected to the second gate in the current unit row, and the light emission signal line is connected to the first light emission control transistor in the next unit row through a light emission signal connection line.

[0014] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes multiple conductive layers, the first gate and the second gate are arranged in the same conductive layer, the first gate and the light-emitting signal line are arranged in different conductive layers, the first gate and the light-emitting signal connecting line are arranged in different conductive layers, and the light-emitting signal connecting line and the light-emitting signal line are arranged in different conductive layers.

[0015] In an exemplary embodiment, the multiple conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence on the substrate along a direction away from the substrate, the first gate and the second gate are arranged in the first conductive layer, the light-emitting signal line is arranged in the third conductive layer, the light-emitting signal line is connected to the second gate through a via, the light-emitting signal connection line is arranged in the fourth conductive layer, the first end of the light-emitting signal connection line is connected to the light-emitting signal line in the current unit row through a via, and the second end of the light-emitting signal connection line is connected to the first gate in the next unit row through a via.

[0016] In an exemplary embodiment, the multiple conductive layers also include a fifth conductive layer arranged on a side of the fourth conductive layer away from the substrate, the first power line is arranged in the fifth conductive layer, and the orthographic projection of the first power line on the display substrate plane at least partially overlaps with the orthographic projection of the light-emitting signal connection line on the display substrate plane.

[0017] In an exemplary embodiment, at least one circuit unit further includes a first initial signal line extending along a pixel row direction and a first connecting line extending along a pixel column direction, wherein the first initial signal line is configured to provide a first initial signal to the pixel driving circuit, and the first initial signal line and the first connecting line are connected to form a mesh connection structure for transmitting the first initial signal.

[0018] In an exemplary embodiment, an orthographic projection of the first connection line on the plane of the display substrate does not overlap with an orthographic projection of the gate electrode of the driving transistor on the plane of the display substrate.

[0019] In an exemplary embodiment, the pixel driving circuit further includes a compensation transistor, an active layer of the compensation transistor and an active layer of the driving transistor are interconnected via an active connecting line, and an orthographic projection of the first connecting line on the plane of the display substrate at least partially does not overlap with an orthographic projection of the active connecting line on the plane of the display substrate.

[0020] In an exemplary embodiment, at least one circuit unit further includes a second initial signal line extending along a pixel row direction and a second connecting line extending along a pixel column direction, wherein the second initial signal line is configured to provide a second initial signal to the pixel driving circuit, and the second initial signal line and the second connecting line are connected to form a mesh connection structure for transmitting the second initial signal.

[0021] In an exemplary embodiment, an orthographic projection of the second connection line on the plane of the display substrate does not overlap with an orthographic projection of the gate electrode of the driving transistor on the plane of the display substrate.

[0022] In an exemplary embodiment, the pixel driving circuit further includes a compensation transistor, an active layer of the compensation transistor and an active layer of the driving transistor are connected to each other via an active connecting line, and an orthographic projection of the second connecting line on the plane of the display substrate at least partially does not overlap with an orthographic projection of the active connecting line on the plane of the display substrate.

[0023] In an exemplary embodiment, at least one circuit unit further includes a third connection line extending along the pixel row direction and a second power line extending along the pixel column direction, and the second power line and the third connection line are connected to form a mesh connection structure for transmitting the second power signal.

[0024] In an exemplary embodiment, an orthographic projection of the second power line on the plane of the display substrate does not overlap with an orthographic projection of the gate electrode of the driving transistor on the plane of the display substrate.

[0025] In an exemplary embodiment, the pixel driving circuit further includes a compensation transistor, an active layer of the compensation transistor and an active layer of the driving transistor are connected to each other via an active connecting line, and an orthographic projection of the second power line on the plane of the display substrate at least partially does not overlap with an orthographic projection of the active connecting line on the plane of the display substrate.

[0026] In an exemplary embodiment, the pixel driving circuit further includes a storage capacitor and a first capacitor; the storage capacitor includes a first plate and a second plate, the orthographic projection of the first plate on the display substrate plane at least partially overlaps with the orthographic projection of the second plate on the display substrate plane, the first plate serves as the gate electrode of the driving transistor, and the second plate is connected to the first power line; the first capacitor includes a third plate and a fourth plate, the orthographic projection of the third plate on the display substrate plane at least partially overlaps with the orthographic projection of the fourth plate on the display substrate plane, the third plate is respectively connected to the first electrode of the driving transistor and the second electrode of the first light-emitting control transistor, and the fourth plate is connected to the first power line.

[0027] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes at least a semiconductor layer, a first conductive layer, and a second conductive layer, which are sequentially arranged on a base in a direction away from the base, the third electrode plate is arranged in the semiconductor layer, the first electrode plate is arranged in the first conductive layer, and the second electrode plate and the fourth electrode plate are arranged in the second conductive layer.

[0028] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0029] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0031] FIG1 is a schematic structural diagram of a display device;

[0032] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0033] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0034] FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0035] FIG5 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0036] FIG6 is a schematic diagram of a display substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0037] 7A and 7B are schematic diagrams of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0038] 8A and 8B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0039] FIG9 is a schematic diagram of a display substrate after a fourth insulating layer pattern is formed according to the present disclosure;

[0040] 10A and 10B are schematic diagrams of a display substrate after a third conductive layer pattern is formed thereon according to the present disclosure;

[0041] FIG11 is a schematic diagram of a display substrate after forming a first flat layer pattern according to the present disclosure;

[0042] 12A and 12B are schematic diagrams of a display substrate after a fourth conductive layer pattern is formed thereon according to the present disclosure;

[0043] 12C to 12E are schematic diagrams of a meshed connection structure of a first initial signal and a second initial signal according to the present disclosure;

[0044] FIG13 is a schematic diagram of a display substrate after forming a second flat layer pattern according to the present disclosure;

[0045] 14A and 14B are schematic diagrams of a display substrate after forming an anode conductive layer pattern according to the present disclosure;

[0046] FIG15 is a schematic diagram of a display substrate according to the present disclosure after a pixel definition layer pattern is formed;

[0047] FIG16 is a schematic diagram of an equivalent circuit of another pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0048] FIG17 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0049] FIG18 is a schematic diagram of another display substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0050] 19A and 19B are schematic diagrams of another display substrate after forming a first conductive layer pattern according to the present disclosure;

[0051] 20A and 20B are schematic diagrams of another display substrate after forming a second conductive layer pattern according to the present disclosure;

[0052] FIG21 is a schematic diagram of another display substrate after forming a fourth insulating layer pattern according to the present disclosure;

[0053] 22A and 22B are schematic diagrams of another display substrate after forming a third conductive layer pattern according to the present disclosure;

[0054] FIG23 is a schematic diagram of another display substrate after forming a first flat layer pattern according to the present disclosure;

[0055] 24A and 24B are schematic diagrams of another display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0056] FIG25 is a schematic diagram of another display substrate after forming a second planar layer pattern according to the present disclosure;

[0057] 26A and 26B are schematic diagrams of another display substrate after forming a fifth conductive layer pattern according to the present disclosure;

[0058] FIG26C is a schematic diagram of a meshed connection structure of an initial signal and a second power supply according to the present disclosure;

[0059] FIG27 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0060] 28A and 28B are schematic diagrams of another display substrate after forming a third conductive layer pattern according to the present disclosure;

[0061] FIG29 is a schematic diagram of another display substrate after forming a first planar layer pattern according to the present disclosure;

[0062] 30A and 30B are schematic diagrams of another display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0063] 30C and 30D are schematic diagrams of another meshed connection structure of an initial signal and a second power supply according to the present disclosure;

[0064] 31A and 31B are schematic diagrams of another display substrate after forming an anode conductive layer pattern according to the present disclosure;

[0065] FIG32 is a schematic diagram of another display substrate according to the present disclosure after a pixel definition layer pattern is formed;

[0066] 33A and 33B are schematic diagrams of another display substrate after forming an anode conductive layer pattern according to the present disclosure.

[0067] Explanation of Reference Numerals: 11—first active layer; 12—second active layer; 13—third active layer; 14—fourth active layer; 15—fifth active layer; 16—sixth active layer; 17—seventh active layer; 18—active connection line; 21—first scanning signal line; 22—second scanning signal line; 23—third scanning signal line; 31—first initial signal line; 32—second initial signal line; 41—first connection electrode; 42—second connection electrode; 43—third connection electrode; 44—fourth connection electrode; 45—fifth connection electrode; 46—sixth connection electrode; 47—seventh connection electrode; 48—eighth connection electrode; 49—ninth connection electrode; 51—eleventh connection electrode; 52—twelfth connection electrode; 53—thirteenth connection electrode; 54—fourteenth connection electrode; 55—fifteenth connection electrode; 56—luminous signal connection line; 61—first power line; 62—data signal line; 63—anode connection electrode; 64—second power line; 71—first electrode plate; 72—second electrode plate; 73—third electrode plate; 74—fourth electrode plate; 75—opening; 76—electrode plate connection bar; 81—first connection line; 82—second connection line; 83—third connection line; 90—anode; 91—first signal line; 92—second signal line; 93—luminous signal line; 101—substrate; 102—driving circuit layer; 103—luminous structure layer; 104—packaging structure layer. DETAILED DESCRIPTION

[0068] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0069] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0070] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0071] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0072] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0073] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0074] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0075] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0076] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0077] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0078] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0079] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0080] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to the data signal lines DATA1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines DATA1 to Dn on a pixel row basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to the scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit the scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The emission driver can generate emission signals to be supplied to the emission signal lines EM1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines EM1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0081] FIG2 is a schematic diagram of a planar structure of a display substrate. As shown in FIG2 , the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit may include a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0082] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 and the fourth subpixel P4 may be green subpixels (G) that emit green light, and the third subpixel P3 may be a blue subpixel (B) that emits blue light. In an exemplary embodiment, the subpixels may be rectangular, rhombus, pentagonal, or hexagonal, and the four subpixels may be arranged in a diamond shape to form an RGBG pixel arrangement. In other exemplary embodiments, the four subpixels may be arranged horizontally, vertically, or in a square, etc., which is not limited in this disclosure.

[0083] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangular arrangement, which is not limited in the present disclosure.

[0084] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of four sub-pixels in the display area. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the drive circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0085] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting device, which may include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0086] The exemplary embodiments of the present disclosure provide a display substrate. In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate. On a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one of the circuit units may include a pixel driving circuit, and the pixel driving circuit is configured to output a corresponding current to the connected light-emitting device. The light-emitting structure layer may include a plurality of light-emitting units, at least one of the light-emitting units may include a light-emitting device, the light-emitting device being connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device being configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0087] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.

[0088] An exemplary embodiment of the present disclosure shows that a substrate may include multiple circuit units constituting multiple unit rows and multiple unit columns, at least one circuit unit includes a pixel driving circuit and at least one control line, and the control line is configured to provide a light-emitting control signal to the pixel driving circuit; in at least one circuit unit, the pixel driving circuit includes at least a driving transistor, a first light-emitting control transistor and a second light-emitting control transistor, the first electrode of the first light-emitting control transistor is connected to a first power line, the second electrode of the first light-emitting control transistor is connected to the first electrode of the driving transistor, and the first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor; the first light-emitting control transistor and the second light-emitting control transistor are connected to different control lines, and the first light-emitting control transistor and the second light-emitting control transistor are respectively arranged on both sides of the driving transistor unit column direction.

[0089] In an exemplary embodiment, at least one control line includes a first signal line and a second signal line, the first light emission control transistor is connected to the first signal line, the second light emission control transistor is connected to the second signal line, and the first signal line and the second signal line are respectively arranged on both sides of the column direction of the driving transistor unit.

[0090] In an exemplary embodiment, at least one control line includes a light emission signal line connected to the second light emission control transistor in a current cell row, and the light emission signal line is connected to the first light emission control transistor in a next cell row.

[0091] The display substrate of the exemplary embodiments of the present disclosure will be described below with reference to some examples.

[0092] Figure 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 4, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. The pixel driving circuit is connected to nine signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, first signal line EM1, second signal line EM2, first initial signal line INIT1, second initial signal line INIT2, first power line VDD, and data signal line DATA).

[0093] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the second end of the storage capacitor C, respectively; the second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively; the third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively; the fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively; and the fourth node N4 is further connected to the first electrode of the light emitting device EL.

[0094] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the first node N1.

[0095] In the exemplary embodiment, a gate electrode of the first transistor T1 is connected to the second scan signal line S2, a first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and a second electrode of the first transistor is connected to the first node N1. A gate electrode of the second transistor T2 is connected to the first scan signal line S1, a first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to the third node N3. A gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3. A gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2. A gate electrode of the fifth transistor T5 is connected to the first signal line EM1, a first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2. A gate electrode of the sixth transistor T6 is connected to the second signal line EM2, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4. A gate electrode of the seventh transistor T7 is connected to the third scan signal line S3, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0096] The present disclosure connects the fifth transistor T5 to the first signal line EM1 and the sixth transistor T6 to the second signal line EM2, that is, the fifth transistor T5 and the sixth transistor T6 are controlled by two light-emitting signal lines respectively, thereby realizing separate control of the fifth transistor T5 and the sixth transistor T6.

[0097] In an exemplary embodiment, the light emitting device EL may be an OLED including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode). The first electrode of the light emitting device EL is connected to the fourth node N4, and the second electrode of the light emitting device EL is connected to the second power supply line VSS.

[0098] In an exemplary embodiment, the signal of the first power line VDD may be a high-level signal that is continuously provided, and the signal of the second power line VSS may be a low-level signal that is continuously provided.

[0099] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0100] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0101] Figure 5 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating a planar structure of eight circuit units (two unit rows and four unit columns). As shown in Figure 5, the display substrate can include multiple circuit units within a plane parallel to the display substrate. Multiple circuit units arranged sequentially along a first direction X are called unit rows, and multiple circuit units arranged sequentially along a second direction Y are called unit columns. The multiple unit rows and multiple unit columns constitute an array of circuit units arranged in an array, with the first direction X intersecting the second direction Y.

[0102] In an exemplary embodiment, at least one circuit unit may include a pixel driving circuit, which is respectively connected to a first power line 61, a first signal line 91, and a second signal line 92, wherein the first power line 61 is configured to provide a first power signal to the pixel driving circuit, the first signal line 91 is configured to provide a first light-emitting control signal to the pixel driving circuit, and the second signal line 92 is configured to provide a second light-emitting control signal to the pixel driving circuit, and the first light-emitting control signal and the second light-emitting control signal are different signals.

[0103] In an exemplary embodiment, the first signal line 91 and the second signal line 92 may be shaped as a straight line or a zigzag line with the main portion extending along the first direction X, and the first power line 61 may be shaped as a straight line or a zigzag line with the main portion extending along the second direction Y.

[0104] In this disclosure, "A extends along direction B" means that A can include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B."

[0105] In an exemplary embodiment, at least one pixel driving circuit may include at least a plurality of transistors, and the plurality of transistors may include at least a third transistor T3 as a driving transistor, a fifth transistor T5 as a first emission control transistor, and a sixth transistor T6 as a second emission control transistor. A gate electrode of the fifth transistor T5 is connected to the first signal line 91, a first electrode of the fifth transistor T5 is connected to the first power line 61, a second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3, a gate electrode of the sixth transistor T6 is connected to the second signal line 92, and a first electrode of the sixth transistor T6 is connected to the second electrode of the third transistor T3.

[0106] In an exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 may be disposed on both sides of the third transistor T3 in the first direction X (unit row direction). For example, the fifth transistor T5 may be disposed on a side opposite to the first direction X of the third transistor T3, and the sixth transistor T6 may be disposed on a side of the third transistor T3 in the first direction X.

[0107] In an exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 may be disposed on both sides of the third transistor T3 in the second direction Y (unit column direction). For example, the fifth transistor T5 may be disposed on a side opposite to the second direction Y of the third transistor T3, and the sixth transistor T6 may be disposed on a side of the third transistor T3 in the second direction Y.

[0108] In an exemplary embodiment, the first signal line 91 and the second signal line 92 may be provided on both sides of the third transistor T3 in the second direction Y (unit column direction). For example, the first signal line 91 may be provided on one side of the third transistor T3 in the opposite direction of the second direction Y, and the second signal line 92 may be provided on one side of the third transistor T3 in the second direction Y.

[0109] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a plurality of conductive layers, and the first signal line 91 and the second signal line 92 may be provided in different conductive layers.

[0110] In an exemplary embodiment, the sixth transistor T6 may include at least a sixth gate electrode, which may serve as the second gate of the present disclosure. The sixth gate electrode and the second signal line 92 may be provided in different conductive layers, and the second signal line 92 may be connected to the sixth gate electrode through a via.

[0111] In an exemplary embodiment, the sixth gate electrode and the first signal line 91 may be provided in the same conductive layer.

[0112] In an exemplary embodiment, the pixel driving circuit may further include a second transistor T2 serving as a compensation transistor. A gate electrode of the second transistor T2 is connected to the first scan signal line 21, a first electrode of the second transistor T2 is connected to the gate electrode of the third transistor T3 via the first connection electrode 41, and a second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6, respectively.

[0113] In an exemplary embodiment, the orthographic projection of the first connecting electrode 41 on the display substrate plane at least partially overlaps with the orthographic projection of the first signal line 91 on the display substrate plane, and the orthographic projection of the first connecting electrode 41 on the display substrate plane at least partially overlaps with the orthographic projection of the first scanning signal line 21 on the display substrate plane, that is, the first connecting electrode 41 overlaps with the first signal line 91 and the first scanning signal line 21 at the same time.

[0114] In an exemplary embodiment, the pixel driving circuit may further include a first transistor T1 as a first initialization transistor, the gate electrode of the first transistor T1 being connected to the second scanning signal line 22, the first electrode of the first transistor T1 being connected to the first initial signal line 31, the second electrode of the first transistor T1 being connected to the gate electrode of the third transistor T3 via the first connecting electrode 41, the first initial signal line 31 being configured to provide a first initial signal to the pixel driving circuit, and the shape of the first initial signal line 31 may be a straight line or a broken line extending along the first direction X.

[0115] In an exemplary embodiment, at least one circuit unit may further include a first connection line 81 extending along the second direction Y, the first connection line 81 being connected to the first initial signal line 31 to form a mesh connection structure for transmitting the first initial signal on the display substrate.

[0116] In an exemplary embodiment, the pixel driving circuit may further include a seventh transistor T7 serving as a second initialization transistor, wherein a gate electrode of the seventh transistor T7 is connected to the third scanning signal line 23, a first electrode of the seventh transistor T7 is connected to a second initial signal line 32, and a second electrode of the seventh transistor T7 is connected to a second electrode of the sixth transistor T6. The second initial signal line 32 is configured to provide a second initial signal to the pixel driving circuit, and the shape of the second initial signal line 32 may be a straight line or a broken line extending along the first direction X.

[0117] In an exemplary embodiment, at least one circuit unit may further include a second connection line 82 extending along the second direction Y, the second connection line 82 being connected to the second initial signal line 32 to form a mesh connection structure on the display substrate for transmitting the second initial signal.

[0118] In an exemplary embodiment, the first preliminary signal line 31 and the second preliminary signal line 32 may be disposed in each cell row, and the first connection lines 81 and the second connection lines 82 may be alternately disposed in a plurality of cell columns.

[0119] In an exemplary embodiment, the pixel driving circuit may further include a fourth transistor T4 serving as a data writing transistor. The gate electrode of the fourth transistor T4 is connected to the third scan signal line 23, the first electrode of the fourth transistor T4 is connected to the data signal line 62, and the second electrode of the fourth transistor T4 is connected to the first electrode of the third transistor T3. The second transistor T2 and the fourth transistor T4 may be disposed on both sides of the third transistor T3 in the second direction Y (unit column direction). For example, the second transistor T2 may be disposed on a side of the third transistor T3 in the opposite direction of the second direction Y, and the fourth transistor T4 may be disposed on a side of the third transistor T3 in the second direction Y.

[0120] In an exemplary embodiment, within a plane perpendicular to the display substrate, the display substrate may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on a base. The semiconductor layer may include an active layer of a plurality of transistors, the first conductive layer may include at least a first signal line 91, a plurality of scan signal lines, and gate electrodes of a plurality of transistors, the second conductive layer may include at least a second initial signal line 32, the third conductive layer may include at least the first initial signal line 31, the second signal line 92, and a plurality of connection electrodes, and the fourth conductive layer may include at least a first power line 61, a first connection line 81, and a second connection line 82.

[0121] In an exemplary embodiment, the display substrate may further include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer and a first planarizing layer, the first insulating layer may be disposed between the base and the semiconductor layer, the second insulating layer may be disposed between the semiconductor layer and the first conductive layer, the third insulating layer may be disposed between the first conductive layer and the second conductive layer, the fourth insulating layer may be disposed between the second conductive layer and the third conductive layer, and the first planarizing layer may be disposed between the third conductive layer and the fourth conductive layer.

[0122] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes the deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes the coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0123] In an exemplary embodiment, taking eight circuit units (two unit rows and four unit columns) as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0124] (11) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, as shown in FIG6 .

[0125] In an exemplary embodiment, the semiconductor layer of each circuit unit may include a first active layer 11 of the first transistor T1 to a seventh active layer 17 of the seventh transistor T7, and the first active layer 11 and the second active layer 12 are an integrated structure connected to each other, and the third active layer 13 to the seventh active layer 17 are an integrated structure connected to each other.

[0126] In an exemplary embodiment, in the first direction X, the fourth active layer 14 and the fifth active layer 15 in the Nth unit column can be located on the side of the third active layer 13 of the present circuit unit away from the N+1th unit column, and the sixth active layer 16 can be located on the side of the third active layer 13 of the present circuit unit close to the N+1th unit column, that is, the fifth active layer 15 and the sixth active layer 16 are respectively located on both sides of the third active layer 13 in the first direction X.

[0127] In an exemplary embodiment, in the second direction Y, the first active layer 11, the second active layer 12 and the fifth active layer 15 in the Mth unit row can be located on the side of the third active layer 13 of the present circuit unit away from the M+1th unit row, and the fourth active layer 14, the sixth active layer 16 and the seventh active layer 17 can be located on the side of the third active layer 13 of the present circuit unit close to the M+1th unit row, that is, the fifth active layer 15 and the sixth active layer 16 are respectively located on both sides of the third active layer 13 in the second direction Y.

[0128] The present disclosure arranges the fifth transistor T5 and the sixth transistor T6 on both sides of the third transistor T3 in the first direction X and the second direction Y, thereby facilitating separate control of the fifth transistor T5 and the sixth transistor T6.

[0129] In an exemplary embodiment, the first active layer 11 may be shaped like an "n", the second active layer 12 and the seventh active layer 17 may be shaped like an "L", the third active layer 13 may be shaped like an "Ω", and the fourth active layer 14, the fifth active layer 15, and the sixth active layer 16 may be shaped like an "I".

[0130] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer, i.e., the second region 11-2 of the first active layer and the first region 12-1 of the second active layer are interconnected. The first region 13-1 of the third active layer may serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer, i.e., the first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer are interconnected. The second region 13-2 of the third active layer may serve as the first region 16-1 of the sixth active layer, i.e., the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer are interconnected. The second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer, i.e., the second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer are interconnected. The first region 11-1 of the first active layer 11, the second region 12-2 of the second active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, and the first region 17-1 of the seventh active layer may be separately provided.

[0131] In an exemplary embodiment, the first semiconductor layer may be made of polycrystalline silicon (p-Si), meaning the first to seventh transistors are LTPS transistors. In an exemplary embodiment, patterning the first semiconductor film through a patterning process may include: first forming an amorphous silicon (a-Si) film on the first insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and then crystallizing the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, patterning the polycrystalline silicon film to form a first semiconductor layer pattern.

[0132] (12) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG7A and FIG7B , where FIG7B is a plan view schematic diagram of the first conductive layer in FIG7A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0133] In an exemplary embodiment, the first conductive layer pattern of each circuit unit includes at least a first scan signal line 21 , a second scan signal line 22 , a third scan signal line 23 , a sixth gate electrode 26 , a first plate 71 of a storage capacitor, and a first signal line 91 .

[0134] In an exemplary embodiment, the first electrode plate 71 may be rectangular, with chamfered or grooved corners. The orthographic projection of the first electrode plate 71 on the substrate at least partially overlaps the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 71 may serve as both a plate of the storage capacitor and a gate electrode of the third transistor T3.

[0135] In an exemplary embodiment, the shape of the first scanning signal line 21 can be a straight line or a broken line with the main part extending along the first direction X. The first scanning signal line 21 can be located on the side of the first electrode 71 in the opposite direction of the second direction Y. The side of the first scanning signal line 21 away from the first electrode 71 is connected to the gate block 21-1. The area where the first scanning signal line 21 and the gate block 21-1 overlap with the second active layer can serve as the gate electrode of the second transistor T2 of the dual-gate structure.

[0136] In an exemplary embodiment, the shape of the second scanning signal line 22 can be a straight line or a broken line with the main portion extending along the first direction X. The second scanning signal line 22 can be located on the side of the first scanning signal line 21 away from the first electrode 71. The area where the second scanning signal line 22 overlaps with the first active layer can serve as the gate electrode of the first transistor T1 of the dual-gate structure.

[0137] In an exemplary embodiment, the shape of the third scan signal line 23 can be a straight line or a broken line with the main portion extending along the first direction X. The third scan signal line 23 can be located on the side of the first electrode 71 in the opposite direction of the second direction Y. The area where the third scan signal line 23 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4, and the area where the third scan signal line 23 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7. That is, the fourth transistor T4 and the seventh transistor T7 of the present disclosure are controlled to be turned on and off by the same scan signal line.

[0138] In an exemplary embodiment, the shape of the first signal line 91 can be a straight line or a broken line with the main portion extending along the first direction X. The first signal line 91 can be located between the first scanning signal line 21 and the first electrode 71. The area where the first signal line 91 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5.

[0139] In an exemplary embodiment, the sixth gate electrode 26 may be in the shape of a strip extending along the first direction X. The sixth gate electrode 26 may be located between the third scan signal line 23 and the first electrode plate 71. The region where the sixth gate electrode 26 overlaps with the sixth active layer may serve as the gate electrode of the sixth transistor T6. In an exemplary embodiment, the sixth gate electrode 26 is configured to be connected to a second signal line formed subsequently.

[0140] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23 and the first signal line 91 may include an overlapping area with the first semiconductor layer and an area not overlapping with the first semiconductor layer. The width of at least one signal line in the area overlapping with the first semiconductor layer may be greater than the width of at least one signal line in the area not overlapping with the first semiconductor layer, and the width may be the dimension in the second direction Y.

[0141] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the first active layer to the seventh active layer are both conductorized.

[0142] (13) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG8A and FIG8B , where FIG8B is a plan view schematic diagram of the second conductive layer in FIG8A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0143] In an exemplary embodiment, the second conductive layer pattern of each circuit unit may include at least a second preliminary signal line 32 and a second plate 72 of a storage capacitor.

[0144] In an exemplary embodiment, the outline of the second electrode plate 72 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 72 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 71 on the substrate. The second electrode plate 72 can serve as another electrode plate of the storage capacitor, and the first electrode plate 71 and the second electrode plate 72 constitute the storage capacitor of the pixel driving circuit.

[0145] In an exemplary embodiment, an opening 75 is provided on the second electrode plate 72. Opening 75 can be rectangular and located in the central region of the second electrode plate 72, forming an annular structure. Opening 75 exposes the third insulating layer covering the first electrode plate 71, and the orthographic projection of the first electrode plate 71 on the substrate includes the orthographic projection of the opening 75 on the substrate. In an exemplary embodiment, opening 75 is configured to accommodate a ninth via hole to be formed later. The ninth via hole is located within opening 75 and exposes the first electrode plate 71, allowing a first connecting electrode to be formed later to be connected to the first electrode plate 71.

[0146] In an exemplary embodiment, the second conductive layer of each circuit unit may further include a plate connecting bar 76. The plate connecting bar 76 may be in the shape of a bar extending along the first direction X. The plate connecting bar 76 may be disposed on one side of the second plate 72 in the first direction X or on a side opposite to the first direction X. The first end of the plate connecting bar 76 is connected to the second plate 72 in the circuit unit in question, and the second end of the plate connecting bar 76 is connected to the second plate 72 in the adjacent circuit unit in the first direction X. This allows the second plates 72 in adjacent circuit units in a row of units to form an interconnected, integrated structure. Because the second plate 72 in each circuit unit is connected to a subsequently formed first power line, by forming the second plates 72 of adjacent circuit units into an interconnected, integrated structure, the second plates of the integrated structure can be reused as power signal lines. This ensures that multiple second plates in a row of units have the same potential, which helps improve panel uniformity, prevent display defects on the display substrate, and ensure the display quality of the display substrate.

[0147] In an exemplary embodiment, the second initial signal line 32 may be in the shape of a straight line or a zigzag line, with a main portion thereof extending along the first direction X. The second initial signal line 32 may be located on a side of the third scan signal line 23 away from the second electrode plate 72. In an exemplary embodiment, the second initial signal line 32 is configured to be connected to the first region of the seventh active layer via a subsequently formed sixth connection electrode.

[0148] (14) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG. 9 .

[0149] In an exemplary embodiment, the plurality of vias in each circuit unit may include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, and a twelfth via V12.

[0150] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed first initial connection block to the first region of the first active layer through the via hole.

[0151] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer (also the first region of the second active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the first active layer, and the second via hole V2 is configured to connect a subsequently formed first connecting electrode to the second region of the first active layer (also the first region of the second active layer) through the via hole.

[0152] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the second region of the second active layer, and the third via hole V3 is configured to connect a subsequently formed fifth connecting electrode to the second region of the second active layer through the via hole.

[0153] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second area of ​​the third active layer (also the first area of ​​the sixth active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the second area of ​​the third active layer, and the fourth via hole V4 is configured to connect the subsequently formed fifth connecting electrode to the second area of ​​the third active layer (also the first area of ​​the sixth active layer) through the via hole.

[0154] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the fifth via hole V5 are etched away to expose the surface of the first area of ​​the fourth active layer, and the fifth via hole V5 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the fourth active layer through the via hole.

[0155] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the first region of the fifth active layer, and the sixth via hole V6 is configured to connect a subsequently formed second connecting electrode to the first region of the fifth active layer through the via hole.

[0156] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the second region of the sixth active layer (also the second region of the seventh active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the second region of the sixth active layer, and the seventh via hole V7 is configured to connect a subsequently formed fourth connecting electrode to the second region of the sixth active layer (also the second region of the seventh active layer) through the via hole.

[0157] In an exemplary embodiment, the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via hole V8 are etched away to expose the surface of the first region of the seventh active layer, and the eighth via hole V8 is configured to connect the subsequently formed sixth connecting electrode to the first region of the seventh active layer through the via hole.

[0158] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the opening 75 on the substrate, the fourth insulating layer and the third insulating layer in the ninth via hole V9 are etched away to expose the surface of the first electrode 71, and the ninth via hole V9 is configured to connect the subsequently formed first connecting electrode to the first electrode 71 through the via hole.

[0159] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the second electrode plate 72 on the substrate, the fourth insulating layer in the tenth via hole V10 is etched away, exposing the surface of the second electrode plate 72, and the tenth via hole V10 is configured to connect the subsequently formed second connecting electrode to the second electrode plate 72 through the via hole.

[0160] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second initial signal line 32 on the substrate, the fourth insulating layer in the eleventh via hole V11 is etched away to expose the surface of the second initial signal line 32, and the eleventh via hole V11 is configured to connect the subsequently formed sixth connecting electrode to the second initial signal line 32 through the via hole.

[0161] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the sixth gate electrode 26 on the substrate, the fourth insulating layer and the third insulating layer in the twelfth via V12 are etched away to expose the surface of the sixth gate electrode 26, and the twelfth via V12 is configured to connect a subsequently formed second signal line to the sixth gate electrode 26 through the via.

[0162] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as shown in FIG10A and FIG10B , where FIG10B is a plan view schematic diagram of the third conductive layer in FIG10A . In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0163] In an exemplary embodiment, the third conductive layer of each circuit unit may include at least: a first initial signal line 31, a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode 46, a seventh connection electrode 47, an eighth connection electrode 48 and a second signal line 92.

[0164] In an exemplary embodiment, the shape of the first initial signal line 31 can be a straight line or a broken line extending along the first direction X. The first initial signal line 31 can be located on the side of the first scanning signal line 21 away from the second electrode 72. The positive projection of the first initial signal line 31 on the substrate at least partially overlaps with the positive projection of the second scanning signal line 22 on the substrate. The first initial signal line 31 with a constant voltage can play a shielding role, reducing the influence of the second scanning signal line 22 on the pixel driving circuit.

[0165] In an exemplary embodiment, the shape of the second signal line 92 can be a straight line or a broken line extending along the first direction X, the second signal line 92 can be located between the third scanning signal line 23 and the second electrode 72, and the second signal line 92 can be connected to the sixth gate electrode 26 of each circuit unit through the twelfth via V12 of each circuit unit, so that the second signal line 92 can control the conduction and disconnection of the sixth transistor T6.

[0166] In an exemplary embodiment, the first connection electrode 41 may be in the shape of a strip extending along the second direction Y. A first end of the first connection electrode 41 is connected to the second region of the first active layer (also the first region of the second active layer) via a second via hole V2, and a second end of the first connection electrode 41 is connected to the first electrode plate 71 via a ninth via hole V9. In an exemplary embodiment, because the first electrode plate 71 also serves as the gate electrode of the third transistor T3, the first connection electrode 51 causes the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 71 to have the same potential, thereby forming a first node N1 of the pixel driving circuit.

[0167] In an exemplary embodiment, the orthographic projection of the first connection electrode 41 on the substrate at least partially overlaps with the orthographic projection of the first scan signal line 21 on the substrate, and the orthographic projection of the first connection electrode 41 on the substrate at least partially overlaps with the orthographic projection of the first signal line 91 on the substrate. That is, the first connection electrode 41 overlaps both the first scan signal line 21 and the first signal line 91. Compared to the existing structure in which the first node N1 overlaps with one signal line, the present disclosure arranges for the first node N1 of the pixel driving circuit to overlap with both the first scan signal line 21 and the first signal line 91. This allows the coupling effect on the first node N1 to be complemented by the transition of the two signal lines.

[0168] In an exemplary embodiment, the second connection electrode 42 may be in the shape of a strip extending along the second direction Y. A first end of the second connection electrode 42 is connected to the first region of the fifth active layer via a sixth via hole V6, and a second end of the second connection electrode 42 is connected to the second electrode plate 72 via a tenth via hole V10. In an exemplary embodiment, the second connection electrode 42 ensures that the first electrode of the fifth transistor T5 and the second electrode plate 72 of the storage capacitor in each circuit unit have the same potential.

[0169] In an exemplary embodiment, a first power connection block 42-1 may be provided between the first end and the second end of the second connection electrode 42. The shape of the first power connection block 42-1 may be block-shaped (such as rectangular). The orthographic projection of the first power connection block 42-1 on the substrate may be located within the range of the orthographic projection of the second electrode plate 72 on the substrate. The first power connection block 42-1 is configured to be connected to a first power line formed subsequently.

[0170] In an exemplary embodiment, the third connection electrode 43 may be in a block shape (e.g., a rectangular shape) and is connected to the first region of the fourth active layer through a fifth via hole V5. In an exemplary embodiment, the third connection electrode 43 may serve as a first electrode of the fourth transistor T4 and is configured to be connected to a subsequently formed data signal line.

[0171] In an exemplary embodiment, the fourth connection electrode 44 may be in a block shape (e.g., a rectangle), and is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through a seventh via hole V7. In an exemplary embodiment, the fourth connection electrode 44 may simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the fourth connection electrode 44 is configured to be connected to a subsequently formed anode connection electrode.

[0172] In an exemplary embodiment, the fifth connection electrode 45 may be in the shape of a strip extending along the second direction Y. A first end of the fifth connection electrode 45 is connected to the second region of the second active layer via a third via hole V3, and a second end of the fifth connection electrode 45 is connected to the first region of the sixth active layer via a fourth via hole V4. In an exemplary embodiment, since the first region of the sixth active layer can serve as the second region of the third active layer, the fifth connection electrode 45 causes the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 to have the same potential, forming a third node N3 of the pixel driving circuit. The second active layer can serve as the compensation active layer of the present disclosure, and the sixth active layer can serve as the second light emission control active layer of the present disclosure. The second and sixth active layers are disposed in the semiconductor layer, and the fifth connection electrode is disposed in the third conductive layer. Therefore, the sixth active layer and the fifth connection electrode are disposed in different film layers.

[0173] In an exemplary embodiment, the shape of the sixth connection electrode 46 can be a strip shape extending along the first direction X, the first end of the sixth connection electrode 46 is connected to the first region of the seventh active layer through the eighth via V8, and the second end of the sixth connection electrode 46 is connected to the second initial signal line 32 through the eleventh via V11, so that the second initial signal line 32 can write the second initial signal into the first electrode of the seventh transistor T7.

[0174] In an exemplary embodiment, the sixth connection electrode 46 in some circuit cells may be connected to an initial connection block 46-1. The initial connection block 46-1 may be in a block shape (e.g., a rectangle). The initial connection block 46-1 is configured to connect to a second connection line formed subsequently. For example, the initial connection block 46-1 may be provided in the circuit cells of the Nth cell column and the N+2th cell column.

[0175] In an exemplary embodiment, the shape of the seventh connection electrode 47 can be a block shape (such as a rectangle), and the seventh connection electrode 47 can be arranged on a side of the first initial signal line 31 close to the first scanning signal line 21. The first end of the seventh connection electrode 47 is connected to the first initial signal line 31, and the second end of the seventh connection electrode 47 is connected to the first region of the first active layer through the first via hole V1, so that the first initial signal line 31 can write the first initial signal into the first electrode of the first transistor T1.

[0176] In an exemplary embodiment, the first preliminary signal line 31 and the seventh connection electrode 47 may be an integral structure connected to each other.

[0177] In an exemplary embodiment, the shape of the eighth connection electrode 48 can be a block shape (such as a rectangle), and the eighth connection electrode 48 can be arranged on the side of the first initial signal line 31 close to the first scanning signal line 21. The first end of the eighth connection electrode 48 is connected to the first initial signal line 31, and the second end of the eighth connection electrode 48 extends toward the direction of the first scanning signal line 21. The eighth connection electrode 48 can serve as a node shielding electrode. The positive projection of the eighth connection electrode 48 on the substrate at least partially overlaps with the positive projection of the second active layer between the two gate electrodes of the second transistor T2 on the substrate. The eighth connection electrode 48 with a constant voltage can play a shielding role, reducing the influence of the signal in the pixel driving circuit on the node between the two gate electrodes of the second transistor T2, thereby ensuring the electrical performance of the second transistor T2.

[0178] In an exemplary embodiment, the first preliminary signal line 31 and the eighth connection electrode 48 may be an integral structure connected to each other.

[0179] In an exemplary embodiment, the eighth connection electrode 48 in the circuit units of the N+1th unit column and the N+3th unit column is also configured to be connected to the first connection line formed subsequently, while the eighth connection electrode 48 in the circuit units of the Nth unit column and the N+2th unit column serves as a dummy electrode (dummy-pad) and is not connected to the fourth conductive layer formed subsequently.

[0180] (16) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the third conductive layer, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 11 .

[0181] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least a twenty-first via V21 , a twenty-second via V22 , and a twenty-third via V23 .

[0182] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the first power connection block 42-1 on the substrate, the first flat layer in the twenty-first via V21 is removed, exposing the surface of the first power connection block 42-1, and the twenty-first via V21 is configured to connect the subsequently formed first power line to the first power connection block 42-1 through the via.

[0183] In an exemplary embodiment, the twenty-first via hole V21 may be referred to as a power via hole, and the orthographic projection of the twenty-first via hole V21 on the substrate may be located within the range of the orthographic projection of the second electrode plate 72 on the substrate.

[0184] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the third connecting electrode 43 on the substrate, the first flat layer in the twenty-second via hole V22 is removed, exposing the surface of the third connecting electrode 43, and the twenty-second via hole V22 is configured to connect a subsequently formed data signal line to the third connecting electrode 43 through the via hole.

[0185] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 44 on the substrate, the first flat layer in the twenty-third via hole V23 is removed, exposing the surface of the fourth connecting electrode 44, and the twenty-third via hole V23 is configured to connect the subsequently formed anode connecting electrode to the fourth connecting electrode 44 through the via hole.

[0186] In an exemplary embodiment, a twenty-fourth via hole V24 and a twenty-fifth via hole V25 may be further provided on the first planar layer.

[0187] In an exemplary embodiment, the orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the eighth connection electrode 48 on the substrate. The first planar layer within the twenty-fourth via hole V24 is removed, exposing the surface of the eighth connection electrode 48. The twenty-fourth via hole V24 is configured to allow a subsequently formed first connection line to be connected to the eighth connection electrode 48 through the via hole. In an exemplary embodiment, the twenty-fourth via hole V24 may be provided in the circuit cells of the (N+1)th unit column and the (N+3)th unit column.

[0188] In an exemplary embodiment, the orthographic projection of the twenty-fifth via hole V25 on the substrate is within the range of the orthographic projection of the initial connection block 46-1 on the substrate. The first planar layer within the twenty-fifth via hole V25 is removed, exposing the surface of the initial connection block 46-1. The twenty-fifth via hole V25 is configured to allow a subsequently formed second connection line to be connected to the initial connection block 46-1 through the via hole. In an exemplary embodiment, the twenty-fifth via hole V25 can be provided in the circuit cells of the Nth unit column and the N+2th unit column.

[0189] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the first flat layer, as shown in FIG12A and FIG12B , where FIG12B is a planar schematic diagram of the fourth conductive layer in FIG12A . In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0190] In an exemplary embodiment, the fourth conductive layer in each circuit unit includes at least a first power supply line 61 , a data signal line 62 , and an anode connection electrode 63 .

[0191] In an exemplary embodiment, the first power line 61 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The first power line 61 is connected to the first power connection block 42-1 through the twenty-first via V21. Since the first power connection block 42-1 is connected to the second connection electrode 42, and the second connection electrode 42 is connected to the first electrode of the fifth transistor T5 and the second plate 72 of the storage capacitor, the first power line 61 writes the first power signal to the fifth transistor T5 and the second plate 72 of the storage capacitor.

[0192] In an exemplary embodiment, the data signal line 62 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The data signal line 62 is connected to the third connection electrode 43 through the twenty-second via hole V22. Since the third connection electrode 43 is connected to the first region of the fourth active layer, the data signal line 62 is connected to the first electrode of the fourth transistor T4. The data signal line 62 can write a data signal to the first electrode of the fourth transistor T4.

[0193] In an exemplary embodiment, the anode connection electrode 63 may be in the shape of a strip extending along the second direction Y. The anode connection electrode 63 is connected to the fourth connection electrode 44 via a twenty-third via hole V23. The anode connection electrode 63 is configured to be connected to a subsequently formed anode. Since the fourth connection electrode 44 is connected to the second region of the sixth active layer and the second region of the seventh active layer, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting device to emit light.

[0194] In exemplary embodiments, the fourth conductive layer may further include a first connection line 81 and a second connection line 82 .

[0195] In an exemplary embodiment, the first connection line 81 can be in the shape of a straight line or a zigzag line extending along the second direction Y. The first connection line 81 is connected to the eighth connection electrode 48 via the twenty-fourth via hole V24. Since the eighth connection electrode 48 is connected to the first initial signal line 31, the first initial signal line 31 extending along the first direction X and the first connection line 81 extending along the second direction Y are interconnected, forming a mesh-like interconnected structure on the display substrate. By providing the first initial signal line 31 and the first connection line 81 to form a mesh-like interconnected structure, the present disclosure not only effectively reduces signal line resistance and reduces the voltage drop of the first initial signal, but also effectively improves the uniformity of the first initial signal across the display substrate, effectively improving display uniformity and enhancing display quality.

[0196] In an exemplary embodiment, the second connection line 82 can be shaped as a straight line or a zigzag line extending along the second direction Y. The second connection line 82 is connected to the initial connection block 46-1 via the twenty-fifth via V25. Since the initial connection block 46-1 is connected to the sixth connection electrode 46, and the sixth connection electrode 46 is connected to the second initial signal line 32, the second initial signal line 32 extending along the first direction X and the second connection line 82 extending along the second direction Y are interconnected, forming a mesh-like interconnected structure on the display substrate. By providing the second initial signal line 32 and the second connection line 82 to form a mesh-like interconnected structure, the present disclosure not only effectively reduces signal line resistance and reduces the voltage drop of the second initial signal, but also effectively improves the uniformity of the second initial signal across the display substrate, effectively improving display uniformity and enhancing display quality.

[0197] Figure 12C is a schematic diagram of the first initial signal mesh connectivity structure of an exemplary embodiment of the present disclosure, Figure 12D is a schematic diagram of the second initial signal mesh connectivity structure of an exemplary embodiment of the present disclosure, and Figure 12E is a schematic diagram of the first initial signal mesh connectivity structure and the second initial signal mesh connectivity structure of an exemplary embodiment of the present disclosure.

[0198] As shown in Figures 12C and 12E , the first initial signal line 31 can be connected to the eighth connection electrode 48, and a first connection block 81-1 can be provided on the first connection line 81. The first connection block 81-1 can be in the shape of a strip extending along the first direction X. The first end of the first connection block 81-1 is connected to the first connection line 81, and the second end of the first connection block 81-1 is connected to the eighth connection electrode 48 through a via. This achieves interconnection between the first initial signal line 31 extending in the first direction X and the first connection line 81 extending in the second direction Y, forming a first initial signal mesh connection structure on the display substrate.

[0199] In an exemplary embodiment, the first connection line 81 and the first connection block 81 - 1 may be an integral structure connected to each other.

[0200] As shown in Figures 12D and 12E, a second connection block 82-1 can be provided on the second connection line 82. The second connection block 82-1 can be in a block shape. A first end of the second connection block 82-1 is connected to the second connection line 82, and a second end of the second connection block 82-1 is connected to the initial connection block 46-1 via a via. The initial connection block 46-1 is connected to the second initial signal line 32 via a via. This achieves interconnection between the second initial signal line 32 extending in the first direction X and the second connection line 82 extending in the second direction Y, forming a second initial signal mesh connection structure on the display substrate.

[0201] In an exemplary embodiment, the second connection line 82 and the second connection block 82 - 1 may be an integral structure connected to each other.

[0202] As shown in Figure 12E, the first initial signal line 31, the initial connection block 46-1 and the eighth connection electrode 48 can be set in the third conductive layer, the second initial signal line 32 can be set in the second conductive layer, and the first connection line 81 and the second connection line 82 can be set in the fourth conductive layer.

[0203] In an exemplary embodiment, the first connection line 81 and the second connection line 82 may be provided in different circuit units. For example, the first connection line 81 may be provided in the circuit units of the N+1th and N+3th cell columns, and the second connection line 82 may be provided in the circuit units of the Nth and N+2th cell columns. For another example, the first connection line 81 may be provided in the circuit units of the Nth and N+2th cell columns, and the second connection line 82 may be provided in the circuit units of the N+1th and N+3th cell columns.

[0204] In an exemplary embodiment, the first initial signal line 31 and the second initial signal line 32 can be set in each unit row, and the first connecting line 81 and the second connecting line 82 can be alternately set in multiple unit columns, which can make full use of the layout space, avoid affecting the light transmittance due to the setting of the first connecting line 81 and the second connecting line 82, and improve the display effect.

[0205] (18) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fourth conductive layer, wherein a plurality of vias are provided on the second planar layer, as shown in FIG. 13 .

[0206] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least an anode via V30 .

[0207] In an exemplary embodiment, the orthographic projection of the anode via V30 on the substrate is within the range of the orthographic projection of the anode connecting electrode 63 on the substrate, the second flat layer in the anode via V30 is removed to expose the surface of the anode connecting electrode 63, and the anode via V30 is configured to connect a subsequently formed anode to the anode connecting electrode 63 through the via.

[0208] At this point, the driving circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include multiple circuit units, each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a first signal line, a second signal line, a data signal line, a first power line, a first initial signal line, and a second initial signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planar layer, a fourth conductive layer, and a second planar layer stacked in sequence on the substrate.

[0209] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0210] (19) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process, and forming an anode conductive layer on the second flat layer, as shown in FIG14A and FIG14B , where FIG14B is a plan view schematic diagram of the anode conductive layer in FIG14A .

[0211] In an exemplary embodiment, the anode conductive layer may include a plurality of anodes 90, each of which may be connected to the anode connection electrode 63 of the corresponding circuit unit through the anode via V30. Since the anode connection electrode 63 is connected to the fourth connection electrode 44, and the fourth connection electrode 44 is connected to the second region of the sixth active layer and the second region of the seventh active layer, corresponding connections between the light-emitting device and the pixel driving circuit are achieved, and the pixel driving circuit can drive the light-emitting device to emit light.

[0212] In an exemplary embodiment, the plurality of anodes 90 may include a first anode of a red light-emitting device, a second anode of a first green light-emitting device, a third anode of a blue light-emitting device, and a fourth anode of a second green light-emitting device. The first anode, the second anode, the third anode, and the fourth anode may be sequentially arranged along the first direction X, and the first anode, the second anode, the third anode, and the fourth anode of adjacent rows may be staggered to form an RGBG pixel arrangement.

[0213] (20) Forming a pixel definition layer pattern. In an exemplary embodiment, forming the pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, and patterning the pixel definition film through a patterning process to form the pixel definition layer pattern, as shown in FIG. 15 .

[0214] In an exemplary embodiment, the pixel definition layer may include a plurality of pixel openings K, and each pixel opening K may expose a surface of the anode 90 .

[0215] In an exemplary embodiment, the subsequent preparation process may include: forming an organic light-emitting layer using an evaporation or inkjet printing process, connecting the organic light-emitting layer to an anode through a pixel opening, forming a cathode on the organic light-emitting layer, and connecting the cathode to the organic light-emitting layer; and forming an encapsulation structure layer, which may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of an organic material. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer.

[0216] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0217] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The anode conductive layer can be a single layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a multilayer composite structure, such as ITO / Ag / ITO. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The first planar layer and the second planar layer can be made of organic materials, such as resin. The pixel definition layer can be made of polyimide, acrylic, or polyethylene terephthalate. The cathode may be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or an alloy made of any one or more of the above metals.

[0218] An exemplary embodiment of the present disclosure provides a display substrate, in which a fifth transistor and a sixth transistor are separately controlled, the fifth transistor T5 is connected to a first signal line, the sixth transistor T6 is connected to a second signal line, and the first signal line and the second signal line jointly adjust the duty cycle of pulse width modulation (PWM), thereby achieving ultra-high frequency and higher precision pulse width modulation, light signal duty cycle compensation, low grayscale compensation, and improved afterimage.

[0219] The present disclosure displays a substrate in which the first signal line and the second signal line are arranged on different conductive layers, the first signal line and the second signal line are arranged on both sides of the third transistor T3 in the second direction, and the fifth transistor T5 and the sixth transistor T6 are arranged on both sides of the third transistor T3 in the first direction and the second direction, which is conducive to achieving separate control of the fifth transistor T5 and the sixth transistor T6.

[0220] The disclosed display substrate arranges the first node of the pixel driving circuit to overlap with the first scanning signal line and the first signal line respectively, and can complement the coupling influence on the first node through the jump of the two signal lines.

[0221] The display substrate disclosed herein forms a mesh-like interconnected structure by setting a first initial signal line extending in a first direction in the main body and a first connecting line extending in a second direction in the main body, and by setting a second initial signal line extending in the first direction in the main body and a second connecting line extending in the second direction in the main body. This not only effectively reduces the resistance of the initial signal line and reduces the voltage drop of the initial voltage, but also effectively improves the uniformity of the initial voltage in the display substrate, effectively improves the display uniformity, and improves the display quality and display quality.

[0222] The disclosed display substrate reduces the influence of the signal in the pixel driving circuit on the node between the two gate electrodes of the second transistor T2 by providing a node shielding electrode, thereby ensuring the electrical performance of the second transistor T2.

[0223] The preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0224] FIG16 is a schematic diagram of an equivalent circuit of another exemplary embodiment of the present disclosure. As shown in FIG16 , the main structure of the pixel driving circuit of the present embodiment is substantially the same as that shown in FIG4 , except that the pixel driving circuit of this embodiment further includes a first capacitor C1, a first end of which is connected to the first power line VDD, and a second end of which is connected to the second node N2.

[0225] In an exemplary embodiment, the gate electrode of the fifth transistor T5 in the pixel driving circuit of this embodiment is connected to the light-emitting signal line EM_n-1 in the previous unit row, and the gate electrode of the sixth transistor T6 is connected to the light-emitting signal line EM_n in the current unit row, thereby realizing separate control of the fifth transistor T5 and the sixth transistor T6.

[0226] Figure 17 is a schematic diagram of another display substrate structure according to an exemplary embodiment of the present disclosure, illustrating a planar structure of eight circuit units (two unit rows and four unit columns). In this exemplary embodiment, the main structure of the display substrate of this embodiment is substantially the same as that shown in Figure 5 , except that only one light-emitting signal line is provided in each display unit of this embodiment. This light-emitting signal line is connected to the gate electrode of the sixth transistor T6 in the current unit row and to the gate electrode of the fifth transistor T5 in the next unit row.

[0227] In an exemplary embodiment, at least one circuit unit may include a pixel driving circuit, which is respectively connected to the first power line 61 and the light emitting signal line 93, and the light emitting signal line 93 is configured to provide a light emitting control signal to the sixth transistor T6 in the current unit row and the fifth transistor T5 in the next unit row.

[0228] In an exemplary embodiment, at least one pixel driving circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7, and the positions and connection relationships of the above transistors are substantially the same as those in the previous embodiment.

[0229] In an exemplary embodiment, the shape of the light emitting signal line 93 may be a straight line or a zigzag line with a main portion extending along the first direction X. The light emitting signal line 93 may be disposed on one side of the third transistor T3 in the second direction Y.

[0230] In an exemplary embodiment, the fifth transistor T5 may include at least a fifth gate electrode, and the sixth transistor T6 may include at least a sixth gate electrode. The fifth gate electrode may serve as the first gate electrode of the present disclosure, and the sixth gate electrode may serve as the second gate electrode of the present disclosure. In at least one circuit unit, the light emitting signal line 93 is connected to the sixth gate electrode in the current unit row, and the light emitting signal line 93 is connected to the fifth gate electrode in the next unit row via the light emitting signal connection line 56.

[0231] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include multiple conductive layers, the fifth gate electrode and the sixth gate electrode may be arranged in the same conductive layer, the fifth gate electrode (sixth gate electrode) and the light-emitting signal line 93 may be arranged in different conductive layers, the fifth gate electrode (sixth gate electrode) and the light-emitting signal connection line 56 may be arranged in different conductive layers, and the light-emitting signal connection line 56 and the light-emitting signal line 93 may be arranged in different conductive layers.

[0232] In an exemplary embodiment, the multiple conductive layers may include at least a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence on the substrate in a direction away from the substrate, the fifth gate electrode and the sixth gate electrode may be arranged in the first conductive layer, the light-emitting signal line 93 may be arranged in the third conductive layer, and the light-emitting signal connection line 56 may be arranged in the fourth conductive layer.

[0233] In an exemplary embodiment, the light-emitting signal line 93 can be connected to the sixth gate electrode through a via, and the shape of the light-emitting signal connection line 56 can be a strip shape extending along the second direction Y. The first end of the light-emitting signal connection line 56 is connected to the light-emitting signal line 93 in the current unit row through a via, and the second end of the light-emitting signal connection line 56 extends from the current unit row to the next unit row, and is connected to the fifth gate electrode in the next unit row through a via.

[0234] In an exemplary embodiment, the multiple conductive layers may further include a fifth conductive layer disposed on a side of the fourth conductive layer away from the substrate, and the first power line 61 may be disposed in the fifth conductive layer, and the orthographic projection of the first power line 61 on the display substrate plane at least partially overlaps with the orthographic projection of the light-emitting signal connection line 56 on the display substrate plane.

[0235] In an exemplary embodiment, at least one circuit unit may include a first initial signal line 31 extending along a first direction X and a first connection line 81 extending along a second direction Y, wherein the first connection line 81 is connected to the first initial signal line 31 to form a mesh connection structure on the display substrate for transmitting the first initial signal.

[0236] In an exemplary embodiment, at least one circuit unit may include a second initial signal line 32 extending along the first direction X and a second connection line 82 extending along the second direction Y, wherein the second connection line 82 is connected to the second initial signal line 32 to form a mesh connection structure on the display substrate for transmitting the second initial signal.

[0237] In an exemplary embodiment, at least one circuit unit may include a third connection line 83 extending along the first direction X and a second power line 64 extending along the second direction Y, and the third connection line 83 is connected to the second power line 64 to form a mesh connection structure for transmitting the second power signal on the display substrate.

[0238] In an exemplary embodiment, taking eight circuit units (two unit rows and four unit columns) as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0239] (21) A semiconductor layer pattern is formed. The process of forming the semiconductor layer pattern and the structure of the semiconductor layer are basically the same as those shown in FIG6 . The semiconductor layer may include a first active layer 11 to a seventh active layer 17 . The difference is that the first active layer 11 to the seventh active layer 17 are an integrated structure connected to each other, and the semiconductor layer also includes a third plate 73 of the first capacitor, as shown in FIG18 .

[0240] In an exemplary embodiment, the second region 13-2 of the third active layer can simultaneously serve as the second region 12-2 of the second active layer and the first region 16-1 of the sixth active layer, that is, the second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer are interconnected. Unlike the example of FIG6 in which there is no connection between the second active layer and the third active layer, in this embodiment, the second region 12-2 of the second active layer and the second region 13-2 of the third active layer are connected via an active connection line 18. That is, one end of the active connection line 18 is connected to the second region 12-2 of the second active layer 12, and the other end of the active connection line 18 is connected to the second region 13-2 of the third active layer 13. The second active layer 12, the third active layer 13, and the active connection line 18 form an integrated structure that is interconnected.

[0241] In an exemplary embodiment, the third electrode plate 73 may be block-shaped (e.g., rectangular) and may be disposed on a side of the third active layer 13 of the circuit unit that is away from the (N+1)th cell column. The third electrode plate 73 is respectively connected to the first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer. In an exemplary embodiment, the third electrode plate 73 may serve as one plate of the first capacitor.

[0242] (22) A first conductive layer pattern is formed. The process of forming the first conductive layer pattern and the structure of the first conductive layer are substantially the same as those shown in FIG. 7A and FIG. 7B , except that the first conductive layer is provided with a fifth gate electrode 25 and no light-emitting signal line is provided, as shown in FIG. 19A and FIG. 19B . FIG. 19B is a plan view schematically illustrating the first conductive layer in FIG. 19A .

[0243] In an exemplary embodiment, the first conductive layer pattern in each circuit unit may include a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a fifth gate electrode 25, a sixth gate electrode 26 and a first plate 71 of a storage capacitor, and the structures of the first scan signal line 21 to the third scan signal line 23, the sixth gate electrode 26 and the first plate 71 are substantially the same as those in the aforementioned embodiment.

[0244] In an exemplary embodiment, the fifth gate electrode 25 may be in the shape of a strip extending along the first direction X. The fifth gate electrode 25 may be located between the first scan signal line 21 and the first electrode plate 71. The region where the fifth gate electrode 25 overlaps with the fifth active layer may serve as the gate electrode of the fifth transistor T5. In an exemplary embodiment, the fifth gate electrode 25 is configured to be connected to a subsequently formed light emitting signal connection line, and the sixth gate electrode 26 is configured to be connected to a subsequently formed light emitting signal line.

[0245] In an exemplary embodiment, an orthographic projection of the first electrode plate 71 on the substrate does not overlap with an orthographic projection of the third electrode plate 73 on the substrate.

[0246] (23) A second conductive layer pattern is formed. The process of forming the second conductive layer pattern and the structure of the second conductive layer are basically the same as those shown in Figures 8A and 8B. The difference is that the second conductive layer is also provided with a fourth electrode 74 of the first capacitor, as shown in Figures 20A and 20B. Figure 20B is a planar schematic diagram of the second conductive layer in Figure 20A.

[0247] In an exemplary embodiment, the second conductive layer pattern of each circuit unit may include at least a second initial signal line 32, a second plate 72 of a storage capacitor, and a fourth plate 74 of a first capacitor, and the structures of the second initial signal line 32 and the second plate 72 are substantially the same as those in the aforementioned embodiment.

[0248] In an exemplary embodiment, the shape of the fourth plate 74 can be rectangular, and the corners of the rectangle can be chamfered. The fourth plate 74 can be set on the side of the second plate 72 of this circuit unit away from the N+1th unit column. The positive projection of the fourth plate 74 on the substrate at least partially overlaps with the positive projection of the third plate 73 on the substrate. The fourth plate 74 can serve as another plate of the first capacitor, and the third plate 73 and the fourth plate 74 constitute the first capacitor of the pixel driving circuit.

[0249] In an exemplary embodiment, the second electrode plate 72 and the fourth electrode plate 74 of each circuit unit may be an integral structure connected to each other.

[0250] (24) A fourth insulating layer pattern is formed. The process of forming the fourth insulating layer pattern and the structure of the multiple vias are basically the same as those shown in FIG9 , except that the multiple vias also include a thirteenth via V13 , but do not include the third via and the fourth via, as shown in FIG21 .

[0251] In an exemplary embodiment, the plurality of vias in each circuit unit may include at least a first via V1, a second via V2, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, and a thirteenth via V13.

[0252] The positions and connection structures of the first through hole V1 to the second through hole V2 and the fifth through hole V5 to the twelfth through hole V12 are substantially the same as those in the aforementioned embodiment.

[0253] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the fifth gate electrode 25 on the substrate, the fourth insulating layer and the third insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the fifth gate electrode 25, and the thirteenth via hole V13 is configured to connect the subsequently formed ninth connecting electrode to the fifth gate electrode 25 through the via hole.

[0254] (25) A third conductive layer pattern is formed. The process of forming the third conductive layer and the structure of the third conductive layer are basically the same as those shown in Figures 10A and 10B. The difference is that the third conductive layer is also provided with a ninth connecting electrode 49, and no fifth connecting electrode is provided, as shown in Figures 22A and 22B. Figure 22B is a planar schematic diagram of the third conductive layer in Figure 22A.

[0255] In an exemplary embodiment, the third conductive layer in each circuit unit may include at least: a first initial signal line 31, a light-emitting signal line 93, a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a sixth connecting electrode 46, a seventh connecting electrode 47, an eighth connecting electrode 48 and a ninth connecting electrode 49, and the structures of the first initial signal line 31, the first connecting electrode 41 to the fourth connecting electrode 44, and the sixth connecting electrode 46 to the eighth connecting electrode 48 are substantially the same as those in the aforementioned embodiments.

[0256] In an exemplary embodiment, the shape of the light-emitting signal line 93 can be a straight line or a broken line extending along the first direction X. The light-emitting signal line 93 can be located between the third scanning signal line 23 and the second electrode 72. The light-emitting signal line 93 can be connected to the sixth gate electrode 26 of each circuit unit through the twelfth via V12 of each circuit unit, so that the light-emitting signal line 93 can control the conduction and disconnection of the sixth transistor T6.

[0257] In an exemplary embodiment, a light-emitting connection block 93-1 may also be provided on the side of the light-emitting signal line 93 away from the second electrode plate 72. The shape of the light-emitting connection block 93-1 may be a block shape (such as a rectangle). The first end of the light-emitting connection block 93-1 is connected to the light-emitting signal line 93, and the second end of the light-emitting connection block 93-1 extends in a direction away from the second electrode plate 72. The light-emitting connection block 93-1 is configured to be connected to a light-emitting signal connection line formed subsequently.

[0258] In an exemplary embodiment, an orthographic projection of the first connection electrode 41 on the substrate at least partially overlaps with an orthographic projection of the first scan signal line 21 on the substrate.

[0259] In an exemplary embodiment, the first power connection block 42-1 can be set at the second end of the second connection electrode 42, and the shape of the first power connection block 42-1 can be block-shaped (such as rectangular), and the positive projection of the first power connection block 42-1 on the substrate can be located within the range of the positive projection of the second electrode plate 72 on the substrate. The first power connection block 42-1 is configured to be connected to the first power line formed subsequently.

[0260] In an exemplary embodiment, a preliminary connection block 46 - 1 may be provided in a circuit cell of an N-th cell column, the preliminary connection block 46 - 1 being configured to be connected to a second connection line formed subsequently.

[0261] In an exemplary embodiment, the shape of the ninth connection electrode 49 can be a block shape (such as a rectangle), and the ninth connection electrode 49 can be arranged between the first initial signal line 31 and the second electrode 72. The ninth connection electrode 49 is connected to the fifth gate electrode 25 through the thirteenth via V13, and the ninth connection electrode 49 is configured to be connected to the subsequently formed light-emitting signal connection line.

[0262] (26) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the third conductive layer, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 23 .

[0263] In an exemplary embodiment, the plurality of via holes on the first planar layer include at least a twenty-first via hole V21 , a twenty-second via hole V22 , a twenty-third via hole V23 , a twenty-fourth via hole V24 , a twenty-fifth via hole V25 , a twenty-sixth via hole V26 , and a twenty-seventh via hole V27 .

[0264] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the first power connection block 42-1 on the substrate. The first flat layer within the twenty-first via hole V21 is removed, exposing the surface of the first power connection block 42-1. The twenty-first via hole V21 is configured to connect a subsequently formed eleventh connection electrode to the first power connection block 42-1 through the via hole. In an exemplary embodiment, the twenty-first via hole V21 can be provided in each circuit unit.

[0265] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate may be located within the range of the orthographic projection of the second electrode plate 72 on the substrate.

[0266] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is within the range of the orthographic projection of the third connection electrode 43 on the substrate. The first planar layer within the twenty-second via hole V22 is removed, exposing the surface of the third connection electrode 43. The twenty-second via hole V22 is configured to connect a subsequently formed twelfth connection electrode to the third connection electrode 43 through the via hole. In an exemplary embodiment, the twenty-second via hole V22 may be provided in each circuit unit.

[0267] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is within the range of the orthographic projection of the fourth connection electrode 44 on the substrate. The first planar layer within the twenty-third via hole V23 is removed, exposing the surface of the fourth connection electrode 44. The twenty-third via hole V23 is configured to connect a subsequently formed thirteenth connection electrode to the fourth connection electrode 44 through the via hole. In an exemplary embodiment, the twenty-third via hole V23 may be provided in each circuit unit.

[0268] In an exemplary embodiment, the orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the eighth connection electrode 48 on the substrate. The first planar layer within the twenty-fourth via hole V24 is removed, exposing the surface of the eighth connection electrode 48. The twenty-fourth via hole V24 is configured to connect a subsequently formed fourteenth connection electrode to the eighth connection electrode 48 through the via hole. In an exemplary embodiment, the twenty-fourth via hole V24 may be provided in each circuit unit.

[0269] In an exemplary embodiment, the orthographic projection of the twenty-fifth via hole V25 on the substrate is within the range of the orthographic projection of the initial connection block 46-1 on the substrate. The first flat layer within the twenty-fifth via hole V25 is removed, exposing the surface of the initial connection block 46-1. The twenty-fifth via hole V25 is configured to connect a subsequently formed fifteenth connection electrode to the initial connection block 46-1 through the via hole. In an exemplary embodiment, the twenty-fifth via hole V25 may be provided in a circuit unit of the Nth unit column.

[0270] In an exemplary embodiment, the orthographic projection of the twenty-sixth via hole V26 on the substrate is located within the range of the orthographic projection of the light-emitting connection block 93-1 of the light-emitting signal line 93 on the substrate. The first flat layer within the twenty-sixth via hole V26 is removed, exposing the surface of the light-emitting connection block 93-1. The twenty-sixth via hole V26 is configured to connect a subsequently formed light-emitting signal connection line to the light-emitting connection block 93-1 through the via hole. In an exemplary embodiment, the twenty-sixth via hole V26 can be provided in each circuit unit.

[0271] In an exemplary embodiment, the orthographic projection of the twenty-seventh via hole V27 on the substrate is located within the range of the orthographic projection of the ninth connection electrode 49 on the substrate. The first planar layer within the twenty-seventh via hole V27 is removed, exposing the surface of the ninth connection electrode 49. The twenty-seventh via hole V27 is configured to allow a subsequently formed light-emitting signal connection line to be connected to the ninth connection electrode 49 through the via hole. In an exemplary embodiment, the twenty-seventh via hole V27 may be provided in each circuit unit.

[0272] (27) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the first flat layer, as shown in FIG. 24A and FIG. 24B , where FIG. 24B is a planar schematic diagram of the fourth conductive layer in FIG. 24A .

[0273] In an exemplary embodiment, the fourth conductive layer includes at least an eleventh connecting electrode 51 , a twelfth connecting electrode 52 , a thirteenth connecting electrode 53 , a fourteenth connecting electrode 54 , a fifteenth connecting electrode 55 , a light emitting signal connecting line 56 and a third connecting line 83 .

[0274] In an exemplary embodiment, the eleventh connection electrode 51 may be in a block shape (e.g., a rectangle). The eleventh connection electrode 51 is connected to the first power connection block 42-1 through the twenty-first via hole V21. The eleventh connection electrode 51 is configured to be connected to a first power line formed subsequently. In an exemplary embodiment, the eleventh connection electrode 51 may be provided in each circuit unit.

[0275] In an exemplary embodiment, an orthographic projection of the eleventh connecting electrode 51 on the substrate at least partially overlaps with an orthographic projection of the second electrode plate 72 on the substrate.

[0276] In an exemplary embodiment, the twelfth connection electrode 52 may be in the shape of a strip extending along the second direction Y. The twelfth connection electrode 52 is connected to the third connection electrode 43 through the 22nd via hole V22. The twelfth connection electrode 52 is configured to be connected to a subsequently formed data signal line. In an exemplary embodiment, the twelfth connection electrode 52 may be provided in each circuit unit.

[0277] In an exemplary embodiment, the thirteenth connection electrode 53 may be in the shape of a strip extending along the second direction Y. The thirteenth connection electrode 53 is connected to the fourth connection electrode 44 through the twenty-third via hole V23. The thirteenth connection electrode 53 is configured to be connected to the anode connection electrode formed later. In an exemplary embodiment, the thirteenth connection electrode 53 may be provided in each circuit unit.

[0278] In an exemplary embodiment, the shape of the fourteenth connecting electrode 54 can be a block shape (such as a rectangle) or a strip shape, and the fourteenth connecting electrode 54 is connected to the eighth connecting electrode 48 through the twenty-fourth via hole V24. In an exemplary embodiment, the fourteenth connecting electrode 54 can be provided in each circuit unit, and the fourteenth connecting electrode 54 in the circuit units of the Nth unit column, the N+1th unit column, and the N+3th unit column is a block shape (such as a rectangle). The block-shaped fourteenth connecting electrode 54 is a dummy electrode (dummy-pad) and is not connected to the fifth conductive layer formed subsequently. The dummy electrode is configured to ensure etching uniformity and uniformity between sub-pixels. The fourteenth connecting electrode 54 in the circuit unit of the N+2th unit column is a strip shape, and the fourteenth connecting electrode 54 in the N+2th unit column is configured to be connected to the first connecting line formed subsequently.

[0279] In an exemplary embodiment, the fifteenth connection electrode 55 may be block-shaped (e.g., rectangular), connected to the initial connection block 46-1 through the twenty-fifth via hole V25, and configured to be connected to a second connection line formed subsequently. In an exemplary embodiment, the fifteenth connection electrode 55 may be provided in a circuit cell of the Nth cell column.

[0280] In an exemplary embodiment, the light-emitting signal connection line 56 may be in the shape of a strip extending along the second direction Y. A first end of the light-emitting signal connection line 56 is connected to the light-emitting connection block 93-1 of the circuit unit in the current unit row through the twenty-sixth via hole V26. A second end of the light-emitting signal connection line 56 extends along the second direction Y to the circuit unit in the next unit row and is connected to the ninth connection electrode 49 of the circuit unit in the next unit row through the twenty-seventh via hole V27. In an exemplary embodiment, the light-emitting signal connection line 56 may be provided in each circuit unit.

[0281] In this exemplary embodiment, since the light-emitting connection block 93-1 of the circuit unit in the current unit row is connected to the light-emitting signal line 93 in the current unit row, and the ninth connection electrode 49 of the circuit unit in the next unit row is connected to the fifth gate electrode 25 of the circuit unit, the light-emitting signal connection line 56 connects the light-emitting signal line 93 in the current unit row to the fifth gate electrode 25 in the next unit row. Therefore, the light-emitting signal line 93 in the current unit row can control not only the conduction and disconnection of the sixth transistor T6 in the current unit row, but also the conduction and disconnection of the fifth transistor T5 in the next unit row. That is, in the circuit units of the current unit row, the fifth transistor T5 is controlled by the light-emitting signal line 93 of the previous unit row, and the sixth transistor T6 is controlled by the light-emitting signal line 93 of the current unit row. For example, the light-emitting signal line 93 in the M-1th unit row can control the conduction and disconnection of the sixth transistor T6 in the M-1th unit row, while simultaneously controlling the conduction and disconnection of the fifth transistor T5 in the Mth unit row. For another example, the light-emitting signal line 93 in the Mth unit row can control the on / off of the sixth transistor T6 in the Mth unit row, and simultaneously control the on / off of the fifth transistor T5 in the M+1th unit row. That is, in the circuit unit of the Mth unit row, the fifth transistor T5 is controlled by the light-emitting signal line 93 in the M-1th unit row, and the sixth transistor T6 is controlled by the light-emitting signal line 93 in the Mth unit row. For another example, the light-emitting signal line 93 in the M+1th unit row can control the on / off of the sixth transistor T6 in the M+1th unit row, and simultaneously control the on / off of the fifth transistor T5 in the M+2th unit row.

[0282] In an exemplary embodiment, the shape of the third connection line 83 can be a straight line or a broken line extending along the first direction X, the third connection line 83 can be located between the first scan signal line 21 and the second electrode 72, and the third connection line 83 is configured to be connected to the second power line formed subsequently.

[0283] In an exemplary embodiment, a second power connection block 83-1 is connected to a side of the third connection line 83 near the first scan signal line 21. The second power connection block 83-1 may be block-shaped (e.g., rectangular) and configured to connect to a second power line formed later. In an exemplary embodiment, the second power connection block 83-1 may be provided in the circuit cells of the (N+1)th unit column and the (N+3)th unit column.

[0284] In an exemplary embodiment, the orthographic projection of the third connection line 83 on the substrate does not overlap with the orthographic projection of the second electrode 72 on the substrate, and the orthographic projection of the third connection line 83 on the substrate at least partially overlaps with the orthographic projections of the first connection electrode 41 and the second connection electrode 42 on the substrate.

[0285] (28) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fourth conductive layer, wherein a plurality of vias are provided on the second planar layer, as shown in FIG. 25 .

[0286] In an exemplary embodiment, the plurality of via holes on the second planar layer include at least a thirty-first via hole V31 , a thirty-second via hole V32 , a thirty-third via hole V33 , a thirty-fourth via hole V34 , a thirty-fifth via hole V35 , and a thirty-sixth via hole V36 .

[0287] In an exemplary embodiment, the orthographic projection of the thirty-first via hole V31 on the substrate is within the range of the orthographic projection of the eleventh connection electrode 51 on the substrate. The second planar layer within the thirty-first via hole V31 is removed, exposing the surface of the thirty-first via hole V31. The thirty-first via hole V31 is configured to connect a subsequently formed first power line to the eleventh connection electrode 51 through the via hole. In an exemplary embodiment, the thirty-first via hole V31 may be provided in each circuit unit.

[0288] In an exemplary embodiment, the orthographic projection of the thirty-second via hole V32 on the substrate is located within the range of the orthographic projection of the twelfth connection electrode 52 on the substrate. The second planar layer within the thirty-second via hole V32 is removed, exposing the surface of the twelfth connection electrode 52. The thirty-second via hole V32 is configured to allow a subsequently formed data signal line to be connected to the twelfth connection electrode 52 through the via hole. In an exemplary embodiment, the thirty-second via hole V32 may be provided in each circuit unit.

[0289] In an exemplary embodiment, the orthographic projection of the thirty-third via hole V33 on the substrate is located within the range of the orthographic projection of the thirteenth connecting electrode 53 on the substrate. The second planar layer within the thirty-third via hole V33 is removed, exposing the surface of the thirteenth connecting electrode 53. The thirty-third via hole V33 is configured to connect a subsequently formed anode connecting electrode to the thirteenth connecting electrode 53 through the via hole. In an exemplary embodiment, the thirty-third via hole V33 may be provided in each circuit unit.

[0290] In an exemplary embodiment, the orthographic projection of the thirty-fourth via hole V34 on the substrate is located within the range of the orthographic projection of the fourteenth connecting electrode 54 on the substrate. The second planar layer within the thirty-fourth via hole V34 is removed, exposing the surface of the fourteenth connecting electrode 54. The thirty-fourth via hole V34 is configured to allow a subsequently formed first connecting wire to be connected to the fourteenth connecting electrode 54 through the via hole. In an exemplary embodiment, the thirty-fourth via hole V34 may be provided in the circuit unit of the (N+2)th unit column.

[0291] In an exemplary embodiment, the orthographic projection of the thirty-fifth via hole V35 on the substrate is within the range of the orthographic projection of the fifteenth connecting electrode 55 on the substrate. The second planar layer within the thirty-fifth via hole V35 is removed, exposing the surface of the fifteenth connecting electrode 55. The thirty-fifth via hole V35 is configured to allow a subsequently formed second connecting wire to be connected to the fifteenth connecting electrode 55 through the via hole. In an exemplary embodiment, the thirty-fifth via hole V35 may be provided in a circuit cell in the Nth cell column.

[0292] In an exemplary embodiment, the orthographic projection of the thirty-sixth via V36 on the substrate is located within the range of the orthographic projection of the second power connection block 83-1 of the third connection line 83 on the substrate. The second planar layer within the thirty-sixth via V36 is removed, exposing the surface of the second power connection block 83-1. The thirty-sixth via V36 is configured to connect a subsequently formed second power line to the second power connection block 83-1 through the via. In an exemplary embodiment, the thirty-sixth via V36 can be provided in the circuit cells of the (N+1)th unit column and the (N+3)th unit column.

[0293] (29) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the second flat layer, as shown in FIG. 26A and FIG. 26B , where FIG. 26B is a plan view schematic diagram of the fifth conductive layer in FIG. 26A . In an exemplary embodiment, the fifth conductive layer may be referred to as a third source / drain metal (SD3) layer.

[0294] In an exemplary embodiment, the fifth conductive layer may include at least a first power line 61 , a data signal line 62 , an anode connection electrode 63 , a second power line 64 , a first connection line 81 , and a second connection line 82 .

[0295] In an exemplary embodiment, the first power line 61 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The first power line 61 is connected to the eleventh connection electrode 51 through the thirty-first via V31. Since the eleventh connection electrode 51 is connected to the first power connection block 42-1, the first power connection block 42-1 is connected to the second connection electrode 42, and the second connection electrode 42 is connected to the first electrode of the fifth transistor T5, the second plate 72 of the storage capacitor, and the fourth plate 74 of the first capacitor, the first power line 61 can write the first power signal to the first electrode of the fifth transistor T5, the second plate 72 of the storage capacitor, and the fourth plate 74 of the first capacitor. In an exemplary embodiment, the first power line 61 can be provided in each circuit unit.

[0296] In an exemplary embodiment, the orthographic projection of the first power line 61 on the substrate at least partially overlaps with the orthographic projection of the luminous signal connection line 56 on the substrate. The first power line 61 with a constant voltage can act as a shield, reduce the impact of the luminous signal on the pixel driving circuit, and stabilize the potential of the luminous signal.

[0297] In an exemplary embodiment, the data signal line 62 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The data signal line 62 is connected to the twelfth connection electrode 52 through the thirty-second via hole V32. Since the twelfth connection electrode 52 is connected to the third connection electrode 43, and the third connection electrode 43 is connected to the first region of the fourth active layer, the data signal line 62 is connected to the first electrode of the fourth transistor T4. The data signal line 62 can write a data signal to the first electrode of the fourth transistor T4. In an exemplary embodiment, the data signal line 62 can be provided in each circuit unit.

[0298] In an exemplary embodiment, the anode connection electrode 63 may be in the shape of a strip extending along the first direction X or along the second direction Y. The anode connection electrode 63 is connected to the thirteenth connection electrode 53 via the thirty-third via hole V33. The anode connection electrode 63 is configured to be connected to a subsequently formed anode. Since the thirteenth connection electrode 53 is connected to the fourth connection electrode 44, and the fourth connection electrode 44 is connected to the second region of the sixth active layer and the second region of the seventh active layer, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting device to emit light. In an exemplary embodiment, the anode connection electrode 63 may be provided in each circuit unit.

[0299] In an exemplary embodiment, the second power line 64 can be shaped as a straight line or a broken line extending along the second direction Y. The second power line 64 is connected to the second power connection block 83-1 via the thirty-sixth via V36. Since the second power connection block 83-1 is connected to the third connection line 83, the third connection line 83 extending along the first direction X of the main body is interconnected with the second power line 64 extending along the second direction Y of the main body, forming a mesh-like interconnected structure on the display substrate. The present disclosure forms a mesh-like interconnected structure by forming the second power line 64 and the third connection line 83, which not only effectively reduces the resistance of the second power line and reduces the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, effectively improving display uniformity and enhancing display quality. In an exemplary embodiment, the second power line 64 can be provided in the circuit units of the N+1th unit column and the N+3th unit column.

[0300] In an exemplary embodiment, the shape of the first connection line 81 can be a straight line or a broken line extending along the second direction Y, and the first connection line 81 is connected to the fourteenth connection electrode 54 through the thirty-fourth via V34. Since the fourteenth connection electrode 54 is connected to the eighth connection electrode 48, and the eighth connection electrode 48 is connected to the first initial signal line 31, the first initial signal line 31 extending along the first direction X of the main part and the first connection line 81 extending along the second direction Y of the main part are connected to each other, forming a mesh connection structure on the display substrate. The present disclosure forms a mesh connection structure by forming a mesh connection structure with the first initial signal line 31 and the first connection line 81, which can not only effectively reduce the resistance of the initial signal line and reduce the voltage drop of the first initial signal, but also effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality. In an exemplary embodiment, the first connection line 81 can be arranged in the circuit unit of the N+2th unit column.

[0301] In an exemplary embodiment, the shape of the second connection line 82 can be a straight line or a broken line extending along the second direction Y, and the second connection line 82 is connected to the fifteenth connection electrode 55 through the thirty-fifth via V35. Since the fifteenth connection electrode 55 is connected to the initial connection block 46-1, the initial connection block 46-1 is connected to the sixth connection electrode 46, and the sixth connection electrode 46 is connected to the second initial signal line 32, the second initial signal line 32 extending along the first direction X of the main part and the second connection line 82 extending along the second direction Y of the main part are connected to each other, forming a mesh-like interconnected structure on the display substrate. The present disclosure forms a mesh-like interconnected structure by forming a mesh-like interconnected structure with the second initial signal line 32 and the second connection line 82, which can not only effectively reduce the resistance of the initial signal line and reduce the voltage drop of the second initial signal, but also effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality. In an exemplary embodiment, the second connection line 82 can be set in the circuit unit of the Nth unit column.

[0302] Figure 26C is a schematic diagram of an initial signal mesh connectivity structure and a second power mesh connectivity structure according to an exemplary embodiment of the present disclosure. As shown in Figure 26C, a second power connection block 83-1 may be provided on the third connection line 83, and the second power line 64 is connected to the second power connection block 83-1 via a via. This interconnection between the third connection line 83 extending in the main body along the first direction X and the second power line 64 extending in the main body along the second direction Y is achieved, forming a second power mesh connectivity structure on the display substrate. The first connection line 81 is connected to the fourteenth connection electrode 54 via a via, and the fourteenth connection electrode 54 is connected to the eighth connection electrode 48 via a via. The eighth connection electrode 48 is connected to the first initial signal line 31, thus interconnecting the first initial signal line 31 extending in the main body along the first direction X and the first connection line 81 extending in the main body along the second direction Y, forming a first initial signal mesh connectivity structure on the display substrate. The second connection line 82 is connected to the fifteenth connection electrode 55 through a via, the fifteenth connection electrode 55 is connected to the initial connection block 46-1 through a via, and the initial connection block 46-1 is connected to the second initial signal line 32, thereby realizing the mutual connection between the second initial signal line 32 extending along the first direction X of the main part and the second connection line 82 extending along the second direction Y of the main part, forming a second initial signal network connection structure on the display substrate.

[0303] In an exemplary embodiment, the second initial signal line 32 can be set in the second conductive layer, the first initial signal line 31, the initial connection block 46-1 and the eighth connection electrode 48 can be set in the third conductive layer, the fourteenth connection electrode 54, the fifteenth connection electrode 55 and the third connection line 83 can be set in the fourth conductive layer, and the second power line 64, the first connection line 81 and the second connection line 82 can be set in the fifth conductive layer.

[0304] In an exemplary embodiment, the first initial signal line 31, the second initial signal line 32 and the third connection line 83 can be arranged in each unit row, and the first connection line 81, the second power line 64, the second connection line 82 and the second power line 64 can be alternately arranged in the unit column, and one first connection line 81, one second connection line 82 and two second power lines 64 are respectively arranged in the four unit columns. The first connection line 81, the second connection line 82 and the second power line 64 are arranged in different unit columns, which can make full use of the layout space, avoid affecting the light transmittance, and improve the display effect.

[0305] In an exemplary embodiment, the Nth cell column may be provided with a second connection line 82 , the N+1th cell column may be provided with a second power line 64 , the N+2th cell column may be provided with a first connection line 81 , and the N+3th cell column may be provided with a second power line 64 .

[0306] (30) Forming a third flat layer pattern. In an exemplary embodiment, forming the third flat layer pattern may include: coating a third flat film on the substrate on which the aforementioned pattern is formed, patterning the third flat film using a patterning process to form a third flat layer covering the fifth conductive layer, wherein a plurality of anode vias are provided on the third flat layer, and the anode vias are configured to connect a subsequently formed anode to the anode connection electrode through the vias.

[0307] At this point, the drive circuit layer is completed on the substrate. In a plane parallel to the display substrate, the drive circuit layer may include multiple circuit units, each of which may include a pixel drive circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a light-emitting signal line, a data signal line, a first power line, a first initial signal line, and a second initial signal line connected to the pixel drive circuit. The light-emitting signal line is respectively connected to the sixth transistor T6 in the current unit row and the fifth gate electrode 25 in the next unit row. In a plane perpendicular to the display substrate, the drive circuit layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planar layer, a fourth conductive layer, a second planar layer, a fifth conductive layer, and a third planar layer stacked sequentially on the substrate.

[0308] In an exemplary embodiment, after the driver circuit layer is prepared, a light-emitting structure layer is first prepared on the driver circuit layer, and then an encapsulation structure layer is formed. The light-emitting structure layer may include an anode conductive layer, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode conductive layer may include multiple anodes, the pixel definition layer may include multiple pixel openings, and the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer.

[0309] The display substrate provided in this embodiment also implements separate control of the fifth and sixth transistors, enabling ultra-high frequency, higher-precision pulse width modulation, light signal duty cycle compensation, low grayscale compensation, and improved image retention. In at least one circuit unit of this embodiment, the sixth transistor T6 is controlled by the light signal line of its own unit row, while the fifth transistor T5 is controlled by the light signal line of the previous unit row. That is, the fifth transistor T5 is driven (cascaded) by the light signal line of the previous-stage sixth transistor T6. This not only reduces the capacitance at the output of the first node N1, preventing the first node N1 from being affected by the light signal line, but also reduces the number of light signal lines, facilitating high resolution.

[0310] This embodiment shows that the substrate is provided with a fifth gate electrode and a sixth gate electrode in the first conductive layer, a light-emitting signal line is provided in the third conductive layer, the light-emitting signal line is connected to the sixth gate electrode through a via, and a light-emitting signal connection line is provided in the fourth conductive layer. The first end of the light-emitting signal connection line is connected to the light-emitting signal line in the current unit row, and the second end of the light-emitting signal connection line is connected to the fifth gate electrode in the next unit row. The cascaded light-emitting control signal is transferred using the light-emitting signal connection line located in the SD2 layer, and the first power line of the SD3 layer shields the light-emitting signal connection line, thereby effectively stabilizing the potential of the light-emitting signal.

[0311] The display substrate disclosed herein forms a mesh-like interconnected structure by providing a third connecting line extending in a first direction from the main portion and a second power line extending in a second direction from the main portion. This not only effectively reduces the resistance of the second power line and reduces the voltage drop of the second power supply voltage, but also effectively improves the uniformity of the second power supply voltage in the display substrate, effectively improves the display uniformity, and improves the display quality and display quality.

[0312] The display substrate disclosed herein adopts a 3SD mode and adds a first capacitor, forming a mesh connection structure of the second power supply signal, a mesh connection structure of the first initial signal, and a mesh connection structure of the second initial signal on the display substrate, further improving the display effect.

[0313] FIG27 is a schematic diagram of another display substrate according to an exemplary embodiment of the present disclosure, illustrating a planar structure of eight circuit units (two unit rows and four unit columns). In this exemplary embodiment, the main structure of the display substrate of this embodiment is substantially the same as that shown in FIG17 , except that this embodiment employs a 2SD structure.

[0314] In an exemplary embodiment, the multiple conductive layers may include at least a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence on the substrate in a direction away from the substrate, the fifth gate electrode and the sixth gate electrode may be arranged in the first conductive layer, the third connecting line 83 and the light-emitting signal line 93 may be arranged in the third conductive layer, and the light-emitting signal connecting line 56, the first power line 61, the data signal line 62, the second power line 64, the first connecting line 81 and the second connecting line 82 may be arranged in the fourth conductive layer.

[0315] In an exemplary embodiment, taking eight circuit units (two unit rows and four unit columns) as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0316] (31) A semiconductor layer pattern is formed. The process of forming the semiconductor layer pattern and the structure of the semiconductor layer are basically the same as those shown in FIG. 18 .

[0317] (32) A first conductive layer pattern is formed. The process of forming the first conductive layer pattern and the structure of the first conductive layer are substantially the same as those shown in FIG. 19A and FIG. 19B .

[0318] (33) A second conductive layer pattern is formed. The process of forming the second conductive layer pattern and the structure of the second conductive layer are substantially the same as those shown in FIG. 20A and FIG. 20B .

[0319] (34) A fourth insulating layer pattern is formed. The process of forming the fourth insulating layer pattern and the structure of the plurality of via holes are substantially the same as those shown in FIG. 21 .

[0320] (35) A third conductive layer pattern is formed. The process of forming the third conductive layer and the structure of the third conductive layer are basically the same as those shown in Figures 22A and 22B. The difference is that the third conductive layer is also provided with a third connecting line 83, as shown in Figures 28A and 28B. Figure 28B is a planar schematic diagram of the third conductive layer in Figure 28A.

[0321] In an exemplary embodiment, the third conductive layer in each circuit unit may include at least: a first initial signal line 31, a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a sixth connecting electrode 46, a seventh connecting electrode 47, an eighth connecting electrode 48, a ninth connecting electrode 49, a third connecting line 83 and a light-emitting signal line 93, and the structures of the first initial signal line 31, the light-emitting signal line 93, the first connecting electrode 41 to the fourth connecting electrode 44, and the sixth connecting electrode 46 to the ninth connecting electrode 49 are substantially the same as those in the aforementioned embodiments.

[0322] In an exemplary embodiment, the shape of the third connection line 83 can be a straight line or a broken line extending along the first direction X, the third connection line 83 can be located between the first scanning signal line 21 and the light emitting signal line 93, and the third connection line 83 is configured to be connected to the second power line formed subsequently.

[0323] In an exemplary embodiment, a second power connection block 83-1 is connected to a side of the third connection line 83 near the first scan signal line 21. The second power connection block 83-1 may be block-shaped (e.g., rectangular) and configured to connect to a second power line formed later. In an exemplary embodiment, the second power connection block 83-1 may be provided in the circuit cells of the (N+1)th unit column and the (N+3)th unit column.

[0324] In an exemplary embodiment, the orthographic projection of the third connection line 83 on the substrate at least partially overlaps with the orthographic projection of the second electrode 72 on the substrate, and the orthographic projection of the third connection line 83 on the substrate does not overlap with the orthographic projection of the first connection electrode 41 and the second connection electrode 42 on the substrate.

[0325] (36) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the third conductive layer, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 29 .

[0326] In an exemplary embodiment, the plurality of vias on the first planar layer include at least a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, a twenty-fourth via V24, a twenty-fifth via V25, a twenty-sixth via V26, a twenty-seventh via V27, and a twenty-eighth via V28.

[0327] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the first power connection block 42-1 on the substrate. The first flat layer within the twenty-first via V21 is removed, exposing the surface of the first power connection block 42-1. The twenty-first via V21 is configured to allow a subsequently formed first power line to be connected to the first power connection block 42-1 through the via. In an exemplary embodiment, the twenty-first via V21 can be provided in each circuit unit.

[0328] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate may be located within the range of the orthographic projection of the second electrode plate 72 on the substrate.

[0329] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the third connection electrode 43 on the substrate. The first planar layer within the twenty-second via hole V22 is removed, exposing the surface of the third connection electrode 43. The twenty-second via hole V22 is configured to connect a subsequently formed data signal line to the third connection electrode 43 through the via hole. In an exemplary embodiment, the twenty-second via hole V22 may be provided in each circuit unit.

[0330] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the fourth connection electrode 44 on the substrate. The first planar layer within the twenty-third via hole V23 is removed, exposing the surface of the fourth connection electrode 44. The twenty-third via hole V23 is configured to connect a subsequently formed anode connection electrode to the fourth connection electrode 44 through the via hole. In an exemplary embodiment, the twenty-third via hole V23 may be provided in each circuit unit.

[0331] In an exemplary embodiment, the orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the eighth connection electrode 48 on the substrate. The first planar layer within the twenty-fourth via hole V24 is removed, exposing the surface of the eighth connection electrode 48. The twenty-fourth via hole V24 is configured to allow a subsequently formed first connection line to be connected to the eighth connection electrode 48 through the via hole. In an exemplary embodiment, the twenty-fourth via hole V24 may be provided in the circuit unit of the (N+2)th unit column.

[0332] In an exemplary embodiment, the orthographic projection of the twenty-fifth via hole V25 on the substrate is within the range of the orthographic projection of the initial connection block 46-1 on the substrate. The first flat layer within the twenty-fifth via hole V25 is removed, exposing the surface of the initial connection block 46-1. The twenty-fifth via hole V25 is configured to allow a subsequently formed second connection line to be connected to the initial connection block 46-1 through the via hole. In an exemplary embodiment, the twenty-fifth via hole V25 may be provided in a circuit unit of the Nth unit column.

[0333] In an exemplary embodiment, the orthographic projection of the twenty-sixth via hole V26 on the substrate is located within the range of the orthographic projection of the light-emitting connection block 93-1 of the light-emitting signal line 93 on the substrate. The first flat layer within the twenty-sixth via hole V26 is removed, exposing the surface of the light-emitting connection block 93-1. The twenty-sixth via hole V26 is configured to connect a subsequently formed light-emitting signal connection line to the light-emitting connection block 93-1 through the via hole. In an exemplary embodiment, the twenty-sixth via hole V26 can be provided in each circuit unit.

[0334] In an exemplary embodiment, the orthographic projection of the twenty-seventh via hole V27 on the substrate is located within the range of the orthographic projection of the ninth connection electrode 49 on the substrate. The first planar layer within the twenty-seventh via hole V27 is removed, exposing the surface of the ninth connection electrode 49. The twenty-seventh via hole V27 is configured to allow a subsequently formed light-emitting signal connection line to be connected to the ninth connection electrode 49 through the via hole. In an exemplary embodiment, the twenty-seventh via hole V27 may be provided in each circuit unit.

[0335] In an exemplary embodiment, the orthographic projection of the twenty-eighth via V28 on the substrate is located within the range of the orthographic projection of the second power connection block 83-1 of the third connection line 83 on the substrate. The first flat layer within the twenty-eighth via V28 is removed, exposing the surface of the second power connection block 83-1. The twenty-eighth via V28 is configured to connect a subsequently formed second power line to the second power connection block 83-1 through the via. In an exemplary embodiment, the twenty-eighth via V28 can be provided in the circuit cells of the (N+1)th unit column and the (N+3)th unit column.

[0336] (37) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the first flat layer, as shown in FIG30A and FIG30B , where FIG30B is a planar schematic diagram of the fourth conductive layer in FIG30A .

[0337] In an exemplary embodiment, the fourth conductive layer includes at least a light emitting signal connection line 56 , a first power line 61 , a data signal line 62 , an anode connection electrode 63 , a second power line 64 , a first connection line 81 , and a second connection line 82 .

[0338] In an exemplary embodiment, the light-emitting signal connection line 56 may be in the shape of a strip extending along the second direction Y. A first end of the light-emitting signal connection line 56 is connected to the light-emitting connection block 93-1 of the circuit unit in the current unit row through the twenty-sixth via hole V26. A second end of the light-emitting signal connection line 56 extends along the second direction Y to the circuit unit in the next unit row and is connected to the ninth connection electrode 49 of the circuit unit in the next unit row through the twenty-seventh via hole V27. In an exemplary embodiment, the light-emitting signal connection line 56 may be provided in each circuit unit.

[0339] In an exemplary embodiment, since the light-emitting connection block 93-1 of the circuit unit in the current unit row is connected to the light-emitting signal line 93 in the current unit row, and the ninth connection electrode 49 of the circuit unit in the next unit row is connected to the fifth gate electrode 25 of the circuit unit, the light-emitting signal connection line 56 realizes the connection between the light-emitting signal line 93 in the current unit row and the fifth gate electrode 25 in the next unit row. The light-emitting signal line 93 in the current unit row can not only control the conduction and disconnection of the sixth transistor T6 in the current unit row, but also control the conduction and disconnection of the fifth transistor T5 in the next unit row, that is, in the circuit unit of the current unit row, the fifth transistor T5 is controlled by the light-emitting signal line 93 of the previous unit row, and the sixth transistor T6 is controlled by the light-emitting signal line 93 of the current unit row.

[0340] In an exemplary embodiment, the first power line 61 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The first power line 61 is connected to the first power connection block 42-1 via a twenty-first via hole V21. Since the first power connection block 42-1 is connected to the second connection electrode 42, and the second connection electrode 42 is connected to the first electrode of the fifth transistor T5, the second plate 72 of the storage capacitor, and the fourth plate 74 of the first capacitor, the first power line 61 can write the first power signal to the first electrode of the fifth transistor T5, the second plate 72 of the storage capacitor, and the fourth plate 74 of the first capacitor. In an exemplary embodiment, the first power line 61 may be provided in each circuit unit.

[0341] In an exemplary embodiment, the data signal line 62 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The data signal line 62 is connected to the third connection electrode 43 through the twenty-second via hole V22. Since the third connection electrode 43 is connected to the first region of the fourth active layer, the data signal line 62 is connected to the first electrode of the fourth transistor T4. The data signal line 62 can write a data signal to the first electrode of the fourth transistor T4. In an exemplary embodiment, the data signal line 62 may be provided in each circuit unit.

[0342] In an exemplary embodiment, the anode connection electrode 63 may be in the shape of a strip extending along the first direction X or the second direction Y. The anode connection electrode 63 is connected to the fourth connection electrode 44 via a twenty-third via hole V23. The anode connection electrode 63 is configured to connect to a subsequently formed anode. Since the fourth connection electrode 44 is connected to the second region of the sixth active layer and the second region of the seventh active layer, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting device to emit light. In an exemplary embodiment, the anode connection electrode 63 may be provided in each circuit unit.

[0343] In an exemplary embodiment, the second power line 64 may be in the form of a straight line or a zigzag line extending along the second direction Y. The second power line 64 is connected to the second power connection block 83-1 via the twenty-eighth via hole V28. Since the second power connection block 83-1 is connected to the third connection line 83, the third connection line 83 extending along the first direction X and the second power line 64 extending along the second direction Y are interconnected, forming a mesh-like interconnected structure on the display substrate. In an exemplary embodiment, the second power line 64 may be provided in the circuit cells of the N+1th and N+3th cell columns.

[0344] In an exemplary embodiment, an orthographic projection of the second power line 64 on the substrate does not overlap with an orthographic projection of the gate electrode (ie, the first plate) of the third transistor on the substrate.

[0345] In an exemplary embodiment, an orthographic projection of the second power supply line 64 on the substrate at least partially does not overlap with an orthographic projection of the active connection line 18 connecting the second active layer and the third active layer in the semiconductor layer on the substrate.

[0346] In an exemplary embodiment, the first connection line 81 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The first connection line 81 is connected to the eighth connection electrode 48 through the twenty-fourth via hole V24. Since the eighth connection electrode 48 is connected to the first initial signal line 31, the first initial signal line 31, whose main portion extends along the first direction X, is interconnected with the first connection line 81, whose main portion extends along the second direction Y, forming a network-like interconnected structure on the display substrate. In an exemplary embodiment, the first connection line 81 may be provided in the circuit unit of the (N+2)th unit column.

[0347] In an exemplary embodiment, an orthographic projection of the first connection line 81 on the substrate does not overlap with an orthographic projection of the gate electrode (ie, the first plate) of the third transistor on the substrate.

[0348] In an exemplary embodiment, an orthographic projection of the first connection line 81 on the substrate at least partially does not overlap with an orthographic projection of the active connection line 18 connecting the second active layer and the third active layer in the semiconductor layer on the substrate.

[0349] In an exemplary embodiment, the second connection line 82 may be in the form of a straight line or a zigzag line extending along the second direction Y. The second connection line 82 is connected to the initial connection block 46-1 via the twenty-fifth via hole V25. Because the initial connection block 46-1 is connected to the sixth connection electrode 46, and the sixth connection electrode 46 is connected to the second initial signal line 32, the second initial signal line 32, whose main portion extends along the first direction X, and the second connection line 82, whose main portion extends along the second direction Y, are interconnected, forming a network-like interconnected structure on the display substrate. In an exemplary embodiment, the second connection line 82 may be provided in the circuit unit of the Nth unit column.

[0350] In an exemplary embodiment, an orthographic projection of the second connection line 82 on the substrate does not overlap with an orthographic projection of the gate electrode (ie, the first plate) of the third transistor on the substrate.

[0351] In an exemplary embodiment, an orthographic projection of the second connection line 82 on the substrate at least partially does not overlap with an orthographic projection of the active connection line 18 connecting the second active layer and the third active layer in the semiconductor layer on the substrate.

[0352] Figures 30C and 30D are schematic diagrams of another exemplary embodiment of the present disclosure, showing another initial signal mesh connectivity structure and a second power mesh connectivity structure. As shown in Figure 30C, the first initial signal line 31, the second initial signal line 32, and the third connection line 83 can be arranged in each cell row, and the first connection line 81, the second power line 64, the second connection line 82, and the second power line 64 can be arranged alternately in four consecutive cell columns. For example, the Nth cell column can be provided with a second connection line 82, the N+1th cell column can be provided with a second power line 64, the N+2th cell column can be provided with a first connection line 81, and the N+3th cell column can be provided with a second power line 64. As shown in Figure 30D, the first initial signal line 31, the second initial signal line 32, and the third connection line 83 can be arranged in each cell row, and the first connection line 81, the second power line 64, the second connection line 82, and the second power line 64 can be arranged alternately in eight consecutive cell columns. For example, the Nth unit column can be provided with a second connection line 82, the N+2th unit column can be provided with a second power line 64, the N+4th unit column can be provided with a first connection line 81, the N+5th unit column can be provided with a second power line 64, and the N+1th unit column, the N+3th unit column, the N+5th unit column and the N+7th unit column are not provided with the first connection line, the second connection line and the second power line, and the present disclosure does not limit this.

[0353] (38) Forming a second flat layer pattern. In an exemplary embodiment, forming the second flat layer pattern may include: coating a second flat film on the substrate on which the aforementioned pattern is formed, patterning the second flat film using a patterning process to form a second flat layer covering the fourth conductive layer, wherein the second flat layer is provided with a plurality of anode vias, the anode vias being configured to connect a subsequently formed anode to the anode connection electrode through the vias.

[0354] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is first prepared on the driving circuit layer, and then an encapsulation structure layer is formed, which will not be described in detail here.

[0355] The display substrate provided in this embodiment also implements separate control of the fifth and sixth transistors, enabling ultra-high frequency, higher-precision pulse width modulation, light signal duty cycle compensation, low grayscale compensation, and improved image retention. In at least one circuit unit of this embodiment, the sixth transistor T6 is controlled by the light signal line of its own unit row, while the fifth transistor T5 is controlled by the light signal line of the previous unit row. That is, the fifth transistor T5 is driven (cascaded) by the light signal line of the previous-stage sixth transistor T6. This not only reduces the capacitance at the output of the first node N1, preventing the first node N1 from being affected by the light signal line, but also reduces the number of light signal lines, facilitating high resolution.

[0356] The display substrate of this embodiment adopts the 2SD mode and adds the first capacitor to form a mesh connection structure of the second power signal, a mesh connection structure of the first initial signal, and a mesh connection structure of the second initial signal on the display substrate, thereby further improving the display effect.

[0357] Figures 31A and 31B are schematic diagrams of another display substrate according to the present disclosure after forming an anode conductive layer pattern. Figure 31B is a plan view schematic diagram of the anode conductive layer in Figure 31A. For the display substrates of the aforementioned embodiments, since dummy electrodes are provided in the third or fourth conductive layer, the consistency of the film layers in each sub-pixel can be ensured by providing auxiliary electrodes in the anode conductive layer.

[0358] In an exemplary embodiment, taking the display substrate shown in FIG17 as an example, the anode conductive layer may include a plurality of anodes 90, each of which may be connected to the anode connection electrode of the corresponding circuit unit through an anode via. An auxiliary electrode 90A may be provided on at least one anode 90, wherein the first end of the auxiliary electrode 90A is connected to the anode 90, and the second end of the auxiliary electrode 90A extends in a direction away from the anode 90. The orthographic projection of the auxiliary electrode 90A on the substrate at least partially overlaps with the orthographic projection of the fourteenth connection electrode, which serves as a virtual electrode, on the substrate, as shown in FIG31A and FIG31B. FIG31A and FIG31B illustrate only one auxiliary electrode 90A provided on one anode 90 as an example. In practice, auxiliary electrodes 90A may be provided on multiple anodes 90, each of which may at least partially overlap with multiple virtual electrodes, or multiple auxiliary electrodes 90A may be provided on one anode 90. This is not limited in the present disclosure. By providing an auxiliary electrode on at least one anode, the present disclosure can ensure the consistency of the film layer in each sub-pixel and reduce visual defects.

[0359] In an exemplary embodiment, the anode 90 and the auxiliary electrode 90A may be an integral structure connected to each other.

[0360] Figure 32 is a schematic diagram of another display substrate according to the present disclosure after forming a pixel definition layer pattern. As shown in Figure 32, the pixel definition layer may include multiple pixel openings K, each of which may expose the surface of the anode. At least one pixel opening K may be connected to a sub-opening K1, which may expose the surface of the auxiliary electrode.

[0361] In an exemplary embodiment, the pixel opening K and the sub-opening K1 may be communicated with each other.

[0362] Figures 33A and 33B are schematic diagrams of another embodiment of the present disclosure after a patterned anode conductive layer is formed on a display substrate. Figure 33B is a plan view of the anode conductive layer in Figure 33A. The structure of the anode conductive layer in this embodiment is substantially the same as that shown in Figures 31A and 31B, except that auxiliary electrode 90A is provided separately, i.e., anode 90 is not connected to auxiliary electrode 90A.

[0363] In an exemplary embodiment, taking the display substrate shown in FIG17 as an example, the anode conductive layer may include a plurality of anodes 90 and at least one auxiliary electrode 90A. Each anode 90 may be connected to the anode connection electrode of the corresponding circuit unit through an anode via. The orthographic projection of the auxiliary electrode 90A on the substrate at least partially overlaps with the orthographic projection of the fourteenth connection electrode as a virtual electrode on the substrate, as shown in FIG33A and FIG33B. FIG33A and FIG33B only illustrate the example of providing an auxiliary electrode 90A in the anode conductive layer. In fact, the anode conductive layer may be provided with a plurality of auxiliary electrodes 90A, and the plurality of auxiliary electrodes 90A respectively overlap at least partially with the plurality of virtual electrodes. The auxiliary electrode 90A may be provided in a floating state. In the subsequent formation of the pixel definition layer, no sub-opening is provided at the location of the auxiliary electrode 90A, and the present disclosure does not limit this. The present disclosure can ensure the consistency of the film layer in each sub-pixel and reduce visualization defects by providing at least one auxiliary electrode in the anode conductive layer.

[0364] In an exemplary embodiment, the auxiliary electrode provided on the anode conductive layer may be applied to the structures of the display substrates shown in FIG. 5 and FIG. 27 , and the present disclosure is not limited thereto.

[0365] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0366] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0367] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0368] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit and at least one control line, wherein the control line is configured to provide a light-emitting control signal to the pixel driving circuit; in at least one circuit unit, the pixel driving circuit at least comprises a driving transistor, a first light-emitting control transistor and a second light-emitting control transistor, wherein a first electrode of the first light-emitting control transistor is connected to a first power line, a second electrode of the first light-emitting control transistor is connected to a first electrode of the driving transistor, and a first electrode of the second light-emitting control transistor is connected to a second electrode of the driving transistor; the first light-emitting control transistor and the second light-emitting control transistor are connected to different control lines, and the first light-emitting control transistor and the second light-emitting control transistor are respectively arranged on both sides of the driving transistor unit column direction.

2. The display substrate according to claim 1, in, At least one control line includes a first signal line and a second signal line, the first light emission control transistor is connected to the first signal line, the second light emission control transistor is connected to the second signal line, and the first signal line and the second signal line are respectively arranged on both sides of the column direction of the driving transistor unit.

3. The display substrate according to claim 2, in, In a direction perpendicular to the display substrate, the display substrate includes a plurality of conductive layers, and the first signal line and the second signal line are arranged in different conductive layers.

4. The display substrate according to claim 3, in, The second light emission control transistor includes at least a second gate, the second gate and the first signal line are arranged in the same conductive layer, and the second gate and the second signal line are arranged in different conductive layers.

5. The display substrate according to claim 2, in, The pixel driving circuit also includes a compensation transistor, a gate electrode of the compensation transistor is connected to the first scanning signal line, a first electrode of the compensation transistor is connected to the gate electrode of the driving transistor through a first connecting electrode, and a second electrode of the compensation transistor is respectively connected to the second electrode of the driving transistor and the first electrode of the second light-emitting control transistor; an orthographic projection of the first connecting electrode on a display substrate plane at least partially overlaps with an orthographic projection of the first signal line on a display substrate plane, and an orthographic projection of the first connecting electrode on a display substrate plane at least partially overlaps with an orthographic projection of the first scanning signal line on a display substrate plane.

6. The display substrate according to claim 5, in, The compensation transistor at least includes a compensation active layer, the second light emission control transistor at least includes a second light emission control active layer, and the second area of ​​the compensation active layer is connected to the first area of ​​the second light emission control active layer through a fifth connection electrode; In a direction perpendicular to the display substrate, the display substrate includes at least one semiconductor layer and at least one conductive layer, the compensation active layer and the second light emission control active layer are arranged in the semiconductor layer, and the fifth connection electrode is arranged in the conductive layer.

7. The display substrate according to claim 5, in, The pixel driving circuit also includes a data writing transistor, a first electrode of the data writing transistor is connected to the data signal line, a second electrode of the data writing transistor is connected to the first electrode of the driving transistor, and the data writing transistor and the compensation transistor are respectively arranged on both sides of the driving transistor unit column direction.

8. The display substrate according to claim 1, in, At least one control line includes a light emission signal line, the light emission signal line is connected to the second light emission control transistor in the present unit row, and the light emission signal line is connected to the first light emission control transistor in the next unit row.

9. The display substrate according to claim 8, in, The first light emission control transistor includes at least a first gate, the second light emission control transistor includes at least a second gate, the light emission signal line is connected to the second gate in the current unit row, and the light emission signal line is connected to the first light emission control transistor in the next unit row through a light emission signal connection line.

10. The display substrate according to claim 9, in, In a direction perpendicular to the display substrate, the display substrate includes multiple conductive layers, the first gate and the second gate are arranged in the same conductive layer, the first gate and the light-emitting signal line are arranged in different conductive layers, the first gate and the light-emitting signal connecting line are arranged in different conductive layers, and the light-emitting signal connecting line and the light-emitting signal line are arranged in different conductive layers.

11. The display substrate according to claim 10, in, The multiple conductive layers at least include a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are sequentially arranged on the substrate along a direction away from the substrate, the first gate and the second gate are arranged in the first conductive layer, the light-emitting signal line is arranged in the third conductive layer, the light-emitting signal line is connected to the second gate through a via hole, the light-emitting signal connecting line is arranged in the fourth conductive layer, the first end of the light-emitting signal connecting line is connected to the light-emitting signal line in the current unit row through a via hole, and the second end of the light-emitting signal connecting line is connected to the first gate in the next unit row through a via hole.

12. The display substrate according to claim 11, in, The multiple conductive layers also include a fifth conductive layer arranged on a side of the fourth conductive layer away from the substrate, the first power line is arranged in the fifth conductive layer, and the orthographic projection of the first power line on the display substrate plane at least partially overlaps with the orthographic projection of the luminous signal connection line on the display substrate plane.

13. The display substrate according to any one of claims 1 to 12, in, At least one circuit unit also includes a first initial signal line extending along the pixel row direction and a first connecting line extending along the pixel column direction, the first initial signal line is configured to provide a first initial signal to the pixel driving circuit, the first initial signal line and the first connecting line are connected to form a mesh connection structure for transmitting the first initial signal.

14. The display substrate according to claim 13, in, The orthographic projection of the first connecting line on the plane of the display substrate does not overlap with the orthographic projection of the gate electrode of the driving transistor on the plane of the display substrate.

15. The display substrate according to claim 13, in, The pixel driving circuit also includes a compensation transistor, an active layer of the compensation transistor and an active layer of the driving transistor are connected to each other via an active connecting line, and an orthographic projection of the first connecting line on the display substrate plane does not overlap at least partially with an orthographic projection of the active connecting line on the display substrate plane.

16. The display substrate according to any one of claims 1 to 12, in, At least one circuit unit also includes a second initial signal line extending along the pixel row direction and a second connecting line extending along the pixel column direction, the second initial signal line is configured to provide a second initial signal to the pixel driving circuit, and the second initial signal line and the second connecting line are connected to form a mesh connection structure for transmitting the second initial signal.

17. The display substrate according to claim 16, in, The orthographic projection of the second connecting line on the plane of the display substrate does not overlap with the orthographic projection of the gate electrode of the driving transistor on the plane of the display substrate.

18. The display substrate according to claim 16, in, The pixel driving circuit also includes a compensation transistor, the active layer of the compensation transistor and the active layer of the driving transistor are connected to each other through an active connecting line, and the orthographic projection of the second connecting line on the display substrate plane does not overlap with the orthographic projection of the active connecting line on the display substrate plane at least partially.

19. The display substrate according to any one of claims 1 to 12, in, At least one circuit unit further includes a third connection line extending along the pixel row direction and a second power line extending along the pixel column direction, and the second power line and the third connection line are connected to form a mesh connection structure for transmitting a second power signal.

20. The display substrate according to claim 19, in, An orthographic projection of the second power line on the plane of the display substrate does not overlap with an orthographic projection of the gate electrode of the driving transistor on the plane of the display substrate.

21. The display substrate according to claim 19, in, The pixel driving circuit also includes a compensation transistor, an active layer of the compensation transistor and an active layer of the driving transistor are connected to each other through an active connecting line, and an orthographic projection of the second power line on the display substrate plane and an orthographic projection of the active connecting line on the display substrate plane at least partially do not overlap.

22. The display substrate according to any one of claims 1 to 12, in, The pixel driving circuit also includes a storage capacitor and a first capacitor; the storage capacitor includes a first electrode plate and a second electrode plate, the orthographic projection of the first electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane, the first electrode plate serves as the gate electrode of the driving transistor, and the second electrode plate is connected to the first power line; the first capacitor includes a third electrode plate and a fourth electrode plate, the orthographic projection of the third electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the fourth electrode plate on the display substrate plane, the third electrode plate is respectively connected to the first electrode of the driving transistor and the second electrode of the first light-emitting control transistor, and the fourth electrode plate is connected to the first power line.

23. The display substrate according to claim 22, in, In a direction perpendicular to the display substrate, the display substrate includes at least a semiconductor layer, a first conductive layer, and a second conductive layer, which are arranged in sequence on the substrate in a direction away from the substrate, the third electrode plate is arranged in the semiconductor layer, the first electrode plate is arranged in the first conductive layer, and the second electrode plate and the fourth electrode plate are arranged in the second conductive layer.

24. A display device comprising the display substrate according to any one of claims 1 to 23.

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