Electrostatic discharge protection device and manufacturing method therefor

Abstract

An electrostatic discharge (ESD) protection device and a manufacturing method therefor. The ESD protection device comprises: an N well (122), a P well (124), a first P-type region (132), a second P-type region (134), a third P-type region (136), and a first N-type region (142). The first P-type region (132) is located in the N well (122). The second P-type region (134) is located in the N well (122). The third P-type region (136) is located in the P well (124). The first N-type region (142) is located in the P well (124). The second P-type region (134) is in short circuit connection to the third P-type region (136), the first P-type region (132) and the N well (122) are connected to an anode, and the first N-type region (142) and the P well (124) are connected to a cathode.

Description

Electrostatic discharge protection device and manufacturing method thereof

[0001] Related applications

[0002] This application claims priority to Chinese patent application number 202311238491.9, filed on September 25, 2023, entitled “ESD protection device and manufacturing method thereof,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present invention relates to the field of semiconductor manufacturing, in particular to an electrostatic discharge (ESD) protection device and a method for manufacturing the ESD protection device. Background Art

[0004] Electrostatic discharge (ESD) protection is an important part of integrated circuit (IC) design. Referring to Figure 1, an ESD protection device is provided between the anode (also known as the positive electrode) and the cathode (also known as the negative electrode).

[0005] Silicon controlled rectifiers (SCRs), devices with the ability to discharge large currents, are commonly used as ESD protection structures in circuits. However, due to their low holding voltage, SCRs are prone to latch-up when the parasitic PNPN structure in integrated circuits forms positive feedback to discharge current, leading to circuit failure. This significantly limits their application.

[0006] Summary of the Invention

[0007] Based on this, the present application provides an ESD protection device with a high holding voltage.

[0008] An ESD protection device includes an N-well, a P-well, a first P-type region, a second P-type region, a third P-type region, and a first N-type region. The first P-type region is located in the N-well. The second P-type region is located in the N-well. The third P-type region is located in the P-well. The first N-type region is located in the P-well. The second P-type region is short-circuited to the third P-type region; the first P-type region and the N-well are connected to an anode, and the first N-type region and the P-well are connected to a cathode.

[0009] In one embodiment, the ESD protection device further includes: an N-well lead-out region, located in the N-well, the doping concentration of the N-well lead-out region is greater than the doping concentration of the N-well, and the N-well is connected to the anode through the N-well lead-out region; and a P-well lead-out region, located in the P-well, the doping concentration of the P-well lead-out region is greater than the doping concentration of the P-well, and the P-well is connected to the cathode through the P-well lead-out region.

[0010] In one embodiment, the doping concentration of the second P-type region is greater than the doping concentration of the P-well.

[0011] In one embodiment, the doping concentration of the third P-type region is greater than the doping concentration of the P-well.

[0012] In one embodiment, the second P-type region and the third P-type region are short-circuited by a metal interconnection layer.

[0013] In one embodiment, the ESD protection device further includes a substrate, and the N-well and the P-well are located in the substrate.

[0014] In one embodiment, the substrate is a P-type substrate.

[0015] In one embodiment, the doping concentration of the first P-type region is greater than the doping concentration of the P-well.

[0016] In one embodiment, the doping concentration of the first N-type region is greater than the doping concentration of the N-well.

[0017] In one embodiment, an interlayer dielectric layer is formed on the N-well and the P-well, a metal interconnect layer is formed on the interlayer dielectric layer, and the metal interconnect layer includes metal interconnect lines. Contact holes are formed directly above the second P-type region and the third P-type region, penetrating the interlayer dielectric layer, and metal is formed in the contact holes. The second P-type region and the third P-type region are short-circuited via the contact holes and the metal interconnect lines electrically connected to the contact holes.

[0018] In one embodiment, corresponding contact holes are provided for the N-well lead-out region and the first P-type region, metal is formed in the contact holes, and the N-well lead-out region and the first P-type region are connected to the anode via metal interconnections electrically connected to the contact holes.

[0019] In one embodiment, the P-well lead-out region and the first N-type region are provided with corresponding contact holes, metal is formed in the contact holes, and the P-well lead-out region and the first N-type region are connected to the cathode via metal interconnections electrically connected to the contact holes.

[0020] The present application also provides a method for manufacturing an ESD protection device.

[0021] A method for manufacturing an ESD protection device includes: forming an N-well and a P-well in a substrate; forming a first P-type region and a second P-type region in the N-well, and forming a third P-type region and a first N-type region in the P-well; connecting the first P-type region and the N-well to an anode, and connecting the first N-type region and the P-well to a cathode; and forming a metal interconnect layer, wherein the metal interconnect layer short-circuitly connects the second P-type region and the third P-type region.

[0022] In one embodiment, the manufacturing method of the ESD protection device further includes forming an N-well lead-out region in the N-well and forming a P-well lead-out region in the P-well, wherein: the doping concentration of the N-well lead-out region is greater than the doping concentration of the N-well, and the N-well is connected to the anode through the N-well lead-out region; the doping concentration of the P-well lead-out region is greater than the doping concentration of the P-well, and the P-well is connected to the cathode through the P-well lead-out region.

[0023] In one embodiment, the N-well and the P-well are formed in a substrate, including: obtaining a wafer having a substrate; coating a photoresist on the upper surface of the wafer and exposing it using a corresponding photomask; developing to expose an injection window, and correspondingly injecting N-type ions and P-type ions through the injection window to form the N-well and the P-well.

[0024] In one embodiment, the forming of the metal interconnection layer includes: forming an interlayer dielectric layer on the upper surface of the wafer; forming contact holes penetrating the interlayer dielectric layer by patterning; filling metal in the contact holes; and forming a metal interconnection layer on the interlayer dielectric layer, wherein the metal interconnection layer includes a plurality of metal interconnection lines.

[0025] In one embodiment, the doping concentration of the second P-type region is greater than the doping concentration of the P-well.

[0026] In one embodiment, the doping concentration of the third P-type region is greater than the doping concentration of the P-well.

[0027] In one embodiment, the substrate is a P-type substrate.

[0028] In one embodiment, the doping concentration of the first P-type region is greater than the doping concentration of the P-well.

[0029] In one embodiment, the doping concentration of the first N-type region is greater than the doping concentration of the N-well. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0031] FIG1 is an exemplary circuit architecture incorporating an ESD protection device in the related art;

[0032] FIG2 is a schematic structural diagram of an exemplary SCR of the related art;

[0033] FIG3 is a circuit diagram of the SCR of the related art shown in FIG2 ;

[0034] FIG4 is a schematic structural diagram of an ESD protection device according to an embodiment of the present application;

[0035] FIG5 is a circuit diagram of the ESD protection device shown in FIG4 ;

[0036] FIG6 is a schematic structural diagram of an ESD protection device according to another embodiment of the present application;

[0037] 7 is a flow chart of a method for manufacturing an ESD protection device according to an embodiment of the present application;

[0038] FIG8 is a schematic structural diagram of an ESD device after an N-well and a P-well are formed in a substrate in one embodiment of the present application. DETAILED DESCRIPTION

[0039] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0041] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there can be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings of the present invention.

[0042] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0045] The semiconductor field terms used in this article are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0046] Figure 2 is a schematic diagram of the structure of an exemplary silicon-controlled rectifier (SCR) in the related art, and Figure 3 is a circuit schematic diagram of the SCR shown in Figure 2. The SCR structure forms N+ contacts and P+ contacts in the N-well and P-well. When an ESD pulse arrives, the PN junction formed by the N-well and P-well undergoes avalanche breakdown, forming a large number of electron-hole pairs. Electrons and holes are collected by the N-well and P-well, respectively, forming a voltage drop on the flow path. When the voltage drop is greater than 0.7V, the PNP transistor and NPN transistor of the SCR turn on, forming positive feedback and discharging current. However, after the PNP transistor and NPN transistor of the SCR structure are triggered, the maintenance voltage is low, and the protected device or circuit is prone to latch-up during normal operation, causing device or circuit failure.

[0047] An embodiment of the present application proposes an ESD protection device. By adding a P+ island in the N-well and P-well, it is equivalent to embedding a parallel PNP transistor Qp. Therefore, when an ESD pulse comes and the ESD protection device forms positive feedback, the SCR in the ESD protection device can be shunted, thereby increasing the holding voltage of the ESD protection device.

[0048] FIG4 is a schematic diagram of the structure of an ESD protection device according to an embodiment of the present application, and FIG5 is a schematic diagram of the circuit diagram of the ESD protection device shown in FIG4 . The ESD protection device includes an N-well 122, a P-well 124, a first P-type region 132, a second P-type region 134, a third P-type region 136, and a first N-type region 142. The first P-type region 132 and the second P-type region 134 are located in the N-well 122, and the third P-type region 136 and the first N-type region 142 are located in the P-well 124. The second P-type region 134 is short-circuited to the third P-type region 136. The first P-type region 132 and the N-well 122 are connected to an anode, and the first N-type region 142 and the P-well 124 are connected to a cathode. First P-type region 132 serves as the emitter of the PNP transistor in the SCR. N-well 122 serves as the base of the PNP transistor and the collector of the NPN transistor in the SCR. P-well 124 serves as the collector of the PNP transistor and the base of the NPN transistor. First N-type region 142 serves as the emitter of the NPN transistor. First P-type region 132 also serves as the emitter of the parallel PNP transistor Qp. N-well 122 also serves as the base of PNP transistor Qp. Second P-type region 134, third P-type region 136, and P-well 124 serve as the collector of PNP transistor Qp. In Figure 5, R_NW is the parasitic resistance of N-well 122, and R_PW is the parasitic resistance of P-well 124.

[0049] The ESD protection device described above includes a second P-type region 134 in the N-well 122 and a third P-type region 136 in the P-well 124. The second P-type region 134 and the third P-type region 136 are short-circuited, effectively creating a parallel connection for a PNP transistor Qp. This provides an additional current discharge path when an ESD pulse strikes, thereby increasing the holding voltage of the ESD protection device and mitigating latch-up.

[0050] In one embodiment of the present application, as shown in FIG6 , the ESD protection device further includes an N-well lead-out region 144 and a P-well lead-out region 138. The N-well lead-out region 144 is located in the N-well 122. The doping concentration of the N-well lead-out region 144 is greater than the doping concentration of the N-well 122. The N-well 122 is connected to the anode via the N-well lead-out region 144. The P-well lead-out region 138 is located in the P-well 124. The doping concentration of the P-well lead-out region 138 is greater than the doping concentration of the P-well 124. The P-well 124 is connected to the cathode via the P-well lead-out region 138.

[0051] In the ESD protection device shown in FIG6 , the first P-type region 132, the second P-type region 134, and the N-well lead-out region 144 are located in the N-well 122, and the third P-type region 136, the first N-type region 142, and the P-well lead-out region 138 are located in the P-well 124. The second P-type region 134 is short-circuited to the third P-type region 136. The first P-type region 132 and the N-well lead-out region 144 are connected to an anode, and the first N-type region 142 and the P-well lead-out region 138 are connected to a cathode. The first P-type region 132 serves as the emitter of the PNP transistor in the SCR, and the N-well lead-out region 144 serves as the base of the PNP transistor and the collector of the NPN transistor in the SCR. The P-well lead-out region 138 serves as the collector of the PNP transistor and the base of the NPN transistor. The first N-type region 142 serves as the emitter of the NPN transistor. The first P-type region 132 also serves as the emitter of the parallel PNP transistor Qp. The N-well lead-out region 144 also serves as the base of the PNP transistor Qp. The second P-type region 134, the third P-type region 136 and the P-well lead-out region 138 serve as the collector of the PNP transistor Qp.

[0052] In one embodiment of the present application, the doping concentration of the second P-type region 134 is greater than the doping concentration of the P-well 124. Since the doping concentration of the second P-type region 134 is greater than the doping concentration of the P-well 124, the reverse breakdown voltage of the PN junction formed by the second P-type region 134 and the N-well 122 is lower than the reverse breakdown voltage of the PN junction formed by the P-well 124 and the N-well 122. Therefore, the avalanche breakdown voltage is also lower, thereby reducing the turn-on voltage of the ESD protection device.

[0053] In one embodiment of the present application, the doping concentration of the third P-type region 136 is greater than the doping concentration of the P-well 124 .

[0054] In one embodiment of the present application, the doping concentration of the first P-type region 132 is greater than the doping concentration of the P-well 124 .

[0055] In one embodiment of the present application, the doping concentration of the first N-type region 142 is greater than the doping concentration of the N-well 122 .

[0056] In one embodiment of the present application, the ESD protection device further includes a substrate 110. In one embodiment of the present application, the substrate 110 is a semiconductor substrate, and its material can be undoped single crystal silicon, impurity-doped single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), etc. It can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. In one embodiment of the present application, the constituent material of the substrate 110 is P-type single crystal silicon. Devices, such as NMOS and / or PMOS transistors, can be formed on the substrate 110. Accordingly, conductive components can also be formed in the substrate 110. The conductive components can be the gate, source, or drain of the transistor, or metal interconnect structures electrically connected to the transistor, etc. In addition, the substrate 110 may further be formed with an isolation structure such as STI (Shallow Trench Isolation).

[0057] In one embodiment of the present application, the second P-type region 134 and the third P-type region 136 are short-circuited via a metal interconnect layer. Specifically, an interlayer dielectric (ILD) layer is formed on the N-well 122 and the P-well 124, and a metal interconnect layer is formed on the interlayer dielectric layer. The metal interconnect layer includes metal interconnects. The present application does not limit the number of metal interconnects. Contact holes are formed directly above the second P-type region 134 and the third P-type region 136, penetrating the interlayer dielectric layer. Metal (e.g., tungsten plugs) are formed in the contact holes. The second P-type region 134 and the third P-type region 136 are short-circuited via the contact holes (the metal in the contact holes) and the metal interconnects electrically connected to the contact holes (the metal in the contact holes). Alternatively, corresponding contact holes may be provided on the N-well lead-out region 144 and the first P-type region 132 and filled with metal. The N-well lead-out region 144 and the first P-type region 132 are then connected to the anode via metal interconnects electrically connected to the contact holes. Similarly, corresponding contact holes can be set on the P-well lead-out region 138 and the first N-type region 142 and filled with metal, and then the P-well lead-out region 138 and the first N-type region 142 are connected to the cathode through metal interconnections electrically connected to the contact holes.

[0058] The present application accordingly provides a method for manufacturing an ESD protection device. FIG7 is a flow chart of a method for manufacturing an ESD protection device according to an embodiment of the present application, comprising the following steps S610 to S630.

[0059] S610 , forming an N-well 122 and a P-well 124 in the substrate.

[0060] A wafer having a substrate 110 is obtained, and an N-well 122 and a P-well 124 are formed in the substrate 110 by doping, as shown in FIG8 . Alternatively, the N-well 122 and the P-well 124 are formed by doping on a substrate having an epitaxial layer. Specifically, the N-well 122 and the P-well 124 can be formed by patterning and ion implantation. Patterning can be performed by coating a photoresist on the upper surface of the wafer, exposing the wafer using a corresponding photomask, and then developing the wafer to expose an implantation window. N-type ions and P-type ions are then implanted through the implantation window to form the N-well 122 and the P-well 124.

[0061] In one embodiment of the present application, substrate 110 is a semiconductor substrate. Its material may be undoped single crystal silicon, doped single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc. It may also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. In an embodiment of the present application, substrate 110 is formed of P-type single crystal silicon. Devices, such as NMOS and / or PMOS transistors, may be formed on substrate 110. Accordingly, conductive members may also be formed in substrate 110. These conductive members may be gates, sources, or drains of transistors, or metal interconnects electrically connected to the transistors, etc. Furthermore, substrate 110 may also be formed with isolation structures such as STI (shallow trench isolation).

[0062] S620, forming a first P-type region 132 and a second P-type region 134 in the N-well 122, and forming a third P-type region 136 and a first N-type region 142 in the P-well 124; connecting the first P-type region 132 and the N-well 122 to an anode, and connecting the first N-type region 142 and the P-well 124 to a cathode.

[0063] 4 , first P-type region 132 and second P-type region 134 are formed in N-well 122, and third P-type region 136 and first N-type region 142 are formed in P-well 124. Step S620 also forms first P-type region 132, second P-type region 134, third P-type region 136, and first N-type region 142 through patterning and ion implantation.

[0064] S630 , forming a metal interconnection layer, wherein the metal interconnection layer short-circuits the second P-type region and the third P-type region.

[0065] In one embodiment of the present application, an interlayer dielectric layer is first formed on the top surface of the wafer. Contact holes (including contact holes on the second P-type region 134 and the third P-type region 136) are then patterned to penetrate the interlayer dielectric layer. The contact holes are then filled with metal (e.g., tungsten plugs), and a metal interconnect layer is formed on the interlayer dielectric layer. The metal interconnect layer includes a plurality of metal interconnects. The second P-type region 134 and the third P-type region 136 are short-circuited via the contact holes (the metal in the contact holes) and the metal interconnects electrically connected to the contact holes (the metal in the contact holes).

[0066] The above-described method for manufacturing an ESD protection device includes providing a second P-type region 134 in the N-well 122 and a third P-type region 136 in the P-well 124. The second P-type region 134 and the third P-type region 136 are short-circuited, effectively creating a parallel connection for a PNP transistor Qp. This provides an additional current discharge path when an ESD pulse strikes, thereby increasing the holding voltage of the ESD protection device and mitigating latch-up.

[0067] In one embodiment of the present application, the method for manufacturing an ESD protection device further includes forming an N-well lead-out region 144 in the N-well 122 and forming a P-well lead-out region 138 in the P-well 124. The doping concentration of the N-well lead-out region 144 is greater than the doping concentration of the N-well 122, and the N-well 122 is connected to the anode via the N-well lead-out region 144; the doping concentration of the P-well lead-out region 138 is greater than the doping concentration of the P-well 124, and the P-well 124 is connected to the cathode via the P-well lead-out region 138.

[0068] In one embodiment of the present application, the N-well lead-out region 144 can be formed in the same process step as the first N-type region 142 in the P-well; the P-well lead-out region 138 can be formed in the same process step as the first P-type region 132, the second P-type region 134 and the third P-type region 136 in the P-well.

[0069] In one embodiment of the present application, the doping concentration of the second P-type region 134 is greater than the doping concentration of the P-well 124 .

[0070] In one embodiment of the present application, the doping concentration of the third P-type region 136 is greater than the doping concentration of the P-well 124 .

[0071] In one embodiment of the present application, the doping concentration of the first P-type region 132 is greater than the doping concentration of the P-well 124 .

[0072] In one embodiment of the present application, the doping concentration of the first N-type region 142 is greater than the doping concentration of the N-well 122 .

[0073] It should be understood that, although the various steps in the flowchart of the present application are shown in sequence as indicated by the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0074] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0075] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. An electrostatic discharge (ESD) protection device, comprising: N-well; P well; A first P-type region, located in the N-well; A second P-type region, located in the N-well; A third P-type region, located in the P-well; A first N-type region, located in the P-well; The second P-type region is short-circuited to the third P-type region; the first P-type region and the N-well are connected to an anode, and the first N-type region and the P-well are connected to a cathode.

2. The ESD protection device according to claim 1, characterized in that: Also includes: An N-well lead-out region, located in the N-well, the doping concentration of the N-well lead-out region is greater than the doping concentration of the N-well, and the N-well is connected to the anode through the N-well lead-out region; A P-well lead-out region is located in the P-well, the doping concentration of the P-well lead-out region is greater than the doping concentration of the P-well, and the P-well is connected to the cathode through the P-well lead-out region.

3. The ESD protection device according to claim 1 or 2, characterized in that: The doping concentration of the second P-type region is greater than the doping concentration of the P-well.

4. The ESD protection device according to any one of claims 1 to 3, characterized in that: The doping concentration of the second P-type region is greater than the doping concentration of the P-well.

5. The ESD protection device according to any one of claims 1 to 4, characterized in that: The second P-type region and the third P-type region are short-circuited by a metal interconnection layer.

6. The ESD protection device according to any one of claims 1 to 5, characterized in that: A substrate is also included, in which the N-well and the P-well are located.

7. The ESD protection device according to claim 6, characterized in that: The substrate is a P-type substrate.

8. The ESD protection device according to any one of claims 1 to 7, characterized in that: The doping concentration of the first P-type region is greater than the doping concentration of the P-well; and / or The doping concentration of the first N-type region is greater than the doping concentration of the N-well.

9. The ESD protection device according to claim 5, characterized in that: An interlayer dielectric layer is formed on the N-well and the P-well, a metal interconnect layer is formed on the interlayer dielectric layer, and the metal interconnect layer includes metal interconnect lines; A contact hole penetrating the interlayer dielectric layer is formed directly above the second P-type region and the third P-type region, and a metal is formed in the contact hole; The second P-type region and the third P-type region are short-circuited and connected through the contact hole and the metal interconnection line electrically connected to the contact hole.

10. The ESD protection device according to claim 2, characterized in that: The N-well lead-out region and the first P-type region are provided with corresponding contact holes, metal is formed in the contact holes, and the N-well lead-out region and the first P-type region are connected to the anode through metal interconnection lines electrically connected to the contact holes.

11. The ESD protection device according to claim 2, characterized in that: The P-well lead-out region and the first N-type region are provided with corresponding contact holes, metal is formed in the contact holes, and the P-well lead-out region and the first N-type region are connected to the cathode through metal interconnection lines electrically connected to the contact holes.

12. A method for manufacturing an ESD protection device, comprising: forming an N-well and a P-well in a substrate; forming a first P-type region and a second P-type region in the N-well, and forming a third P-type region and a first N-type region in the P-well; connecting the first P-type region and the N-well to an anode, and connecting the first N-type region and the P-well to a cathode; A metal interconnection layer is formed, wherein the metal interconnection layer short-circuits the second P-type region and the third P-type region.

13. The method for manufacturing an ESD protection device according to claim 12, further comprising forming an N-well lead-out region in the N-well and forming a P-well lead-out region in the P-well, wherein: The doping concentration of the N-well lead-out region is greater than the doping concentration of the N-well; the N-well is connected to the anode through the N-well lead-out region; The doping concentration of the P-well lead-out region is greater than the doping concentration of the P-well; and the P-well is connected to the cathode through the P-well lead-out region.

14. The method for manufacturing an ESD protection device according to claim 12 or 13, characterized in that: Forming the N-well and the P-well in a substrate includes: obtaining a wafer having a substrate; Coating a photoresist on the upper surface of the wafer and performing exposure using a corresponding photomask; The implantation windows are exposed by development, and N-type ions and P-type ions are implanted through the implantation windows to form the N-well and the P-well.

15. The method for manufacturing an ESD protection device according to claim 14, characterized in that: The forming of the metal interconnection layer comprises: forming an interlayer dielectric layer on the upper surface of the wafer; forming a contact hole penetrating the interlayer dielectric layer by patterning; Filling the contact holes with metal; A metal interconnection layer is formed on the interlayer dielectric layer, wherein the metal interconnection layer includes a plurality of metal interconnection lines.

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