Array substrate and display panel

Abstract

Disclosed is an array substrate. In the array substrate, a control electrode of a driving transistor, a second electrode of a compensation transistor, and a second electrode of a first reset transistor are all electrically connected to a first conductive connection portion, and a first electrode of the driving transistor and a second electrode of a data writing transistor are both electrically connected to a second conductive connection portion. The orthographic projection of a first conductive portion of the first conductive connection portion on a substrate overlaps with the orthographic projection of a first scanning signal line on the substrate. The orthographic projection of the first conductive portion of the first conductive connection portion on the substrate overlaps with the orthographic projection of a second scanning signal line on the substrate. A first shielding layer is configured to have a constant voltage signal, and the first shielding layer comprises a first shielding pattern. In a direction along the thickness of the substrate, the first shielding pattern is located between the first scanning signal line and the first conductive portion, and / or in the direction of the thickness of the substrate, the first shielding pattern is located between the second scanning signal line and the first conductive portion.

Description

Array substrate and display panel

[0001] This application claims priority to Chinese patent application No. 202311244269.X filed on September 25, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0003] OLED (Organic Light Emitting Diode) display devices have become one of the most competitive and promising display devices due to their advantages such as self-luminescence, fast response speed, high brightness, full viewing angle, and flexible display.

[0004] Summary of the Invention

[0005] In one aspect, an array substrate is provided. The array substrate includes a substrate and a drive circuit layer located on the substrate. The drive circuit layer includes: multiple pixel drive circuits, multiple first scan signal lines, multiple second scan signal lines, and a first shielding layer. The multiple pixel drive circuits are located on one side of the substrate and arranged in multiple rows and columns. A pixel drive circuit includes a first reset transistor, a compensation transistor, a drive transistor, a data write transistor, a first conductive connection portion, and a second conductive connection portion. The control electrode of the drive transistor, the second electrode of the compensation transistor, and the second electrode of the first reset transistor are all electrically connected to the first conductive connection portion, and the first electrode of the drive transistor and the second electrode of the data write transistor are both electrically connected to the second conductive connection portion. Multiple first scan signal lines are located on one side of the substrate, extending in the row direction and arranged sequentially in the column direction. One first scan signal line is electrically connected to the control electrode of the data write transistor in a row of pixel drive circuits. The orthographic projection of the first conductive portion of the first conductive connection portion on the substrate overlaps with the orthographic projection of the first scan signal line on the substrate. A plurality of second scanning signal lines are located on one side of the substrate, and the plurality of second scanning signal lines extend in the row direction and are arranged in sequence in the column direction. A second scanning signal line is electrically connected to the control electrode of the compensation transistor of a row of pixel driving circuits. The orthographic projection of the first conductive portion of the first conductive connection portion on the substrate overlaps with the orthographic projection of the second scanning signal line on the substrate. The first shielding layer is configured to have a constant voltage signal, and the first shielding layer includes a first shielding pattern. Along the thickness direction of the substrate, the first shielding pattern is located between the first scanning signal line and the first conductive portion; and / or, along the thickness direction of the substrate, the first shielding pattern is located between the second scanning signal line and the first conductive portion.

[0006] In some embodiments, the drive circuit layer includes a semiconductor layer, a first gate metal layer, a second gate metal layer, and a first routing metal layer stacked on the substrate. The semiconductor layer is located on the substrate. The semiconductor layer includes the first and second electrodes of the first reset transistor, the first and second electrodes of the compensation transistor, the first and second electrodes of the drive transistor, and the first and second electrodes of the data write transistor. The first gate metal layer is located on a side of the semiconductor layer away from the substrate. The first gate metal layer includes a control electrode of the first reset transistor, a control electrode of the drive transistor, and a control electrode of the data write transistor. The second gate metal layer is located on a side of the first gate metal layer away from the semiconductor layer. The first routing metal layer is located on a side of the second gate metal layer away from the first gate metal layer. The first routing metal layer includes the first scan signal line and the second scan signal line.

[0007] In some embodiments, the first conductive portion is located in the semiconductor layer, one end of the first conductive portion is electrically connected to the second electrode of the first reset transistor, and the other end of the first conductive portion is electrically connected to the control electrode of the drive transistor and the second electrode of the compensation transistor. The first conductive portion includes a first conductive sub-portion and a second conductive sub-portion connected to each other, the orthographic projection of the first conductive sub-portion on the substrate overlaps with the orthographic projection of the first scan signal line on the substrate, and the orthographic projection of the first conductive sub-portion on the substrate is located within the boundary of the orthographic projection of the first shielding pattern on the substrate; and / or the orthographic projection of the second conductive sub-portion on the substrate overlaps with the orthographic projection of the second scan signal line on the substrate, and the orthographic projection of the second conductive sub-portion on the substrate is located within the boundary of the orthographic projection of the first shielding pattern on the substrate.

[0008] In some embodiments, the first conductive portion further includes a third conductive sub-portion, one end of the third conductive sub-portion being electrically connected to the first conductive sub-portion, and the other end of the third conductive sub-portion being electrically connected to the second conductive sub-portion. An orthographic projection of the third conductive sub-portion on the substrate is located within a boundary of an orthographic projection of the first shielding pattern on the substrate.

[0009] In some embodiments, along the column direction, the first shielding pattern includes a first edge and a second edge, the first edge being located on a side of the second edge away from the driving transistor. A first minimum spacing between an orthographic projection of the first edge on the substrate and an orthographic projection of the first conductive sub-section on the substrate away from the second conductive sub-section is greater than or equal to 1 μm; and / or a second minimum spacing between an orthographic projection of the second edge on the substrate and an orthographic projection of the second conductive sub-section on the substrate away from the first conductive sub-section is greater than or equal to 1 μm.

[0010] In some embodiments, along the row direction, the third minimum spacing between the boundary of the orthographic projection of the first shielding pattern on the substrate and the boundary of the orthographic projection of the first conductive sub-section on the substrate is greater than or equal to 1 μm; and / or, along the row direction, the fourth minimum spacing between the boundary of the orthographic projection of the first shielding pattern on the substrate and the boundary of the orthographic projection of the first conductive sub-section on the substrate is greater than or equal to 1 μm.

[0011] In some embodiments, the first shielding pattern includes a first shielding sub-portion extending in the row direction and a second shielding sub-portion extending in the column direction. The orthographic projection of the first shielding sub-portion on the substrate overlaps with the orthographic projection of the second scan signal line on the substrate. The orthographic projection of the second shielding sub-portion on the substrate overlaps with the orthographic projection of the first conductive connection portion on the substrate.

[0012] In some embodiments, along the column direction, the first reset transistor is located on a side of the first scan signal line away from the second scan signal line. The orthographic projection of the first shielding pattern on the substrate does not overlap with the orthographic projection of the first reset transistor on the substrate.

[0013] In some embodiments, the pixel driving circuit further includes a storage capacitor, the storage capacitor including a first plate and a second plate, the first plate of the storage capacitor being electrically connected to the first conductive connection portion, the second plate of the storage capacitor being electrically connected to a first power signal line, the first power signal line being configured to provide a first power signal, and the first power signal being a constant voltage signal. In the case where the driving circuit layer includes a first gate metal layer and a second gate metal layer, the first gate metal layer further includes the first plate of the storage capacitor, the first plate of the storage capacitor being reused as the control electrode of the driving transistor. The second gate metal layer further includes the second plate of the storage capacitor, and the first shielding layer is electrically connected to the second plate of the storage capacitor.

[0014] In some embodiments, the first shielding layer is on the same layer as the second plate of the storage capacitor.

[0015] In some embodiments, the second gate metal layer also includes a first auxiliary connection portion, one end of the first auxiliary connection portion is electrically connected to the second plate of the storage capacitor, the other end of the first auxiliary connection portion is electrically connected to the first shielding pattern, and the orthographic projection of the first auxiliary connection portion on the substrate does not overlap with the orthographic projection of the control electrode of the compensation transistor on the substrate.

[0016] In some embodiments, an orthographic projection of the first auxiliary connection portion on the substrate does not overlap with an orthographic projection of the second electrode of the compensation transistor on the substrate.

[0017] In some embodiments, the first shielding layer further includes a second shielding pattern, and an orthographic projection of the second shielding pattern on the substrate overlaps with an orthographic projection of the second conductive connection portion on the substrate.

[0018] In some embodiments, the compensation transistor is a dual-gate transistor, and the control electrode of the compensation transistor includes a first control electrode and a second control electrode. When the driving circuit layer includes a first gate metal layer and a semiconductor layer, the first gate metal layer includes a first conductive pattern, and the first conductive pattern includes the first and second control electrodes of the compensation transistor. The semiconductor layer includes a first channel portion and a second channel portion of the compensation transistor, and the semiconductor layer also includes a second auxiliary connecting portion, one end of the second auxiliary connecting portion is electrically connected to the first channel portion of the compensation transistor, and the other end of the second auxiliary connecting portion is electrically connected to the second channel portion of the compensation transistor.

[0019] In some embodiments, the first shielding layer further includes a third shielding pattern, and an orthographic projection of the third shielding pattern on the substrate overlaps with an orthographic projection of the second auxiliary connecting portion on the substrate.

[0020] In some embodiments, an orthographic projection of the third shielding pattern on the substrate does not overlap with an orthographic projection of the first control electrode and the second control electrode of the compensation transistor on the substrate.

[0021] In some embodiments, the first conductive pattern further includes a third auxiliary connection portion, the third auxiliary connection portion being located on a side of the first and second control electrodes of the compensation transistor away from the driving transistor. One end of the third auxiliary connection portion is electrically connected to both the first and second control electrodes of the compensation transistor, and the other end of the third auxiliary connection portion is electrically connected to the second scan signal line.

[0022] In some embodiments, the pixel driving circuit further includes a first emission control transistor and a second emission control transistor. A first electrode of the first emission control transistor is electrically connected to a first power signal line, a second electrode of the first emission control transistor is electrically connected to a first electrode of the driving transistor, and a control electrode of the first emission control transistor is electrically connected to a first enable signal line. A first electrode of the second emission control transistor is electrically connected to a second electrode of the driving transistor, a second electrode of the second emission control transistor is electrically connected to an output terminal of the pixel driving circuit, and a control electrode of the second emission control transistor is electrically connected to a second enable signal line. Along the column direction, the first emission control transistor is located between the driving transistor and the second emission control transistor.

[0023] In some embodiments, the array substrate further includes a bottom shielding layer located between the substrate and the pixel driving circuit, wherein an orthographic projection of the bottom shielding layer on the substrate covers an orthographic projection of the driving transistor on the substrate.

[0024] In another aspect, a display panel is provided. The display panel includes: an array substrate as described in any of the above embodiments. The display panel also includes a light-emitting device layer located on a side of the array substrate away from the substrate; the light-emitting device layer includes a plurality of light-emitting devices, and the light-emitting devices are electrically connected to the pixel driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0026] FIG1 is a structural diagram of a display device according to some embodiments;

[0027] FIG2 is a structural diagram of a display panel according to some embodiments;

[0028] FIG3 is a cross-sectional view of a display panel according to some embodiments;

[0029] FIG4 is a cross-sectional view of an array substrate according to some embodiments;

[0030] FIG5 is a structural diagram of an array substrate according to some embodiments;

[0031] FIG6 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments;

[0032] FIG7 is a timing diagram of a pixel driving circuit according to some embodiments;

[0033] FIG8 is a measured timing diagram of a pixel driving circuit according to some possible implementations;

[0034] FIG9 is a film layer diagram of a pixel driving circuit according to some embodiments;

[0035] FIG10 is a measured timing diagram of a pixel driving circuit according to some embodiments;

[0036] FIG11 is a film layer diagram of the semiconductor layer and the first gate metal layer in FIG9 ;

[0037] FIG12 is a film layer diagram of the semiconductor layer, the first gate metal layer, and the second gate metal layer in FIG9 ;

[0038] FIG13 is a film layer diagram of the semiconductor layer, the first gate metal layer, the second gate metal layer and the first wiring metal layer in FIG9;

[0039] FIG14 is a partial enlarged view of M in FIG13;

[0040] FIG. 15 is a film layer diagram of a pixel driving circuit and a bottom shielding layer according to some embodiments. DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0042] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0043] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0044] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood broadly. For example, "connected" can mean fixed, removable, or integrated; it can be directly connected or indirectly connected through an intermediary. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0045] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0046] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0047] As used herein, the term "if" is optionally interpreted to mean "when" or "upon...", depending on the context. Similarly, the phrases "if it is determined that..." or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determination that...", depending on the context.

[0048] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0049] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0050] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0051] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0052] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0053] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0054] In the circuit structure provided in the embodiments of the present disclosure, the first electrode of each transistor is one of the source and the drain, and the second electrode of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be structurally symmetrical, the source and drain can be structurally identical. In other words, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be structurally identical.

[0055] FIG. 1 is a structural diagram of a display device according to some embodiments.

[0056] As shown in FIG. 1 , some embodiments of the present disclosure provide a display device 300 , which includes a display panel 200 .

[0057] Exemplarily, the display device 300 further includes a frame and other electronic accessories.

[0058] Exemplarily, the display device 300 may be an electroluminescent display device or a photoluminescent display device. If the display device is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). If the display device is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0059] Exemplarily, the display device 300 can be any display device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is expected that the display device of the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, camera view displays (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0060] Some embodiments of the present disclosure further provide a display panel. This display panel can be used as the display panel in the display device provided in any of the above embodiments. Of course, this display panel can also be used in other display devices, and this disclosure does not limit this.

[0061] Figure 2 is a structural diagram of a display panel according to some embodiments, illustrating the structure of a display area in the display panel. It should be noted that Figure 2 only illustrates the structure of the display area of ​​the display panel, while omitting the structure of the peripheral area, for example, omitting the scan drive circuit.

[0062] In some embodiments, as shown in FIG. 2 , the display panel 200 includes an active area (AA) and a peripheral area SA. The peripheral area SA may be located on at least one side of the display area AA (e.g., one side; or, for example, all four sides, i.e., including the upper and lower sides and the left and right sides).

[0063] The display panel 200 includes a plurality of sub-pixels P disposed in a display area AA. The plurality of sub-pixels P may be arranged in an array. Through light emitted by the plurality of sub-pixels P, the display panel 200 may display an image in the display area AA.

[0064] Specifically, the plurality of sub-pixels P may include a plurality of sub-pixels emitting different luminous colors. Exemplarily, the plurality of sub-pixels P include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. The first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each emit three primary colors of light. For example, the first sub-pixel P1 may emit red light, the second sub-pixel P2 may emit green light, and the third sub-pixel P3 may emit blue light.

[0065] Based on this, by adjusting the brightness (grayscale) of sub-pixels P of different colors, multiple colors can be displayed through color combination and superposition, thereby achieving full-color display of the display panel 200.

[0066] As shown in FIG. 2 , a sub-pixel P may include a light-emitting device O and a pixel driving circuit Q coupled to the light-emitting device O.

[0067] The light-emitting device O may be one of an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a light-emitting diode (LED), and a liquid crystal light-emitting device, but is not limited thereto. The embodiments of the present disclosure do not limit the type of light-emitting device. That is, the light-emitting device O may be any other light-emitting device (e.g., a light-emitting device that emits light through discharge), as long as it can emit light so that the display panel 200 can display an image.

[0068] The pixel driving circuit Q can be configured to provide an electrical signal (such as a driving voltage or a driving current) to the light-emitting device O coupled to the pixel driving circuit Q in response to the received scan signal and data signal, so as to drive the light-emitting device O to emit light, so that the display panel 200 can display the picture.

[0069] FIG. 3 is a cross-sectional view of a display panel according to some embodiments.

[0070] As shown in FIG. 3 , the display panel 200 includes an array substrate 100 and a light emitting device layer 210 stacked in sequence. The light emitting device layer 210 is located on a side of the array substrate 100 close to a light emitting surface of the display panel 200 .

[0071] Among them, the array substrate 100 includes multiple pixel driving circuits Q (as shown in Figure 2), the light-emitting device layer 210 includes multiple light-emitting devices O (as shown in Figure 2), and the multiple pixel driving circuits Q are electrically connected to the multiple light-emitting devices O to drive the light-emitting devices O to emit light.

[0072] In some examples, the multiple pixel driving circuits Q and the multiple light-emitting devices O can be electrically connected in a one-to-one correspondence. In other examples, one pixel driving circuit Q can be coupled to multiple light-emitting devices O, or multiple pixel driving circuits Q can be coupled to one light-emitting device O. Below, the present disclosure uses the coupling of one pixel driving circuit Q to one light-emitting device O as an example to schematically illustrate the structure of the display panel 200.

[0073] In some examples, the light emitting device layer 210 includes an anode layer, a light emitting functional layer, and a cathode layer stacked in sequence, wherein the light emitting functional layer includes a light emitting layer.

[0074] In other examples, the light-emitting functional layer includes, in addition to the light-emitting layer, one or more layers of an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL).

[0075] In some examples, the display panel 200 further includes an encapsulation layer 220, which is located on a side of the light-emitting device layer 210 away from the array substrate 100. Here, the encapsulation layer 220 can be an encapsulation film or an encapsulation substrate.

[0076] The encapsulation layer 220 can cover the multiple light-emitting devices O in the light-emitting device layer 210 and encapsulate the light-emitting devices O to prevent moisture and oxygen in the external environment from entering the display panel 200 and damaging the organic materials in the light-emitting devices O, thereby shortening the life of the display panel 200.

[0077] Some embodiments of the present disclosure further provide an array substrate. This array substrate can be used as the array substrate in the display panel provided in any of the above embodiments. Of course, this array substrate can also be used in other display panels, and this disclosure does not limit this.

[0078] Figure 4 is a cross-sectional view of an array substrate according to some embodiments, and Figure 5 is a structural diagram of an array substrate according to some embodiments. Figure 5 illustrates the structure of the display area of ​​the array substrate. It should be noted that Figure 5 only illustrates the structure of the display area of ​​the array substrate, omitting the structure of the peripheral area.

[0079] In some embodiments, as shown in Figures 4 and 5 , the array substrate 100 includes a substrate 10 and a driving circuit layer 20 located on the substrate 10. The driving circuit layer 20 is located on one side of the substrate 10. For example, the driving circuit layer 20 is located on a side of the substrate 10 that is close to the light-emitting device layer 210 (as shown in Figure 3 ). The driving circuit layer 20 includes a plurality of pixel driving circuits Q (as shown in Figure 2 ).

[0080] The plurality of pixel driving circuits Q are arranged in multiple rows and columns. For the convenience of description, the plurality of pixel driving circuits Q are described in this disclosure by taking a matrix arrangement as an example.

[0081] In some examples, the substrate 10 may be a flexible substrate. For example, the material of the substrate 10 may be an organic material. For example, the material of the substrate 10 may be any one of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0082] In other examples, the substrate 10 may be a rigid substrate, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0083] The driving circuit layer 20 further includes a plurality of signal lines. One pixel driving circuit Q needs to be electrically connected to the plurality of signal lines so as to utilize the plurality of signal lines to provide different signals and provide the required signals to the pixel driving circuit Q.

[0084] Exemplarily, the plurality of signal lines may include: a first scan signal line Gate, a second scan signal line Scan, a data signal line Data, a first enable signal line EM1, a second enable signal line EM2, a first reset signal line R1, a second reset signal line R2, a first initialization signal line Vinit1, a second initialization signal line Vinit2, and a first power signal line VDD. FIG5 does not illustrate the first initialization signal line Vinit1 and the second initialization signal line Vinit2.

[0085] In some embodiments, the pixel driving circuit Q includes multiple transistors. In some embodiments, the structure of the pixel driving circuit Q in the present disclosure includes multiple structures, which can be selected according to actual needs. For example, the structure of the pixel driving circuit Q may include "7T1C" or "8T1C" and the like. Here, "T" represents a thin film transistor, and the number in front of "T" represents the number of thin film transistors; "C" represents a storage capacitor C, and the number in front of "C" represents the number of storage capacitors C. The following is an introduction taking the "7T1C" pixel driving circuit as an example.

[0086] Figure 6 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments. Figure 6 illustrates an equivalent circuit diagram of a "7T1C" pixel driving circuit.

[0087] As shown in FIG6 , the pixel driving circuit Q may be a “7T1C” pixel driving circuit Q. The pixel driving circuit Q includes: a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first emission control transistor T5, a second emission control transistor T6, a second reset transistor T7, and a capacitor Cst.

[0088] Since the pixel driving circuit Q needs to be electrically connected to a variety of different types of signal lines, FIG5 also illustrates a variety of signal lines.

[0089] A control electrode c1 of the first reset transistor T1 is electrically connected to the first reset signal line R1 , a first electrode a1 of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit1 , and a second electrode b1 of the first reset transistor T1 is electrically connected to the first node N1 .

[0090] The control electrode c2 of the compensation transistor T2 is electrically connected to the second scan signal line Scan, the first electrode a2 of the compensation transistor T2 is electrically connected to the third node N3, and the second electrode b2 of the compensation transistor T2 is electrically connected to the first node N1.

[0091] In some examples, the second scan signal line Scan used to drive the pixel driving circuit Q in the nth row can be multiplexed as the third scan signal line G3 of the pixel driving circuit Q in the n+3th row. Based on this, when the second scan signal line Scan drives the compensation transistor T2 of the pixel driving circuit Q in the nth row to turn on, it can also drive the first reset transistor T1 of the pixel driving circuit Q in the n+3th row to turn on, thereby resetting the first node N1.

[0092] In other words, the pixel driving circuit Q in the nth row can be driven by the second scanning signal line Scan that drives the pixel driving circuit Q in the n-3th row. In FIG6 , “Scan-3” indicates the second scanning signal line Scan electrically connected to the pixel driving circuit Q in the first three rows.

[0093] Exemplarily, the second scan signal line Scan for driving the pixel drive circuit Q in the n-th row includes two branches, namely a first branch and a second branch. The first branch of the second scan signal line Scan for the pixel drive circuit Q in the n-th row is electrically connected to the pixel drive circuit Q in the n-th row to drive the compensation transistor T2 of the pixel drive circuit Q in the n-th row to turn on. The second branch of the second scan signal line Scan for the pixel drive circuit Q in the n-th row is electrically connected to the pixel drive circuit Q in the n+3-th row to drive the first reset transistor T1 of the pixel drive circuit Q in the n+3-th row to turn on, thereby resetting the first node N1.

[0094] Based on this, there is no need to provide a separate first reset signal line R1 , which can reduce the number of wirings in the array substrate 100 and facilitate the layout of other wirings in the array substrate 100 .

[0095] The control electrode c3 of the driving transistor T3 is electrically connected to the first node N1 , the first electrode a3 of the driving transistor T3 is electrically connected to the second node N2 , and the second electrode b3 of the driving transistor T3 is electrically connected to the third node N3 .

[0096] The control electrode c4 of the data writing transistor T4 is electrically connected to the first scanning signal line Gate, the first electrode a4 of the data writing transistor T4 is electrically connected to the data signal line Data, and the second electrode b4 of the data writing transistor T4 is electrically connected to the second node N2.

[0097] The control electrode c5 of the first light emission control transistor T5 is electrically connected to the first enable signal line EM1, the first electrode a5 of the first light emission control transistor T5 is electrically connected to the first power signal line VDD, and the second electrode b5 of the first light emission control transistor T5 is electrically connected to the second node N2.

[0098] A control electrode c6 of the second light-emitting control transistor T6 is electrically connected to the second enable signal line EM2, a first electrode a6 of the second light-emitting control transistor T6 is electrically connected to a third node N3, a second electrode b6 of the second light-emitting control transistor T6 is electrically connected to a fourth node N4, and the fourth node N4 is electrically connected to the anode of the light-emitting device O. The cathode of the light-emitting device O is electrically connected to the second power signal line VSS. The voltage value of the third power signal provided by the third power signal line VSS is lower than the voltage value of the first power signal provided by the first power signal line VDD.

[0099] The control electrode c7 of the second reset transistor T7 is electrically connected to the second reset signal line R2, the first electrode a7 of the second reset transistor T7 is electrically connected to the second initialization signal line Vinit2, the second electrode b7 of the second reset transistor T7 is electrically connected to the fourth node N4, and the fourth node N4 is electrically connected to the anode of the light-emitting device O.

[0100] The storage capacitor Cts, a first plate Cst- 1 of the storage capacitor Cst is electrically connected to the control electrode c1 of the driving transistor T3 , and a second plate Cst- 2 of the storage capacitor Cst is electrically connected to the first power signal line VDD.

[0101] FIG. 7 is a timing diagram of a pixel driving circuit according to some embodiments.

[0102] In some embodiments, as shown in FIG7 , the driving process of the pixel driving circuit Q shown in FIG6 is as follows: one frame period includes a first stage t1 , a second stage t2 , a third stage t3 , a fourth stage t4 and a fifth stage t5 .

[0103] First stage t1: The first reset signal provided by the first reset signal line (the second scanning signal line Scan-3 electrically connected to the first three rows of pixel driving circuits Q) includes the operating level of the first reset transistor T1, which can control the first reset transistor T1 to turn on, transmit the first initialization signal transmitted by the first initialization signal line Vinit1 to the first node N1, and reset the first node N1, so as to improve the stability of the driving transistor T3 included in the first pixel driving circuit.

[0104] Second stage t2: The second reset signal provided by the second reset signal line R2 includes the operating level of the second reset transistor T7, which can control the second reset transistor T7 to turn on, and transmit the second initialization signal transmitted by the second initialization signal line Vinit2 to the fourth node N4, which is equivalent to resetting the anode of the light-emitting unit O, thereby improving the stability of the light-emitting unit O.

[0105] The first reset signal provided by the first reset signal line (the second scan signal line Scan-3 electrically connected to the first three rows of pixel driving circuits Q) controls the first reset transistor T1 to be continuously turned on. At this time, the potential of the first node N1 can control the driving transistor T3 to be turned on.

[0106] The second scanning signal provided by the second scanning signal line Scan includes the working level of the compensation transistor T2, which controls the compensation transistor T2 to turn on, and can transmit the voltage at the first node N1 to the third node N3, resetting the third node N3, thereby improving the stability of the driving transistor T3 included in the pixel driving circuit Q. And,

[0107] When the compensation transistor T2 and the driving transistor T3 are both turned on, the first initialization signal provided by the first initialization signal line Vinit1 can be written to the second node N2 through the first reset transistor T1 and the driving transistor T3, thereby resetting the second node N2.

[0108] Based on this, in the second stage t2, the first node N1, the second node N2 and the third node N3 are reset, that is, the control electrode c2, the first electrode a3 and the second electrode b3 of the driving transistor T3 are reset, so that the initial state of the driving transistor T3 before the third stage (data writing stage) t3 is fixed, which makes it easier to put the driving transistor T3 in a stable state in the third data stage t3, thereby greatly improving the hysteresis effect of the driving transistor T3.

[0109] Phase 3 t3: The first scan signal provided by the first scan signal line Gate includes the operating level of the data write transistor T4, which controls the data write transistor T4 to turn on. The second scan signal provided by the second scan signal line Scan controls the compensation transistor T2 to continue turning on. At this point, the data write signal provided by the data signal line Data is sequentially transmitted through the data write transistor T4, the drive transistor T3, and the compensation transistor T2 to the first node N1, compensating the first node N1. The potential of the first node N1 gradually rises to Vdata + Vth.

[0110] Where Vdata is the voltage value of the data write signal provided by the data signal line Data, and Vth is the threshold voltage of the driving transistor T3 in the pixel driving circuit. The charging process is completed when the potential of the first node N1 reaches Vdata + Vth. Subsequently, the storage capacitor Cst is discharged to keep the driving transistor T3 included in the first pixel driving circuit continuously turned on, ensuring that the light-emitting device O emits light.

[0111] Fourth stage t4: The first enable signal provided by the first enable signal line EM1 includes the working level of the first light-emitting control transistor T5, which can control the first light-emitting control transistor T5 to turn on, and cooperate with the driving transistor T3 to transmit the first power supply signal provided by the first power supply signal terminal VDD to the third node N3 through the driving transistor T3.

[0112] Fifth stage t5: The first enable signal provided by the first enable signal line EM1 controls the first light-emitting control transistor T5 to continue to be turned on, and the second enable signal provided by the second enable signal line EM2 includes the operating level of the second light-emitting control transistor T6, which can control the second light-emitting control transistor T6 to be turned on, and the first power signal provided by the first power signal terminal VDD received at the third node N3 is transmitted to the fourth node N4. In other words, the first power signal provided by the first power signal terminal VDD is transmitted to the anode of the light-emitting device O.

[0113] Based on this, in the fifth stage t5, the constant voltage power signal provided by the first power signal line VDD can flow through the first light-emitting control transistor T5, the driving transistor T3, and the second light-emitting control transistor T6 in sequence to the anode of the light-emitting device O, and the cathode of the light-emitting device O can be electrically connected to the second power signal line VSS, thereby driving the light-emitting device O to emit light. The first power signal line VDD can be a high power signal line, and the third power signal line VSS can be a low power signal line.

[0114] It should be noted that the "working level" refers to a level that can turn on the operated transistor included therein, and accordingly, the "non-working level" refers to a level that cannot turn on the operated transistor included therein (that is, the transistor is cut off). Depending on factors such as the type of transistor (N-type or P-type) in the circuit structure of the shift register circuit, the working level may be higher or lower than the non-working level. Typically, for a square wave pulse signal used by a pixel driving circuit during operation, the working level corresponds to the level of the square wave pulse portion of the square wave pulse signal, while the non-working level corresponds to the level of the non-square wave pulse portion.

[0115] In addition, in some embodiments, the first power signal line VDD is configured to transmit a DC high-level signal (for example, lower than or equal to the high-level portion of the clock signal). Here, the DC high-level signal is referred to as the first power signal. The following embodiments are the same and will not be repeated here.

[0116] In some embodiments, the first power signal line VDD is configured to transmit a DC high-level signal (eg, higher than or equal to the high-level portion of the clock signal), which is referred to herein as a first voltage signal.

[0117] The second power signal line VSS is configured to transmit a DC low-level signal (eg, lower than or equal to the low-level portion of the clock signal). This DC low-level signal is referred to as the second power signal. The following embodiments are the same and will not be described in detail.

[0118] Exemplarily, the voltage value of the first power signal is greater than the voltage value of the second power signal. The following embodiments are the same as this and will not be described in detail.

[0119] In some examples, as shown in FIG6 , all seven transistors in the pixel driving circuit Q may be P-type transistors.

[0120] In the case that the seven transistors are all P-type transistors, the “operating level” can be understood as a low-level signal, that is, the seven transistors can all be turned on under the control of the low-level signal.

[0121] In some examples, as shown in FIG6 , the seven transistors may all be low temperature polysilicon (LTPS) transistors.

[0122] In other examples, the first reset transistor T1 and the compensation transistor T2 may be N-type transistors. N-type transistors can help reduce the risk of transistor leakage. In other words, they can help reduce the risk of leakage in the first reset transistor T1 and the compensation transistor T2, and can help ensure the stability of the voltage at the first node N1, that is, ensure the stability of the driving transistor T3, thereby improving the brightness maintenance rate of the light-emitting device O within a frame.

[0123] When the first reset transistor T1 and the compensation transistor T2 are N-type transistors, the above-mentioned “operating level” can be understood as a high-level signal. That is, the above-mentioned first reset transistor T1 and the compensation transistor T2 can be turned on under the control of the high-level signal.

[0124] In some examples, the first reset transistor T1 and the compensation transistor T2 may be indium gallium zinc oxide (IGZO) transistors. Oxide transistors have a smaller off-leakage current, thereby reducing the leakage current of the first node N1 through the first reset transistor T1 in the fourth and fifth stages.

[0125] In some other embodiments, the pixel driving circuit Q is an "8T1C" pixel driving circuit Q. In this case, the pixel driving circuit Q further includes a third reset transistor. A control electrode of the third reset transistor is electrically connected to a third reset signal line, a first electrode of the third reset transistor is electrically connected to a third initialization signal line, and a second electrode of the third reset transistor is electrically connected to the second node.

[0126] The second node N2 can be reset using the third initialization signal provided by the third initialization signal line, which is equivalent to resetting the first electrode of the driving transistor T3, thereby improving the stability of the driving transistor T3.

[0127] In some embodiments, the pixel driving circuit Q further includes multiple conductive connections. Each "node" within either the "7T1C" pixel driving circuit or the "8T1C" pixel driving circuit in the aforementioned embodiments represents a node equivalent to the junction of the related couplings in the circuit diagram. Each "node" corresponds to a "conductive connection," which is utilized to electrically connect other structures in the circuit, thereby fulfilling the function of a "node."

[0128] Exemplarily, the plurality of conductive connection portions may include a first conductive connection portion, a second conductive connection portion, and other conductive connection portions. The first conductive connection portion may be a first node N1 (as shown in FIG6 ) in the equivalent circuit diagram of the pixel driving circuit Q, and the second conductive connection portion may be a second node N2 (as shown in FIG6 ) in the equivalent circuit diagram of the pixel driving circuit Q.

[0129] Based on this, the first conductive connection portion is electrically connected to the control electrode c3 of the drive transistor T3, the second electrode b2 of the compensation transistor T2, the second electrode b1 of the first reset transistor T1, and the first electrode plate Cst-1 of the storage capacitor Cst. The second conductive connection portion is electrically connected to the first electrode a3 of the drive transistor T3, the second electrode b4 of the data writing transistor T4, and the second electrode b5 of the first light emission control transistor T5.

[0130] It should be noted that the first conductive portion of the first conductive connection portion can be understood as the structure between the second electrode b2 of the compensation transistor T2 and the second electrode b1 of the first reset transistor T1 on the semiconductor layer POLY. The second conductive connection portion can include: the structure between the first electrode a3 of the drive transistor T3 and the second electrode b5 of the first emission control transistor T5, and the structure between the first electrode a3 of the drive transistor T3 and the second electrode b4 of the data write transistor T4 on the semiconductor layer POLY.

[0131] FIG8 is a measured timing diagram of a pixel driving circuit according to some implementations.

[0132] The inventors have found that, as shown in FIG8 , in actual product testing, the potential of the first node N1 is affected when the potentials of the signals transmitted by the first scan signal line Gate and the second scan signal line Scan jump.

[0133] Specifically, in the third stage t3 (data writing stage): the first scanning signal provided by the first scanning signal line Gate will jump from a low voltage signal to a high voltage signal. The jump of the first scanning signal will increase the voltage of the first node N1, which will cause the driving signal output by the pixel driving circuit Q to the light-emitting unit O to be reduced, affecting the brightness uniformity of the display panel 200 including the array substrate 100 (as shown in Figure 3). In addition, the second scanning signal provided by the second scanning signal line Scan will also jump from a low voltage signal to a high voltage signal. The jump of the second scanning signal will also increase the voltage of the first node N1. Furthermore, it will affect the potential of the control electrode of the driving transistor T3, affect the stability of the driving transistor T3, and thus affect the driving signal output by the pixel driving circuit Q to the light-emitting unit O, affecting the brightness uniformity of the display panel 200 including the array substrate 100.

[0134] Moreover, when the voltages of the signals transmitted by the first scanning signal line Gate and the second scanning signal line Scan jump, the voltage of the first node N1 is pulled up, which aggravates the impact on the stability of the driving transistor T3 and reduces the brightness uniformity of the display panel 200.

[0135] The inventors further discovered that when manufacturing the array substrate, due to the space limitation of the array substrate 100, the orthographic projection of the first scanning signal line Gate on the substrate 10 overlaps with the orthographic projection of the first conductive part of the first conductive connection part on the substrate 10, and the orthographic projection of the second scanning signal line Scan on the substrate 10 overlaps with the orthographic projection of the first conductive part of the first conductive connection part on the substrate 10.

[0136] Based on this, a parasitic capacitance is formed between the first scan signal line Gate and the first conductive portion of the first conductive connection portion, and a parasitic capacitance is formed between the second scan signal line Scan and the first conductive portion of the first conductive connection portion. Furthermore, when the voltage of the signals transmitted by the first scan signal line Gate and the second scan signal line Scan jumps, the potential of the first conductive portion of the first conductive connection portion is correspondingly increased due to capacitive coupling.

[0137] In summary, since the first scanning signal line Gate and the second scanning signal line Scan both overlap with the first conductive connection portion, the signal jump will affect the potential of the control electrode of the driving transistor, affect the stability of the driving transistor T3, affect the driving signal output by the pixel driving circuit Q to the light-emitting unit O, and affect the brightness uniformity of the display panel 200.

[0138] FIG9 is a film layer diagram of a pixel driving circuit according to some embodiments. In FIG9 , only the control electrode of each transistor is marked to represent the corresponding transistor, but it does not mean that the transistor only includes the control electrode.

[0139] Based on this, as shown in FIG9 , an embodiment of the present disclosure provides an array substrate 100 further comprising a first shielding layer 50 configured to have a constant voltage signal. The first shielding layer 50 includes a first shielding pattern 51, and along the thickness direction of the substrate 10, the first shielding pattern 51 is located between the first scan signal line Gate and the first conductive portion 31 of the first conductive connection portion 30, and / or, along the thickness direction of the substrate 10, the first shielding pattern 51 is located between the second scan signal line Scan and the first conductive portion 31 of the first conductive connection portion 30. The thickness direction of the substrate 10 is approximately perpendicular to the row direction X, and the thickness direction of the substrate 10 is approximately perpendicular to the column direction Y.

[0140] As shown in the above structure, the position of the first shielding pattern 51 includes the following three situations:

[0141] The first type: along the thickness direction of the substrate 10, the first shield pattern 51 is located between the first scan signal line Gate and the first conductive portion 31 of the first conductive connection portion 30. That is, the orthographic projections of the first shield pattern 51, the first conductive portion 31 of the first conductive connection portion 30, and the first scan signal line Gate on the substrate 10 have an overlapping area.

[0142] Such a setting is equivalent to using the first shielding pattern 51 with a constant voltage signal to isolate the first scanning signal line Gate and the first conductive part 31 of the first conductive connection part 30, thereby reducing the parasitic capacitance between the first scanning signal line Gate and the first conductive part 31, thereby improving the impact of the first scanning signal transmitted on the first scanning signal line Gate on the first conductive part 31 when the potential jumps, and improving the stability of the first conductive connection part 30.

[0143] The second type: along the thickness direction of the substrate 10, the first shielding pattern 51 is located between the second scan signal line Scan and the first conductive portion 31 of the first conductive connection portion 30. In other words, the orthographic projections of the first shielding pattern 51, the first conductive portion 31 of the first conductive connection portion 30, and the second scan signal line Scan on the substrate 10 have an overlapping area.

[0144] Such a setting is equivalent to using the first shielding pattern 51 with a constant voltage signal to isolate the second scanning signal line Scan and the first conductive part 31 of the first conductive connection part 30, reducing the parasitic capacitance between the second scanning signal line Scan and the first conductive part 31, so as to improve the influence of the second scanning signal transmitted on the second scanning signal line Scan on the first conductive part 31 when the potential jumps, and improve the stability of the first conductive connection part 30.

[0145] The third type: along the thickness direction of the substrate 10, the first shield pattern 51 is located between two scan signal lines (the first scan signal line Gate and the second scan signal line Scan) and the first conductive portion 31 of the first conductive connection portion 30. That is, the orthographic projections of a portion of the first shield pattern 51, the first conductive portion 31 of the first conductive connection portion 30, and the first scan signal line Gate on the substrate 10 overlap, and the orthographic projections of another portion of the first shield pattern 51, the first conductive portion 31 of the first conductive connection portion 30, and the second scan signal line Scan on the substrate 10 overlap.

[0146] This arrangement is equivalent to using the first shield pattern 51 with a constant voltage signal to isolate the two scan signal lines (the first scan signal line Gate and the second scan signal line Scan) from the first conductive portion 31 of the first conductive connection portion 30. The first shield pattern 51 can simultaneously reduce the parasitic capacitance of the two scan signal lines and the first conductive portion 31, thereby reducing the impact of potential jumps of the signals transmitted on the two scan signal lines on the first conductive portion 31, further improving the stability of the first conductive connection portion 30.

[0147] Regardless of any of the above three methods, the first shielding pattern 51 can be used to stabilize the first conductive connection portion 30 (first node N1), thereby ensuring the stability of the driving current output by the driving transistor T3, which is beneficial to improving the uniformity of the brightness of the display panel 200.

[0148] It should be noted that when the angle formed by the thickness direction of the substrate 10 and the row direction X is within the range of 90°±5°, it can be considered that the thickness direction of the substrate 10 and the row direction X are perpendicular.

[0149] When the angle formed by the thickness direction of the substrate 10 and the column direction Y is within the range of 90°±5°, it can be considered that the thickness direction of the substrate 10 and the column direction Y are perpendicular.

[0150] Figure 10 is a measured timing diagram of a pixel driving circuit according to some embodiments. Figure 10 shows a measured timing diagram of a pixel driving circuit Q with a first shielding layer 50 and a measured timing diagram of a pixel driving circuit Q without the first shielding layer 50. Specifically, the solid line in Figure 10 represents the measured timing diagram of the pixel driving circuit Q with the first shielding layer 50, and the dashed line represents the measured timing diagram of the pixel driving circuit Q without the first shielding layer 50.

[0151] As shown in Figure 10, in the test of the actual product, the potential of the first node N1 of the pixel driving circuit Q after the first shielding layer 50 is provided is affected by the signal transmitted by the first scanning signal line Gate and the second scanning signal line Scan. Compared with the potential of the first node N1 of the pixel driving circuit Q after the first shielding layer 50 is not provided, the influence of the signal transmitted by the first scanning signal line Gate and the second scanning signal line Scan is reduced.

[0152] Specifically, simulation experiments show that, in the pixel driving circuit Q without the first shielding layer 50, the capacitance value of the parasitic capacitance between the first conductive connection portion 30 (first node) and the first scan signal line Gate is approximately 0.967fF, and the capacitance value of the parasitic capacitance between the first conductive connection portion 30 (first node) and the second scan signal line Scan is approximately 3.038fF. However, in the pixel driving circuit Q with the first shielding layer 50, the capacitance value of the parasitic capacitance between the first conductive connection portion 30 (first node) and the first scan signal line Gate can be reduced to approximately 0.086fF, and the capacitance value of the parasitic capacitance between the first conductive connection portion 30 (first node) and the second scan signal line Scan can be reduced to approximately 2.06fF.

[0153] The parasitic capacitance between the first conductive connection portion 30 (first node) and the first scan signal line Gate is reduced by approximately 91.1%, and the parasitic capacitance between the first conductive connection portion 30 (first node) and the second scan signal line Scan is reduced by approximately 32.2%. In other words, the parasitic capacitance between the first conductive connection portion 30 (first node) and the two scan signal lines can be significantly reduced, thereby reducing the influence of the two scan signal lines on the first conductive connection portion 30 (first node), thereby improving the stability of the potential of the first conductive connection portion 30 (first node).

[0154] In summary, the array substrate 100 provided in some embodiments of the present disclosure is additionally provided with a first shielding layer 50, and the first shielding layer 50 is disposed between the film layer where the first conductive portion 31 of the first conductive connection portion 30 is located and the film layer where the two scan signal lines (the first scan signal line Gate and the second scan signal line Scan) are located. Furthermore, the orthographic projection of the first shielding pattern 51 of the first shielding layer 50 on the substrate 10 is arranged to overlap with the first overlapping region; and / or, the orthographic projection of the first shielding pattern 51 of the first shielding layer 50 on the substrate 10 is arranged to overlap with the second overlapping region. The orthographic projection of the first scan signal line Gate on the substrate 10 and the orthographic projection of the first conductive portion 31 of the first conductive connection portion 30 on the substrate 10 form an overlapping region as the first overlapping region. The orthographic projection of the second scan signal line Scan on the substrate 10 and the orthographic projection of the first conductive portion 31 of the first conductive connection portion 30 on the substrate 10 form an overlapping region as the second overlapping region.

[0155] Based on this, the first shielding pattern 51 is used to isolate at least one of the two scanning signal lines from the first conductive portion 31 of the first conductive connection portion 30, thereby reducing the impact of signal potential jumps transmitted on the scanning signal line on the first conductive portion 31, further improving the stability of the first conductive connection portion 30. In other words, the stability of the potential of the first node N1 in the pixel driving circuit Q can be better improved, thereby ensuring the stability of the driving current output by the driving transistor T3, which is conducive to improving the uniformity of the brightness of the display panel 200.

[0156] The above embodiment mainly introduces how to improve the voltage stability of the first node N1 (as shown in FIG5 ) by using the first shielding pattern 51. The following first introduces the position arrangement of each transistor in the pixel driving circuit Q, and then introduces the specific structure of the first shielding pattern 51.

[0157] In some embodiments, as shown in Figure 9, along the column direction Y, the first reset transistor T1, the data writing transistor T4 and the compensation transistor T2 are located on the same side of the driving transistor T3, and the first light-emitting control transistor T5, the second light-emitting control transistor T6 and the second reset transistor T7 are located on the other side of the driving transistor T3.

[0158] The compensation transistor T2 is located between the first reset transistor T1 and the driving transistor T3 along the column direction Y. The data writing transistor T4 overlaps with the first conductive connection portion 30 along the row direction X.

[0159] Along the column direction Y, the first emission control transistor T5, the second emission control transistor T6, and the second reset transistor T7 are sequentially arranged away from the drive transistor T3, with the first emission control transistor T5 being adjacent to the drive transistor T3. Because the first electrode Cst-1 of the storage capacitor Cst is reused as the control electrode c3 of the drive transistor T3, arranging the first emission control transistor T5 adjacent to the drive transistor T3 facilitates electrical connection between the second electrode b5 of the first emission control transistor T5 and the second electrode Cst-2 of the storage capacitor, thereby achieving electrical connection between the second electrode b5 of the first emission control transistor T5 and the first power signal line VDD.

[0160] The second light-emitting control transistor T6 is located between the first light-emitting control transistor T5 and the second reset transistor T7, so that the second light-emitting control transistor T6 is closer to the driving transistor T3 relative to the second reset transistor T7, so that the first electrode a6 of the second light-emitting control transistor T6 is electrically connected to the second electrode b3 of the driving transistor T3.

[0161] In addition, the second light emission control transistor T6 and the second reset transistor T7 may be disposed adjacent to each other to facilitate electrical connection between the second electrode b6 of the second light emission control transistor T6 and the second electrode b7 of the second reset transistor T7.

[0162] Based on the above arrangement, it is helpful to simplify the layout of the array substrate 100 and prevent the problem of short circuit caused by the need to wind the conductive parts in the array substrate 100.

[0163] Next, the arrangement of each film layer in the array substrate 100 is introduced.

[0164] Figure 11 is a film layer diagram of the semiconductor layer and the first gate metal layer in Figure 9, Figure 12 is a film layer diagram of the semiconductor layer, the first gate metal layer and the second gate metal layer in Figure 9, and Figure 13 is a film layer diagram of the semiconductor layer, the first gate metal layer, the second gate metal layer and the first routing metal layer in Figure 9.

[0165] In some embodiments, in combination with Figures 9 and 11 to 13, the driving circuit layer 20 (as shown in Figure 4) includes a semiconductor layer POLY, a first gate metal layer Gate1, a second gate metal layer Gate2, a first routing metal layer SD1 and a second routing metal layer SD2 stacked on the substrate 10.

[0166] 9 and 11 , the semiconductor layer POLY is located on the substrate 10 , and the semiconductor layer POLY may include the first electrodes and the second electrodes of the seven transistors in the aforementioned “7T1C” pixel driving circuit.

[0167] Exemplarily, the semiconductor layer POLY may include a first electrode a1 and a second electrode b1 of a first reset transistor T1, a first electrode a2 and a second electrode b2 of a compensation transistor T2, a first electrode a3 and a second electrode b3 of a drive transistor T3, and a first electrode a4 and a second electrode b4 of a data write transistor T4. In the case of an "8T1C" pixel drive circuit Q, the semiconductor layer POLY may further include a first electrode and a second electrode of a third reset transistor.

[0168] 9 and 11 , the first gate metal layer Gate1 is located on a side of the semiconductor layer POLY away from the substrate 10. The first gate metal layer Gate1 may include control electrodes of seven transistors in the aforementioned “7T1C” pixel driving circuit.

[0169] Exemplarily, the first gate metal layer Gate1 may include a control electrode c1 of the first reset transistor T1, a control electrode c2 of the compensation transistor T2, a control electrode c3 of the drive transistor T3, and a control electrode c4 of the data write transistor T4. In the case of an "8T1C" pixel drive circuit Q, the first gate metal layer Gate1 may also include a control electrode of a third reset transistor.

[0170] Exemplarily, the material of the first gate metal layer Gate1 includes a conductive metal, and the conductive metal may include at least one of aluminum, copper, and molybdenum, but the present disclosure is not limited thereto.

[0171] Illustratively, a first gate insulating layer is provided between the semiconductor layer POLY and the first gate metal layer Gate1 , and the first gate insulating layer electrically insulates the semiconductor layer POLY from the first gate metal layer Gate1 .

[0172] For example, the material of the first gate insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the first gate insulating layer may include silicon dioxide, but the present disclosure is not limited thereto.

[0173] It should be noted that, as shown in FIG9 , the orthographic projection of the semiconductor layer POLY on the substrate 10 overlaps with the orthographic projection of the first gate metal layer Gate1 on the substrate 10. The portion of the semiconductor layer POLY covered by the first gate metal layer Gate1 constitutes the channel portion of each transistor, and the portion of the semiconductor layer POLY not covered by the first gate metal layer Gate1 is a conductive portion, constituting the first electrode or the second electrode of each transistor.

[0174] In addition, the first gate metal layer Gate1 further includes a plurality of second enable signal lines EM2 , which extend along the row direction X and are arranged in the column direction Y.

[0175] Exemplarily, the second enable signal line EM2 includes a first portion, the orthographic projection of the first portion of the second enable signal line EM2 on the substrate 10 overlaps with the semiconductor layer POLY, and the first portion of the second enable signal line EM2 is multiplexed as the control electrode c6 of the second light emitting control transistor T6.

[0176] Based on this, the control electrode c6 of the second light-emitting control transistor T6 does not need to be manufactured separately, and the control electrode c6 of the second light-emitting control transistor T6 and the second enable signal line EM2 do not need to be provided with a conductive part to achieve electrical connection between the two, which can simplify the process of the array substrate 100.

[0177] As shown in Figures 9 and 12 , the second gate metal layer Gate2 is located on a side of the first gate metal layer Gate1 away from the semiconductor layer POLY. The second gate metal layer Gate2 may include multiple first initialization signal lines Vinit1 and multiple second initialization signal lines Vinit2. The multiple first initialization signal lines Vinit1 extend along the row direction X and are arranged in the column direction Y. The multiple second initialization signal lines Vinit2 also extend along the row direction X and are arranged in the column direction Y.

[0178] The second gate metal layer Gate2 may further include a plurality of first enable signal lines EM1 , which extend along a row direction X and are arranged in a column direction Y.

[0179] Furthermore, the first plate Cst-1 of the storage capacitor Cst can be located in the first gate metal layer Gate1, and the second plate Cst-2 of the storage capacitor Cst can be located in the second gate metal layer Gate2. The orthographic projection of the second plate Cst-2 of the storage capacitor Cst on the substrate 10 at least partially overlaps with the orthographic projection of the first plate Cst-1 of the storage capacitor Cst on the substrate 10 to form the storage capacitor Cst.

[0180] For example, the first plate Cst-1 of the storage capacitor Cst located on the first gate metal layer Gate1 can be reused as the control electrode c3 of the drive transistor T3. This eliminates the need for a separate control electrode c3 of the drive transistor T3, simplifying the manufacturing process of the pixel drive circuit Q. Furthermore, the second plate Cst-2 of the storage capacitor Cst can be directly electrically connected to the control electrode c1 of the drive transistor T3, eliminating the need for a separate connection, which also facilitates the layout of the pixel drive circuit Q.

[0181] For example, the second gate metal layer Gate2 may be made of the same material as the first gate metal layer Gate1. It is understood that in other examples, the second gate metal layer Gate2 may be made of a different material than the first gate metal layer Gate1. The embodiments of the present disclosure are not limited thereto.

[0182] For example, a second gate insulating layer may be provided between the second gate metal layer Gate2 and the first gate metal layer Gate1 , so as to electrically insulate the second gate metal layer Gate2 from the first gate metal layer Gate1 .

[0183] For example, the material of the second gate insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the second gate insulating layer may include silicon dioxide, but the present disclosure is not limited thereto.

[0184] 9 and 13 , the first routing metal layer SD1 is located on a side of the second gate metal layer Gate2 away from the first gate metal layer Gate1. The first routing metal layer SD1 includes a plurality of first scan signal lines Gate and a plurality of second scan signal lines Scan.

[0185] A plurality of first scanning signal lines Gate extend along the row direction X and are arranged in the column direction Y. One first scanning signal line Gate is electrically connected to a control electrode c4 of a data writing transistor T4 of a row of pixel driving circuits Q.

[0186] Multiple second scanning signal lines Scan extend along the row direction X and are arranged in the column direction Y. One second scanning signal line Scan is electrically connected to the control electrode c3 of the compensation transistor T2 of a row of pixel driving circuits Q. Along the column direction Y, the second scanning signal line Scan is located between the first scanning signal line Gate and the driving transistor T3.

[0187] The first routing metal layer SD1 further includes a plurality of first enable signal lines EM1, a plurality of first reset signal lines R1, and a plurality of second reset signal lines R2. The plurality of first enable signal lines EM1, the plurality of first reset signal lines R1, and the plurality of second reset signal lines R2 all extend along the row direction X and are arranged in the column direction Y.

[0188] The row direction X and the column direction Y are both parallel to the substrate 10 and are arranged to intersect.

[0189] In some examples, the row direction X and the column direction Y may be approximately perpendicular, and in this case, the angle between the row direction X and the column direction Y is approximately 90°. For example, the angle between the row direction X and the column direction Y may be 85°, 90°, or 95°.

[0190] Exemplarily, the material package of the first wiring metal layer SD1 may be a titanium (Ti)-aluminum (Al)-titanium (Ti) multi-layer composite material.

[0191] For example, a first planarization layer (PLN) is provided between the first wiring metal layer SD1 and the second gate metal layer Gate2 to electrically insulate the first wiring metal layer SD1 from the second gate metal layer Gate2.

[0192] Exemplarily, the material of the first planarization layer is generally an organic material. For example, the material of the first planarization layer may include at least one of polyimide (English full name: Polyimide, English abbreviation: PI), acrylic-based polymer, or silicon-based polymer.

[0193] In addition, the first routing metal layer SD1 may include a plurality of conductive parts, and the conductive parts are used to connect transistors in the pixel driving circuit Q and signal lines.

[0194] In some examples, as shown in FIG. 13 , the plurality of conductive portions include a first transfer portion PAD1 , where the first transfer portion PAD1 is configured to electrically connect the first electrode a1 of the first reset transistor T1 and the first initialization signal line Vinit1 .

[0195] The plurality of conductive portions further include a second transfer portion PAD2 , which is used to electrically connect the first electrode a4 of the data writing transistor T4 and the data signal line Data.

[0196] The plurality of conductive portions further include a third transfer portion PAD3 , which is used to electrically connect the second electrode Cst- 2 of the storage capacitor Cst and the first electrode a5 of the first light emitting control transistor T5 .

[0197] The plurality of conductive portions further include a fourth transfer portion PAD4 , which is used to electrically connect the first electrode a7 of the second reset transistor T7 and the second initialization signal line Vinit2 .

[0198] The multiple conductive portions also include an anode adapter PAD5. One end of the anode adapter PAD5 is electrically connected to the second electrode b6 of the second light-emitting control transistor T6 and the second electrode b7 of the second reset transistor T7. The other end of the anode adapter PAD5 is electrically connected to the anode of the light-emitting device in the light-emitting device layer. This electrically connects the pixel driving circuit Q to the light-emitting device O.

[0199] The multiple conductive parts also include a sixth transfer part PAD6, one end of the sixth transfer part PAD6 includes a first part, the positive projection of the first part of the sixth transfer part PAD6 on the substrate 10 overlaps with the semiconductor layer POLY, and the first part of the sixth transfer part PAD6 is reused as the control electrode c5 of the first light-emitting control transistor T5.

[0200] Furthermore, the orthographic projection of the other end of the sixth adapter PAD6 on the substrate 10 overlaps with the orthographic projection of the first enable signal line EM1 on the substrate 10, so that the other end of the sixth adapter PAD6 is electrically connected to the first enable signal line EM1. For example, the other end of the sixth adapter PAD6 is electrically connected to the first enable signal line EM1 through a via.

[0201] With such configuration, the control electrode c5 of the first light emitting control transistor T5 can be electrically connected to the first enable signal line EM1 .

[0202] As shown in FIG. 9 , the second wiring metal layer SD2 is located on a side of the first wiring metal layer SD1 away from the first gate metal layer Gate1 .

[0203] In some examples, the material of the second routing metal layer SD2 can be the same as that of the first routing metal layer SD1. It is understood that the material of the second routing metal layer SD2 can be different from that of the first routing metal layer SD1. The embodiments of the present disclosure are not limited to this.

[0204] Exemplarily, a second planarization layer is provided between the second routing metal layer SD2 and the first routing metal layer SD1 , and the second planarization layer electrically insulates the second routing metal layer SD2 from the first routing metal layer SD1 .

[0205] Exemplarily, the material of the second planarization layer is generally an organic material. For example, the material of the second planarization layer may include at least one of polyimide (English full name: Polyimide, English abbreviation: PI), acrylic-based polymer, or silicon-based polymer.

[0206] In addition, the second wiring metal layer SD2 may further include a plurality of first power signal lines VDD and a plurality of data signal lines Data.

[0207] A plurality of first power signal lines VDD are arranged along the row direction X and extend in the column direction Y. The first power signal lines VDD are configured to provide a first power signal, which is a constant voltage signal, to the pixel driving circuit Q. The first power signal lines VDD can be electrically connected to the third adapter PAD3 through a via, thereby electrically connecting the third adapter PAD3 to the second plate Cst-2 of the storage capacitor Cst and the first electrode a5 of the first emission control transistor T5.

[0208] In some examples, the orthographic projection of the first power signal line VDD on the substrate 10 overlaps with the orthographic projections of the driving transistor T3 and the first emission control transistor T5 on the substrate 10. Based on this, the first power signal line VDD can be electrically connected to the second plate Cst-2 of the storage capacitor Cst and the first electrode a5 of the first emission control transistor T5.

[0209] A plurality of data signal lines Data are arranged along a row direction X and extend in a column direction Y. The data signal lines Data are configured to provide data write signals to the pixel driving circuit Q. The data signal lines Data can be electrically connected to the second adapter portion PAD2 through a via, and thereby electrically connected to the first electrode a4 of the data write transistor T4 via the second adapter portion PAD2.

[0210] In some examples, the data signal line Data is located on a side of the first power signal line VDD away from the driving transistor T3 along the row direction X. That is, the data signal line Data can be placed closer to the data writing transistor T4 relative to the first power signal line VDD, thereby preventing the data signal line Data from being short-circuited with other conductive parts when electrically connected to the data writing transistor T4 through a via.

[0211] In some embodiments, as shown in FIG9 , based on the film layer division of the pixel driving circuit Q in the array substrate 100, the first scan signal line Gate and the second scan signal line Scan are located in the first routing metal layer SD1, and the first conductive portion 31 of the first conductive connection portion 30 can be located in the semiconductor layer POLY. One end of the first conductive portion 31 is electrically connected to the second electrode b1 of the first reset transistor T1, and the other end of the first conductive portion 31 is electrically connected to the second electrode b2 of the compensation transistor T2. For example, the other end of the first conductive portion 31 can be reused as the second electrode b2 of the compensation transistor T2.

[0212] Furthermore, the first conductive connection portion 30 also includes a second conductive portion 32, which is located on the first metal trace layer SD1. The other end of the first conductive portion 31 can also be electrically connected to the control electrode c3 of the drive transistor T3 via the second conductive portion 32. Therefore, the first conductive connection portion 30 utilizes the first conductive portion 31 and the second conductive portion 32 to electrically connect the second electrode b1 of the first reset transistor T1, the second electrode b2 of the compensation transistor T2, and the control electrode c3 of the drive transistor T3.

[0213] Since the shielding layer 50 is located in the film layer between the film layer where the two scanning signal lines (the first scanning signal line Gate and the second scanning signal line Scan) are located and the film layer where the first conductive part 31 of the first conductive connection part 30 is located, the first shielding pattern 51 of the shielding layer 50 is used to isolate the two scanning signal lines and the first conductive part 31 of the first conductive connection part 30, thereby improving the voltage stability of the first conductive connection part 30.

[0214] Based on this, the shielding layer 50 is located in a film layer between the first wiring metal layer SD1 and the semiconductor layer POLY. For example, the shielding layer 50 can be located in the second gate metal layer Gate2. Alternatively, when the array substrate 100 includes another metal layer located between the second gate metal layer Gate2 and the first wiring metal layer SD1, the shielding layer 50 can be located in the second gate metal layer Gate2 or another gate metal layer. The embodiments of the present disclosure are not limited to this.

[0215] In some embodiments, as shown in Figures 9 and 12, since the second plate Cst-2 of the storage capacitor Cst in the pixel driving circuit Q is electrically connected to the first power signal line VDD, the first power signal line VDD is configured to provide a first power signal, which is a constant voltage signal.

[0216] Based on this, the first shielding layer 50 can be set to be electrically connected to the second plate Cst-2 of the storage capacitor Cst, so that the first shielding layer 50 can receive the constant voltage signal (first power signal) provided by the first power signal line VDD to achieve the first shielding layer 50 having a constant voltage signal.

[0217] With this configuration, no separate constant voltage signal line is required to transmit the constant voltage signal to the first shielding layer 50 , which can reduce the number of signal lines of the array substrate 100 and facilitate the layout of the array substrate 100 .

[0218] In some embodiments, as shown in Figures 9 and 12, when the first shielding layer 50 is electrically connected to the second plate Cst-2 of the storage capacitor Cst, since the second plate Cst-2 of the storage capacitor Cst is located in the second gate metal layer Gate2, the first shielding layer 50 can be set to be on the same layer as the second plate Cst-2 of the storage capacitor Cst.

[0219] This arrangement satisfies the requirement that the first shielding layer 50 be located between the first wiring metal layer SD1 and the semiconductor layer POLY to isolate the two scanning signal lines from the first conductive portion 31 of the first conductive connection portion 30. Furthermore, the first shielding layer 50 and the second electrode plate Cst-2 of the storage capacitor Cst can be formed using the same mask through a single patterning process, thereby simplifying the manufacturing process of the array substrate 100.

[0220] It should be noted that "same layer" refers to a layer structure formed using the same film-forming process to form a specific pattern, and then using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0221] The following description will be made by taking the first shielding layer 50 and the second electrode plate Cst- 2 of the storage capacitor Cst as an example.

[0222] In some embodiments, as shown in Figure 13, the second gate metal layer Gate2 also includes a first auxiliary connection portion G1, one end of the first auxiliary connection portion G1 is electrically connected to the second plate Cst-2 of the storage capacitor Cst, and the other end of the first auxiliary connection portion G1 is electrically connected to the first shielding pattern 51 to achieve electrical connection between the second plate Cst-2 of the storage capacitor Cst and the first shielding pattern 51.

[0223] Along the row direction X, the first auxiliary connection portion G1 is located between the compensation transistor T2 and the second conductive connection portion 40. Since the control electrode c2 of the compensation transistor T2 is located on the first gate metal layer Gate1, when the first auxiliary connection portion G1 is formed on the second gate metal layer Gate2 on the side of the first gate metal layer Gate1 away from the substrate 10, it is equivalent to forming the first auxiliary connection portion G1 on the side of the control electrode c2 of the compensation transistor T2 away from the substrate 10.

[0224] Because the control electrode c2 of the compensation transistor T2 has a certain thickness, a step is formed on the surface of the second gate insulation layer (the insulation layer between the first gate metal layer Gate1 and the second gate metal layer Gate2) away from the substrate 10. This step can easily cause cracks to form on the first auxiliary connection portion G1 formed on the side of the second gate insulation layer away from the substrate 10, affecting the quality of the first auxiliary connection portion G1 and, in turn, the voltage stabilization effect of the first shielding pattern 51.

[0225] Based on this, the orthographic projection of the first auxiliary connection portion G1 on the substrate 10 is set to not overlap with the orthographic projection of the control electrode c2 of the compensation transistor T2 on the substrate 10 to prevent cracks from occurring in the first auxiliary connection portion G1.

[0226] Furthermore, since the second electrode b2 of the compensation transistor T2 located in the semiconductor layer POLY needs to be electrically connected to the second conductive connection portion 40 located on the first routing metal layer SD1 through a via, if the orthographic projection of the first auxiliary connection portion G1 on the substrate 10 overlaps with the orthographic projection of the second electrode b2 of the compensation transistor T2 on the substrate 10, the first auxiliary connection portion G1 may be easily formed in the via, resulting in a short circuit with the second electrode b2 of the compensation transistor T2.

[0227] Based on this, the orthographic projection of the first auxiliary connection portion G1 on the substrate 10 can be set to have no overlap with the orthographic projection of the second electrode b2 of the compensation transistor T2 on the substrate 10 to prevent the first auxiliary connection portion G1 and the second electrode b2 of the compensation transistor T2 from being short-circuited.

[0228] The above embodiment, combined with the relevant drawings, primarily describes the film position of the first shielding layer 50 in the array substrate 100 and the corresponding positional definition. The following describes the specific structure and positional definition of the first shielding pattern 51 of the first shielding layer 50 in combination with the relevant drawings, so as to facilitate the use of the first shielding pattern 51 to achieve a voltage stabilization effect at the first node N1.

[0229] FIG14 is a partial enlarged view of M in FIG13 .

[0230] In some embodiments, as shown in Figures 9, 13, and 14, the first conductive portion 31 includes a first conductive sub-portion 311 and a second conductive sub-portion 312 that are connected. The orthographic projection of the first conductive sub-portion 311 on the substrate 10 overlaps with the orthographic projection of the first scan signal line on the substrate 10, and the orthographic projection of the second conductive sub-portion 312 on the substrate 10 overlaps with the orthographic projection of the second scan signal line Scan on the substrate 10. Based on the above structure, the position of the first shielding pattern 51 includes the following three situations.

[0231] The first type: when the orthographic projection of the first conductive sub-portion 311 on the substrate 10 overlaps with the orthographic projection of the first scanning signal line Gate on the substrate 10, the orthographic projection of the first conductive sub-portion 311 on the substrate 10 can be set to be within the boundary of the orthographic projection of the first shielding pattern 51 on the substrate 10.

[0232] Based on this, the first shielding pattern 51 can be used to completely cover the first conductive sub-section 311, so as to better isolate the first conductive sub-section 311 and the first scanning signal line Gate, reduce the parasitic capacitance between the first conductive sub-section 311 and the first scanning signal line Gate, and improve the impact of the voltage jump of the first scanning signal transmitted by the first scanning signal line Gate on the first conductive sub-section 311, improve the impact of the first scanning signal line Gate on the first conductive connection part 30 (first node N1), and improve the stability of the driving transistor T3.

[0233] Exemplarily, the portion where the orthographic projection of the first conductive portion 31 on the substrate 10 overlaps with the orthographic projection of the first scan signal line Gate on the substrate 10 is the first conductive sub-portion 311. Based on this, the orthographic projection of the first conductive sub-portion 311 on the substrate 10 is set within the boundary of the orthographic projection of the first shielding pattern 51 on the substrate 10. This is equivalent to using the first shielding pattern 51 to completely cover the portion where the orthographic projection of the first conductive portion 31 and the first scan signal line Gate on the substrate 10 overlap.

[0234] Based on this, the influence of the voltage jump of the first scanning signal transmitted by the first scanning signal line Gate on the first conductive connection portion 30 can be further reduced, thereby improving the stability of the driving transistor T3.

[0235] The second type: when the orthographic projection of the second conductive sub-portion 312 on the substrate 10 overlaps with the orthographic projection of the second scanning signal line Scan on the substrate 10, the orthographic projection of the second conductive sub-portion 312 on the substrate 10 can be set to be within the boundary of the orthographic projection of the first shielding pattern 51 on the substrate 10.

[0236] Based on this, the first shielding pattern 51 can be used to completely cover the second conductive sub-section 312, so as to better isolate the second conductive sub-section 312 and the second scanning signal line Scan, reduce the parasitic capacitance between the second conductive sub-section 312 and the second scanning signal line Scan, and improve the impact of the voltage jump of the first scanning signal transmitted by the second scanning signal line Scan on the second conductive sub-section 312, improve the impact of the second scanning signal line Scan on the first conductive connection part 30 (first node N1), and improve the stability of the driving transistor T3.

[0237] Exemplarily, the portion where the orthographic projection of the first conductive portion 31 on the substrate 10 overlaps with the orthographic projection of the second scan signal line Scan on the substrate 10 is the second conductive sub-portion 312. Based on this, the orthographic projection of the second conductive sub-portion 312 on the substrate 10 is set to be within the boundary of the orthographic projection of the first shielding pattern 51 on the substrate 10. This is equivalent to using the first shielding pattern 51 to completely cover the portion where the orthographic projection of the first conductive portion 31 and the second scan signal line Scan on the substrate 10 overlap.

[0238] Based on this, the influence of the voltage jump of the first scanning signal transmitted by the second scanning signal line Scan on the first conductive connection portion 30 can be further reduced, thereby improving the stability of the driving transistor T3.

[0239] The third type: when the orthographic projection of the first conductive sub-section 311 on the substrate 10 overlaps with the orthographic projection of the first scanning signal line Gate on the substrate 10, and the orthographic projection of the second conductive sub-section 312 on the substrate 10 overlaps with the orthographic projection of the second scanning signal line Scan on the substrate 10, the orthographic projection of the first conductive sub-section 311 on the substrate 10 and the orthographic projection of the second conductive sub-section 312 on the substrate 10 are set to be within the boundary of the orthographic projection of the first shielding pattern 51 on the substrate 10.

[0240] Based on this, the first shielding pattern 51 can be used to completely cover the first conductive sub-section 311 and the second conductive sub-section 312 in the first conductive section 30, which can reduce the impact of the voltage jump of the signal transmitted by the two scanning signal lines (the first scanning signal line Gate and the second scanning signal line Scan) on the first conductive sub-section 311, improve the impact of the two scanning signal lines on the first conductive connection section 30 (the first node N1), and improve the stability of the driving transistor T3.

[0241] In some embodiments, in combination with Figures 9, 13 and 14, the first conductive portion 31 also includes a third conductive sub-portion 313, and the orthographic projection of the third conductive sub-portion 313 on the substrate 10 does not overlap with the orthographic projections of the two scanning signal lines (the first scanning signal line Gate and the second scanning signal line Scan) on the substrate 10. One end of the third conductive sub-portion 313 is electrically connected to the first conductive sub-portion 311, and the other end of the third conductive sub-portion 313 is electrically connected to the second conductive sub-portion 312.

[0242] Although the orthographic projections of the third conductive sub-section 313 and the two scan signal lines on the substrate 10 do not overlap, since the third conductive sub-section 313 is used to electrically connect the first conductive sub-section 311 and the second conductive sub-section 312, the third conductive sub-section 313 is relatively close to the two scan signal lines. This creates parasitic capacitance between the third conductive sub-section 313 and the two scan signal lines, and the potential of the third conductive sub-section 313 is affected by the two scan signal lines. Furthermore, the potential of the third conductive sub-section 313 is directly affected by the potentials of the first conductive sub-section 311 and the second conductive sub-section 312.

[0243] Based on this, when the orthographic projection of the first conductive sub-section 311 on the substrate 10 overlaps with the orthographic projection of the first scanning signal line Gate on the substrate 10, and the orthographic projection of the second conductive sub-section 312 on the substrate 10 overlaps with the orthographic projection of the second scanning signal line Scan on the substrate 10, the orthographic projection of the third conductive sub-section 313 on the substrate 10 can be set to overlap with the orthographic projection of the first shielding pattern 51 on the substrate 10.

[0244] The first shielding pattern 51 is used to increase the capacitance at the location of the third conductive sub-portion 313, thereby enhancing the stability of the potential at the location of the third conductive sub-portion 313. Thus, the first shielding pattern 51 can be used to mitigate the influence of the two scanning signal lines on the first conductive connection portion 30 (first node N1), thereby improving the stability of the driving transistor T3.

[0245] In some examples, in combination with Figures 9, 13 and 14, when the orthographic projection of the first conductive sub-portion 311 on the substrate 10 and the orthographic projection of the second conductive sub-portion 312 on the substrate 10 are both located within the boundary of the orthographic projection of the first shielding pattern 51 on the substrate 10, the orthographic projection of the third conductive sub-portion 313 on the substrate 10 is set to be located within the boundary of the orthographic projection of the first shielding pattern 51 on the substrate 10.

[0246] Based on this, the first shielding pattern 51 can be used to further increase the capacitance at the location of the third conductive sub-portion 313, thereby better enhancing the stability of the potential at the location of the third conductive sub-portion 313. In this way, the first shielding pattern 51 can be used to better reduce the influence of the two scanning signal lines on the first conductive connection portion 30 (first node N1), thereby improving the stability of the driving transistor T3.

[0247] In some embodiments, as shown in conjunction with Figures 9, 13, and 14, along the column direction Y, the first shield pattern 51 includes a first edge L1 and a second edge L2, with the first edge L1 being located on a side of the second edge L2 away from the driving transistor T3. When the orthographic projections of the first conductive sub-portion 311 and the second conductive sub-portion 312 on the substrate 10 are both within the boundaries of the orthographic projection of the first shield pattern 51 on the substrate 10, the first shield pattern 51 may extend outward relative to the first conductive sub-portion 311 and the second conductive sub-portion 312 of the first conductive portion 31 in the following three situations.

[0248] The first method is to set a first minimum distance D1 between the orthographic projection of the first edge L1 on the substrate 10 and the orthographic projection of the side F1 of the first conductive sub-portion 311 away from the second conductive sub-portion 312 on the substrate 10 to be greater than or equal to 1 μm.

[0249] This is equivalent to expanding the first edge L1 of the first shielding pattern 51 relative to the first conductive sub-portion 311 by more than 1 μm (including 1 μm), which can not only increase the size of the first shielding pattern 51 and enhance the voltage stabilization effect of the first shielding pattern 51, but also facilitate the first shielding pattern 51 to completely cover the first conductive sub-portion 311, preventing the problem of the first shielding pattern 51 not being able to completely cover the first conductive sub-portion 311 due to process errors, thereby improving the isolation effect of the first shielding pattern 51.

[0250] In some examples, the first minimum distance D1 is greater than or equal to 2 μm, which can further enhance the voltage stabilizing effect of the shielding pattern 51 and further improve the isolation effect of the first shielding pattern 51 .

[0251] Exemplarily, the first minimum distance D1 is approximately 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm.

[0252] Taking the first minimum spacing D1 of approximately 1 μm as an example: due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error floating range of the first minimum spacing D1 is within 5%×1 μm, it can also be considered that the size of the first minimum spacing D1 satisfies the requirement of being equal to 1 μm.

[0253] In some embodiments, as shown in FIG9 , FIG13 , and FIG14 , the first reset transistor T1 is located on a side of the first scan signal line Gate away from the second scan signal line Scan along the column direction Y. That is, along the column direction Y, the first reset transistor T1 and the first scan signal line Gate are adjacently disposed.

[0254] Based on this, when expanding the first shielding pattern 51, it is necessary to limit the orthographic projection of the first shielding pattern 51 on the substrate 10 to not overlap with the orthographic projection of the first reset transistor T1 on the substrate 10. That is, along the column direction Y, there is a gap between the first edge L1 of the first shielding pattern 51 and the first reset transistor T1.

[0255] This prevents the first reset transistor T1 from forming a parasitic capacitance with the first shield pattern 51, preventing the control electrode of the first reset transistor T1 from affecting the potential of the first shield pattern 51 when receiving the first reset signal, thereby reducing the voltage stabilizing effect of the first shield pattern 51 on the first conductive connection portion 30. Furthermore, the first shield pattern 51 is prevented from affecting the control electrode of the first reset transistor T1, thereby preventing the first reset transistor T1 from affecting its open state and thus affecting the reset effect on the first conductive connection portion 30 (first node N1).

[0256] Second: a second minimum distance D2 between the orthographic projection of the second edge L2 on the substrate 10 and the orthographic projection of the side F2 of the second conductive sub-portion 312 away from the first conductive sub-portion 311 on the substrate 10 may be set to be greater than or equal to 1 μm.

[0257] This is equivalent to expanding the second edge L2 of the first shielding pattern 51 relative to the second conductive sub-portion 312 by more than 1 μm (including 1 μm), which can not only increase the size of the first shielding pattern 51 and enhance the voltage stabilization effect of the first shielding pattern 51, but also facilitate the first shielding pattern 51 to completely cover the second conductive sub-portion 312, preventing the problem of the first shielding pattern 51 not being able to completely cover the second conductive sub-portion 312 due to process errors, thereby improving the isolation effect of the first shielding pattern 51.

[0258] In some examples, the second minimum distance D2 is greater than or equal to 2 μm, which can further enhance the voltage stabilization effect of the shielding pattern 51 and further improve the isolation effect of the first shielding pattern 51 .

[0259] Exemplarily, the second minimum distance D2 is approximately 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm.

[0260] Taking the second minimum spacing D2 of approximately 1 μm as an example: due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error floating range of the second minimum spacing D2 is within 5%×1 μm, it can also be considered that the size of the second minimum spacing D2 satisfies the requirement of being equal to 1 μm.

[0261] In some embodiments, as shown in FIG. 9 , FIG. 13 , and FIG. 14 , along the column direction Y, the second scan signal line Scan is located between the first scan signal line Gate and the driving transistor T3 .

[0262] The control electrode c3 of the driving transistor T3 is located on the first gate metal layer Gate1. When the first shield pattern 51 is formed in a film layer above the first gate metal layer Gate1, for example, when the first shield pattern 51 is located on the second gate metal layer Gate2, it is equivalent to forming the first shield pattern 51 on the side of the control electrode c3 of the driving transistor T3 away from the substrate 10.

[0263] Because the control electrode c3 of the driving transistor T3 has a certain thickness, a step is formed on the surface of the second gate insulating layer (the insulating layer between the first gate metal layer Gate1 and the second gate metal layer Gate2) away from the substrate 10. This step can easily cause cracks to form on the first shielding pattern 51 formed on the side of the second gate insulating layer away from the substrate 10, affecting the voltage stabilization effect of the first shielding pattern 51.

[0264] Based on this, when expanding the first shield pattern 51, the orthographic projection of the first shield pattern 51 on the substrate 10 must be limited to not overlap with the orthographic projection of the drive transistor T3 on the substrate 10. That is, along the column direction Y, a gap exists between the second edge L2 of the first shield pattern 51 and the first reset transistor T1. This can alleviate the problem of cracks in the first shield pattern 51 caused by the drive transistor T3.

[0265] In some examples, the second electrode b2 of the compensation transistor T2 is located between the drive transistor T3 and the second scan signal line Scan along the column direction Y. That is, the second scan signal line Scan and the second electrode b2 of the compensation transistor T2 are adjacent to each other along the column direction Y. The second electrode b2 of the compensation transistor T2 must be electrically connected to the second conductive connection portion 40 on the first routing metal layer SD1 through a via. If the orthographic projection of the first shielding pattern 51 on the substrate 10 overlaps with the orthographic projection of the second electrode b2 of the compensation transistor T2 on the substrate 10, the first shielding pattern 51 may be formed within the via, resulting in a short circuit with the second electrode b2 of the compensation transistor T2.

[0266] Based on this, when expanding the first shielding pattern 51, the orthographic projection of the first shielding pattern 51 on the substrate 10 must be limited to not overlap with the orthographic projection of the second electrode b2 of the compensation transistor T2. That is, along the column direction Y, a gap exists between the second edge L2 of the first shielding pattern 51 and the second electrode b2 of the compensation transistor T2. This prevents short circuits between the first shielding pattern 51 and the second electrode b2 of the compensation transistor T2.

[0267] The third type: a first minimum distance D1 between the orthographic projection of the first edge L1 on the substrate 10 and the orthographic projection of the side F1 of the first conductive sub-portion 311 away from the second conductive sub-portion 312 on the substrate 10 can be set to be greater than or equal to 1 μm, and a second minimum distance D2 between the orthographic projection of the second edge L2 on the substrate 10 and the orthographic projection of the side F2 of the second conductive sub-portion 312 away from the first conductive sub-portion 311 on the substrate 10 can be set to be greater than or equal to 1 μm.

[0268] This configuration is equivalent to simultaneously expanding the first edge L1 and the second edge L2 of the first shielding pattern 51 by more than 1 μm (inclusive), thereby increasing the size of the first shielding pattern 51 and enhancing the voltage stabilization effect of the first shielding pattern 51. It also facilitates the first shielding pattern 51 to completely cover the first conductive sub-portion 311 and the second conductive sub-portion 312, preventing the first shielding pattern 51 from being unable to completely cover the first conductive sub-portion 311 and the second conductive sub-portion 312 due to process errors and other reasons, thereby improving the isolation effect of the first shielding pattern 51.

[0269] In some embodiments, in combination with Figures 9, 13 and 14, when the orthographic projections of the first conductive sub-section 311 and the second conductive sub-section 312 on the substrate 10 are both within the boundaries of the orthographic projection of the first shielding pattern 51 on the substrate 10: the outward expansion of the first shielding pattern 51 relative to the first conductive sub-section 311 and the second conductive sub-section 312 in the first conductive section 31 includes the following three situations.

[0270] Type 1: Along the row direction X, the third minimum distance D3 between the orthographic projection of the edge of the first shielding pattern 51 on the substrate 10 and the orthographic projection of the boundary of the first conductive sub-portion 311 on the substrate 10 is greater than or equal to 1 μm. In the row direction X, the edge of the first shielding pattern 51 includes a third edge L3 and a fourth edge L4 that are oppositely disposed.

[0271] That is, the third minimum distance D3 between the third edge L3 of the first shielding pattern 51 projected on the substrate 10 and the boundary of the first conductive sub-portion 311 projected on the substrate 10 is greater than or equal to 1 μm, and the third minimum distance D3 between the fourth edge L4 of the first shielding pattern 51 projected on the substrate 10 and the boundary of the first conductive sub-portion 311 projected on the substrate 10 is greater than or equal to 1 μm.

[0272] This configuration is equivalent to expanding the third edge L3 and the fourth edge L4 of the first shielding pattern 51 by more than 1 μm (inclusive), which not only increases the size of the first shielding pattern 51 and enhances the voltage stabilization effect of the first shielding pattern 51. It also facilitates the first shielding pattern 51 to completely cover the first conductive sub-portion 311, preventing the first shielding pattern 51 from being unable to completely cover the first conductive sub-portion 311 due to process errors and other reasons, thereby improving the isolation effect of the first shielding pattern 51.

[0273] In some examples, the third minimum distance D3 is greater than or equal to 2 μm, which can further enhance the voltage stabilization effect of the shielding pattern 51 and further improve the isolation effect of the first shielding pattern 51 .

[0274] Exemplarily, the third minimum distance D3 is approximately 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm.

[0275] Taking the third minimum spacing D3 of approximately 1 μm as an example: due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error floating range of the third minimum spacing D3 is within 5%×1 μm, it can also be considered that the size of the third minimum spacing D3 satisfies the requirement of being equal to 1 μm.

[0276] Second: Along the row direction X, the fourth minimum spacing between the orthographic projection of the edge of the first shielding pattern 51 on the substrate 10 and the orthographic projection of the boundary of the first conductive sub-portion 311 on the substrate 10 is greater than or equal to 1 μm. In the row direction X, the edge of the first shielding pattern 51 includes a third edge L3 and a fourth edge L4 that are oppositely disposed.

[0277] That is, the fourth minimum distance D4 between the third edge L3 of the first shielding pattern 51 projected on the substrate 10 and the boundary of the second conductive sub-portion 312 projected on the substrate 10 is greater than or equal to 1 μm, and the fourth minimum distance D4 between the fourth edge L4 of the first shielding pattern 51 projected on the substrate 10 and the boundary of the second conductive sub-portion 312 projected on the substrate 10 is greater than or equal to 1 μm.

[0278] This configuration is equivalent to expanding the third edge L3 and the fourth edge L4 of the first shielding pattern 51 by more than 1 μm (inclusive), which not only increases the size of the first shielding pattern 51 and enhances the voltage stabilization effect of the first shielding pattern 51. It also facilitates the first shielding pattern 51 to completely cover the second conductive sub-portion 312, preventing the first shielding pattern 51 from being unable to completely cover the second conductive sub-portion 312 due to process errors and other reasons, thereby improving the isolation effect of the first shielding pattern 51.

[0279] In some examples, the fourth minimum distance D4 is greater than or equal to 2 μm, which can further enhance the voltage stabilization effect of the shielding pattern 51 and further improve the isolation effect of the first shielding pattern 51 .

[0280] Exemplarily, the fourth minimum distance D4 is approximately 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm.

[0281] Taking the fourth minimum spacing D4 of approximately 1 μm as an example: due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error floating range of the fourth minimum spacing D4 is within 5%×1 μm, it can also be considered that the size of the fourth minimum spacing D4 satisfies the requirement of being equal to 1 μm.

[0282] The third type: along the row direction X, the edge of the first shielding pattern 51 is projected onto the substrate 10, and the third minimum spacing D3 between the edge of the first conductive sub-portion 311 and the boundary of the projected sub-portion on the substrate 10 is greater than or equal to 1 μm, and the fourth minimum spacing between the edge of the first conductive sub-portion 311 and the boundary of the projected sub-portion on the substrate 10 is greater than or equal to 1 μm.

[0283] This configuration is equivalent to expanding the third edge L3 and the fourth edge L4 of the first shielding pattern 51 by more than 1 μm (inclusive), which not only increases the size of the first shielding pattern 51 and enhances the voltage stabilization effect of the first shielding pattern 51. It also facilitates the first shielding pattern 51 to completely cover the first conductive sub-portion 311 and the second conductive sub-portion 312, preventing the first shielding pattern 51 from being unable to completely cover the first conductive sub-portion 311 and the second conductive sub-portion 312 due to process errors and other reasons, thereby improving the isolation effect of the first shielding pattern 51.

[0284] It should be noted that, when the third edge L3 and the fourth edge L4 of the first shielding pattern 51 are expanded, it is possible to prevent the third edge L3 and the fourth edge L4 of the first shielding pattern 51 from overlapping with other structures in the pixel driving circuit Q to prevent affecting the life of the first shielding pattern 51 and the voltage stabilization effect.

[0285] The above embodiment mainly describes the outward expansion of the first shielding pattern 51 relative to the first conductive portion 31 in conjunction with the relevant drawings. The structure of the first shielding pattern 51 will be described below in conjunction with the relevant drawings.

[0286] 9 , 13 , and 14 , the first shield pattern 51 includes a first shielding sub-portion 511 extending along the row direction X and a second shielding sub-portion 512 extending along the column direction Y. That is, the orthographic projection of the first shield pattern 51 on the substrate 10 is L-shaped.

[0287] The extension direction of the second shielding sub-portion 512 is substantially parallel to the extension direction of the first conductive portion 31. The orthographic projection of the second shielding sub-portion 512 on the substrate 10 is arranged to overlap with the orthographic projection of the first conductive connecting portion 30 on the substrate 10. The second shielding sub-portion 512 of the first shielding pattern 51 is used to isolate the first conductive portion 31 of the first conductive connecting portion 30 from two scanning signal lines (a first scanning signal line Gate and a second scanning signal line Scan), thereby improving the stability of the driving transistor T3.

[0288] The orthographic projection of the first shielding sub-portion 511 on the substrate 10 does not overlap with the orthographic projection of the first conductive portion 31 on the substrate 10 , but does overlap with the orthographic projection of the second scan signal line Scan on the substrate 10 .

[0289] On the one hand, the first shielding sub-portion 511 can be used to increase the size of the first shielding pattern 51 to improve the voltage stabilizing effect of the first shielding pattern 51 on the first conductive connection portion 30 (first node). On the other hand, the first shielding sub-portion 511 can also be used to increase the overlapping area of ​​the orthographic projection of the first shielding pattern 51 and the second scan signal line Scan on the substrate 10 to further reduce the influence of the second scan signal line Scan on the first conductive connection portion 30 (first node), thereby improving the voltage stabilizing effect of the first shielding pattern 51 on the first conductive connection portion 30 (first node).

[0290] In addition, the first shielding pattern 51 can be electrically connected to the first auxiliary connection portion G1 through the first shielding sub-portion 511. As shown in the above structure, the first shielding sub-portion 511 is equivalent to extending the first shielding pattern 51 along the row direction X, which can facilitate the electrical connection between the first shielding pattern 51 and the first auxiliary connection portion G1 to prevent the orthographic projection of the first auxiliary connection portion G1 on the substrate 10 from overlapping with the orthographic projections of the poles of the compensation transistor T2 on the substrate 10, thereby causing related problems.

[0291] The above embodiment mainly describes the structure of the first shielding pattern 51 of the first shielding layer 50 with reference to the relevant drawings. The following describes other shielding patterns in the first shielding layer 50 with reference to the relevant drawings. For example, the first shielding layer 50 also includes a second shielding pattern 52 and a third shielding pattern 53.

[0292] In some embodiments, as shown in FIG. 9 and FIG. 12 , the first shielding layer 50 further includes a second shielding pattern 52 , and an orthographic projection of the second shielding pattern 52 on the substrate 10 overlaps with an orthographic projection of the second conductive connection portion 40 on the substrate 10 .

[0293] The second shielding pattern 52 and the second conductive connection portion 40 may form a parasitic capacitor, thereby increasing the capacitance of the second conductive connection portion 40 and enhancing the stability of the voltage of the second conductive connection portion 40 .

[0294] Based on this, the situation where the second conductive connection portion 40 is pulled by the AC signal transmitted by its adjacent signal line can be improved, thereby improving the stability of the second conductive connection portion 40 (second node). This is equivalent to improving the stability of the driving transistor T3, which is conducive to ensuring the brightness uniformity of the display panel 200.

[0295] In some embodiments, as shown in conjunction with FIG. 9 and FIG. 12 , an orthographic projection of the second shielding pattern 52 on the substrate 10 overlaps with an orthographic projection of a portion of the second conductive connection portion 40 on the substrate 10 .

[0296] On the one hand, the second shielding pattern 52 can be used to increase the capacitance of the second conductive connection part 40 and enhance the voltage stability of the second conductive connection part 40. On the other hand, it can also prevent the capacitance of the second conductive connection part 40 from being too large, which may lead to increased power consumption.

[0297] The proportion of some second conductive connection parts 40 to the entire second conductive connection parts 40 can be adjusted according to specific circumstances, and the embodiments of the present disclosure are not limited thereto.

[0298] In some embodiments, as shown in combination with FIG. 9 and FIG. 12 , the compensation transistor T2 is a dual-gate transistor, which can improve the leakage current of the compensation transistor T2 and reduce the impact on the first conductive connection portion 31 (first node).

[0299] The control electrode c2 of the compensation transistor T2 includes a first control electrode c21 and a second control electrode c22. The first gate metal layer Gate1 includes a first conductive pattern C, which includes the first control electrode c21 and the second control electrode c22 of the compensation transistor T2. The semiconductor layer POLY includes a first channel portion H1 and a second channel portion H2 of the compensation transistor T2. The semiconductor layer POLY also includes a second auxiliary connecting portion G2. One end of the second auxiliary connecting portion G2 is electrically connected to the first channel portion H1 of the compensation transistor T2, and the other end of the second auxiliary connecting portion G2 is electrically connected to the second channel portion H2 of the compensation transistor T2.

[0300] In some embodiments, as shown in conjunction with FIG9 and FIG12 , the first shielding layer 50 further includes a third shielding pattern 53. The orthographic projection of the third shielding pattern 53 on the substrate 10 overlaps with the orthographic projection of the second auxiliary connection portion G2 on the substrate 10. Based on this, the third shielding pattern 53 can be used to further compensate for the leakage current of the transistor T2 and reduce the impact on the first conductive connection portion 31 (first node).

[0301] In some embodiments, as shown in conjunction with FIG9 and FIG12 , the orthographic projection of the third shielding pattern 53 on the substrate 10 does not overlap with the orthographic projections of the first control electrode c21 and the second control electrode c22 of the compensation transistor T2 on the substrate 10. This prevents cracks in the third shielding pattern 53, which can occur when the third shielding pattern 53 is formed on a side away from the first control electrode c21 and the second control electrode c22 of the compensation transistor T2. This improves the quality of the third shielding pattern 53.

[0302] In some embodiments, as shown in conjunction with Figures 9 and 12 , the first conductive pattern C further includes a third auxiliary connection portion G3, which is located on a side of the first and second control electrodes c21 and c22 of the compensation transistor T2 that is away from the driving transistor T3. Based on the above structure, the third auxiliary connection portion G3 electrically connects the control electrode c2 (first and second control electrodes c21 and c22) of the compensation transistor T2 to the second scan signal line Scan.

[0303] This configuration allows the second scan signal line Scan to be moved away from the driving transistor T3, so that it is located between the second electrode b2 of the compensation transistor T2 and the first scan signal line Gate. This prevents the orthographic projection of the second scan signal line Scan on the substrate 10 from overlapping the second electrode b2 of the compensation transistor T2. This also prevents the second scan signal line Scan (located in the first routing metal layer SD1) from shorting the second conductive portion 32 (located in the first routing metal layer SD1) electrically connected to the second electrode b2 of the compensation transistor T2.

[0304] In some examples, the orthographic projection of the third auxiliary connection portion G3 on the substrate 10 may be in the shape of a ├. Based on this, the third auxiliary connection portion G3 may be divided into a first sub-portion G31, a second sub-portion G32, and a third sub-portion G33. The first end of the first sub-portion G31, the first end of the second sub-portion G32, and the first end of the third sub-portion G33 are connected to the same point, so that the first sub-portion G31, the second sub-portion G32, and the third sub-portion G33 constitute the third auxiliary connection portion G3.

[0305] Among them, the second end of the first sub-part G31 is electrically connected to the second scan signal line Scan, the second end of the second sub-part G32 is electrically connected to the first control electrode c21 of the compensation transistor T2, and the second end of the third sub-part G33 is electrically connected to the second control electrode c22 of the compensation transistor T2.

[0306] Based on this, the third auxiliary connection portion G3 can be used to electrically connect the control electrode c2 (the first control electrode c21 and the second control electrode c22 ) of the compensation transistor T2 to the second scan signal line Scan.

[0307] In some examples, the second sub-portion G32 extends along the row direction X, and overlaps with the first control electrode c21 of the compensation transistor T2 along the row direction X, so that the second sub-portion G32 is electrically connected to the first control electrode c21 of the compensation transistor T2.

[0308] Illustratively, the structure formed by the second sub-portion G32 and the first control electrode c21 of the compensation transistor T2 has no other bending portions, which can reduce the size of the third auxiliary connection portion G3 and facilitate layout on the array substrate 100 .

[0309] In some examples, the third sub-portion G33 extends along the column direction Y and overlaps with the second control electrode c22 of the compensation transistor T2 along the column direction Y, so that the third sub-portion G33 is electrically connected to the second control electrode c22 of the compensation transistor T2.

[0310] Illustratively, the structure formed by the third sub-portion G33 and the second control electrode c22 of the compensation transistor T2 has no other bending portions, which can reduce the size of the third auxiliary connection portion G3 and facilitate layout on the array substrate 100 .

[0311] In some examples, the first sub-portion G31 and the third sub-portion G33 extend along the column direction Y, and the extension direction of the line connecting the first sub-portion G31 and the third sub-portion G33 is parallel to the column direction Y. In other words, the structure formed by the first sub-portion G31 and the third sub-portion G33 does not have other bending portions, which can reduce the size of the third auxiliary connecting portion G3 and facilitate layout on the array substrate 100.

[0312] FIG. 15 is a film layer diagram of a pixel driving circuit and a bottom shielding layer according to some embodiments.

[0313] In some embodiments, as shown in FIG15 , the array substrate 100 further includes a bottom shield metal (BSM) 50 , which is located between the substrate 10 and the pixel driving circuit Q. The orthographic projection of the bottom shield metal 50 on the substrate 10 covers the orthographic projection of the driving transistor T3 on the substrate 10 .

[0314] Based on this, the bottom shielding layer 50 can be used to shield the driving transistor T3 from static electricity. In addition, the bottom shielding layer 50 can also serve as a light shielding layer to reduce the impact of external light incident from the substrate 10 side on the semiconductor layer POLY, thereby improving the performance of the semiconductor layer POLY.

[0315] In some examples, the orthographic projection of the driving transistor T3 on the substrate 10 is located within the boundary of the orthographic projection of the bottom shielding layer 50 on the substrate 10 , so that the bottom shielding layer 50 can completely cover the driving transistor T3 to shield the driving transistor T3 from the influence of static electricity.

[0316] In some examples, the bottom shielding layer 50 is configured to receive a first power signal, thereby reducing static electricity accumulation on the bottom shielding layer 50 .

[0317] In addition, the two bottom shielding layers 50 corresponding to two adjacent pixel driving circuits Q can be electrically connected via the connecting portion, which can reduce the impedance of the bottom shielding layer 50 .

[0318] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising a substrate and a driving circuit layer located on the substrate; The driving circuit layer includes: A plurality of pixel driving circuits, located on one side of the substrate and arranged in multiple rows and columns; one pixel driving circuit includes a first reset transistor, a compensation transistor, a driving transistor, a data writing transistor, a first conductive connection portion, and a second conductive connection portion; The control electrode of the driving transistor, the second electrode of the compensation transistor, and the second electrode of the first reset transistor are all electrically connected to the first conductive connection portion, and the first electrode of the driving transistor and the second electrode of the data writing transistor are both electrically connected to the second conductive connection portion; A plurality of first scanning signal lines, located on one side of the substrate, the plurality of first scanning signal lines all extend in the row direction and are arranged in sequence in the column direction, and one first scanning signal line is electrically connected to the control electrode of the data writing transistor of one row of pixel driving circuits; the orthographic projection of the first conductive portion of the first conductive connection portion on the substrate overlaps with the orthographic projection of the first scanning signal line on the substrate; A plurality of second scanning signal lines, located on one side of the substrate, the plurality of second scanning signal lines all extend in the row direction and are arranged in sequence in the column direction, and one second scanning signal line is electrically connected to the control electrode of the compensation transistor of one row of pixel driving circuits; the orthographic projection of the first conductive portion of the first conductive connection portion on the substrate overlaps with the orthographic projection of the second scanning signal line on the substrate; and, A first shielding layer, the first shielding layer is configured to have a constant voltage signal, the first shielding layer includes a first shielding pattern; in the thickness direction of the substrate, the first shielding pattern is located between the first scanning signal line and the first conductive portion; and / or, in the thickness direction of the substrate, the first shielding pattern is located between the second scanning signal line and the first conductive portion.

2. The array substrate according to claim 1, wherein, The driving circuit layer includes: A semiconductor layer, located on the substrate; the semiconductor layer includes the first and second electrodes of the first reset transistor, the first and second electrodes of the compensation transistor, the first and second electrodes of the driving transistor, and the first and second electrodes of the data writing transistor; A first gate metal layer, located on the side of the semiconductor layer away from the substrate; the first gate metal layer includes the control electrodes of the first reset transistor, the driving transistor, and the data writing transistor; A second gate metal layer, located on the side of the first gate metal layer away from the semiconductor layer; and, A first wiring metal layer, located on the side of the second gate metal layer away from the first gate metal layer; the first wiring metal layer includes the first scanning signal lines and the second scanning signal lines.

3. The array substrate according to claim 2, wherein The first conductive portion is located in the semiconductor layer, one end of the first conductive portion is electrically connected to the second electrode of the first reset transistor, and the other end of the first conductive portion is electrically connected to the control electrode of the driving transistor and the second electrode of the compensation transistor; The first conductive portion includes a first electron - conducting portion and a second electron - conducting portion connected to each other. The orthographic projection of the first electron - conducting portion on the substrate overlaps with the orthographic projection of the first scan signal line on the substrate, and the orthographic projection of the first electron - conducting portion on the substrate is located within the boundary of the orthographic projection of the first shielding pattern on the substrate; and / or, The orthographic projection of the second electron - conducting portion on the substrate overlaps with the orthographic projection of the second scan signal line on the substrate, and the orthographic projection of the second electron - conducting portion on the substrate is located within the boundary of the orthographic projection of the first shielding pattern on the substrate.

4. The array substrate according to claim 3, wherein, The first conductive portion further includes a third electron - conducting portion. One end of the third electron - conducting portion is electrically connected to the first electron - conducting portion, and the other end of the third electron - conducting portion is electrically connected to the second electron - conducting portion; The orthographic projection of the third electron - conducting portion on the substrate is located within the boundary of the orthographic projection of the first shielding pattern on the substrate.

5. The array substrate according to claim 3 or 4, wherein In the column direction, the first shielding pattern includes a first edge and a second edge. The first edge is located on the side of the second edge away from the driving transistor; The first minimum distance between the orthographic projection of the first edge on the substrate and the orthographic projection of the side of the first electron - conducting portion away from the second electron - conducting portion on the substrate is greater than or equal to 1 μm; and / or, The second minimum distance between the orthographic projection of the second edge on the substrate and the orthographic projection of the side of the second electron - conducting portion away from the first electron - conducting portion on the substrate is greater than or equal to 1 μm.

6. The array substrate according to any one of claims 3 to 5, wherein, In the row direction, the third minimum distance between the boundary of the orthographic projection of the first shielding pattern on the substrate and the boundary of the orthographic projection of the first electron - conducting portion on the substrate is greater than or equal to 1 μm; and / or, In the row direction, the fourth minimum distance between the boundary of the orthographic projection of the first shielding pattern on the substrate and the boundary of the orthographic projection of the first electron - conducting portion on the substrate is greater than or equal to 1 μm.

7. The array substrate according to any one of claims 1 to 6, wherein, The first shielding pattern includes a first shielding sub - portion extending in the row direction and a second shielding sub - portion extending in the column direction; The orthographic projection of the first shielding sub - portion on the substrate overlaps with the orthographic projection of the second scan signal line on the substrate; the orthographic projection of the second shielding sub - portion on the substrate overlaps with the orthographic projection of the first conductive connection portion on the substrate.

8. The array substrate according to any one of claims 1 to 7, wherein, In the column direction, the first reset transistor is located on the side of the first scan signal line away from the second scan signal line; The orthographic projection of the first shielding pattern on the substrate does not overlap with the orthographic projection of the first reset transistor on the substrate.

9. The array substrate according to any one of claims 1 to 8, wherein, The pixel driving circuit further includes a storage capacitor. The storage capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the storage capacitor is electrically connected to the first conductive connection portion, and the second electrode plate of the storage capacitor is electrically connected to a first power signal line. The first power signal line is configured to provide a first power signal, and the first power signal is a constant - voltage signal; When the driving circuit layer includes a first gate metal layer and a second gate metal layer, the first gate metal layer further includes a first electrode plate of the storage capacitor, and the first electrode plate of the storage capacitor is multiplexed as a control electrode of the driving transistor; The second gate metal layer further includes a second electrode plate of the storage capacitor, and the first shielding layer is electrically connected to the second electrode plate of the storage capacitor.

10. The array substrate according to claim 9, wherein, The first shielding layer is on the same layer as the second electrode plate of the storage capacitor.

11. The array substrate according to claim 9 or 10, wherein, The second gate metal layer further includes a first auxiliary connection portion. One end of the first auxiliary connection portion is electrically connected to the second electrode plate of the storage capacitor, and the other end of the first auxiliary connection portion is electrically connected to the first shielding pattern. Moreover, a positive projection of the first auxiliary connection portion on the substrate does not overlap with a positive projection of a control electrode of the compensation transistor on the substrate.

12. The array substrate according to claim 11, wherein, A positive projection of the first auxiliary connection portion on the substrate does not overlap with a positive projection of a second pole of the compensation transistor on the substrate.

13. The array substrate according to any one of claims 1 to 12, wherein, The first shielding layer further includes a second shielding pattern, and a positive projection of the second shielding pattern on the substrate overlaps with a positive projection of the second conductive connection portion on the substrate.

14. The array substrate according to any one of claims 2 to 13, wherein, The compensation transistor is a double-gate transistor, and a control electrode of the compensation transistor includes a first control electrode and a second control electrode; When the driving circuit layer includes a first gate metal layer and a semiconductor layer, the first gate metal layer includes a first conductive pattern, and the first conductive pattern includes the first control electrode and the second control electrode of the compensation transistor; The semiconductor layer includes a first channel portion and a second channel portion of the compensation transistor. The semiconductor layer further includes a second auxiliary connection portion. One end of the second auxiliary connection portion is electrically connected to the first channel portion of the compensation transistor, and the other end of the second auxiliary connection portion is electrically connected to the second channel portion of the compensation transistor.

15. The array substrate according to claim 14, wherein, The first shielding layer further includes a third shielding pattern, and a positive projection of the third shielding pattern on the substrate overlaps with a positive projection of the second auxiliary connection portion on the substrate.

16. The array substrate according to claim 15, wherein, A positive projection of the third shielding pattern on the substrate does not overlap with positive projections of the first control electrode and the second control electrode of the compensation transistor on the substrate.

17. The array substrate according to any one of claims 14 to 16, wherein The first conductive pattern further includes a third auxiliary connection portion, and the third auxiliary connection portion is located on a side of the first control electrode and the second control electrode of the compensation transistor away from the driving transistor; One end of the third auxiliary connection portion is electrically connected to both the first control electrode and the second control electrode of the compensation transistor, and the other end of the third auxiliary connection portion is electrically connected to the second scanning signal line.

18. The array substrate according to any one of claims 1 to 17, wherein, The pixel driving circuit further includes: a first light-emitting control transistor. A first pole of the first light-emitting control transistor is electrically connected to a first power signal line, a second pole of the first light-emitting control transistor is electrically connected to a first pole of the driving transistor, and a control electrode of the first light-emitting control transistor is electrically connected to a first enable signal line; A second light-emitting control transistor, a first pole of the second light-emitting control transistor is electrically connected to a second pole of the driving transistor, a second pole of the second light-emitting control transistor is electrically connected to an output end of the pixel driving circuit, and a control pole of the second light-emitting control transistor is electrically connected to a second enable signal line; In a column direction, the first light-emitting control transistor is located between the driving transistor and the second light-emitting control transistor.

19. The array substrate according to any one of claims 1 to 18, further comprising: A bottom shielding layer, located between the substrate and the pixel driving circuit, and a positive projection of the bottom shielding layer on the substrate covers a positive projection of the driving transistor on the substrate.

20. A display panel, comprising: The array substrate according to any one of claims 1 to 19; And, A light-emitting device layer, located on a side of the array substrate away from the substrate; The light-emitting device layer includes a plurality of light-emitting devices, and the light-emitting devices are electrically connected to the pixel driving circuit.

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