Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises: a base (10), the base (10) comprising a display region and a first frame region; a plurality of sub-pixels; a plurality of data lines, the plurality of data lines being electrically connected to the plurality of sub-pixels; a plurality of data line leads (50) located in the first frame region, the plurality of data line leads (50) being electrically connected to the plurality of data lines; and a plurality of drive chip pins (53) located in the first frame region, one drive chip pin (53) being electrically connected to one data line lead (50), and the plurality of drive chip pins (53) being located on the side of the plurality of data line leads (50) away from the base (10). At least one recess structure (60) is provided on the side surface of each drive chip pin (53) away from the base (10), the at least one recess structure (60) comprises a recess bottom (61) and recess walls (63), the at least one recess structure (60) has a recess depth in the thickness direction of the display substrate, and the recess depth ranges from 0.40 micrometers to 0.65 micrometers.

Description

Display substrate and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 27, 2023, with application number 202311267001.8 and invention name “Display Substrate and Display Device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] With the continuous development of display technology, the structural forms of display substrates have also become more diverse. Low-temperature polycrystalline oxide (LTPO) display substrates integrate low-temperature polycrystalline silicon thin-film transistors and oxide thin-film transistors on the same display substrate. LTPO display substrates can achieve high resolution (Pixel Per Inch, PPI) and low-frequency drive, which can reduce the power consumption of display devices and improve the display quality of display devices.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] Embodiments of the present disclosure provide a display substrate and a display device.

[0007] In one aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0008] A substrate comprising a display area and a first frame area located on one side of the display area;

[0009] A plurality of sub-pixels are located in the display area;

[0010] a plurality of data lines located in the display area, and electrically connected to the plurality of sub-pixels;

[0011] a plurality of data line leads, located in the first frame area, and the plurality of data line leads are electrically connected to the plurality of data lines;

[0012] a plurality of driver chip pins located in the first frame area, one of the driver chip pins being electrically connected to a data line lead, and the plurality of driver chip pins being located on a side of the plurality of data line leads away from the substrate;

[0013] Among them, there is at least one groove structure on the side surface of the driver chip pin away from the substrate, and the at least one groove structure includes a groove bottom and a groove wall connecting the groove bottom. The at least one groove structure has a groove depth along the thickness direction of the display substrate, and the groove depth ranges from 0.40 microns to 0.65 microns.

[0014] In an exemplary embodiment, in a plane perpendicular to the display substrate, the first border area includes a first metal layer, a second metal layer, a third metal layer and a fourth metal layer located on one side of the substrate and stacked in sequence; the first metal layer includes the multiple data line leads, and the fourth metal layer includes the multiple driver chip pins.

[0015] In an exemplary embodiment, in a plane perpendicular to the display substrate, the first border area further includes at least one insulating layer, and the at least one insulating layer is located between the first metal layer and the second metal layer; the second metal layer includes at least one connecting electrode, a portion of the connecting electrode is located in a via hole of the at least one insulating layer, and is in contact and connected with the surface of the data line lead away from the substrate.

[0016] In an exemplary embodiment, the at least one insulating layer includes a first inorganic layer and a second inorganic layer, and the second inorganic layer is farther away from the substrate than the first inorganic layer; in the line width direction of the data line lead, the orthographic projection of the via provided in the first inorganic layer on the display substrate is located within the orthographic projection of the data line lead on the display substrate, and the orthographic projection of the via provided in the second inorganic layer on the display substrate includes the orthographic projection of the data line lead on the display substrate, and the orthographic projection of the via provided in the second inorganic layer on the display substrate is larger than the orthographic projection of the data line lead on the display substrate.

[0017] In an exemplary embodiment, an insulating layer is provided between the first metal layer and the second metal layer, and in the line width direction of the data line lead, the orthographic projection of the via hole provided in the insulating layer is located within the orthographic projection of the data line lead on the display substrate.

[0018] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display area includes a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer located on one side of the substrate and stacked in sequence; the first metal layer and the first gate metal layer are in the same layer structure, the second metal layer and the first source-drain metal layer are in the same layer structure, and the third metal layer and the second source-drain metal layer are in the same layer structure.

[0019] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display area includes a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer located on one side of the substrate and stacked in sequence; the first metal layer and the second gate metal layer are in the same layer structure, the second metal layer and the first source-drain metal layer are in the same layer structure, and the third metal layer and the second source-drain metal layer are in the same layer structure.

[0020] In an exemplary embodiment, the second metal layer includes at least one first connecting electrode, and the third metal layer includes at least one second connecting electrode; at least a portion of the surface of the second connecting electrode away from the substrate is in contact with the groove structure of the driver chip pin, and a portion of the surface of the first connecting electrode close to the substrate is in contact with the data line lead.

[0021] In an exemplary embodiment, the first connecting electrode has a first sub-groove, the second connecting electrode has a second sub-groove, the orthographic projection of the groove structure of the driving chip pin on the display substrate is located within the orthographic projection of the second sub-groove on the display substrate, and the orthographic projection of the second sub-groove on the display substrate is located within the orthographic projection of the first sub-groove on the display substrate.

[0022] In an exemplary embodiment, in a plane perpendicular to the display substrate, the first border area further includes a leveling layer, wherein the leveling layer is located between the substrate and the first metal layer; the leveling layer includes at least one leveling block; in the line width direction of the data line lead, the orthographic projection of the data line lead on the display substrate includes the orthographic projection of the leveling block on the display substrate.

[0023] In an exemplary embodiment, in a plane perpendicular to the display substrate, the first border area further includes a leveling layer, the leveling layer is located between the first metal layer and the second metal layer, and the leveling layer includes at least one leveling block; in the line width direction of the data line lead, the orthographic projection of the leveling block on the display substrate includes the orthographic projection of the data line lead on the display substrate, and the data line lead is electrically connected to the groove structure of the driving chip pin via the leveling block.

[0024] In an exemplary embodiment, in a plane perpendicular to the display substrate, the first border area further includes at least one insulating layer, the at least one insulating layer is located between the first metal layer and the second metal layer, and the surface of the at least one insulating layer away from the substrate is flush with the surface of the data line lead and the leveling block away from the substrate.

[0025] In an exemplary embodiment, the second metal layer includes at least one first connecting electrode, and the third metal layer includes at least one second connecting electrode; the data line lead is connected to the groove structure of the driver chip pin via the first connecting electrode and the second connecting electrode;

[0026] Wherein, a surface of the first connecting electrode away from the substrate is a plane.

[0027] In an exemplary embodiment, a surface of the second connecting electrode away from the substrate is a plane.

[0028] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display area includes a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer, which are located on one side of the substrate and stacked in sequence; the second metal layer and the first source / drain metal layer are in the same layer structure, and the third metal layer and the second source / drain metal layer are in the same layer structure;

[0029] The leveling layer and one of the first gate metal layer and the second gate metal layer are in the same layer structure, and the first metal layer and the other one of the first gate metal layer and the second gate metal layer are in the same layer structure.

[0030] On the other hand, an embodiment of the present disclosure provides a display device, which includes the display substrate described in any of the above embodiments.

[0031] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0032] Summary of the Figures

[0033] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0034] FIG1 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

[0035] FIG2 is a schematic plan view of a display substrate according to an embodiment of the present disclosure;

[0036] FIG3 is a partial cross-sectional schematic diagram of a display area of ​​a display substrate according to an embodiment of the present disclosure;

[0037] FIG4 is a partial cross-sectional diagram of a driver chip pin of a display substrate according to an embodiment of the present disclosure;

[0038] FIG5 is a second partial cross-sectional diagram of driver chip pins of a display substrate according to an embodiment of the present disclosure;

[0039] FIG6 is a third partial cross-sectional diagram of driver chip pins of a display substrate according to an embodiment of the present disclosure;

[0040] FIG7 is a fourth partial cross-sectional diagram of driver chip pins of a display substrate according to an embodiment of the present disclosure;

[0041] FIG8 is a fifth partial cross-sectional diagram of driver chip pins of a display substrate according to an embodiment of the present disclosure;

[0042] 9A to 9G are schematic diagrams showing a process for preparing driver chip pins of a display substrate according to an embodiment of the present disclosure;

[0043] FIG10 is a partial cross-sectional diagram of driver chip pins of a display substrate according to another embodiment of the present disclosure;

[0044] FIG11 is a partial cross-sectional schematic diagram of a driver chip pin of a display substrate according to another embodiment of the present disclosure;

[0045] FIG12 is a second partial cross-sectional diagram of driver chip pins of a display substrate according to another embodiment of the present disclosure;

[0046] 13A to 13H are schematic diagrams showing a process for preparing driver chip pins of a display substrate according to another embodiment of the present disclosure;

[0047] FIG14 is a partial cross-sectional schematic diagram of a display device according to an embodiment of the present disclosure.

[0048] Details

[0049] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0050] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0051] The ordinal numbers such as "first," "second," and "third" in this disclosure are provided to avoid confusion among constituent elements, and are not intended to limit the number. The "plurality" in this disclosure includes two or more.

[0052] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements are appropriately changed according to the direction in which the constituent elements are described. Therefore, the words and phrases are not limited to those described in the specification and can be appropriately replaced according to the circumstances.

[0053] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0054] In this disclosure, a transistor refers to a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0055] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged.

[0056] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0057] In this disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0058] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0059] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0060] The embodiment of the present disclosure provides a display substrate. The display substrate includes: a substrate, including a display area and a first frame area located on one side of the display area, a plurality of sub-pixels located in the display area, a plurality of data lines located in the display area, and the plurality of data lines and the plurality of sub-pixels are electrically connected, a plurality of data line leads located in the first frame area, and the plurality of data line leads are electrically connected to the plurality of data lines, a plurality of driver chip pins located in the first frame area, one of the driver chip pins is electrically connected to one of the data line leads, and the plurality of driver chip pins are located on a side of the plurality of data line leads away from the substrate; wherein, at least one groove structure is provided on a surface on a side of the driver chip pin away from the substrate, the at least one groove structure includes a groove bottom and a groove wall connecting the groove bottom, and the at least one groove structure has a groove depth along the thickness direction of the display substrate, and the groove depth ranges from 0.40 microns to 0.65 microns.

[0061] The display substrate provided by the embodiment of the present disclosure limits the groove depth of the groove structure of the driving chip pins in the first frame area. After the display substrate is assembled into a display device, the electrical components waiting to be installed can be reliably connected to the first frame area through the groove structure, thereby avoiding problems such as dark lines and improving the yield rate of the display device.

[0062] FIG1 is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure. As shown in FIG1 , the display device may include a timing controller 21, a data driver 22, a scan driver circuit 23, a light-emitting driver circuit 24, and a sub-pixel array 25. In some examples, the sub-pixel array 25 may include a plurality of sub-pixels PX arranged in a regular pattern. The scan driver circuit 23 may be configured to provide scan signals to the sub-pixels PX along scan lines. The data driver 22 may be configured to provide data voltages to the sub-pixels PX along data lines. The light-emitting driver circuit 24 may be configured to provide light-emitting control signals to the sub-pixels PX along light-emitting control lines. The timing controller 21 may be configured to control the scan driver circuit 23, the light-emitting driver circuit 24, and the data driver 22.

[0063] In one exemplary embodiment, as shown in FIG1 , the timing controller 21 may provide grayscale values ​​and control signals suitable for the specifications of the data driver 22 to the data driver 22. The timing controller 21 may also provide a scan clock signal, a scan start signal, and the like suitable for the specifications of the scan driver 23 to the scan driver 23. The timing controller 21 may also provide a light-emission clock signal, a light-emission start signal, and the like suitable for the specifications of the light-emission driver 24 to the light-emission driver 24. The data driver 22 may use the grayscale values ​​and control signals received from the timing controller 21 to generate data voltages to be supplied to a plurality of data lines, which may include data lines DL1 to DLi. For example, the data driver 22 may sample grayscale values ​​using clock signals and apply data voltages corresponding to the grayscale values ​​to the data lines DL1 to DLi in units of sub-pixel rows. The scan driver 23 may use the scan clock signal, the scan start signal, and the like received from the timing controller 21 to generate scan signals to be supplied to a plurality of scan lines, which may include scan lines GL1 to GLj. For example, the scan driver circuit 23 can sequentially provide scan signals having on-level pulses to the scan lines. In some examples, the scan driver circuit 23 can include a shift register that can sequentially transmit scan start signals provided in the form of on-level pulses to the next-level circuit under the control of a scan clock signal to generate scan signals. The light-emitting driver circuit 24 can generate light-emitting control signals to be provided to the light-emitting control lines E1 to Eo based on the light-emitting clock signal, light-emitting start signal, etc. received from the timing controller 21. For example, the light-emitting driver circuit 24 can sequentially provide light-emitting control signals having off-level pulses to the light-emitting control lines. The light-emitting driver circuit 24 can include a shift register that can sequentially transmit light-emitting start signals provided in the form of off-level pulses to the next-level circuit under the control of a clock signal to generate light-emitting control signals. Wherein, i, j, and o are all natural numbers.

[0064] In one exemplary embodiment, a display device may include a display substrate. A scan driver circuit and a light-emitting driver circuit may be directly disposed on the display substrate. For example, the scan driver circuit may be disposed on the left side frame of the display substrate, and the light-emitting driver circuit may be disposed on the right side frame of the display substrate. Alternatively, the scan driver circuit and the light-emitting driver circuit may be disposed on both the left and right sides of the display substrate. In some examples, the scan driver circuit and the light-emitting driver circuit may be formed together with the sub-pixels during the process of forming the sub-pixels.

[0065] In one exemplary embodiment, the data driver may be provided on a separate chip or printed circuit board to be connected to the sub-pixels via signal access pins on the display substrate. For example, the data driver may be formed using a chip-on-glass, chip-on-plastic, chip-on-film, or the like to form a first frame provided on the display substrate to be connected to the signal access pins. The timing controller may be provided separately from the data driver or integrally with the data driver. However, the embodiments of the present disclosure are not limited thereto. In some examples, the data driver may be provided directly on the display substrate.

[0066] Figure 2 is a planar schematic diagram of a display substrate according to an embodiment of the present disclosure. As shown in Figure 2, the display substrate may include a display area AA and a peripheral area surrounding the display area AA. The peripheral area may include a first border area B1 located on one side of the display area AA and a second border area B2 located on the other side of the display area AA. In the embodiment of the present disclosure, the first border area B1 may also be referred to as a binding area. The second border area B2 may be located on at least two sides of the first border area B1. For example, the first border area B1 may be the lower border of the display substrate, and the second border area B2 may include the upper border, left border, and right border of the display substrate. In some examples, the display area AA may be a flat area including a plurality of sub-pixels PX forming a sub-pixel array, and the plurality of sub-pixels PX are configured to display dynamic images or still images. The display area may also be referred to as an active area. In some examples, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as curling, bending, folding, or rolling up.

[0067] In an exemplary embodiment, the second border area B2 may include a circuit area, a power line area, a crack dam area and a cutting area arranged in sequence along the direction of the display area AA. The circuit area can be connected to the display area AA, and the circuit area can at least include a gate drive circuit (for example, including multiple cascaded shift registers), and the multiple shift registers can be electrically connected to the multiple scan lines in the display area AA. The power line area is connected to the circuit area, and the power line area can at least include a low-level power line, which can extend in a direction parallel to the edge of the display area and can be connected to the cathode of the display area AA. The crack dam area can be connected to the power line area, and the crack dam area can at least include multiple cracks set on the composite insulating layer. The cutting area can be connected to the crack dam area, and the cutting area can at least include a cutting groove set on the composite insulating layer. The cutting groove can be configured so that after all the film layers of the display substrate are prepared, the cutting equipment can cut along the cutting groove.

[0068] In one exemplary embodiment, as shown in FIG2 , the display area AA may include a plurality of sub-pixels PX, a plurality of scan lines GL, and a plurality of data lines DL. The plurality of scan lines GL may extend along a first direction X, and the plurality of data lines DL may extend along a second direction Y. The orthographic projections of the plurality of scan lines GL and the plurality of data lines DL on the display substrate intersect to form a plurality of sub-pixel regions, with a sub-pixel PX disposed within each sub-pixel region. The plurality of data lines DL are electrically connected to the plurality of sub-pixels PX. For example, one data line DL is electrically connected to a column of sub-pixels PX. The plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of data lines DL may extend to the first border area B1. The plurality of scan lines GL are electrically connected to the plurality of sub-pixels PX. The plurality of scan lines GL may be configured to provide gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signals may include scan signals and light emission control signals.

[0069] In an exemplary embodiment, as shown in FIG2 , the first direction X may be the extending direction (row direction) of the scan lines GL in the display area AA, and the second direction Y may be the extending direction (column direction) of the data lines DL in the display area AA. The first direction X and the second direction Y may intersect. For example, the first direction X and the second direction Y may be perpendicular to each other. In the embodiment of the present disclosure, the first direction X is also the line width direction of the data lines DL.

[0070] In one exemplary embodiment, as shown in FIG2 , along a direction away from the display area AA, the first border area B1 may include a first sub-area B11, a bending area B12, and a second sub-area B13. The first sub-area B11 may be connected to the second border areas B2 on its left and right sides at both ends along the first direction X. In the disclosed embodiment, the first sub-area B11 may also be referred to as a first fan-out area, and the first sub-area B11 may be connected to the display area AA.

[0071] In an exemplary embodiment, as shown in FIG2 , the bending region B12 may be connected between the first sub-region B11 and the second sub-region B13. For example, the bending region B12 may include a composite insulating layer having a groove, and the groove may be configured to bend a portion of the first border region B1 toward the back of the display area AA.

[0072] In an exemplary embodiment, the width of the bending region B12 along the second direction Y may range from 0.5 mm to 1.0 mm. For example, the width of the bending region B12 along the second direction Y may be 1.0 mm.

[0073] In an exemplary embodiment, as shown in FIG2 , the second sub-area B13 may include a plurality of pins. The second sub-area B13 may include a circuit layout area, a driver chip area 131, and a binding pin area arranged in sequence along a direction away from the display area AA. The circuit layout area may include at least an electrostatic discharge circuit, and the electrostatic discharge circuit may be configured to prevent electrostatic damage to the display substrate by eliminating static electricity. The driver chip area 131 may be configured to arrange a driver chip (Integrated Circuit, IC), and the driver chip area 131 may include a plurality of driver chip pins 53. The driver chip may be electrically connected to the data line DL of the display area AA through the driver chip pins 53 and the data line lead 50. The first frame area B1 may include a plurality of data line leads 50, and the plurality of data line leads 50 are electrically connected to the plurality of data lines DL. For example, the data line leads 50 are connected to the data lines DL in a one-to-one correspondence. The driver chip may be configured to generate a signal required for driving the sub-pixel and provide the drive signal to the data line of the display area. For example, the drive signal may be a data signal that drives the luminous brightness of the sub-pixel. The binding pin area may include a plurality of binding pins, and the binding pins may be configured to be bound and connected to at least one corresponding circuit board (e.g., a flexible printed circuit (FPC)). The driver chip pins 53 in the driver chip area 131 may be electrically connected to the binding pins in the binding pin area through pin connection lines. In an exemplary embodiment, a pixel unit of the display area AA may include a plurality of sub-pixels. For example, a pixel unit may include three sub-pixels, and the three sub-pixels may be red sub-pixels, green sub-pixels, and blue sub-pixels, respectively. However, the embodiments of the present disclosure are not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, respectively.

[0074] In one exemplary embodiment, the shape of the sub-pixels can be a rectangle, a diamond, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern. When a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, the present disclosure is not limited to this.

[0075] In an exemplary embodiment, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may be P-type transistors, or may be N-type transistors. Using transistors of the same type in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product. In other examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors.

[0076] In an exemplary embodiment, a plurality of transistors in a pixel circuit may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, while oxide thin-film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, i.e., an LTPS+Oxide (LTPO for short) display substrate, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0077] In an exemplary embodiment, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, the embodiments of the present disclosure are not limited to this.

[0078] Figure 3 is a partial cross-sectional schematic diagram of the display region of a display substrate according to an embodiment of the present disclosure. As shown in Figure 3, the display region of the display substrate, in a direction perpendicular to the display substrate, may include: a substrate 10, and, sequentially disposed on substrate 10, a circuit structure layer 20, a light-emitting structure layer 30, an encapsulation layer 40, and a touch structure layer 100. The touch structure layer 100 may include a stacked protective layer (overcoating, OC) 101, a touch layer, and a touch insulation layer.

[0079] In an exemplary embodiment, the substrate 10 may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz. The flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fiber, and the like.

[0080] In an exemplary embodiment, the substrate 10 may be a composite film layer. For example, as shown in FIG3 , the substrate 10 may be a composite film layer having three film layers. For example, the substrate 10 may include a first inorganic sublayer, an organic layer, and a second inorganic sublayer stacked in sequence.

[0081] In one exemplary embodiment, as shown in FIG3 , the circuit structure layer 20 may include multiple transistors and storage capacitors that constitute the pixel circuit. FIG3 illustrates an example in which each sub-pixel includes only one transistor and one storage capacitor. The circuit structure layer 20 may include a semiconductor layer disposed on one side of a substrate 10, a first insulating layer 11 covering the semiconductor layer, a first conductive layer 11-1 disposed on the first insulating layer 11, a second insulating layer 12 covering the first conductive layer 11-1, a second conductive layer 12-1 disposed on the second insulating layer 12, a third insulating layer 13 covering the second conductive layer 12-1, a third conductive layer 13-1 disposed on the third insulating layer 13, a fourth conductive layer 14-1 located on a side of the third conductive layer 13-1 away from the substrate 10, and a fourth insulating layer 14. The semiconductor layer may include an active layer 16 of a transistor. The first conductive layer 11-1 may include a gate electrode 17 of the transistor and a first capacitor electrode 18 of a storage capacitor. The second conductive layer 12-1 may include a second capacitor electrode 19 of the storage capacitor. The third conductive layer 13-1 may include a source electrode 110 and a drain electrode 111 of the transistor, as well as a data line. The fourth conductive layer 14-1 may include a pixel connection electrode 112, and the pixel connection electrode 112 may be configured to be connected to the anode 113 of the light-emitting element. In the embodiment of the present disclosure, in the display area of ​​the display substrate, the first conductive layer may also be referred to as a first gate metal layer, the second conductive layer may also be referred to as a second gate metal layer, the third conductive layer may also be referred to as a first source-drain metal layer, and the fourth conductive layer may also be referred to as a second source-drain metal layer. The first insulating layer 11 may also be referred to as a first gate insulating (GI1) layer, the second insulating layer 12 may also be referred to as a second gate insulating (GI2) layer, the third insulating layer 13 may also be referred to as an interlayer insulating (ILD) layer, and the fourth insulating layer 14 may also be referred to as a first flat (PLN1) layer.

[0082] In an exemplary embodiment, the material of the conductive layer can be a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0083] In an exemplary embodiment, the conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0084] In an exemplary embodiment, the material of the insulating layer may include any one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, polyether resin, etc.

[0085] In an exemplary embodiment, the material of the insulating layer may include any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), etc., and may be a single layer, a multilayer, or a composite layer.

[0086] In one exemplary embodiment, as shown in FIG3 , the light-emitting structure layer 30 may include an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode layer may include an anode 113 of the light-emitting element, which is electrically connected to the pixel connection electrode 112. A pixel opening is provided on the pixel definition layer, exposing at least a portion of the surface of the anode 113. The organic light-emitting layer is at least partially disposed within the pixel opening and is connected to the anode 113. The cathode of the light-emitting element is disposed on the organic light-emitting layer and is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color when driven by the anode 113 and the cathode.

[0087] In an exemplary embodiment, the encapsulation layer 40 may include two or more film layers. For example, the encapsulation layer 40 may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer 30.

[0088] Figure 4 is a partial cross-sectional schematic diagram of the driver chip pins of the display substrate of the present embodiment. As shown in Figure 4, within a plane perpendicular to the display substrate, the first border region of the display substrate may include a substrate 10, a first insulating layer 11 located on one side of the substrate 10, a first conductive layer 11-1 located on the side of the first insulating layer 11 away from the substrate 10, a second insulating layer 12 located on the side of the first conductive layer 11-1 away from the substrate 10, a third insulating layer 13 located on the side of the second insulating layer 12 away from the substrate 10, a third conductive layer 13-1 located on the side of the third insulating layer 13 away from the substrate 10, a fourth conductive layer 14-1 located on the side of the third conductive layer 13 away from the substrate 10, a fourth insulating layer 14 located on the side of the fourth conductive layer 14-1 away from the substrate 10, a fifth insulating layer 15 located on the side of the fourth conductive layer 14-1 away from the substrate 10, and a fifth conductive layer 15-1 located on the side of the fifth insulating layer 15 away from the substrate 10. As shown in Figure 4, in the present embodiment, the thickness direction of the display substrate is defined as a third direction, and the third direction is labeled as Z. In the embodiment of the present disclosure, the first direction X, the second direction Y, and the third direction Z may be perpendicular to each other.

[0089] In the embodiment of the present disclosure, in the first frame area of ​​the display substrate, the conductive layer including the data line lead can also be referred to as the first metal layer, the third conductive layer 13-1 can also be referred to as the second metal layer, the fourth conductive layer 14-1 can also be referred to as the third metal layer, and the fifth conductive layer 15-1 can also be referred to as the fourth metal layer. In the embodiment of the present disclosure, the film layers shared by the first frame area and the display area have the same label. For example, the first insulating layer of the first frame area and the first insulating layer of the display area are both the first insulating layer 11, and the second insulating layer of the first frame area and the second insulating layer of the display area are both the second insulating layer 12. In the embodiment of the present disclosure, the fifth conductive layer 15-1 located in the display area can also be referred to as the touch layer, and the fifth insulating layer 15 can also be referred to as the touch insulating layer. In this exemplary embodiment, the second insulating layer 12 located in the first frame area can also be referred to as the first inorganic layer, and the third insulating layer 13 can also be referred to as the second inorganic layer.

[0090] As shown in Figure 4, the first conductive layer 11-1 in the first frame area of ​​the display substrate may include at least one data line lead 50. For example, a plurality of data line leads 50 may be arranged at intervals along the first direction X and extend along the second direction Y. In the embodiment of the present disclosure, the first direction is also the line width direction of the data line lead 50. As shown in Figure 4, only one data line lead 50 is shown as an example, and the data line lead 50 extends along the second direction Y as an example. In the first frame area of ​​the display substrate, the third conductive layer 13-1 may include at least one first connecting electrode 51, the fourth conductive layer 14-1 may include at least one second connecting electrode 52, and the fifth conductive layer 15-1 may include at least one driving chip pin 53. The driving chip pin 53 is connected to the data line lead 50 via the second connecting electrode 52 and the first connecting electrode 51 to realize signal transmission.

[0091] In an exemplary embodiment, as shown in FIG4 , the third conductive layer 13 - 1 in the first border region of the display substrate may include at least one first connection electrode 51. A portion of the first connection electrode 51 is in contact and connected to a portion of the data line lead 50 via vias located in the second insulating layer 12 and the third insulating layer 13. As shown in FIG4 , the second insulating layer 12 may be provided with at least one first via K1. The first via K1 penetrates the second insulating layer 12 along the thickness direction of the display substrate and exposes a portion of the surface of the data line lead 50 away from the substrate 10. The orthographic projection of the data line lead 50 on the display substrate may include the orthographic projection of the first via K1 on the display substrate. The second insulating layer 12 may protect the edge of the data line lead 50, prevent corrosion of the data line lead by water, oxygen, etc., and extend the service life of the display substrate.

[0092] In one exemplary embodiment, as shown in FIG4 , the third insulating layer 13 may be provided with at least one second via K2. The second via K2 penetrates the third insulating layer 13 along the thickness direction of the display substrate and exposes a portion of the surface of the second insulating layer 12 on the side away from the substrate 10. The orthographic projection of the second via K2 on the display substrate may include the orthographic projection of the first via K1 on the display substrate, and the orthographic projection of the second via K2 on the display substrate may be larger than the orthographic projection of the first via K1 on the display substrate. In the first direction X, the orthographic projection of the second via K2 on the display substrate may include the orthographic projection of the data line lead 50 on the display substrate. For example, in the first direction X, the orthographic projection of the second via K2 on the display substrate may be larger than the orthographic projection of the data line lead 50 on the display substrate. By limiting the relative relationship between the apertures of the second via hole and the first via hole, the height difference of the first connecting electrode along the thickness direction of the display substrate can be reduced, so as to facilitate the conductive connection between the components (for example, the driver chip) and the driver chip pins in the first frame area in subsequent processes, avoid the problem of virtual connection, improve the yield of the display substrate, and enhance the reliability of the display substrate.

[0093] In one exemplary embodiment, as shown in FIG4 , at least a portion of the first connection electrode 51 may be located within the first via hole K1 and the second via hole K2. A portion of the first connection electrode 51 may be in contact with a portion of the surface of the data line lead 50 facing away from the substrate 10, a portion of the first connection electrode 51 may be in contact with a portion of the surface of the second insulating layer 12 facing away from the substrate 10, and a portion of the first connection electrode 51 may be in contact with a portion of the surface of the third insulating layer 13 facing away from the substrate 10. As shown in FIG4 , the orthographic projection of the first connection electrode 51 on the display substrate may include the orthographic projection of the second via hole K2 on the display substrate.

[0094] In an exemplary embodiment, as shown in FIG. 4 , the fourth insulating layer 14 may be provided with at least one third via hole K3 , and the third via hole K3 penetrates the fourth insulating layer 14 along the thickness direction of the display substrate.

[0095] In an exemplary embodiment, as shown in FIG4 , the fourth conductive layer 14 - 1 may include at least one second connecting electrode 52 . A portion of the second connecting electrode 52 may be located within the third via hole K3 . The orthographic projection of the fourth insulating layer 14 on the display substrate may include an edge of the orthographic projection of the second connecting electrode 52 on the display substrate. The second connecting electrode 52 is in contact with and connected to the first connecting electrode 51 , and the orthographic projection of the second connecting electrode 52 on the display substrate may include the orthographic projection of the first connecting electrode 51 on the display substrate. For example, the orthographic projection of the second connecting electrode 52 on the display substrate may be larger than the orthographic projection of the first connecting electrode 51 on the display substrate.

[0096] In an exemplary embodiment, as shown in FIG4 , the fifth insulating layer 15 may be provided with at least one fourth via hole K4. The fourth via hole K4 penetrates the fifth insulating layer 15 along the thickness direction of the display substrate and exposes a portion of the surface of the second connection electrode 52 on a side away from the substrate 10. The orthographic projection of the fourth via hole K4 on the display substrate may be located within the range of the orthographic projection of the second connection electrode 52 on the display substrate.

[0097] In an exemplary embodiment, as shown in Figure 4, the fifth conductive layer 15-1 may include at least one driver chip pin 53, and at least a portion of the driver chip pin 53 may be located within the fourth via K4. For example, the orthographic projection of the driver chip pin 53 on the display substrate may include the orthographic projection of the fourth via K4 on the display substrate.

[0098] In an exemplary embodiment, as shown in FIG4 , the driver chip pin 53 has a groove structure 60 , and the groove structure 60 is recessed toward one side of the substrate 10 . The groove structure 60 is configured to accommodate a conductive adhesive, such as an anisotropic conductive adhesive, to achieve an electrical connection between a component to be mounted and the data line lead 50 . For example, the component to be mounted may be a driver chip (Integrated Circuit, IC). The driver chip can transmit signals to the data line lead 50 via the driver chip pin 53 , and the data line lead 50 transmits the signals to the data line.

[0099] In an exemplary embodiment, as shown in FIG4 , the groove structure 60 includes a groove bottom 61, a groove top 62, and a groove wall 63. The groove bottom 61 and the groove top 62 may be arranged opposite each other along the thickness direction of the display substrate, with the groove bottom 61 being closer to the substrate 10 than the groove top 62. The groove wall 63 may extend along the thickness direction of the display substrate, and the groove wall 63 may have a first end and a second end arranged opposite each other. The first end of the groove wall 63 may be connected to the groove bottom 61, and the second end of the groove wall 63 may extend in a direction away from the substrate 10. The groove top 62 has a first end and a second end arranged opposite each other. The first end of the groove top 62 may be connected to the second end of the groove wall 63, and the second end of the groove top 62 extends in a direction away from the first end. The orthographic projection of the groove top 62 on the display substrate may be annular. For example, the orthographic projection of the groove top 62 on the display substrate may be a circular ring or a rectangular ring, etc.

[0100] In an exemplary embodiment, as shown in FIG4 , there is a distance H between the groove bottom 61 and the groove top 62 along the thickness direction of the display substrate, and the distance H may range from 0.55 microns to 0.65 microns. For example, the distance H may be 0.63 microns, or the distance H may be 0.60 microns, or the distance H may be 0.55 microns. In the embodiment of the present disclosure, the distance H may also be referred to as the groove depth of the groove structure 60. The display substrate provided by the embodiment of the present disclosure limits the groove depth of the groove structure to less than 0.65 microns, so that the components to be installed (for example, a driver chip) to be installed subsequently can be firmly connected to the data line lead via the groove structure, thereby avoiding the problem of virtual connection and improving the reliability of the display device.

[0101] In one exemplary embodiment, as shown in FIG4 , the second connecting electrode 52 has a second sub-groove. The second sub-groove has a second groove bottom 521, a second groove top 522, and a second groove wall 523. The second groove bottom 521 and the second groove top 522 may be arranged opposite each other along the thickness direction of the display substrate, with the second groove bottom 521 being closer to the substrate 10 than the second groove top 522. The second groove wall 523 may extend along the thickness direction of the display substrate. The second groove wall 523 has a first end and a second end opposite each other. The first end of the second groove wall 523 may be connected to the second groove bottom 521, and the second end of the second groove wall 523 may extend away from the substrate 10. The second groove top 522 has a first end and a second end opposite each other. The first end of the second groove top 522 may be connected to the second end of the second groove wall 523, and the second end of the second groove top 522 extends away from the first end. The orthographic projection of the second groove top 522 onto the display substrate may be annular. For example, the orthographic projection of the second groove top 522 onto the display substrate may be a circular ring or a rectangular ring.

[0102] In an exemplary embodiment, as shown in Figure 4, the groove top 62 is in contact with the second groove top 522. Compared with the structure in which an insulating layer is provided between the groove top 62 and the second groove top 522, the groove top 62 is in contact with the second groove top 522. The groove depth of the groove structure 60 can be reduced, which is beneficial to the subsequent fixation of the components to be installed (for example, the driver chip) and can avoid the virtual connection of the components to be installed.

[0103] In one exemplary embodiment, as shown in FIG4 , the first connecting electrode 51 has a first sub-groove. The first sub-groove has a first groove bottom 511, a first groove top 512, and a first groove wall 513. The first groove bottom 511 and the first groove top 512 may be arranged opposite each other along the thickness direction of the display substrate, with the first groove bottom 511 closer to the substrate 10 than the first groove top 512. The first groove wall 513 may extend along the thickness direction of the display substrate. The first groove wall 513 has a first end and a second end opposite each other. The first end of the first groove wall 513 may be connected to the first groove bottom 511, and the second end of the first groove wall 513 may extend away from the substrate 10. The first groove top 512 has a first end and a second end opposite each other. The first end of the first groove top 512 may be connected to the second end of the first groove wall 513, and the second end of the first groove top 512 extends away from the first end. The orthographic projection of the first groove top 512 onto the display substrate may be annular. For example, the orthographic projection of the first groove top 512 onto the display substrate may be a circular ring or a rectangular ring.

[0104] In an exemplary embodiment, as shown in Figure 4, the first groove top 512 is in contact with the second groove top 522. Compared with the structure in which an insulating layer is provided between the first groove top 512 and the second groove top 522, the contact connection between the first groove top 512 and the second groove top 522 can reduce the groove depth of the groove structure 60, which is beneficial to the subsequent fixation of the components to be installed (for example, the driver chip) and can avoid the virtual connection of the components to be installed.

[0105] FIG5 is a second partial cross-sectional schematic diagram of a driver chip pin of a display substrate according to an embodiment of the present disclosure. As shown in FIG5 , within a plane perpendicular to the display substrate, the first border region of the display substrate may include a substrate 10, a first insulating layer 11 located on one side of the substrate 10, a first conductive layer 11-1 located on the side of the first insulating layer 11 away from the substrate 10, a second insulating layer 12 located on the side of the first conductive layer 11-1 away from the substrate 10, a third conductive layer 13-1 located on the side of the second insulating layer 12 away from the substrate 10, a fourth conductive layer 14-1 located on the side of the third conductive layer 13-1 away from the substrate 10, a fourth insulating layer 14 located on the side of the second insulating layer 12 away from the substrate 10, a fifth insulating layer 15 located on the side of the fourth conductive layer 14-1 away from the substrate 10, and a fifth conductive layer 15-1 located on the side of the fifth insulating layer 15 away from the substrate 10. The main structure of the driver chip pin shown in FIG5 is substantially the same as that of the driver chip pin shown in FIG4 , except that the third insulating layer does not extend into the first border region, which can reduce the number of film layers in the first border region and optimize the film layer structure in the first border region.

[0106] Figure 6 is a third partial cross-sectional diagram of the driver chip pins of the display substrate of the present embodiment. As shown in Figure 6, within a plane perpendicular to the display substrate, the first border region of the display substrate may include a substrate 10, a first insulating layer 11 located on one side of the substrate 10, a first conductive layer 11-1 located on a side of the first insulating layer 11 away from the substrate 10, a second insulating layer 12 located on a side of the first conductive layer 11-1 away from the substrate 10, a third insulating layer 13 located on a side of the second insulating layer 12 away from the substrate 10, a third conductive layer 13-1 located on a side of the third insulating layer 13 away from the substrate 10, a fourth insulating layer 14 located on a side of the third insulating layer 13 away from the substrate 10, a fourth conductive layer 14-1 located on a side of the fourth insulating layer 14 away from the substrate 10, a fifth insulating layer 15 located on a side of the fourth conductive layer 14-1 away from the substrate 10, and a fifth conductive layer 15-1 located on a side of the fifth insulating layer 15 away from the substrate 10. The main structure of the driver chip pin shown in Figure 6 is basically the same as the main structure of the driver chip pin shown in Figure 4 above. The difference is that the portion of the surface of the third conductive layer 13-1 on the side away from the substrate 10 close to the fourth insulating layer 14 is basically flush with the portion of the surface of the fourth insulating layer 14 on the side away from the substrate 10 close to the third conductive layer 13-1, and the fourth conductive layer 14-1 is located on the side of the fourth insulating layer 14 away from the substrate 10, which can simplify the preparation process of the third via K3 and reduce the preparation cost of the display substrate.

[0107] Figure 7 is a partial cross-sectional schematic diagram of the driver chip pins of the display substrate of the present embodiment. As shown in Figure 7, within a plane perpendicular to the display substrate, the first border region of the display substrate may include a substrate 10, a first insulating layer 11 located on one side of the substrate 10, a first conductive layer 11-1 located on a side of the first insulating layer 11 away from the substrate 10, a second insulating layer 12 located on a side of the first conductive layer 11-1 away from the substrate 10, a third insulating layer 13 located on a side of the second insulating layer 12 away from the substrate 10, a third conductive layer 13-1 located on a side of the third insulating layer 13 away from the substrate 10, a fourth insulating layer 14 located on a side of the third insulating layer 13 away from the substrate 10, a fourth conductive layer 14-1 located on a side of the fourth insulating layer 14 away from the substrate 10, a fifth insulating layer 15 located on a side of the fourth insulating layer 14 away from the substrate 10, and a fifth conductive layer 15-1 located on a side of the fifth insulating layer 15 away from the substrate 10. The main structure of the driver chip pin shown in Figure 7 is basically the same as the main structure of the driver chip pin shown in Figure 6 above. The difference is that the portion of the surface of the fourth conductive layer 14-1 on the side away from the substrate 10 and close to the fifth insulating layer 15 is basically flush with the portion of the surface of the fifth insulating layer 15 on the side away from the substrate 10 and close to the fourth conductive layer 14-1, which can simplify the preparation process of the fourth via K4 and reduce the preparation cost of the display substrate.

[0108] FIG8 is a partial cross-sectional schematic diagram (five) of the driver chip pins of the display substrate according to an embodiment of the present disclosure. As shown in FIG8 , within a plane perpendicular to the display substrate, the first frame region of the display substrate may include a substrate 10, a first insulating layer 11 located on one side of the substrate 10, a first conductive layer 11-1 located on the side of the first insulating layer 11 away from the substrate 10, a second insulating layer 12 located on the side of the first conductive layer 11-1 away from the substrate 10, a third conductive layer 13-1 located on the side of the second insulating layer 12 away from the substrate 10, a fourth insulating layer 14 located on the side of the second insulating layer 12 away from the substrate 10, a fourth conductive layer 14-1 located on the side of the fourth insulating layer 14 away from the substrate 10, a fifth insulating layer 15 located on the side of the fourth insulating layer 14 away from the substrate 10, and a fifth conductive layer 15-1 located on the side of the fifth insulating layer 15 away from the substrate 10. The main structure of the driver chip pins shown in FIG8 is substantially the same as that of the driver chip pins shown in FIG7 , except that the third insulating layer does not extend into the first frame region, thereby simplifying the film layer structure in the first frame region.

[0109] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0110] Taking the structure of the driver chip pins of the display substrate shown in FIG4 as an example, the preparation process of the driver chip pins of the display substrate may include the following steps (11) to (17):

[0111] (11) Forming a first conductive layer pattern. Forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on one side of a substrate 10, and patterning the first conductive film through a patterning process to form a first insulating layer 11 on one side of the substrate 10 and a first conductive layer pattern located on one side of the first insulating layer 11. The first conductive layer 11-1 may include at least one data line lead 50, as shown in FIG9A.

[0112] (12) Forming a third insulating layer pattern. Forming the third insulating layer pattern may include: sequentially depositing a second insulating film and a third insulating film on one side of the substrate 10 having the aforementioned pattern formed thereon, patterning the third insulating film using a half-tone mask patterning process to form a second insulating layer pattern on one side of the first conductive layer 11-1, and forming a third insulating layer pattern on one side of the second insulating layer pattern, as shown in FIG9B .

[0113] As shown in FIG9B , the second insulating layer 12 may have at least one first via hole K1. The first via hole K1 penetrates the second insulating layer 12 along the thickness direction of the display substrate and exposes a portion of the surface of the data line lead 50 away from the substrate 10. The orthographic projection of the data line lead 50 on the display substrate may include the orthographic projection of the first via hole K1 on the display substrate. The second insulating layer 12 may protect the edge of the data line lead 50. The first via hole K1 may be a circular hole, an elliptical hole, a rectangular hole, a hexagonal hole, etc.

[0114] As shown in FIG9B , the third insulating layer 13 may have at least one second via K2. The second via K2 extends through the third insulating layer 13 along the thickness of the display substrate and exposes a portion of the surface of the second insulating layer 12 facing away from the substrate 10. The orthographic projection of the second via K2 on the display substrate may include the orthographic projection of the first via K1 on the display substrate, and the orthographic projection of the second via K2 on the display substrate may be larger than the orthographic projection of the first via K1 on the display substrate. In the first direction X, the orthographic projection of the second via K2 on the display substrate may include the orthographic projection of the data line lead 50 on the display substrate. For example, in the first direction X, the orthographic projection of the second via K2 on the display substrate may be larger than the orthographic projection of the data line lead 50 on the display substrate. By defining the relative relationship between the apertures of the second via and the first via, the height difference of the subsequently formed first connecting electrode along the thickness of the display substrate can be reduced, thereby facilitating the conductive connection between the components to be mounted (e.g., the driver chip) and the driver chip pins in the first frame area in subsequent steps and avoiding the problem of false connections.

[0115] (13) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include depositing a third conductive film on one side of the substrate 10 having the aforementioned pattern formed thereon, and patterning the third conductive film through a patterning process to form a third conductive layer pattern on one side of the third insulating layer 13, as shown in FIG9C . The third conductive layer 13-1 may include at least one first connection electrode 51.

[0116] As shown in FIG9C , at least a portion of the first connecting electrode 51 may be located within the first via hole K1 and the second via hole K2. The first connecting electrode 51 has a first sub-groove. The first sub-groove has a first groove bottom 511, a first groove top 512, and a first groove wall 513. The first groove bottom 511 and the first groove top 512 may be arranged opposite each other along the thickness direction of the display substrate, with the first groove bottom 511 closer to the substrate 10 than the first groove top 512. The first groove wall 513 may extend along the thickness direction of the display substrate. The first groove wall 513 has a first end and a second end that are arranged opposite each other. The first end of the first groove wall 513 may be connected to the first groove bottom 511, and the second end of the first groove wall 513 may extend away from the substrate 10. The first groove top 512 has a first end and a second end that are arranged opposite each other. The first end of the first groove top 512 may be connected to the second end of the first groove wall 513, and the second end of the first groove top 512 extends away from the first end. The orthographic projection of the first groove top 512 on the display substrate may be annular.

[0117] As shown in FIG9C , the first groove top 512 may contact the surface of the second insulating layer 12 on the side away from the substrate 10. As previously mentioned, limiting the relative relationship between the apertures of the second via hole K2 and the first via hole K1 may reduce the distance between the first groove top 512 and the first groove bottom 511 along the thickness direction of the display substrate, thereby reducing the groove depth of the groove structure subsequently formed.

[0118] (14) Forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include depositing a fourth conductive film on one side of the substrate 10 having the aforementioned pattern formed thereon, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern on one side of the third conductive layer 13-1, as shown in FIG9D.

[0119] As shown in FIG9D , the fourth conductive layer 14-1 may include at least one second connecting electrode 52. The second connecting electrode 52 has a second sub-groove. The second sub-groove has a second groove bottom 521, a second groove top 522, and a second groove wall 523. The second groove bottom 521 and the second groove top 522 may be arranged opposite each other along the thickness direction of the display substrate, with the second groove bottom 521 being closer to the substrate 10 than the second groove top 522. The second groove wall 523 may extend along the thickness direction of the display substrate. The second groove wall 523 has a first end and a second end that are arranged opposite each other. The first end of the second groove wall 523 may be connected to the second groove bottom 521, and the second end of the second groove wall 523 may extend away from the substrate 10. The second groove top 522 has a first end and a second end that are arranged opposite each other. The first end of the second groove top 522 may be connected to the second end of the second groove wall 523, and the second end of the second groove top 522 extends away from the first end. The orthographic projection of the second groove top 522 on the display substrate may be annular.

[0120] As shown in FIG9D , the second groove top 522 and the first groove top 512 can be in contact and connected, which can reduce the groove depth of the groove structure formed subsequently, avoid virtual connection between the components to be installed (for example, the driver chip) and the data line lead 50, and improve the reliability of the display substrate.

[0121] (15) Forming a fourth insulating layer pattern. Forming the fourth insulating layer pattern may include depositing a fourth insulating film on one side of the substrate 10 having the aforementioned pattern formed thereon, and patterning the fourth insulating film through a patterning process to form a fourth insulating layer pattern on one side of the fourth conductive layer 14-1, as shown in FIG9E.

[0122] As shown in Figure 9E, the fourth insulating layer 14 has at least one third via hole K3, which exposes a portion of the surface of the second connecting electrode 52 away from the substrate 10. The fourth insulating layer 14 can protect the edge of the second connecting electrode 52 and improve the second connecting electrode's resistance to water and oxygen.

[0123] (16) Forming a fifth insulating layer pattern. Forming the fifth insulating layer pattern may include depositing a fifth insulating film on one side of the substrate 10 having the aforementioned pattern formed thereon, and patterning the fifth insulating film through a patterning process to form a fifth insulating layer pattern located on one side of the fourth conductive layer 14-1, as shown in FIG9F.

[0124] As shown in FIG9F , the fifth insulating layer 15 may be provided with at least one fourth via hole K4. The fourth via hole K4 penetrates the fifth insulating layer 15 along the thickness direction of the display substrate and exposes a portion of the surface of the second connection electrode 52 on a side away from the substrate 10. The orthographic projection of the fourth via hole K4 on the display substrate may be located within the range of the orthographic projection of the second connection electrode 52 on the display substrate.

[0125] (17) Forming a fifth conductive layer pattern. Forming the fifth conductive layer pattern may include depositing a fifth conductive film on one side of the substrate 10 having the aforementioned pattern formed thereon, and patterning the fifth conductive film through a patterning process to form a fifth conductive layer pattern located on one side of the fifth insulating layer 15, as shown in FIG9G .

[0126] As shown in Figure 9G, the fifth conductive layer 15-1 may include at least one driver chip pin 53, and at least a portion of the driver chip pin 53 may be located within the fourth via K4. For example, the orthographic projection of the driver chip pin 53 on the display substrate may include the orthographic projection of the fourth via K4 on the display substrate.

[0127] As shown in FIG9G , the driver chip pin 53 has a groove structure 60, and the groove structure 60 is recessed toward one side of the substrate 10. The groove structure 60 is configured to accommodate conductive adhesive, etc., to achieve electrical connection between the component to be mounted and the data line lead 50. For example, the component to be mounted may be a driver chip (Integrated Circuit, IC). The driver chip and the data line lead 50 are electrically connected via the groove structure 60.

[0128] The groove structure 60 includes a groove bottom 61, a groove top 62, and a groove wall 63. The groove bottom 61 and the groove top 62 may be arranged relative to each other along the thickness direction of the display substrate, with the groove bottom 61 being closer to the substrate 10 than the groove top 62. The groove wall 63 may extend along the thickness direction of the display substrate. The groove wall 63 has a first end and a second end that are arranged relative to each other. The first end of the groove wall 63 may be connected to the groove bottom 61, and the second end of the groove wall 63 may extend in a direction away from the substrate 10. The groove top 62 has a first end and a second end that are arranged relative to each other. The first end of the groove top 62 may be connected to the second end of the groove wall 63, and the second end of the groove top 62 may extend in a direction away from the first end. The orthographic projection of the groove top 62 on the display substrate may be annular. The groove depth H of the groove structure 60 may be 0.60 microns to 0.65 microns.

[0129] Figure 10 is a partial cross-sectional schematic diagram of the driver chip pins of a display substrate according to another embodiment of the present disclosure. As shown in Figure 10, within a plane perpendicular to the display substrate, the first border region of the display substrate may include a substrate 10, a first insulating layer 11 located on one side of the substrate 10, a second insulating layer 12 located on a side of the first insulating layer 11 away from the substrate 10, a second conductive layer 12-1 located on a side of the second insulating layer 12 away from the substrate 10, a third insulating layer 13 located on a side of the second conductive layer 12-1 away from the substrate 10, a third conductive layer 13-1 located on a side of the third insulating layer 13 away from the substrate 10, a fourth conductive layer 14-1 located on a side of the third conductive layer 13-1 away from the substrate 10, a fourth insulating layer 14 located on a side of the fourth conductive layer 14-1 away from the substrate 10, a fifth insulating layer 15 located on a side of the fourth conductive layer 14-1 away from the substrate 10, and a fifth conductive layer 15-1 located on a side of the fifth insulating layer 15 away from the substrate 10.

[0130] As shown in Figure 10, the second conductive layer 12-1 in the first border region of the display substrate may include at least one data line lead 50. For example, multiple data line leads 50 may be arranged in an interval along the first direction X and extend along the second direction Y. As shown in Figure 10, only one data line lead 50 is illustrated as an example, and the data line lead 50 extends along the second direction Y. In the first border region of the display substrate, the third conductive layer 13-1 may include at least one first connection electrode 51, the fourth conductive layer 14-1 may include at least one second connection electrode 52, and the fifth conductive layer 15-1 may include at least one driver chip pin 53. The driver chip pin 53 is connected to the data line lead 50 via the second connection electrode 52 and the first connection electrode 51 to enable signal transmission.

[0131] In an exemplary embodiment, as shown in FIG10 , the third conductive layer 13 - 1 in the first frame area of ​​the display substrate may include at least one first connecting electrode 51. A portion of the first connecting electrode 51 is in contact and connected to a portion of the data line lead 50 via a via located in the third insulating layer 13. As shown in FIG10 , the third insulating layer 13 may be provided with at least one second via K2, which passes through the third insulating layer 13 along the thickness direction of the display substrate and exposes a portion of the surface of the data line lead 50 away from the substrate 10. The orthographic projection of the data line lead 50 on the display substrate may include the orthographic projection of the second via K2 on the display substrate. The third insulating layer 13 may protect the edge of the data line lead 50, prevent erosion of the data line lead by water, oxygen, etc., and extend the service life of the display substrate. For other structures of the driver chip pin shown in FIG10 , reference may be made to the aforementioned description of the driver chip pin structure shown in FIG4 , and no further details will be given here.

[0132] FIG11 is a partial cross-sectional schematic diagram of the driver chip pins of a display substrate according to another embodiment of the present disclosure. As shown in FIG11 , in a plane perpendicular to the display substrate, the first border region of the display substrate may include a substrate 10, a first insulating layer 11 located on one side of the substrate 10, a first conductive layer 11-1 located on a side of the first insulating layer 11 away from the substrate 10, a second conductive layer 12-1 located on a side of the first conductive layer 11-1 away from the substrate 10, a third insulating layer 13 located on a side of the second conductive layer 12-1 away from the substrate 10, a third conductive layer 13-1 located on a side of the third insulating layer 13 away from the substrate 10, a fourth conductive layer 14-1 located on a side of the third conductive layer 13-1 away from the substrate 10, a fourth insulating layer 14 located on a side of the fourth conductive layer 14-1 away from the substrate 10, a fifth insulating layer 15 located on a side of the fourth conductive layer 14-1 away from the substrate 10, and a fifth conductive layer 15-1 located on a side of the fifth insulating layer 15 away from the substrate 10. In this embodiment, the first conductive layer 11-1 located in the first border region may also be referred to as a leveling layer.

[0133] As shown in FIG11 , the first conductive layer 11-1 may include at least one leveling block 70, and the leveling block 70 may be in the shape of a rectangular block, etc. In the embodiment of the present disclosure, only one leveling block 70 is illustrated as an example. The second conductive layer 12-1 may include at least one data line lead 50. For example, multiple data line leads 50 may be arranged at intervals along the first direction X and extend along the second direction Y. As shown in FIG11 , only one data line lead 50 is illustrated as an example, and the data line lead 50 extends along the second direction Y. In the first border area of ​​the display substrate, the third conductive layer 13-1 may include at least one first connecting electrode 51, the fourth conductive layer 14-1 may include at least one second connecting electrode 52, and the fifth conductive layer 15-1 may include at least one driver chip pin 53. The driver chip pin 53 is connected to the data line lead 50 via the second connecting electrode 52 and the first connecting electrode 51 to realize signal transmission.

[0134] As shown in FIG11 , the orthographic projection of the data line lead 50 on the display substrate may include the orthographic projection of the leveling block 70 on the display substrate. For example, the orthographic projection of the data line lead 50 on the display substrate may be larger than the orthographic projection of the leveling block 70 on the display substrate. The third insulating layer 13 has at least one second via K2, and the orthographic projection of the second via K2 on the display substrate is located within the orthographic projection of the data line lead 50 on the display substrate. As shown in FIG11 , the surface of the data line lead 50 away from the substrate 10 is flush with the surface of the third insulating layer 13 away from the substrate 10. The leveling block 70 can be used to compensate for the height difference between the data line lead 50 and the third insulating layer 13 along the thickness direction of the display substrate, which is beneficial for the flattening of the first connecting electrode and the second connecting electrode to be formed subsequently. The depth H of the groove structure to be formed subsequently can be shortened to avoid virtual connection between the components to be installed (for example, the driver chip) and the display substrate, thereby improving the reliability of the display device.

[0135] In one exemplary embodiment, as shown in FIG11 , the third conductive layer 13 - 1 in the first border region of the display substrate may include at least one first connection electrode 51. Portions of the first connection electrode 51 are in contact and connected to portions of the data line lead 50 via second via holes K2 located in the third insulating layer 13. As shown in FIG11 , the first connection electrode 51 may be rectangular.

[0136] In one exemplary embodiment, as shown in FIG11 , in a first direction X, the orthographic projection of the first connection electrode 51 on the display substrate may include the orthographic projection of the data line lead 50 on the display substrate. The first connection electrode 51 can prevent water and oxygen from corroding the data line lead 50, thereby improving the reliability of the display substrate.

[0137] In one exemplary embodiment, as shown in FIG11 , the fourth conductive layer 14 - 1 in the first border region of the display substrate may include at least one second connection electrode 52 . A portion of the second connection electrode 52 is in contact and connected to a portion of the first connection electrode 51 via a third via K3 located in the fourth insulating layer 14 . As shown in FIG11 , the second connection electrode 52 may be rectangular. The orthographic projection of the second connection electrode 52 on the display substrate may include the orthographic projection of the first connection electrode 51 on the display substrate.

[0138] In one exemplary embodiment, as shown in FIG11 , the fifth conductive layer 15 - 1 in the first border region of the display substrate may include at least one driver chip pin 53. A portion of the driver chip pin 53 is in contact and connected to a portion of the second connection electrode 52 via a fourth via K4 located in the fifth insulating layer 15 . The orthographic projection of the driver chip pin 53 on the display substrate may be within the range of the orthographic projection of the second connection electrode 52 on the display substrate.

[0139] In one exemplary embodiment, as shown in FIG11 , the driver chip pin 53 has a groove structure 60 that is recessed toward one side of the substrate 10. The groove structure 60 is configured to accommodate conductive adhesive to electrically connect the component to be mounted (e.g., the driver chip) to the data line lead 50. The groove structure 60 can limit the conductive particles within the conductive adhesive. After the component to be mounted is assembled on the display substrate, the conductive particles are squeezed by the component to be mounted and can be stably retained within the groove structure 60, ensuring good connectivity between the component to be mounted and the display substrate, thereby improving the reliability of the display substrate.

[0140] In an exemplary embodiment, as shown in FIG11 , the groove structure 60 includes a groove bottom 61, a groove top 62, and a groove wall 63. The groove bottom 61 and the groove top 62 may be arranged opposite each other along the thickness direction of the display substrate, with the groove bottom 61 being closer to the substrate 10 than the groove top 62. The groove wall 63 may extend along the thickness direction of the display substrate, and the groove wall 63 may have a first end and a second end arranged opposite each other. The first end of the groove wall 63 may be connected to the groove bottom 61, and the second end of the groove wall 63 may extend in a direction away from the substrate 10. The groove top 62 has a first end and a second end arranged opposite each other. The first end of the groove top 62 may be connected to the second end of the groove wall 63, and the second end of the groove top 62 extends in a direction away from the first end. The orthographic projection of the groove top 62 on the display substrate may be annular. For example, the orthographic projection of the groove top 62 on the display substrate may be a circular ring or a rectangular ring, etc.

[0141] In an exemplary embodiment, as shown in FIG11 , a distance H is defined between the groove bottom 61 and the groove top 62 along the thickness direction of the display substrate, i.e., the groove depth of the groove structure 60. The distance H may range from 0.40 μm to 0.55 μm. For example, the distance H may be 0.50 μm, or 0.45 μm.

[0142] Figure 12 is a second partial cross-sectional schematic diagram of driver chip pins of a display substrate according to another embodiment of the present disclosure. As shown in Figure 12, within a plane perpendicular to the display substrate, the first border region of the display substrate may include a substrate 10, a first insulating layer 11 located on one side of the substrate 10, a first conductive layer 11-1 located on a side of the first insulating layer 11 away from the substrate 10, a second conductive layer 12-1 located on a side of the first conductive layer 11-1 away from the substrate 10, a third insulating layer 13 located on a side of the second conductive layer 12-1 away from the substrate 10, a third conductive layer 13-1 located on a side of the third insulating layer 13 away from the substrate 10, a fourth conductive layer 14-1 located on a side of the third conductive layer 13 away from the substrate 10, a fourth insulating layer 14 located on a side of the fourth conductive layer 14-1 away from the substrate 10, a fifth insulating layer 15 located on a side of the fourth conductive layer 14-1 away from the substrate 10, and a fifth conductive layer 15-1 located on a side of the fifth insulating layer 15 away from the substrate 10. As shown in Figure 12, the first conductive layer 11-1 may include at least one data line lead 50. The second conductive layer 12-1 may include at least one leveling block 70. In this embodiment, the second conductive layer 12-1 located in the first border area can also be called a leveling layer. The other structures of the driver chip pins can refer to the aforementioned description of the driver chip pin structure shown in Figure 11, which will not be elaborated here.

[0143] Taking the structure of the driver chip pins of the display substrate shown in FIG12 as an example, the preparation process of the driver chip pins of the display substrate may include the following steps (21) to (28):

[0144] (21) Forming a first conductive layer pattern. Forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on one side of a substrate 10, and patterning the first conductive film through a patterning process to form a first insulating layer 11 on one side of the substrate 10 and a first conductive layer pattern located on one side of the first insulating layer 11. The first conductive layer 11-1 may include at least one data line lead 50, as shown in FIG13A.

[0145] (22) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: depositing a second conductive film on one side of the substrate 10 having the aforementioned pattern formed thereon, and patterning the second conductive film through a patterning process to form a second conductive layer pattern on one side of the first conductive layer 11-1, as shown in FIG13B.

[0146] 13B , the second conductive layer 12 - 1 may include at least one leveling block 70 . In the first direction X, the orthographic projection of the leveling block 70 on the display substrate may include the orthographic projection of the data line lead 50 on the display substrate.

[0147] (23) Forming a third insulating layer pattern. Forming the third insulating layer pattern may include depositing a third insulating film on one side of the substrate 10 having the aforementioned pattern formed thereon, and patterning the third insulating film through a patterning process to form a third insulating layer pattern on one side of the second conductive layer 12-1, as shown in FIG13C.

[0148] As shown in FIG13C , the third insulating layer 13 may include at least one second via K2. The second via K2 extends through the thickness of the third insulating layer 13, exposing at least a portion of the surface of the leveling block 70 facing away from the substrate 10. The surface of the leveling block 70 facing away from the substrate 10 may be flush with the surface of the third insulating layer 13 facing away from the substrate 10.

[0149] (24) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include depositing a third conductive film on one side of the substrate 10 having the aforementioned pattern formed thereon, and patterning the third conductive film through a patterning process to form a third conductive layer pattern on one side of the third insulating layer 13, as shown in FIG13D.

[0150] As shown in FIG13D , the third conductive layer 13-1 may include at least one first connection electrode 51. Portions of the first connection electrode 51 may be in contact and connected to portions of the leveling block 70 via second vias K2 located in the third insulating layer 13. The first connection electrode 51 may be rectangular. In the first direction X, the orthographic projection of the first connection electrode 51 on the display substrate may include the orthographic projection of the leveling block 70 on the display substrate.

[0151] (25) Forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include depositing a fourth conductive film on one side of the substrate 10 having the aforementioned pattern formed thereon, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern on one side of the third conductive layer 13-1, as shown in FIG13E.

[0152] 13E , the fourth conductive layer 14-1 may include at least one second connection electrode 52, which contacts a surface of the first connection electrode 51 away from the substrate 10. The orthographic projection of the second connection electrode 52 on the display substrate may include the orthographic projection of the first connection electrode 51 on the display substrate.

[0153] (26) Forming a fourth insulating layer pattern. Forming the fourth insulating layer pattern may include depositing a fourth insulating film on one side of the substrate 10 having the aforementioned pattern formed thereon, and patterning the fourth insulating film through a patterning process to form a fourth insulating layer pattern on one side of the fourth conductive layer 14-1, as shown in FIG13F.

[0154] As shown in FIG. 13F , the fourth insulating layer 14 may include at least one third via hole K3 , and the third via hole K3 exposes at least a portion of the surface of the second connecting electrode 52 away from the substrate 10 .

[0155] (27) Forming a fifth insulating layer pattern. Forming the fifth insulating layer pattern may include depositing a fifth insulating film on one side of the substrate 10 having the aforementioned pattern formed thereon, and patterning the fifth insulating film through a patterning process to form a fifth insulating layer pattern on one side of the fourth conductive layer 14-1, as shown in FIG13G.

[0156] As shown in FIG13G , the fifth insulating layer 15 may include at least one fourth via hole K4. The fourth via hole K4 penetrates the fifth insulating layer 15 along the thickness direction of the display substrate and exposes a portion of the surface of the second connection electrode 52 on the side away from the substrate 10. The fourth via hole K4 allows a subsequently formed driver chip pin to be connected to the second connection electrode 52 via the fourth via hole.

[0157] (28) Forming a fifth conductive layer pattern. Forming the fifth conductive layer pattern may include depositing a fifth conductive film on one side of the substrate 10 having the aforementioned pattern formed thereon, and patterning the fifth conductive film through a patterning process to form a fifth conductive layer pattern on one side of the fifth insulating layer 15, as shown in FIG13H.

[0158] As shown in FIG13H , the fifth conductive layer 15 - 1 may include at least one driver chip pin 53 . Part of the driver chip pin 53 may be located within the fourth via hole K4 , and the driver chip pin 53 is connected to the second connection electrode 52 via the fourth via hole K4 .

[0159] FIG14 is a partial cross-sectional schematic diagram of a display device according to an embodiment of the present disclosure. As shown in FIG14 , the display device includes a display substrate, a conductive adhesive 80, and components to be installed. For example, the components to be installed can be conventional electrical components in the display field. In the embodiment of the present disclosure, the component to be installed is taken as a driver chip 90 (Integrated Circuit, IC) as an example. The driver chip 90 can be connected to the driver chip pin 53 in the first frame area of ​​the display substrate through the conductive adhesive 80. FIG14 shows a partial cross-sectional schematic diagram of the driver chip pin in the first frame area of ​​the display device.

[0160] As shown in Figure 14, the conductive glue 80 may include multiple conductive particles, and part of the conductive particles may be located within the groove structure 60 in the first frame area. After the driving chip 90 is assembled in place, the conductive particles may be squeezed between the driving chip 90 and the groove structure 60, so that the driving chip 90 and the display substrate have good electrical connectivity, avoiding the occurrence of dark lines and other defects in the first frame area, and improving the reliability of the display device.

[0161] Another embodiment of the present disclosure provides a display device, comprising a display substrate as described in any of the above embodiments. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present disclosure are not limited thereto.

[0162] Although the embodiments disclosed herein are as described above, the contents described are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. It should be noted that the above embodiments or implementations are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the implementations without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising: A substrate, comprising a display area and a first frame area located on one side of the display area; A plurality of sub-pixels are located in the display area; A plurality of data lines are located in the display area, and the plurality of data lines are electrically connected to the plurality of sub-pixels; A plurality of data line leads are located in the first frame area, and the plurality of data line leads are electrically connected to the plurality of data lines; A plurality of driver chip pins are located in the first frame area, one of the driver chip pins is electrically connected to a data line lead, and the plurality of driver chip pins are located on a side of the plurality of data line leads away from the substrate; Among them, there is at least one groove structure on the side surface of the driving chip pin away from the substrate, and the at least one groove structure includes a groove bottom and a groove wall connecting the groove bottom. The at least one groove structure has a groove depth along the thickness direction of the display substrate, and the groove depth ranges from 0.40 microns to 0.65 microns.

2. The display substrate according to claim 1, wherein: In a plane perpendicular to the display substrate, the first frame area includes a first metal layer, a second metal layer, a third metal layer and a fourth metal layer located on one side of the substrate and stacked in sequence; the first metal layer includes the multiple data line leads, and the fourth metal layer includes the multiple driver chip pins.

3. The display substrate according to claim 2, wherein: In a plane perpendicular to the display substrate, the first border area also includes at least one insulating layer, and the at least one insulating layer is located between the first metal layer and the second metal layer; the second metal layer includes at least one connecting electrode, a portion of the connecting electrode is located in a via hole of the at least one insulating layer, and is in contact and connected with a surface of the data line lead away from the substrate.

4. The display substrate according to claim 3, wherein: The at least one insulating layer includes a first inorganic layer and a second inorganic layer, and the second inorganic layer is farther away from the substrate than the first inorganic layer; in the line width direction of the data line lead, the orthographic projection of the via hole provided in the first inorganic layer on the display substrate is located within the orthographic projection of the data line lead on the display substrate, and the orthographic projection of the via hole provided in the second inorganic layer on the display substrate includes the orthographic projection of the data line lead on the display substrate, and the orthographic projection of the via hole provided in the second inorganic layer on the display substrate is larger than the orthographic projection of the data line lead on the display substrate.

5. The display substrate according to claim 3, wherein: The insulating layer is provided between the first metal layer and the second metal layer. In the line width direction of the data line lead, the orthographic projection of the via hole provided in the insulating layer on the display substrate is located within the orthographic projection of the data line lead on the display substrate.

6. The display substrate according to any one of claims 2 to 5, wherein: In a plane perpendicular to the display substrate, the display area includes a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are located on one side of the substrate and are stacked in sequence; The first metal layer and the first gate metal layer are in the same layer structure, the second metal layer and the first source-drain metal layer are in the same layer structure, and the third metal layer and the second source-drain metal layer are in the same layer structure.

7. The display substrate according to any one of claims 2 to 5, wherein: In a plane perpendicular to the display substrate, the display area includes a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are located on one side of the substrate and are stacked in sequence; The first metal layer and the second gate metal layer are in the same layer structure, the second metal layer and the first source-drain metal layer are in the same layer structure, and the third metal layer and the second source-drain metal layer are in the same layer structure.

8. The display substrate according to any one of claims 2 to 5, wherein: The second metal layer includes at least one first connecting electrode, and the third metal layer includes at least one second connecting electrode; at least a portion of the surface of the second connecting electrode away from the substrate side is in contact with the groove structure of the driving chip pin, and a portion of the surface of the first connecting electrode close to the substrate side is in contact with the data line lead.

9. The display substrate according to claim 8, wherein: The first connecting electrode has a first sub-groove, the second connecting electrode has a second sub-groove, the orthographic projection of the groove structure of the driving chip pin on the display substrate is located within the orthographic projection of the second sub-groove on the display substrate, and the orthographic projection of the second sub-groove on the display substrate is located within the orthographic projection of the first sub-groove on the display substrate.

10. The display substrate according to claim 2, wherein: In a plane perpendicular to the display substrate, the first border area also includes a leveling layer, and the leveling layer is located between the substrate and the first metal layer; the leveling layer includes at least one leveling block; in the line width direction of the data line lead, the orthographic projection of the data line lead on the display substrate includes the orthographic projection of the leveling block on the display substrate.

11. The display substrate according to claim 2, wherein: In a plane perpendicular to the display substrate, the first border area also includes a leveling layer, the leveling layer is located between the first metal layer and the second metal layer, and the leveling layer includes at least one leveling block; in the line width direction of the data line lead, the orthographic projection of the leveling block on the display substrate includes the orthographic projection of the data line lead on the display substrate, and the data line lead is electrically connected to the groove structure of the driving chip pin via the leveling block.

12. The display substrate according to claim 10 or 11, wherein: In a plane perpendicular to the display substrate, the first border area also includes at least one insulating layer, the at least one insulating layer is located between the first metal layer and the second metal layer, and the surface of the at least one insulating layer away from the substrate is flush with the surface of the data line lead and the surface of the leveling block away from the substrate.

13. The display substrate according to claim 12, wherein: The second metal layer includes at least one first connection electrode, and the third metal layer includes at least one second connection electrode; the data line lead is connected to the groove structure of the driving chip pin via the first connection electrode and the second connection electrode; Wherein, a surface of the first connecting electrode away from the substrate is a plane.

14. The display substrate according to claim 13, wherein: A surface of the second connecting electrode away from the substrate is a plane.

15. The display substrate according to claim 10 or 11, wherein: In a plane perpendicular to the display substrate, the display area includes a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are located on one side of the substrate and are stacked in sequence; The second metal layer and the first source-drain metal layer are in the same layer structure, and the third metal layer and the second source-drain metal layer are in the same layer structure; The leveling layer and one of the first gate metal layer and the second gate metal layer are in the same layer structure, and the first metal layer and the other of the first gate metal layer and the second gate metal layer are in the same layer structure.

16. A display device comprising the display substrate according to any one of claims 1 to 15.

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