Successive approximation register analog-to-digital converter, terminal device, and signal processing method

Abstract

A successive approximation register analog-to-digital converter, comprising a comparator (1), a serial data latch module (2), and a digital-to-analog converter (3). The comparator (1) compares an input signal with a reference signal by bits, and for each bit, after bit comparison is complete, sends a comparison result of the bit to the serial data latch module (2). The serial data latch module (2) generates a first reset signal after receiving the comparison result of the last bit and sends the first reset signal to the digital-to-analog converter (3). The digital-to-analog converter (3) resets on the basis of the first reset signal. As long as the comparison result of the last bit is obtained, the digital-to-analog converter (3) can be immediately reset, removing the time sequence of synchronous data and reset data latch logic and optimizing time decomposition of the successive approximation register analog-to-digital converter, helping to improve a sampling rate. Further provided are a terminal device and a signal processing method.

Description

Successive approximation register type analog-to-digital converter, terminal device and signal processing method

[0001] Cross-references to related publications

[0002] This disclosure claims priority to a Chinese patent application filed with the State Intellectual Property Office on September 28, 2023, with application number CN202311284807.8 and invention name “Successive approximation register type analog-to-digital converter, terminal device and signal processing method”. The entire contents of the application are incorporated by reference into this disclosure. Technical Field

[0003] The embodiments of the present disclosure relate to, but are not limited to, the field of communication technologies, and in particular to a successive approximation register analog-to-digital converter, a terminal device, and a signal processing method. Background Art

[0004] In high-speed ADC (analog-to-digital converter)-based serdes (serial-to-digital converter) applications, the ADC speed requirements are increasing. In 112G serdes applications, the ADC must achieve a 64GHz sampling rate. This is typically achieved using a multi-channel time-interleaved architecture. The internal SUBADC (low-precision sub-analog-to-digital converter) is implemented using a high-speed asynchronous SARADC (successive approximation register analog-to-digital converter). The SARADC is required to achieve a sampling rate of up to 1GHz and a resolution of 7 bits.

[0005] The internal timing of a high-speed asynchronous SAR ADC is very tight, making it difficult to achieve a 1GHz sampling rate. The time left for conversion is very limited, less than 1ns. At 7-bit resolution, the time left for each bit conversion may be only about 100ps, so optimizing its timing is very critical.

[0006] Summary of the Invention

[0007] The present disclosure provides a successive approximation register analog-to-digital converter, a terminal device, and a signal processing method.

[0008] In a first aspect, an embodiment of the present disclosure provides a successive approximation register analog-to-digital converter, comprising a comparator, a serial data latch module, and a digital-to-analog converter, wherein the comparator is configured to compare an input signal with a reference signal bit by bit, and for each bit, after the bit comparison is completed, the comparison result of the bit is sent to the serial data latch module; the serial data latch module is configured to generate a first reset signal after receiving the comparison result of the last bit, and send the first reset signal to the digital-to-analog converter; the digital-to-analog converter is configured to reset according to the first reset signal.

[0009] On the other hand, an embodiment of the present disclosure further provides a terminal device, comprising the successive approximation register analog-to-digital converter as described above.

[0010] On the other hand, an embodiment of the present disclosure also provides a signal processing method, which is applied to the successive approximation register type analog-to-digital converter as described above, and the method includes: comparing the input signal with the reference signal bit by bit; generating a first reset signal after the comparison of the last bit is completed; and resetting the digital-to-analog converter according to the first reset signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG1 is a module diagram of a SAR ADC according to an embodiment of the present disclosure;

[0012] FIG2 is a module diagram of a SAR ADC according to an embodiment of the present disclosure;

[0013] FIG3 is a schematic structural diagram of a SAR ADC according to an embodiment of the present disclosure;

[0014] FIG4 is a schematic diagram of signal timing of a SAR ADC according to an embodiment of the present disclosure;

[0015] FIG5 is a schematic diagram of the structure of a SARADC in the related art;

[0016] FIG6 is a schematic diagram of a signal timing sequence of a SARADC in the related art;

[0017] FIG7 is a schematic diagram showing a time comparison between a SAR ADC according to an embodiment of the present disclosure and a SAR ADC in related art;

[0018] FIG8 is a schematic diagram of a signal processing flow according to an embodiment of the present disclosure; and

[0019] FIG9 is a schematic diagram of a signal processing flow according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art.

[0021] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0022] The terms used herein are used only to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements, and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof is not excluded.

[0023] The embodiments described herein may be described with reference to plan views and / or cross-sectional views, with the aid of idealized schematic diagrams of the present disclosure. Thus, the example illustrations may be modified based on manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to the embodiments shown in the accompanying drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the accompanying drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate specific shapes of the regions of the elements, but are not intended to be limiting.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0025] A single cycle of the high-speed asynchronous SAR ADC clock signal consists of two phases: the sample-and-hold phase and the conversion phase. The sample-and-hold phase primarily samples the input signal. The conversion phase primarily converts the sampled input signal. When the resolution is 7 bits, the conversion phase requires at least seven data comparisons. After each data comparison, the comparison result is transmitted to the DAC via the data latch module. Each data conversion can be divided into three delay times: 1) the comparison delay of the comparator; 2) the data latch logic delay; and 3) the response time of the DAC. After each data conversion, the clock is used to latch the data, which consumes timing. Afterward, the data latch module must be reset to avoid affecting the next sampling phase. In related technologies, both DAC reset and data latch reset are achieved by resetting the data latch logic, and the data latch reset also requires the time of the conversion phase.

[0026] The inventors of the disclosed embodiments discovered that during the conversion phase, the DAC does not need to respond to the last bit of data comparison. As long as the comparator compares the result, normal conversion can proceed, allowing the DAC to be immediately reset. Therefore, the DAC reset can be independently controlled to optimize signal timing. Based on this discovery, the disclosed embodiments provide a successive approximation register analog-to-digital converter (SARADC).

[0027] The present disclosure provides a SAR ADC. As shown in FIG1 , the SAR ADC includes a comparator 1, a serial data latch module 2, and a digital-to-analog converter 3. The comparator 1 is configured to compare an input signal with a reference signal on a bit-by-bit basis. For each bit, after the bit comparison is completed, the comparison result of the bit is sent to the serial data latch module 2. The serial data latch module 2 is configured to generate a first reset signal (dac_rst) after receiving the comparison result of the last bit, and send the first reset signal (dac_rst) to the digital-to-analog converter 3. The digital-to-analog converter is configured to reset according to the first reset signal (dac_rst).

[0028] The serial data latch module 2 latches the comparison result of each bit received, and sends a voltage control signal to the digital-to-analog converter 3 according to the comparison result of each bit. The digital-to-analog converter 3 controls the voltage of the input signal according to the voltage control signal corresponding to each bit.

[0029] The digital-to-analog converter 3 includes but is not limited to a CDAC (capacitive digital-to-analog converter), and may also be other types of digital-to-analog converters, such as a resistive DAC (R2R-DAC) or a current-steering DAC (Current_Steering DACs).

[0030] The disclosed embodiment controls the DAC reset by comparing the last bit of the input signal. The DAC can be reset immediately as soon as the comparison result of the last bit is obtained. This allows data synchronization and data latch reset to be performed in the next cycle, saving the timing of synchronizing data and resetting data latch logic, optimizing the time decomposition of the SAR ADC, and facilitating an increase in the sampling rate.

[0031] It should be noted that the SARADC may further include an asynchronous clock generation module. The asynchronous clock generation module is configured to generate an asynchronous clock signal (clk_async) and send the asynchronous clock signal to the comparator 1. The comparator 1 is configured to compare the input signal with the reference signal on a bit-by-bit basis according to the asynchronous clock signal.

[0032] In some embodiments, as shown in FIG2 , the SARADC may further include a data synchronization module 4 , and the serial data latch module 2 may be further configured to latch the comparison result of each bit and send the comparison result of each bit to the data synchronization module 4 ; the data synchronization module 4 may be configured to perform data synchronization processing on the comparison result of each bit.

[0033] FIG3 is a schematic diagram of the structure of the SARADC provided in an embodiment of the present disclosure, and FIG4 is a schematic diagram of the signal timing of the SARADC provided in an embodiment of the present disclosure. As shown in FIG3 and FIG4 , the data synchronization process (S&H time) includes two stages: S (setup) and H (hold). The data synchronization process occurs after the DAC is reset and before the data latch is reset. The latch output clock signal (dout_latch_clk) is input to the data synchronization module 4. The S stage is between the first reset signal (dac_rst) and the latch output clock signal (dout_latch_clk), and the H stage is from the generation of the latch output clock signal (dout_latch_clk) to before the data latch is reset.

[0034] In some embodiments, the data synchronization module 4 is configured to perform data synchronization processing on the comparison result of each bit in the next sampling and holding phase.

[0035] In some embodiments, the serial data latch module 2 includes a plurality of serial data latch units, the number of which is the same as the number of bits; the data synchronization module 4 includes a plurality of data synchronization units, each corresponding to each serial data latch unit. Each serial data latch unit is configured to latch a comparison result of a corresponding bit and transmit the comparison result of the corresponding bit to a corresponding data synchronization unit; each data synchronization unit is configured to perform data synchronization processing on the comparison result of the corresponding bit.

[0036] As shown in FIG3 , the serial data latch module 2 includes n serial data latch units (D_LATCH N, D_LATCH N-1, ..., D_LATCH 1, D_LATCH 0). Correspondingly, the data synchronization module 4 includes n data synchronization units DFF (D-type flip-flops) connected to each serial data latch unit. The n serial data latch units latch the comparison results of the corresponding bits and send them to the data synchronization units connected thereto for data synchronization. For example, D_LATCH N latches the comparison result D of the nth bit. <n>, and the comparison result D of the nth bit <n>Send it to the corresponding DFF N, which will <n>Perform data synchronization.

[0037] As shown in FIG4 , the asynchronous clock signal (clk_async) generated by the asynchronous clock generation module is a pulse signal. Each rising edge of the asynchronous clock signal triggers a serial data latch unit to output a corresponding bit comparison result to a corresponding synchronization unit.

[0038] In some embodiments, the serial data latch module 2 is further configured to receive a second reset signal (d_latch_rst) and be reset according to the second reset signal (d_latch_rst); the second reset signal (d_latch_rst) is generated in the next sampling and holding phase.

[0039] In some embodiments, the second reset signal can be generated by the data latch unit D_LATCH 0 that latches the last bit comparison result, or the second reset signal can be generated by a clock generator for generating the clock signal (clkin). As shown in Figure 4, the second reset signal (d_latch_rst) is generated during the sample-and-hold phase of the next clock signal cycle. Therefore, the data latch reset can be delayed until the sample-and-hold phase of the next clock signal cycle without affecting the data sampling in the next clock cycle, thus saving the timing of resetting the data latch logic.

[0040] As shown in FIG3 , in the embodiment of the present disclosure, the input signal is a differential signal, including a first input signal (VIP) and a second input signal (VIN). The two input signals are input to the comparator 1 through a sampling switch.

[0041] The digital-to-analog converter 3 includes a first digital-to-analog converter DACP and a second digital-to-analog converter DACN, and the serial data latch module 2 includes a first serial data latch module and a second serial data latch module. The first serial data latch module is a module connected to the first digital-to-analog converter DACP, and the second serial data latch module is a module connected to the second digital-to-analog converter DACN.

[0042] The comparator 1 is configured to, for each bit, send the comparison result of the bit to the first serial data latch module and the second data latch module after the bit comparison is completed; the first serial data latch module is configured to generate a first reset signal (dac_rst) after receiving the comparison result of the last bit, and send the first reset signal (dac_rst) to the first digital-to-analog converter DACP and the second digital-to-analog converter DACN; the first digital-to-analog converter DACP and the second digital-to-analog converter DACN are configured to be reset according to the first reset signal (dac_rst).

[0043] In the embodiment of the present disclosure, the data synchronization module 4 is connected to the first digital-to-analog converter DACP. It should be noted that the data synchronization module 4 may also be connected to the second digital-to-analog converter DACN.

[0044] To clearly illustrate the solution of the embodiment of the present disclosure, the structure and signal timing of the SAR ADC of the embodiment of the present disclosure are compared with the structure and signal timing of the SAR ADC of the related art with reference to FIG. 3-6 .

[0045] Figure 5 is a schematic diagram of the structure of a SAR ADC in the related art. As shown in Figure 5, a traditional differential signal SAR ADC includes a DAC (i.e., DACP and DACN), a comparator, an asynchronous clock generation module, a serial data latch module (D_LATCH N - D_LATCH 0), and a synchronization module (DFFN - DFF0). In traditional high-speed SAR ADCs, the timing of the conversion phase is very tight, requiring the conversion of all bits of data and the reset of the corresponding serial data latch units, which actually also requires resetting the DAC. Figure 6 is a schematic diagram of the signal timing of a SAR ADC in the related art. As shown in Figure 6, since resetting the serial data latch module requires clearing the data latched in each serial data latch unit (i.e., the comparison results of each bit), the second reset signal (d_latch_rst) used to reset the serial data latch module must be generated before the sample-and-hold phase of the next clock cycle, otherwise it will affect data sampling in the next clock cycle. Therefore, when the SAR ADC sampling speed is very fast, the time left for the serial data latch to establish and hold (S&H time) is very small, that is, the data synchronization time is short, resulting in a shortage of timing resources.

[0046] As shown in FIG3 , the differential signal SARADC provided in the embodiment of the present disclosure, compared with the traditional differential signal SARADC, adds a DAC reset signal input terminal at the DAC switching switch, that is, a DAC reset signal input terminal is added to DACP and DACN respectively, for receiving the first reset signal (dac_rst).

[0047] As shown in Figure 4, the timing of the first reset signal (dac_rst) is controlled by an asynchronous clock. When the comparator completes the data comparison of the last bit, it immediately generates the first reset signal (dac_rst), thereby resetting DACP and DACN. Compared with the traditional architecture timing, the latch output clock signal (dout_latch_clk) and the second reset signal (d_latch_rst) can be generated in the sampling and holding phase of the next clock cycle. By comparing Figure 4 and Figure 6, it can be seen that the time (S&H time) left for the serial data latch to establish and hold in the embodiment of the present disclosure is greater than the time left for the serial data latch to establish and hold in the related art. Therefore, the timing of the current clock cycle conversion phase can be relaxed, the problem of shortage of timing resources in the conversion phase can be solved, and the working efficiency of the SARADC can be improved.

[0048] Figure 7 is a timing diagram comparing the SAR ADC of the embodiment of the present disclosure with that of the related art. As shown in Figure 7, in the related art, after completing n-bit data comparisons during the conversion phase, data synchronization, D_LATCH reset, and DAC reset are required, resulting in tight timing resources. However, with the solution of the embodiment of the present disclosure, after completing n-bit data comparisons during the conversion phase, only the DAC reset is performed, and data synchronization and D_LATCH reset can be performed during the sample-and-hold phase of the next clock cycle, thus resolving the issue of tight timing resources during the conversion phase.

[0049] An embodiment of the present disclosure further provides a terminal device, comprising the successive approximation register analog-to-digital converter as described above.

[0050] According to an embodiment of the present disclosure, a terminal device includes a SARADC, which includes a comparator, a serial data latch module, and a digital-to-analog converter. The comparator compares an input signal with a reference signal on a bit-by-bit basis. For each bit, after the bit comparison is completed, the comparison result of the bit is sent to the serial data latch module. The serial data latch module generates a first reset signal after receiving the comparison result of the last bit, and sends the first reset signal to the digital-to-analog converter. The digital-to-analog converter is reset according to the first reset signal. According to an embodiment of the present disclosure, the reset of the digital-to-analog converter is controlled by the comparison result of the last bit of the input signal. As long as the comparison result of the last bit is obtained, the digital-to-analog converter can be reset immediately. In this way, data synchronization and data latch reset can be postponed to the next cycle, saving the timing of synchronizing data and resetting data latch logic, optimizing the time decomposition of the successive approximation register type analog-to-digital converter, and facilitating an increase in sampling rate.

[0051] The present disclosure also provides a signal processing method, which is applied to the aforementioned successive approximation register analog-to-digital converter. As shown in FIG8 and FIG1 , the method includes the following steps:

[0052] Step S11, comparing the input signal with the reference signal bit by bit;

[0053] Step S12, after the last bit is compared, generating a first reset signal; and

[0054] Step S13: Reset the digital-to-analog converter according to the first reset signal.

[0055] In step S11 , the input signal and the reference signal are input into the comparator 1 , and the comparator 1 compares the input signal and the reference signal bit by bit, and sends the comparison result of each bit to the serial data latch module 2 .

[0056] In step S12 , after the last bit is compared, the serial data latch module 2 generates a first reset signal (dac_rst) and sends the first reset signal (dac_rst) to the digital-to-analog converter 3 .

[0057] In step S13 , after receiving the first reset signal (dac_rst), the DAC 3 resets the DAC 3 .

[0058] According to the signal processing method of the embodiment of the present disclosure, the input signal is compared with the reference signal on a bit-by-bit basis. After the comparison of the last bit is completed, a first reset signal is generated, and the digital-to-analog converter is reset according to the first reset signal. According to the embodiment of the present disclosure, the reset of the digital-to-analog converter is controlled by the comparison result of the last bit of the input signal. As long as the comparison result of the last bit is obtained, the digital-to-analog converter can be reset immediately. In this way, data synchronization and data latch reset can be postponed to the next cycle, saving the timing of synchronizing data and resetting data latch logic, optimizing the time decomposition of the successive approximation register type analog-to-digital converter, and facilitating an increase in the sampling rate.

[0059] In some embodiments, after comparing the input signal with the reference signal bit by bit (i.e., step S11), the signal processing method may further include the following steps:

[0060] In step S11 ′, for each bit, after the bit comparison is completed, the comparison result of each bit is latched, and data synchronization processing is performed on the comparison result of each bit.

[0061] In some embodiments, performing data synchronization processing on the comparison result of each bit includes: performing data synchronization processing on the comparison result of each bit in the next sampling and holding phase.

[0062] After receiving the comparison result corresponding to the serial data latch unit, each serial data latch unit of the serial data latch module 2 latches the comparison result and performs data synchronization processing on the comparison result of each bit in the sampling and holding phase of the next clock cycle, and puts the data synchronization originally performed in the current clock cycle into the next clock cycle, thereby solving the problem of tight timing resources in the conversion phase.

[0063] In some embodiments, as shown in FIG9 , the signal processing method may further include the following steps:

[0064] Step S21, generating a second reset signal in the next sampling and holding phase; and

[0065] Step S22: Reset the serial data latch module according to the second reset signal.

[0066] In the sampling phase of the next clock cycle, after receiving the second reset signal (d_latch_rst), the serial data latch module 2 is reset to clear the comparison results of each bit previously latched.

[0067] In some embodiments, when the input signal of the SARADC is a differential signal (including a first input signal VIP and a second input signal VIN), comparing the input signal with the reference signal on a bit-by-bit basis (i.e., step S11) includes the following steps: comparing the first input signal VIP with the reference signal on a bit-by-bit basis, and comparing the second input signal VIN with the reference signal on a bit-by-bit basis.

[0068] The step of generating the first reset signal after the last bit of the first input signal VIP is compared (ie, step S12 ) includes the following steps: generating the first reset signal after the last bit of the first input signal VIP is compared.

[0069] The resetting of the digital-to-analog converter according to the first reset signal (ie, step S13 ) includes the following steps: resetting the first digital-to-analog converter and the second digital-to-analog converter respectively according to the first reset signal.

[0070] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.< / n> < / n> < / n>

Claims

1. A successive approximation register type analog-to-digital converter, comprising a comparator, a serial data latch module and a digital-to-analog converter, wherein The comparator is configured to compare the input signal with the reference signal according to the bit position, and for each bit position, after the bit position comparison is completed, send the comparison result of the bit position to the serial data latch module; The serial data latch module is configured to generate a first reset signal after receiving the comparison result of the last bit, and send the first reset signal to the digital-to-analog converter; The digital-to-analog converter is configured to be reset according to the first reset signal.

2. The successive approximation register analog-to-digital converter as claimed in claim 1, further comprising a data synchronization module, wherein The serial data latch module is further configured to latch the comparison result of each bit position and send the comparison result of each bit position to the data synchronization module; The data synchronization module is configured to perform data synchronization processing on the comparison result of each of the bits.

3. The SAR analog-to-digital converter of claim 2, wherein The data synchronization module is configured to perform data synchronization processing on the comparison result of each bit in the next sampling and holding phase.

4. The successive approximation register analog-to-digital converter according to claim 2, wherein: The serial data latch module includes a plurality of serial data latch units, the number of which is the same as the number of the bits; the data synchronization module includes a plurality of data synchronization units, each of which corresponds to each of the serial data latch units one by one; Each of the serial data latch units is configured to latch a comparison result of a corresponding bit position, and send the comparison result of the corresponding bit position to a corresponding data synchronization unit; Each of the data synchronization units is configured to perform data synchronization processing on the comparison result of the corresponding bit position.

5. The successive approximation register analog-to-digital converter according to claim 1, wherein: The serial data latch module is also configured to receive a second reset signal and reset according to the second reset signal; the second reset signal is generated in the next sampling and holding phase.

6. The successive approximation register analog-to-digital converter according to any one of claims 1 to 5, wherein: The input signal is a differential signal, the digital-to-analog converter includes a first digital-to-analog converter and a second digital-to-analog converter, and the serial data latch module includes a first serial data latch module and a second serial data latch module; The comparator is configured to, for each bit, send the comparison result of the bit to the first serial data latch module and the second data latch module after the bit comparison is completed; The first serial data latch module is configured to generate a first reset signal after receiving the comparison result of the last bit, and send the first reset signal to the first digital-to-analog converter and the second digital-to-analog converter; The first digital-to-analog converter and the second digital-to-analog converter are configured to be reset according to the first reset signal.

7. A terminal device, comprising the successive approximation register analog-to-digital converter according to any one of claims 1 to 6.

8. A signal processing method, applied to the successive approximation register analog-to-digital converter according to any one of claims 1 to 6, the method comprising: Compare the input signal with the reference signal bit by bit; After the last bit is compared, a first reset signal is generated; as well as The digital-to-analog converter is reset according to the first reset signal.

9. The method of claim 8, wherein: After comparing the input signal with the reference signal bit by bit, the method further includes: For each bit, after the bit comparison is completed, the comparison result of each bit is latched, and data synchronization processing is performed on the comparison result of each bit.

10. The method of claim 9, wherein: The data synchronization processing of the comparison results of each bit position includes: In the next sampling and holding phase, data synchronization processing is performed on the comparison results of each bit.

11. The method of claim 8, further comprising: generating a second reset signal in the next sample-and-hold phase; as well as The serial data latch module is reset according to the second reset signal.

12. The method according to any one of claims 8 to 11, wherein: The method is applied to the successive approximation register analog-to-digital converter as claimed in claim 6; the input signal is a differential signal, including a first input signal and a second input signal; The step of comparing the input signal with the reference signal according to the bit position includes: Compare the first input signal with a reference signal bit by bit, and compare the second input signal with a reference signal bit by bit; The step of generating a first reset signal after the last bit is compared comprises: After the last bit of the first input signal is compared, generating the first reset signal; The resetting the digital-to-analog converter according to the first reset signal comprises: The first digital-to-analog converter and the second digital-to-analog converter are reset respectively according to the first reset signal.

Images