Digital-to-analog converter, analog-to-digital converter, chip, and electronic device

Abstract

Embodiments of the present application provide a digital-to-analog converter, an analog-to-digital converter, a chip, and an electronic device. The digital-to-analog converter comprises: a first switched capacitor unit, the first switched capacitor unit comprising a first capacitor network; and a second switched capacitor unit, the second switched capacitor unit comprising a second capacitor network. The second switched capacitor unit is configured to redistribute charges of a first-side electrode sheet of the second capacitor network to output a common-mode voltage. The first switched capacitor unit is configured to connect a second-side electrode sheet of the first capacitor network to an analog input voltage in a sampling stage, and redistribute charges of a first-side electrode sheet of the first capacitor network to output a common-mode voltage.

Description

Digital-to-analog converters, analog-to-digital converters, chips and electronic devices

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 26, 2023, with application number 202311258513.8 and invention name “Digital-to-analog converter, analog-to-digital converter, chip and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to, but are not limited to, the field of integrated circuit technology, and specifically to a digital-to-analog converter, an analog-to-digital converter, a chip, and an electronic device. Background Art

[0003] Currently, a successive approximation analog-to-digital converter (SAR ADC) primarily comprises a digital-to-analog converter (DAC), a common-mode voltage generation module, a comparator, and a logic module. The DAC typically employs a capacitive DAC, which generates an analog output voltage. This analog output voltage is then compared with the common-mode voltage output by the common-mode voltage generation module by a comparator. The logic module then determines the output code value for the next comparison cycle based on the comparator's output. This controls the voltage across one end of the capacitor plates in the DAC and outputs an analog output voltage of a different voltage value. This process repeats until the analog output voltage equals the common-mode voltage, ultimately obtaining the converted digital signal from the logic module.

[0004] Before the DAC can output an analog output voltage, it needs to sample the input voltage signal. Specifically, the input voltage signal needs to be connected to the bottom plates of multiple capacitors, while the common-mode voltage needs to be connected to the top plates of multiple capacitors. The sampling settling process is completed after the charge on the capacitor plates stabilizes. After sampling, the top plates of the multiple capacitors need to be disconnected from the common-mode voltage, and the aforementioned comparator comparison and logic control loop process can be repeated. Technical issues

[0005] However, since the digital-to-analog converter needs to rely on an external common-mode voltage generation module to complete the sampling and establishment process, and the common-mode voltage generation module has requirements for the common-mode voltage establishment speed, output accuracy, and anti-interference, this will lead to the complexity of the successive approximation analog-to-digital converter circuit structure. Technical Solutions

[0006] In view of the above problems, embodiments of the present application provide a digital-to-analog converter, an analog-to-digital converter, a chip, and an electronic device.

[0007] In a first aspect, the present application provides a digital-to-analog converter, comprising:

[0008] A first switched capacitor unit, the first switched capacitor unit comprising a first capacitor network;

[0009] A second switched capacitor unit, the second switched capacitor unit comprising a second capacitor network;

[0010] The second switched capacitor unit is used to redistribute the charge on the first side plate of the second capacitor network and output a common mode voltage;

[0011] The first switched capacitor unit is used to connect the second side plate of the first capacitor network to the analog input voltage during the sampling phase, and to redistribute the charge of the first side plate of the first capacitor network to output a common mode voltage.

[0012] In a second aspect, the present application provides an analog-to-digital converter, comprising the digital-to-analog converter as described in the first aspect.

[0013] In a third aspect, the present application provides a chip comprising the analog-to-digital converter as described in the second aspect.

[0014] In a fourth aspect, the present application provides an electronic device, comprising a device body and a chip as described in the second aspect provided in the device body.

[0015] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] FIG1 shows a schematic diagram of a circuit structure of a successive approximation analog-to-digital converter in conventional technology.

[0018] FIG2 shows a module schematic diagram of an analog-to-digital converter provided in an embodiment of the present application.

[0019] FIG3 shows a module schematic diagram of a digital-to-analog converter provided in an embodiment of the present application.

[0020] FIG4 shows a schematic diagram of charge redistribution on the first side plate of the first capacitor network provided by an embodiment of the present application.

[0021] FIG5 shows another schematic diagram of charge redistribution on the first side plate of the first capacitor network provided in an embodiment of the present application.

[0022] FIG6 shows a module schematic diagram of a first switch capacitor unit provided in an embodiment of the present application.

[0023] FIG7 shows a circuit diagram of a first switch capacitor unit provided in an embodiment of the present application.

[0024] FIG8 shows another circuit diagram of the first switch capacitor unit provided in an embodiment of the present application.

[0025] FIG9 shows a schematic diagram of a state of the first switch capacitor unit provided in an embodiment of the present application.

[0026] FIG10 shows another state schematic diagram of the first switch capacitor unit provided in an embodiment of the present application.

[0027] FIG11 shows a module schematic diagram of a second switched capacitor unit provided in an embodiment of the present application.

[0028] FIG12 shows a circuit diagram of a second switched capacitor unit provided in an embodiment of the present application.

[0029] FIG13 shows another circuit diagram of the second switched capacitor unit provided in an embodiment of the present application.

[0030] FIG14 shows a schematic diagram of a state of the second switch capacitor unit provided in an embodiment of the present application.

[0031] FIG15 shows another state diagram of the second switch capacitor unit provided in an embodiment of the present application.

[0032] FIG16 shows a circuit diagram of a digital-to-analog converter provided in an embodiment of the present application.

[0033] FIG17 shows another circuit diagram of a digital-to-analog converter provided in an embodiment of the present application.

[0034] FIG18 shows another module schematic diagram of the first switch capacitor unit provided in an embodiment of the present application.

[0035] FIG19 shows another circuit diagram of the first switch capacitor unit provided in an embodiment of the present application.

[0036] Among them, 10 is a first switch capacitor unit, 11 is a first capacitor network, 12 is a first switch network, and 13 is a second switch network;

[0037] 20 second switch capacitor unit, 21 second capacitor network, 22 third switch network;

[0038] First capacitors C11-C1n, first redistribution switch S01, first preset voltage V1, second preset voltage V2, first switch S1, second switch S2, first control switches S11-S1n;

[0039] Reference voltage Vref, power supply voltage VDD, ground terminal gnd, analog input voltage VIN, common mode voltage Vcm, analog output voltage Vdac;

[0040] A first internal weighted capacitor C1, a second internal weighted capacitor C2, a third internal weighted capacitor C3, and a fourth internal weighted capacitor C4;

[0041] second capacitors C21-C2n, second redistribution switch S02, third preset voltage V3, fourth preset voltage V4, third switch S3, fourth switch S4, second control switches S21-S2n, preset holding voltage V5;

[0042] 100 digital-to-analog converters, 200 comparators, 300 logic modules.

[0043] Implementation Methods of the Application

[0044] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0045] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0046] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0047] Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0048] In the description of the embodiments of this application, words such as "example" or "for example" are used to indicate an example, illustration, or description. Any embodiment or design described as "for example" or "for example" in the embodiments of this application is not to be construed as being preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to clearly present relative concepts.

[0049] In addition, in the embodiments of the present application, "plurality" refers to two or more. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two, or more. For example, "including at least one" means including one, two, or more, and does not limit which ones are included. For example, "including at least one of A, B, and C" means including A, B, C, A and B, A and C, B and C, or A, B, and C.

[0050] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0051] The first electrode / first end of each transistor used in the embodiments of the present application is one of the source and the drain, and the second electrode / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable, that is, the first electrode / first end and the second electrode / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode / first end of the transistor is the source, and the second electrode / second end is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode / first end of the transistor is the drain, and the second electrode / second end is the source.

[0052] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual components, but represent the junction points of related couplings in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0053] Currently, analog-to-digital converters (ADCs) are commonly used in fields such as communications, control, signal processing, and computer systems. These converters convert input voltage signals into digital signals and then output them for use in digital systems. For example, a successive approximation ADC (SAR ADC) is shown in Figure 1, which illustrates a conventional SAR ADC circuit. The SAR ADC primarily includes a DAC, a common-mode voltage generator, a comparator, and a logic module.

[0054] The digital-to-analog converter (DAC) is primarily composed of multiple parallel-connected sampling capacitors C1, C2, ..., Cn. The lower plate of each sampling capacitor C1, C2, ..., Cn is controlled by a switch (not shown) to receive an analog input voltage VIN, a reference voltage Vref, or ground gnd. The upper plates of the sampling capacitors C1, C2, ..., Cn are connected to the non-inverting input of a comparator. The DAC outputs an analog output voltage Vdac to the non-inverting input of the comparator. A switch SW is connected between the non-inverting and inverting inputs of the comparator. A common-mode voltage generation module outputs a common-mode voltage Vcm, which is output to the inverting input of the comparator.

[0055] During the sampling phase, switch SW is closed, connecting the lower plates of the sampling capacitors C1, C2, …, Cn to the analog input voltage Vin. The upper plates are connected to the output of the common-mode voltage generator module via switch SW to receive the common-mode voltage Vcm. After the sampling is fully settled, Vdac = Vcm, and the voltage across the sampling capacitors is Vcm - Vin.

[0056] During the conversion phase, the lower plate of the sampling capacitor no longer receives the analog input voltage and, depending on logic control, is connected to the reference voltage or ground, while switch SW is simultaneously opened. At this point, the voltage Vdac at the comparator's non-inverting input is Vref*Ceq / Ctotal-VIN+Vcm, where Ceq is the sampling capacitor with its lower plate connected to the reference voltage Vref, and Ctotal is the total capacitance of the entire array of sampling capacitors C1, C2, ..., Cn. The comparator's non-inverting input voltage is Vcm, while the negative input voltage is Vcm.

[0057] During the comparison process of the comparator, the Vcm term is eliminated as the common-mode voltage during the transcoding comparison process. The comparator actually determines the positive or negative value of Vref*Ceq / Ctotal-VIN. The logic module determines the output code value of the next comparison cycle based on the output result of the comparator to control the size of the sampling capacitor Ceq, so that the voltage Vdac on the positive input terminal of the comparator gradually approaches the common-mode voltage Vcm value until the analog output voltage Vdac equals the common-mode voltage Vcm, and finally obtains the converted digital signal from the logic module.

[0058] However, since the digital-to-analog converter needs to rely on the common-mode voltage generation module to complete the sampling and establishment process, and the common-mode voltage generation module has requirements for the common-mode voltage establishment speed, output accuracy, and anti-interference, this will lead to the complexity of the successive approximation analog-to-digital converter circuit structure.

[0059] Before introducing the digital-to-analog converter, analog-to-digital converter, chip and electronic device of the present application, the application scenario background information of the voltage buffer of the embodiment of the present application is first introduced.

[0060] Referring to FIG. 2 , FIG. 2 shows a schematic block diagram of an analog-to-digital converter according to an embodiment of the present application. The analog-to-digital converter includes a digital-to-analog converter 100, a comparator 200, and a logic module 300. The second switched capacitor unit 20 of the digital-to-analog converter 100 can provide a common-mode voltage Vcm to the inverting input terminal of the comparator 200. Simultaneously, the first switched capacitor unit 10 of the digital-to-analog converter 100 can establish a common-mode voltage Vcm sampling operation through charge redistribution of the first-side electrode plates thereof. That is, during the analog-to-digital converter's conversion of analog signals to digital signals, there is no need to connect the common-mode voltage Vcm to the first-side electrode plates of the first capacitor network 11. Instead, the first-side electrodes of the first capacitor network 11 and the second capacitor network 21 each perform charge redistribution to complete the sampling process of the analog input voltage VIN and simultaneously provide the common-mode voltage Vcm. This eliminates the need for a common-mode voltage Vcm generation module in the analog-to-digital converter, simplifying the circuit structure of the analog-to-digital converter. Furthermore, since the charge redistribution feature is used to provide the common-mode voltage Vcm, the output of the common-mode voltage Vcm consumes substantially no power, thereby reducing the energy consumption of the analog-to-digital converter.

[0061] It is understandable that the analog-to-digital converter may also be a hybrid structure analog-to-digital converter consisting of a successive approximation analog-to-digital converter and other analog-to-digital converters, such as Pipeline-SAR ADC, Incremental-SAR ADC, Delta-Sigma-SAR ADC, etc.

[0062] Continuing to refer to FIG3 , FIG3 shows a module diagram of a digital-to-analog converter 100 according to an embodiment of the present application, wherein the digital-to-analog converter 100 includes:

[0063] A first switched capacitor unit 10, the first switched capacitor unit 10 comprising a first capacitor network 11;

[0064] A second switched capacitor unit 20, the second switched capacitor unit 20 comprising a second capacitor network 21;

[0065] The second switched capacitor unit 20 is used to redistribute the charge on the first side plate of the second capacitor network 21 and output a common mode voltage Vcm;

[0066] The first switched capacitor unit 10 is used to connect the second side plate of the first capacitor network 11 to the analog input voltage VIN during the sampling phase, and redistribute the charge on the first side plate of the first capacitor network 11 to output a common mode voltage Vcm.

[0067] In this embodiment, the first switched capacitor unit 10 can redistribute the charge of the first side plate of the first capacitor network 11 by controlling the switch, so that when the second side plate of the first capacitor network 11 is connected to the analog input voltage VIN (i.e., the sampling phase), the first side plate outputs the common mode voltage Vcm, thereby establishing a sampling process, or when the second side plate of the first capacitor network 11 is connected to the reference voltage Vref or grounded (i.e., the conversion phase), the first side plate outputs the analog output voltage Vdac.

[0068] In some embodiments of the present application, the first capacitor network 11 may include multiple capacitors connected in parallel. In some embodiments of the present application, the first capacitor network 11 may include multiple capacitors connected in parallel and some capacitors connected in series, for example, in multiple parallel branches, each parallel branch has two or more capacitors connected in series.

[0069] In some embodiments of the present application, the charge redistribution of the first side plate of the first capacitor network 11 can be achieved by transferring the internal capacitor charges of the first capacitor network 11. For example, referring to FIG4 , FIG4 shows a schematic diagram of the charge redistribution of the first side plate of the first capacitor network 11 in an embodiment of the present application, wherein, when switches S1 and S2 are closed, switch S 01 When disconnected, voltage V1 charges capacitor C1, and voltage V2 charges capacitor C2. After charging is completed, the charge of capacitor C1 is (V1-VIN)C1, and the charge of capacitor C2 is (V2-VIN)C2. Then, switches S1 and S2 are disconnected, and switch S is closed. 01 , according to the charge redistribution and charge conservation principle, we can get the following formula:

[0070] (Vout-VIN)*(C1+C2)=(V1-VIN)C1+(V2-VIN)C2

[0071] After simplifying the above formula, we can get the following formula:

[0072] Vout=V1C1+V2C2

[0073] That is, by controlling the voltage values ​​of voltage V1 and voltage V2 and the capacitance values ​​of capacitors C1 and C2, the output voltage Vout can be controlled, thereby redistributing the charge on the first side plate of the first capacitor network 11 and outputting a common mode voltage Vcm.

[0074] In some embodiments of the present application, charge redistribution of the first side plate of the first capacitor network 11 can be achieved by transferring charge through an external capacitor independent of the first capacitor network 11. For example, referring to FIG5 , FIG5 shows another schematic diagram of charge redistribution of the first side plate of the first capacitor network 11 in an embodiment of the present application, wherein when the switch Sc1 is closed and the switch Sc2 is opened, the voltage V0 charges the capacitor C0 outside the first capacitor network 11. After charging is completed, the charge amount of the capacitor C0 is V0C0. Then, Sc1 is opened and Sc2 is closed. According to the charge redistribution and the charge conservation principle, the following formula can be obtained:

[0075] Vout*(C1+C2+C0)=V0C0

[0076] After converting the above formula, the output voltage Vout is:

[0077] Vout=V0C0 / (C1+C2+C0)

[0078] That is, by controlling the voltage V0 and the capacitance values ​​of capacitors C1, C2 and C0, the output voltage Vout can be controlled, thereby redistributing the charge on the first side plate of the first capacitor network 11 and outputting a common mode voltage Vcm.

[0079] The second switched capacitor unit 20 can redistribute the charge on the first side plate of the second capacitor network 21 by controlling the switch to provide a common mode voltage Vcm to the inverting input terminal of the comparator 200. In some embodiments of the present application, the second capacitor network 21 may include a plurality of capacitors connected in parallel. In some embodiments of the present application, the second capacitor network 21 may include a plurality of capacitors connected in parallel and some capacitors connected in series. For example, in a plurality of parallel branches, the parallel branches have two or more capacitors connected in series.

[0080] In some embodiments of the present application, charge redistribution on the first side plate of the second capacitor network 21 can be achieved by transferring charge between capacitors within the second capacitor network 21. In some embodiments of the present application, charge redistribution on the first side plate of the first capacitor network 11 can be achieved by transferring charge via an external capacitor independent of the first capacitor network 11.

[0081] It should be noted that the first side plate and the second side plate refer to the plates on the same side of the capacitor network (for example, the first capacitor network 11 or the second capacitor network 21). For example, the first side plate can refer to the upper plate of multiple parallel capacitors in the capacitor network, and the second side plate can refer to the lower plate of multiple parallel capacitors in the capacitor network.

[0082] In some embodiments of the present application, the first side plate of the first capacitor network 11 may refer to the upper plate of multiple parallel capacitors in the first capacitor network 11, and the second side plate of the first capacitor network 11 may refer to the lower plate of multiple parallel capacitors in the first capacitor network 11; the first side plate of the second capacitor network 21 may refer to the upper plate of multiple parallel capacitors in the second capacitor network 21, and the second side plate of the second capacitor network 21 may refer to the lower plate of multiple parallel capacitors in the second capacitor network 21.

[0083] In some embodiments of the present application, the first side plate of the first capacitor network 11 may refer to the upper plate of multiple parallel capacitors in the first capacitor network 11, and the second side plate of the first capacitor network 11 may refer to the lower plate of multiple parallel capacitors in the first capacitor network 11; the first side plate of the second capacitor network 21 may refer to the lower plate of multiple parallel capacitors in the second capacitor network 21, and the second side plate of the second capacitor network 21 may refer to the upper plate of multiple parallel capacitors in the second capacitor network 21.

[0084] It can be understood that the first side plate of the first capacitor network 11 can also refer to the lower plate of multiple parallel capacitors in the first capacitor network 11, and the second side plate of the first capacitor network 11 can refer to the upper plate of multiple parallel capacitors in the first capacitor network 11; and the first side plate of the second capacitor network 21 can refer to the upper plate of multiple parallel capacitors in the second capacitor network 21, and the second side plate of the second capacitor network 21 can refer to the lower plate of multiple parallel capacitors in the second capacitor network 21.

[0085] The digital-to-analog converter 100 provided in an embodiment of the present application connects the second side plate of the first capacitor network 11 to the analog input voltage VIN during the sampling phase, causing charge redistribution on the first side plate of the first capacitor network 11 to generate a common-mode voltage Vcm. Simultaneously, the second switched capacitor unit 20 redistributes charge on the first side plate of the second capacitor network 21 to provide the common-mode voltage Vcm, thereby completing the analog-to-digital converter's sampling process for the analog input voltage VIN. That is, during the sampling establishment process, no external common-mode voltage Vcm generation module is required to provide the common-mode voltage Vcm, nor is it necessary to connect the common-mode voltage Vcm to the first side plate of the first capacitor network 11. Instead, the first side plates of the first capacitor network 11 and the second capacitor network 21 each perform charge redistribution to complete the sampling process for the analog input voltage VIN. This eliminates the need for a common-mode voltage Vcm generation module in an analog-to-digital converter (e.g., a successive approximation analog-to-digital converter), simplifying the circuit structure of the analog-to-digital converter. Furthermore, since the charge redistribution feature is used to provide the common-mode voltage Vcm, the process of outputting the common-mode voltage Vcm consumes substantially no power, thereby reducing the energy consumption of the analog-to-digital converter.

[0086] In some embodiments of the present application, referring to Figure 6, Figure 6 shows a module schematic diagram of the first switching capacitor unit 10 in an embodiment of the present application, wherein the first switching capacitor unit 10 also includes a first switching network 12 and a second switching network 13; the first switching network 12 is connected to the first side plate of the first capacitor network 11, and the second switching network 13 is connected to the second side plate of the first capacitor network 11; the first switching network 12 is used to control the charge redistribution of the first side plate and output the common mode voltage Vcm, and the second switching network 13 is used to change the voltage connected to the multiple second side plates, so that the charge of the multiple first side plates is redistributed again and the analog output voltage Vdac is output.

[0087] It should be noted that when the digital-to-analog converter 100 performs sampling, the second switch network 13 controls the second side plate of the first capacitor network 11 to be connected to the analog input voltage VIN, and the first switch network 12 controls the charge redistribution of the first side plate and outputs the common-mode voltage Vcm. At this time, the voltages across the capacitors in the first capacitor network 11 are the analog input voltage VIN and the common-mode voltage Vcm, respectively, thereby completing the sampling establishment process of the digital-to-analog converter 100; when the digital-to-analog converter 100 performs conversion, the second switch network 13 changes the voltage connected to the second side plate of the capacitor in the first capacitor network 11, for example, the second side plates of some capacitors are grounded, and the second side plates of some capacitors are connected to the reference voltage Vref. The charge on the first side plate of the grounded capacitor will be redistributed to the first side plate of the capacitor connected to the reference voltage Vref, thereby changing the potential of the first side plate of the first capacitor network 11, and finally providing the analog output voltage Vdac to the non-inverting input terminal of the comparator 200.

[0088] In some embodiments of the present application, referring to Figure 7, Figure 7 shows a circuit schematic diagram of the first switch capacitor unit 10 in an embodiment of the present application, wherein the first capacitor network 11 includes multiple first capacitors, and the first side plates of the multiple first capacitors are connected to each other; the first switch network 12 includes at least one first redistribution switch S01, and the first redistribution switch S01 is used to control the connection or disconnection of the first side plates between adjacent first capacitors; when the first redistribution switch S01 is disconnected, the potentials of the first side plates of at least two first capacitors are not equal; when the first redistribution switch S01 is closed, the charges of the first side plates of the multiple first capacitors are redistributed.

[0089] For example, referring to Figure 7, the potential of the first side plate of the first capacitor C11 is V1, and the potential of the first side plate of the first capacitor C12 is V2. When the first redistribution switch S01 is closed, the charge of the first side plates of the first capacitor C11 and the first capacitor C12 is redistributed. At this time, the potential of the first side plates of the first capacitor C11 and the first capacitor C12 changes, so that the common-mode voltage Vcm output by the first switch capacitor unit 10 is Vcm=(V1*C11+V2*C12) / (C11+C12).

[0090] At the same time, when the DAC 100 is sampling, the first redistribution switch S01 remains closed, and the switches S11 and S12 of the second switch network 13 control the second plates of the first capacitors C11 and C12 to be connected to the analog input voltage VIN. The voltages across the first capacitors C11 and C12 are the analog input voltage VIN and the common-mode voltage Vcm, respectively, thereby completing the sampling establishment process of the DAC 100. When the DAC 100 is converting, the switches S11 and S12 change the voltages connected to the second plates of the capacitors in the first capacitor network 11. For example, the second plate of the first capacitor C11 is grounded, and the second plate of the first capacitor C12 is connected to the reference voltage Vref. The charge on the first plate of the first capacitor C11 is redistributed to the first plate of the first capacitor C12, thereby changing the potentials of the first plates of the first capacitors C11 and C12, and ultimately providing the analog output voltage Vdac to the non-inverting input of the comparator 200.

[0091] In some embodiments of the present application, referring to FIG8 , FIG8 shows another circuit schematic diagram of the first switch capacitor unit 10 in an embodiment of the present application, wherein a first redistribution switch S01 is provided between any adjacent first side plates of the first capacitor; when the digital-to-analog converter 100 is in the sampling phase, at most one first redistribution switch S01 is configured to be disconnected and then turned on.

[0092] It should be noted that, since at most one first redistribution switch S01 is configured to be disconnected and then turned on, the multiple first capacitors can be divided into two parts. One part of the capacitors connected in parallel can be equivalent to an internal weighted capacitor, and the other part of the capacitors connected in parallel can be equivalent to another internal weighted capacitor. The first redistribution switch S01 configured to be disconnected and then turned on separates the two internal weighted capacitors. By changing the position of the first redistribution switch S01 configured to be disconnected and then turned on, the capacitance value of the internal weighted capacitor can be changed, thereby changing the size of the common-mode voltage Vcm.

[0093] As an example, referring to FIG9 , FIG9 shows a state diagram of the first switched capacitor unit 10 in an embodiment of the present application. When the first redistribution switch S01, which is turned on again after being turned off, is located between the first capacitor C1n-1 and the first side plate of the first capacitor C1n, the capacitance value of one internal weighted capacitor is the sum of the capacitance values ​​of the first capacitor C12, the first capacitor C13, ..., C1n-1, and the capacitance value of the other internal weighted capacitor is the capacitance value of the first capacitor C1n. If, before the first redistribution switch S01 is closed, the voltage of the first side plate of the first capacitor C12, the first capacitor C13, ..., C1n-1 is V1, and the voltage of the first side plate of the first capacitor C1n is V2, then after the first redistribution switch S01 is closed, the magnitude of the common-mode voltage Vcm satisfies the following relationship:

[0094] Vcm=(V1*(C11+C12...+C1n-1)+(V2*C1n)) / (C11+C12...+C1n)

[0095] It can be understood that when the position of the first redistribution switch S01 is changed, the size of the internal weighted capacitor is changed, and the size of the common mode voltage Vcm can be adjusted without changing the voltage.

[0096] In some embodiments of the present application, referring to FIG8 , a plurality of first capacitors are arranged in sequence, and the first side plate of the first capacitor at the head end of the arrangement is used to access a first preset voltage V1, and the first side plate of the first capacitor at the end of the arrangement is used to access a second preset voltage V2; wherein the first preset voltage V1 is not equal to the second preset voltage V2.

[0097] It should be noted that, since the first side plate of the first capacitor located at the head end of the arrangement is connected to the first preset voltage V1, and the first side plate of the first capacitor located at the end of the arrangement is connected to the second preset voltage V2, when any one of the first redistribution switches S01 is configured to be disconnected and then turned on, the first side plates of all the first capacitors can be connected to the first preset voltage V1 or the second preset voltage V2 for charging, and then charge redistribution is performed after the first redistribution switch S01 is turned on, thereby avoiding the phenomenon that the first preset voltage V1 is connected to the first side plate of the middle first capacitor (for example, the first capacitor C12), causing some first capacitors (for example, the first capacitor C11) to be unable to charge.

[0098] In some embodiments of the present application, referring to FIG8 , the first switch network 12 further includes a first switch S1 and a second switch S2; one end of the first switch S1 is connected to the first side plate of the first capacitor located at the head end of the arrangement, and the other end is used to access the first preset voltage V1; one end of the second switch S2 is connected to the first side plate of the first capacitor located at the end of the arrangement, and the other end is used to access the second preset voltage V2.

[0099] It should be noted that when the first switch S1 and the second switch S2 are closed, the first redistribution switch S01 configured to be turned on after being disconnected is in an open state, and the remaining first redistribution switches S01 are in a closed state. At this time, the first preset voltage V1 charges part of the first capacitors, and the second preset voltage V2 charges the other part of the first capacitors; after the first switch S1 and the second switch S2 are disconnected, the first redistribution switch S01 configured to be turned on after being disconnected is in a closed state, so that the first side plates of the multiple first capacitors are charge redistributed, so that the first side plate voltages of the multiple first capacitors are the common mode voltage Vcm.

[0100] It can be understood that multiple first redistribution switches S01 can also be configured to be turned on after being turned off at the same time. For example, refer to Figure 10, which shows another state schematic diagram of the first switch capacitor unit 10 in an embodiment of the present application, wherein the first redistribution switch S01 between the first capacitor C11 and the first capacitor C12 is configured to be turned on after being turned off, and the first redistribution switch S01 between the first capacitor C1n-1 and the first capacitor C1n is configured to be turned on after being turned off. That is, the first preset voltage V1 only charges the first capacitor C11, and the second preset voltage V2 only charges the first capacitor C1n. After the first switch S1 and the second switch S2 are disconnected and all the first redistribution switches S01 are closed, the output common-mode voltage Vcm is Vcm=(V1*C11+V2*C1n) / (C11+C12…+C1n).

[0101] In some embodiments of the present application, referring to FIG. 8 or FIG. 9 , the second switch network 13 includes a plurality of first control switches S11-S1n, each of the first control switches corresponding to a first capacitor on a one-to-one basis; the first control switch is used to control the second side plate of the first capacitor to be connected to the analog input voltage VIN, the reference voltage Vref, or the ground; the first preset voltage V1 and the second preset voltage V2 are any two of the reference voltage Vref, the power supply voltage VDD, or 0V.

[0102] It should be noted that when the first control switch controls the second side plate of the first capacitor to be connected to the analog input voltage VIN, the first switch network 12 can be controlled to redistribute the charge of the first side plates of multiple first capacitors and output the common mode voltage Vcm, thereby realizing the sampling process of the analog input voltage VIN; when the first control switch controls the second side plate of the first capacitor to be connected to the reference voltage Vref or grounded, at this time, the switches of the first switch network 12 (for example, the first switch S1, the second switch S2 or the first redistribution switch S01) remain unchanged. Since the second side plates of some first capacitors are grounded and the second side plates of some first capacitors are connected to the reference voltage Vref, the charge of the first side plates of the grounded capacitors will be redistributed to the first side plates of the capacitors connected to the reference voltage Vref, thereby changing the potential of the first side plates of the first capacitor network 11, and finally providing the analog output voltage Vdac to the non-inverting input terminal of the comparator 200.

[0103] At the same time, since the first preset voltage V1 and the second preset voltage V2 are any two of the reference voltage Vref, the power supply voltage VDD or 0V, the reference voltage Vref, the power supply voltage VDD or 0V are all voltages possessed by the digital-to-analog converter 100 itself, there is no need to additionally generate the first preset voltage V1 and the second preset voltage V2 through a circuit structure, which is conducive to simplifying the circuit structure of the digital-to-analog converter 100.

[0104] Exemplarily, the first preset voltage V1 is the reference voltage Vref, and the second preset voltage V2 is 0V. Since the reference voltage Vref of the digital-to-analog converter 100 has the characteristic of low noise, a more accurate common-mode voltage Vcm can be output through the reference voltage Vref and the 0V ground voltage, avoiding the phenomenon that the common-mode voltage Vcm causes errors due to the jitter of the power supply voltage VDD.

[0105] In some embodiments of the present application, referring to Figure 11, Figure 11 shows a module schematic diagram of the second switched capacitor unit 20 in an embodiment of the present application, wherein the second switched capacitor unit 20 also includes a third switch network; the third switch network 22 is connected to the first side plate of the second capacitor network 21, the second side plate of the second capacitor network 21 is connected to the fifth preset voltage V5, the third switch network 22 is connected to the third preset voltage V3 and the fourth preset voltage V4, and the third switch network 22 is used to control the charge redistribution of the first side plate of the second capacitor network 21 and output the common mode voltage Vcm.

[0106] In some embodiments of the present application, the third switch network 22 can control the charge redistribution of the first-side plates of the second capacitor network 21 and output the common-mode voltage Vcm during the sampling phase. In some embodiments of the present application, the third switch network 22 can control the charge redistribution of the first-side plates of the second capacitor network 21 and output the common-mode voltage Vcm during the conversion phase.

[0107] In some embodiments of the present application, refer to Figure 12, which shows a circuit schematic diagram of the second switching capacitor unit 20 in an embodiment of the present application, wherein the second capacitor network 21 includes multiple second capacitors, and the first side plates of the multiple second capacitors are connected to each other; the third switch network 22 includes at least one second redistribution switch S02, and the second redistribution switch S02 is used to control the connection or disconnection of the first side plates between adjacent second capacitors; when the second redistribution switch S02 is disconnected, the potentials of the first side plates of at least two second capacitors are not equal; when the second redistribution switch S02 is closed, the charges of the first side plates of the multiple second capacitors are redistributed.

[0108] Exemplarily, the potential of the first side plate of the second capacitor C21 is V3, and the potential of the first side plate of the second capacitor C22 is V4. When the second redistribution switch S02 is closed, the charge of the first side plates of the second capacitor C21 and the second capacitor C22 is redistributed. At this time, the potential of the first side plates of the second capacitor C21 and the second capacitor C22 changes, so that the common-mode voltage Vcm output by the second switch capacitor unit 20 is Vcm=(V3*C21+V4*C22) / (C21+C22).

[0109] In some embodiments of the present application, refer to Figure 13, which shows another circuit schematic diagram of the second switch capacitor unit 20 in an embodiment of the present application, wherein a second redistribution switch S02 is provided between any adjacent first side plates of the second capacitor, and at most one second redistribution switch S02 is configured to be disconnected and then turned on.

[0110] It should be noted that, since at most one second redistribution switch S02 is configured to be disconnected and then turned on, the multiple second capacitors can be divided into two parts. A portion of the second capacitors connected in parallel can be equivalent to an internal weighted capacitor, and the other portion of the second capacitors connected in parallel can be equivalent to another internal weighted capacitor. The second redistribution switch S02 configured to be disconnected and then turned on separates the two internal weighted capacitors. By changing the position of the second redistribution switch S02 that is disconnected and then turned on, the capacitance value of the internal weighted capacitor can be changed, thereby changing the magnitude of the common-mode voltage Vcm.

[0111] As an example, referring to FIG. 14 , FIG. 14 shows a state diagram of the second switched capacitor unit 20 in an embodiment of the present application. When the first redistribution switch S01, which is turned on again after being turned off, is located between the first side plates of the second capacitor C2n-1 and the second capacitor C2n, the capacitance value of one internal weighted capacitor is the sum of the capacitance values ​​of the second capacitor C21, the second capacitor C22, ..., and C2n-1, and the capacitance value of the other internal weighted capacitor is the capacitance value of the second capacitor C2n. If, before the second redistribution switch S02 is closed, the voltage of the first side plates of the second capacitors C21, C22, ..., and C2n-1 is V3, and the voltage of the first side plate of the second capacitor C2n is V4, then after the second redistribution switch S02 is closed, the magnitude of the common-mode voltage Vcm satisfies the following relationship:

[0112] Vcm=(V3*(C21+C22...+C2n-1)+(V4*C2n)) / (C21+C22...+C1n)

[0113] It can be understood that when the position of the second redistribution switch S02 is changed, the size of the internal weighted capacitance is changed, and the size of the common mode capacitance can be adjusted without changing the voltage.

[0114] In some embodiments of the present application, referring to FIG. 13 , a plurality of second capacitors are arranged in sequence; the first side plate of the second capacitor at the head end of the arrangement is used to access a third preset voltage V3, and the first side plate of the second capacitor at the end of the arrangement is used to access a fourth preset voltage V4; wherein the third preset voltage V3 is not equal to the fourth preset voltage V4.

[0115] It should be noted that, since the first side plate of the second capacitor located at the head end of the arrangement can be connected to the third preset voltage V3, and the first side plate of the second capacitor located at the end of the arrangement can be connected to the fourth preset voltage, when any second redistribution switch S02 is configured to be disconnected and then turned on, the first side plates of all the second capacitors can be connected to the third preset voltage V3 or the fourth preset voltage V4 for charging, and then charge redistribution is performed after the second redistribution switch S02 is turned on, thereby avoiding the phenomenon that the third preset voltage V3 is connected to the first side plate of the middle second capacitor (for example, the second capacitor C22), causing some second capacitors (for example, the second capacitor C21) to be unable to charge.

[0116] In some embodiments of the present application, referring to FIG. 13 , the third switch network 22 further includes a third switch S3 and a fourth switch S4; one end of the third switch S3 is connected to the first side plate of the second capacitor located at the head end of the arrangement, and the other end is used to access the third preset voltage V3; one end of the fourth switch S4 is connected to the first side plate of the second capacitor located at the end of the arrangement, and the other end is used to access the fourth preset voltage V4.

[0117] It should be noted that when the third switch S3 and the fourth switch S4 are closed, the second redistribution switch S02 configured to be turned on after being disconnected is in an open state, and the remaining second redistribution switches S02 are in a closed state. At this time, the third preset voltage V3 charges part of the second capacitors, and the fourth preset voltage V4 charges the other part of the second capacitors; after the third switch S3 and the fourth switch S4 are disconnected, the second redistribution switch S02 configured to be turned on after being disconnected is closed, so that the first side plates of the multiple second capacitors are charge redistributed, so that the voltage of the first side plates of the multiple second capacitors is the common mode voltage Vcm.

[0118] It can be understood that multiple second redistribution switches S02 can also be configured to be turned on after being turned off at the same time. For example, refer to Figure 15, which shows another state schematic diagram of the second switch capacitor unit 20 in an embodiment of the present application, wherein the second redistribution switch S02 between the second capacitor C21 and the second capacitor C22 is configured to be turned on after being turned off, and the second redistribution switch S02 between the second capacitor C2n-1 and the second capacitor C2n is configured to be turned on after being turned off. That is, the third preset voltage V3 only charges the second capacitor C21, and the fourth preset voltage V4 only charges the second capacitor C2n. After the third switch S3 and the fourth switch S4 are turned off and all the first redistribution switches S01 are closed, the output common-mode voltage Vcm is Vcm=(V3*C21+V4*C2n) / (C21+C22…+C2n).

[0119] In some embodiments of the present application, referring to FIG16 , FIG16 shows a circuit diagram of the digital-to-analog converter 100 in an embodiment of the present application, where the third preset voltage V3 and the fourth preset voltage V4 are any two of the reference voltage Vref, the power supply voltage VDD or 0V, thereby eliminating the need to generate the third preset voltage V3 and the fourth preset voltage V4 through an additional circuit structure, thereby simplifying the circuit structure of the digital-to-analog converter 100.

[0120] In some embodiments of the present application, referring to Figures 13 and 17, Figure 17 shows a circuit schematic diagram of an analog-to-digital converter in an embodiment of the present application, wherein the second side plates of multiple second capacitors are connected to a preset holding voltage V5, which is any one of the reference voltage Vref, the power supply voltage VDD or 0V.

[0121] In some other embodiments of the present application, referring to Figure 17, Figure 17 shows a circuit schematic diagram of an analog-to-digital converter in an embodiment of the present application, wherein the second switch capacitor unit 20 also includes a fourth switch network, the fourth switch network includes multiple groups of second control switches S21-S2n, the second control switches correspond one-to-one to the second capacitors, and the second control switches are used to control the second side plate of the second capacitor to access the reference voltage Vref or ground.

[0122] When the second control switch controls the second side plate of the second capacitor to be connected to the reference voltage Vref or grounded, the switches of the third switch network 22 (for example, the first switch S1, the second switch S2 or the first redistribution switch S01) remain unchanged. Since the second side plates of some of the second capacitors are grounded and the second side plates of some of the second capacitors are connected to the reference voltage Vref, the charge on the first side plate of the grounded second capacitor will be redistributed to the first side plate of the second capacitor connected to the reference voltage Vref, thereby changing the potential of the first side plate of the second capacitor network 21 and ultimately providing the common-mode voltage Vcm to the non-inverting input of the comparator 200.

[0123] In some embodiments of the present application, refer to Figure 18, which shows another module schematic diagram of the first switched capacitor unit 10 in an embodiment of the present application, wherein the first capacitor network 11 includes a first internal weighted capacitor C1 and a second internal weighted capacitor C2, and the second capacitor network 21 includes a third internal weighted capacitor C3 and a fourth internal weighted capacitor C4; the first side plate of the first internal weighted capacitor C1 is used to connect to the first preset voltage V1, and the first side plate of the second internal weighted capacitor C2 is used to connect to the second preset voltage V2; the first side plate of the third internal weighted capacitor C3 is used to connect to the third preset voltage V3, and the first side plate of the fourth internal weighted capacitor C4 is used to connect to the fourth preset voltage V4; the first preset voltage V1, the second preset voltage V2, the third preset voltage V3, the fourth preset voltage V4, the first internal weighted capacitor C1, the second internal weighted capacitor C2, the third internal weighted capacitor C3 and the fourth internal weighted capacitor C4 satisfy the following relationship:

[0124] C1*V1+C2*V2=C3*V3+C4*V4

[0125] C1+C2=C3+C4

[0126] Among them, V1 is the voltage value of the first preset voltage V1, V2 is the voltage value of the second preset voltage V2, V3 is the voltage value of the third preset voltage V3, V4 is the voltage value of the fourth preset voltage V4, C1 is the capacitance value of the first internal weighted capacitor C1, C2 is the capacitance value of the second internal weighted capacitor C2, C3 is the capacitance value of the third internal weighted capacitor C3, and C4 is the capacitance value of the fourth internal weighted capacitor C4.

[0127] It should be noted that the first internal weighted capacitor C1, the second internal weighted capacitor C2, the third internal weighted capacitor C3 or the fourth internal weighted capacitor C4 can be a single capacitor or a plurality of capacitors. Taking Figure 16 as an example, the first internal weighted capacitor C1 can be the first capacitors C11 and C12 connected in parallel, the second internal weighted capacitor C2 can be the first capacitors C13, C14...C1n connected in parallel, the third internal weighted capacitor C3 can be the second capacitors C21 and C22 connected in parallel, and the fourth internal weighted capacitor C4 can be the second capacitors C23, C24...C2n connected in parallel.

[0128] In the above embodiment, since the first preset voltage V1, the second preset voltage V2, the third preset voltage V3, the fourth preset voltage V4, the first internal weight capacitor C1, the second internal weight capacitor C2, the third internal weight capacitor C3, and the fourth internal weight capacitor C4 satisfy the above relationship, based on the relationship between voltage, capacitance, and charge, after charge redistribution, the relationship: (C1*V1+C2*V2) / (C1+C2)=(C3*V3+C4*V4) / (C3+C4) can be obtained. Therefore, during the sampling phase, the output voltages of the capacitors of the first switch S1 and the second switch S2 of the digital-to-analog converter 100 are equal, thereby completing the sampling process of the digital-to-analog converter 100.

[0129] In some embodiments of the present application, the capacitance value of the first internal weighted capacitor C1 is equal to the capacitance value of the third internal weighted capacitor C3, and the capacitance value of the second internal weighted capacitor C2 is equal to the capacitance value of the fourth internal weighted capacitor C4; the voltage value of the first preset voltage V1 is equal to the voltage value of the third preset voltage V3, and the voltage value of the first preset voltage V1 is equal to the voltage value of the third preset voltage V3.

[0130] In some embodiments of the present application, the second capacitor corresponds to the first capacitor one-to-one and has the same capacitance value, and the first redistribution switch S01 and the second redistribution switch S02, which are configured to be opened synchronously and then closed, are positioned opposite to each other to ensure that the capacitance value of the first internal weighted capacitor C1 is equal to the capacitance value of the third internal weighted capacitor C3, and the capacitance value of the second internal weighted capacitor C2 is equal to the capacitance value of the fourth internal weighted capacitor C4.

[0131] For example, taking Figure 16 as an example, the first redistribution switch S01 configured to be opened and then closed is located between the first capacitor C11 and the first capacitor 12, and the second redistribution switch S02 configured to be opened and then closed is located between the second capacitor C21 and the second capacitor 22. That is, the first internal weighted capacitor C1 is the first capacitor C11, the second internal weighted capacitor C2 is the first capacitor C12, C13...C1n, the third internal weighted capacitor C3 is the second capacitor C21, and the fourth internal weighted capacitor C4 is the second capacitor C22, C22...C2n. Since the second capacitors correspond to the first capacitors one-to-one and are equal in size, it can be ensured that the capacitance value of the first internal weighted capacitor C1 is equal to the capacitance value of the third internal weighted capacitor C3, and the capacitance value of the second internal weighted capacitor C2 is equal to the capacitance value of the fourth internal weighted capacitor C4.

[0132] In some embodiments of the present application, refer to FIG. 19 , which is another circuit diagram of the first switch capacitor unit 10 in the embodiment of the present application, wherein:

[0133] The first switch network 12 includes a first switch S1, a second switch S2, and a first redistribution switch S01. One end of the first switch S1 is connected to the first side plate of the first internal weight capacitor C1, and the other end is used to connect to the first preset voltage V1. One end of the second switch S2 is connected to the first side plate of the second internal weight capacitor C2, and the other end is used to connect to the second preset voltage V2. One end of the first redistribution switch S01 is connected to a first node M1 between the first internal weight capacitor C1 and the first switch S1, and the other end is connected to a second node M2 ​​between the second internal weight capacitor C2 and the second switch S2. The first preset voltage V1 and the second preset voltage V2 are not equal.

[0134] The third switch network 22 includes a third switch S3, a fourth switch S4, and a second redistribution switch S02. The third switch S3 has one end connected to the first plate of the third internal weighted capacitor C3 and the other end connected to a third preset voltage V3. The fourth switch S4 has one end connected to the first plate of the fourth internal weighted capacitor C4 and the other end connected to a fourth preset voltage V4. The second redistribution switch S02 has one end connected to a third node M3 between the third internal weighted capacitor C3 and the third switch S3 and the other end connected to a fourth node M4 between the fourth internal weighted capacitor C4 and the fourth switch S4. The third preset voltage V3 and the fourth preset voltage V4 are unequal.

[0135] When the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are closed, and the first redistribution switch S01 and the second redistribution switch S02 are opened, the first preset voltage V1 charges the first internal weight capacitor C1, the second preset voltage V2 charges the second internal weight capacitor C2, the third preset voltage V3 charges the third internal weight capacitor C3, and the fourth preset voltage V4 charges the fourth internal weight capacitor C4. When the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are opened, and the first redistribution switch S01 and the second redistribution switch S02 are closed, the charge on the first side plates of the first internal weight capacitor C1 and the second internal weight capacitor C2 is redistributed to output a common-mode voltage Vcm. Simultaneously, the charge on the first side plates of the third internal weight capacitor C3 and the fourth internal weight capacitor C4 is redistributed to output a common-mode voltage Vcm, thereby completing the sampling settling process of the digital-to-analog converter 100.

[0136] It can be understood that the number of capacitors in the first internal weighted capacitor C1, the second internal weighted capacitor C2, the third internal weighted capacitor C3, or the fourth internal weighted capacitor C4 may also change with the position of the first redistribution switch S01 and the second redistribution switch S02, which are configured to be turned on after being turned off. For example, taking FIG. 16 as an example, when the first redistribution switch S01, which is configured to be turned on after being turned off, is located between the first side plates of the first capacitors C1n-1 and C1n, the first internal weighted capacitor C1 includes the first capacitors C11, C12, and C1n-1, and the second internal weighted capacitor C2 includes the first capacitor C1n.

[0137] It is worth noting that the above content regarding the digital-to-analog converter is intended to clearly illustrate the implementation verification process of this application. Those skilled in the art can make equivalent modified designs under the guidance of this application. For example, some switches (such as the first switch S1, the second switch S2, the third switch S3 or the fourth switch S4, etc.) can be placed outside the analog-to-digital converter; for example, switches (such as the first redistribution switch S01, the second redistribution switch S02, etc.) can use MOS tubes, IGBT tubes or transistors with switching functions.

[0138] The embodiment of the present application also provides an analog-to-digital converter, which includes the above-mentioned digital-to-analog converter 100. Among them, the analog-to-digital converter can be, but is not limited to, a successive approximation register type analog-to-digital converter, a hybrid structure analog-to-digital converter composed of a successive approximation type analog-to-digital converter and other analog-to-digital converters, such as a pipeline-SAR ADC, an incremental-SAR ADC, a delta-sigma-SAR ADC, etc. During the sampling phase, the analog-to-digital converter connects the second side plate of the first capacitor network 11 to the analog input voltage VIN, so that the charge of the first side plate of the first capacitor network 11 is redistributed to generate a common-mode voltage Vcm, and at the same time, the second switching capacitor unit 20 is used to redistribute the charge of the first side plate of the second capacitor network 21 to provide a common-mode voltage Vcm, thereby completing the sampling process of the analog-to-digital converter on the analog input voltage VIN. That is to say, during the sampling establishment process, there is no need for an external common-mode voltage Vcm generating module to provide the common-mode voltage Vcm, and there is no need to connect the common-mode voltage Vcm to the first side plate of the first capacitor network 11. The first side plates of the first capacitor network 11 and the second capacitor network 21 each perform charge redistribution to complete the sampling process of the analog input voltage VIN. On the one hand, the common-mode voltage Vcm generating module in the analog-to-digital converter (such as a successive approximation analog-to-digital converter) is eliminated, thereby simplifying the circuit structure of the analog-to-digital converter. On the other hand, since the common-mode voltage Vcm is provided by the characteristics of charge redistribution, there is basically no power consumption in the process of outputting the common-mode voltage Vcm, thereby reducing the energy consumption of the analog-to-digital converter.

[0139] The present application also provides a chip that can include the aforementioned analog-to-digital converter. The chip can be an integrated circuit (IC), also known as a microcircuit, a microchip, or a wafer / chip. The chip can be, but is not limited to, a system-on-chip (SOC) or a system-in-package (SIP) chip.

[0140] During the sampling phase, the analog-to-digital converter of the chip connects the second side plate of the first capacitor network 11 to the analog input voltage VIN, causing charge redistribution on the first side plate of the first capacitor network 11 to generate a common-mode voltage Vcm. Simultaneously, the second switched capacitor unit 20 is used to redistribute charge on the first side plate of the second capacitor network 21 to provide the common-mode voltage Vcm, thereby completing the analog-to-digital converter's sampling process for the analog input voltage VIN. That is, during the sampling establishment process, no external common-mode voltage Vcm generation module is required to provide the common-mode voltage Vcm, nor is it necessary to connect the common-mode voltage Vcm to the first side plate of the first capacitor network 11. Instead, the first side plates of the first capacitor network 11 and the second capacitor network 21 each perform charge redistribution to complete the sampling process for the analog input voltage VIN. This eliminates the need for a common-mode voltage Vcm generation module in an analog-to-digital converter (e.g., a successive approximation analog-to-digital converter), simplifying the circuit structure of the analog-to-digital converter. Furthermore, since the charge redistribution feature is used to provide the common-mode voltage Vcm, the process of outputting the common-mode voltage Vcm consumes substantially no power, thereby reducing the energy consumption of the analog-to-digital converter.

[0141] The present application also provides an electronic device, which may include a device body and a chip or analog-to-digital converter as described above, disposed in the device body. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a Universal Serial Bus (USB) docking station, a stylus, a True Wireless Stereo (TWS) headset, a car console, a car, a smart wearable device, a mobile terminal, or a smart home device.

[0142] Smart wearable devices include but are not limited to smart watches, smart bracelets, and cervical massagers. Mobile terminals include but are not limited to smartphones, laptops, tablets, and point-of-sales terminals (POS). Smart home devices include but are not limited to smart sockets, smart rice cookers, smart vacuum cleaners, and smart lights.

[0143] During the sampling phase, the analog-to-digital converter (ADC) of the chip in the electronic device connects the second side plate of the first capacitor network 11 to the analog input voltage VIN, causing the first side plate of the first capacitor network 11 to redistribute charge to generate a common-mode voltage Vcm. Simultaneously, the second switched capacitor unit 20 is used to redistribute charge on the first side plate of the second capacitor network 21 to provide the common-mode voltage Vcm, thereby completing the ADC sampling process for the analog input voltage VIN. That is, during the sampling establishment process, no external common-mode voltage Vcm generation module is required to provide the common-mode voltage Vcm, nor is it necessary to connect the common-mode voltage Vcm to the first side plate of the first capacitor network 11. Instead, the first side plates of the first capacitor network 11 and the second capacitor network 21 each perform charge redistribution to complete the sampling process for the analog input voltage VIN. This eliminates the need for a common-mode voltage Vcm generation module in an ADC (e.g., a successive approximation ADC), simplifying the circuit structure of the ADC. Furthermore, since the charge redistribution feature is used to provide the common-mode voltage Vcm, the output of the common-mode voltage Vcm consumes substantially no power, thereby reducing the energy consumption of the ADC.

[0144] The above is only a preferred embodiment of the present application and does not constitute any form of limitation to the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A digital-to-analog converter, comprising: A first switched capacitor unit, wherein the first switched capacitor unit comprises a first capacitor network; A second switched capacitor unit, wherein the second switched capacitor unit includes a second capacitor network; Wherein, the second switch capacitor unit is used to redistribute the charge of the first side plate of the second capacitor network and output a common mode voltage; The first switch capacitor unit is used to connect the second side plate of the first capacitor network to the analog input voltage during the sampling phase, and to redistribute the charge of the first side plate of the first capacitor network to output the common mode voltage.

2. The digital-to-analog converter of claim 1, wherein: The first switch capacitor unit further includes a first switch network and a second switch network; The first switch network is connected to a first side plate of the first capacitor network, and the second switch network is connected to a second side plate of the first capacitor network; The first switch network is used to control the charge redistribution of the first side plates and output the common mode voltage, and the second switch network is used to change the voltage connected to the multiple second side plates so that the charge of the multiple first side plates is redistributed again and an analog output voltage is output.

3. The digital-to-analog converter of claim 2, wherein: The first capacitor network includes a plurality of first capacitors, and first side plates of the plurality of first capacitors are connected to each other; The first switch network includes at least one first redistribution switch, and the first redistribution switch is used to control the connection or disconnection of the first side plates between adjacent first capacitors; When the first redistribution switch is disconnected, the potentials of the first side plates of at least two of the first capacitors are not equal; When the first redistribution switch is closed, charges on the first side plates of the plurality of first capacitors are redistributed.

4. The digital-to-analog converter of claim 3, wherein: The first redistribution switch is disposed between any adjacent first side plates of the first capacitor; When the digital-to-analog converter is in a sampling phase, at most one of the first redistribution switches is configured to be turned off and then turned on.

5. The digital-to-analog converter of claim 4, wherein: The plurality of first capacitors are arranged in sequence; The first side plate of the first capacitor located at the head end of the arrangement is used to connect to the first preset voltage, and the first side plate of the first capacitor located at the end of the arrangement is used to connect to the second preset voltage; Wherein, the first preset voltage is not equal to the second preset voltage.

6. The digital-to-analog converter of claim 5, wherein: The first switch network further includes a first switch and a second switch; One end of the first switch is connected to the first side plate of the first capacitor located at the head end of the arrangement, and the other end is used to connect to the first preset voltage; one end of the second switch is connected to the first side plate of the first capacitor located at the end of the arrangement, and the other end is used to connect to the second preset voltage.

7. A digital-to-analog converter as claimed in claim 5 or 6, wherein: The second switch network includes a plurality of groups of first control switches, and the first control switches correspond to the first capacitors one by one; The first control switch is used to control the second side plate of the first capacitor to be connected to an analog input voltage, a reference voltage or ground; The first preset voltage and the second preset voltage are any two of the reference voltage, the power supply voltage or 0V.

8. The digital-to-analog converter of claim 2, wherein: The second switched capacitor unit further includes a third switch network; The third switch network is connected to the first side plate of the second capacitor network, and the third switch network is used to control the charge redistribution of the first side plate of the second capacitor network and output a common mode voltage.

9. The digital-to-analog converter of claim 8, wherein: The second capacitor network includes a plurality of second capacitors, and the first side plates of the plurality of second capacitors are connected to each other; The third switch network includes at least one second redistribution switch, and the second redistribution switch is used to control the connection or disconnection of the first side plates between adjacent second capacitors; When the second redistribution switch is turned off, the potentials of the first-side plates of at least two of the second capacitors are not equal; When the second redistribution switch is closed, a plurality of the second Charge redistribution of the first side plate of the capacitor.

10. The digital-to-analog converter of claim 9, wherein: The second redistribution switch is disposed between any adjacent first-side plates of the second capacitor, and at most one of the second redistribution switches is configured to be disconnected and then turned on.

11. The digital-to-analog converter of claim 10, wherein: The plurality of second capacitors are arranged in sequence; The first side plate of the second capacitor located at the head end of the arrangement is used to connect to the third preset voltage, and the first side plate of the second capacitor located at the end of the arrangement is used to connect to the fourth preset voltage; The third preset voltage is not equal to the fourth preset voltage.

12. The digital-to-analog converter of claim 11, wherein: The third switch network further includes a third switch and a fourth switch; One end of the third switch is connected to the first side plate of the second capacitor located at the head end of the arrangement, and the other end is used to connect to the third preset voltage; one end of the fourth switch is connected to the first side plate of the second capacitor located at the end of the arrangement, and the other end is used to connect to the fourth preset voltage.

13. The digital-to-analog converter of claim 12, wherein: The third preset voltage and the fourth preset voltage are any two of a reference voltage, a power supply voltage or 0V.

14. The digital-to-analog converter of claim 12, wherein: The second side plates of the plurality of the second capacitors are connected to a preset holding voltage; or The second switch capacitor unit also includes a fourth switch network, the fourth switch network includes multiple groups of second control switches, the second control switches correspond to the second capacitors one by one, and the second control switches are used to control the second side plate of the second capacitor to access the reference voltage or ground.

15. The digital-to-analog converter of claim 8, wherein: The first capacitor network includes a first internal weighted capacitor and a second internal weighted capacitor, and the second capacitor network includes a third internal weighted capacitor and a fourth internal weighted capacitor; The first side plate of the first internal weighted capacitor is used to connect to a first preset voltage, the first side plate of the second internal weighted capacitor is used to connect to a second preset voltage; the first side plate of the third internal weighted capacitor is used to connect to a third preset voltage, and the first side plate of the fourth internal weighted capacitor is used to connect to a third preset voltage. The board is used to access a fourth preset voltage; The first preset voltage, the second preset voltage, the third preset voltage, the fourth preset voltage, the first internal weighted capacitor, the second internal weighted capacitor, the third internal weighted capacitor, and the fourth internal weighted capacitor satisfy the following relationship: C1*V1+C2*V2=C3*V3+C4*V4 C1+C2=C3+C4 Among them, V1 is the voltage value of the first preset voltage, V2 is the voltage value of the second preset voltage, V3 is the voltage value of the third preset voltage, V4 is the voltage value of the fourth preset voltage, C1 is the capacitance value of the first internal weighted capacitor, C2 is the capacitance value of the second internal weighted capacitor, C3 is the capacitance value of the third internal weighted capacitor, and C4 is the capacitance value of the fourth internal weighted capacitor.

16. The digital-to-analog converter of claim 15, wherein: The capacitance value of the first internal weighted capacitor is equal to the capacitance value of the third internal weighted capacitor, and the capacitance value of the second internal weighted capacitor is equal to the capacitance value of the fourth internal weighted capacitor; The voltage value of the first preset voltage is equal to the voltage value of the third preset voltage, and the voltage value of the first preset voltage is equal to the voltage value of the third preset voltage.

17. The digital-to-analog converter of claim 15, wherein: The first switch network includes a first switch, a second switch and a first redistribution switch, one end of the first switch is connected to the first side plate of the first internal weight capacitor, and the other end is used to access a first preset voltage; One end of the second switch is connected to the first side plate of the second internal weight capacitor, and the other end is used to access the second preset voltage; One end of the first redistribution switch is connected to a first node between the first internal weight capacitor and the first switch, and the other end is connected to a second node between the second internal weight capacitor and the second switch, and the first preset voltage is not equal to the second preset voltage.

18. An analog-to-digital converter, wherein: Comprising a digital-to-analog converter as claimed in any one of claims 1 to 17.

19. A chip, wherein: Comprising an analog-to-digital converter as claimed in claim 18.

20. An electronic device, wherein: The invention comprises a device body and the chip as claimed in claim 19 arranged in the device body.

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