Nonvolatile ferroelectric semiconductor memory and preparation method

Abstract

Provided in the present application are a nonvolatile semiconductor memory and a preparation method. The memory comprises a substrate, and a control gate and a storage gate, which are sequentially arranged on the substrate, wherein a source electrode and a drain electrode are arranged on the substrate, and a channel that separates the source electrode from the drain electrode is formed in a substrate region located between the source electrode and the drain electrode; a ferroelectric layer is arranged between the channel and the storage gate, and the storage gate is used for applying a voltage to the upper surface of the ferroelectric layer, so as to change the polarization state of the ferroelectric layer; the control gate is used for controlling the channel to turn on or turn off; and writing, reading and erasing of data are realized by means of controlling the voltages of the storage gate, the source electrode, the control gate and the drain electrode.

Description

Nonvolatile ferroelectric semiconductor memory and preparation method thereof

[0001] Related applications

[0002] This application claims priority to Chinese patent application number 202311274433.1, filed on September 28, 2023, entitled “Non-volatile Ferroelectric Semiconductor Memory and Preparation Method,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of memory technology, and in particular to a non-volatile semiconductor memory and a preparation method thereof. Background Art

[0004] Nonvolatile memory devices, which preserve data after a power outage, are ubiquitous in today's information society. With the development of the semiconductor industry and the increasing popularity of specialized hardware and embedded applications like the Internet of Things, the industry is placing higher demands on nonvolatile memory performance, including power consumption, speed, storage density, reliability, and endurance.

[0005] Currently, ferroelectric field-effect transistors (FeFETs) replace the gate oxide in MOSFET structures with ferroelectric thin films, leveraging the polarization of the ferroelectric film to regulate the on / off state of the channel. By applying voltages of different polarities to the gate, the remnant polarization of the ferroelectric layer can be controlled to switch between two directions, achieving the purpose of storing "0" and "1". These devices have advantages such as fast erase and write speeds, low operating voltages, high storage density, non-destructive readout, and strong repeated erase and write capabilities. However, traditional FeFET structures still have some problems.

[0006] First, traditional 1T-structured FeFET memories suffer from storage density and reliability issues due to write crosstalk. Traditional memory array programming requires simultaneous application of voltage to the gate (word line) and drain (bit line), allowing individual selection and programming of memory cells at the intersection of specific word lines and bit lines in a crossbar array structure. In contrast, the 1T-structured FeFET cannot achieve cross-selection itself because programming is controlled solely by the voltage applied to the gate relative to the channel. Therefore, additional gating devices are required when constructing the crossbar array structure, resulting in reduced integration density.

[0007] Secondly, potential leakage current reduces memory data reliability and increases power consumption. Since the threshold voltage of FeFETs fluctuates strongly and the device threshold voltage is low when the ferroelectric layer is polarized downward, a threshold voltage offset may cause the threshold voltage of the FeFET with a downward polarization direction to be lower than 0V, remaining in the on state when not selected, significantly increasing leakage current, resulting in poor reliability and increased power consumption. To mitigate the impact of leakage current, a higher threshold voltage is often used in FeFET memory designs. However, a higher threshold voltage also results in a higher gate voltage when reading data, which induces a stronger electric field in the ferroelectric layer, interfering with the polarization state of the ferroelectric layer; that is, the corresponding memory cell will be weakly programmed when reading data. Therefore, using a higher threshold voltage cannot effectively improve memory reliability.

[0008] Summary of the Invention

[0009] In view of the above problems, the present application provides a non-volatile semiconductor memory and a preparation method thereof.

[0010] The non-volatile semiconductor memory provided in the present application includes a substrate, a control gate, and a storage gate sequentially arranged above the substrate; wherein a source and a drain are arranged on the substrate, and a substrate region located between the source and the drain forms a channel that isolates the source and the drain; a ferroelectric layer is arranged between the channel and the storage gate, and the storage gate is used to apply a voltage to the upper surface of the ferroelectric layer to change the polarization state of the ferroelectric layer; the control gate is used to control whether the channel is turned on or off, and to control the surface potential of the channel during the data writing process; data writing, reading, and erasing are achieved by controlling the voltages of the storage gate, source, control gate, drain, and substrate.

[0011] In some embodiments, the substrate is of a first doping type, and the source and the drain are of a second doping type opposite to the first doping type.

[0012] In some embodiments, the channel includes a channel under the control gate and a channel under the storage gate; the material of the substrate includes at least one of silicon, germanium, gallium nitride, gallium arsenide, indium arsenide, indium phosphide, silicon carbide, indium antimonide, IGZO (indium gallium zinc oxide), IAZO (indium aluminum zinc oxide), ITZO (indium tin zinc oxide), and ITO (indium tin oxide); and the channel is formed on the substrate in a manner including shallow trench isolation or field oxide isolation.

[0013] In some embodiments, the ferroelectric layer covers a portion of the channel, and the material of the ferroelectric layer includes hafnium oxide, zirconium oxide, hafnium zirconium oxide, hafnium aluminum oxide, hafnium lanthanum oxide, lead titanate, PZT, SBT, and BLT, and is composed of a single layer of any one of the above materials or a multilayer combination of multiple materials. In addition, the ferroelectric layer is formed on the substrate by methods including atomic layer deposition, physical vapor deposition, low pressure chemical vapor deposition, and plasma chemical deposition.

[0014] In some embodiments, a buffer medium is provided on the upper and lower surfaces of the ferroelectric layer respectively; the buffer medium comprises at least one dielectric layer of silicon dioxide, silicon carbide, aluminum oxide, hafnium oxide, HfAlO, HfSiO, Ta2O5 or TaSiO.

[0015] In some embodiments, the cross-section of the storage gate is consistent with the ferroelectric layer, and the control gate covers the area of ​​the channel except the ferroelectric layer; the material of the storage gate includes: doped polysilicon, tantalum, neodymium, titanium nitride, tungsten nitride, tantalum nitride, and metal silicide; an insulating medium is provided between the storage gate and the control gate.

[0016] In some embodiments, when implementing data writing, a positive voltage greater than the polarization reversal threshold is applied to the storage gate and drain of the storage cell to be written, and a positive voltage greater than the threshold voltage is applied to the control gate; the channel of the storage cell is fully opened, the positive voltage of the drain drops at the drain end of the channel, and excluding the position intersecting with the drain, the surface potential of the channel is the source voltage 0V; the voltage of the upper surface of the ferroelectric layer is the positive voltage of the storage gate, and the voltage of the lower surface is the potential of the channel surface 0V, the positive voltage of the storage gate drops in the ferroelectric layer, and there is a downward electric field in the ferroelectric layer, and the polarization state changes; after the voltage is removed, the ferroelectric layer has a residual polarization in the downward direction, and the storage cell is written with "1".

[0017] In some embodiments, when erasing data, a positive voltage with an amplitude greater than the polarization reversal threshold is applied to the substrate where the memory cell to be erased is located, so that the ferroelectric layer is subjected to an upward electric field; after the positive voltage is removed, the ferroelectric layer retains a residual polarization in an upward direction, and the memory cell is erased to "0".

[0018] In some embodiments, when data is read, a voltage greater than the threshold voltage is applied to the control gate, and a read voltage is applied to the storage gate, and the read voltage is between the threshold voltages corresponding to the two polarization states of the ferroelectric layer; if the polarization direction of the ferroelectric layer is downward, the voltage of the storage gate is greater than the threshold voltage, the channel is turned on, and "1" is read; if the polarization direction of the ferroelectric layer is upward, the voltage of the storage gate is less than or equal to the threshold voltage, the channel is turned off, and "0" is read.

[0019] On the other hand, the present application also provides a method for preparing a non-volatile semiconductor memory, comprising: forming a gate dielectric and a buffer dielectric under a ferroelectric layer on a substrate by thermal oxidation or chemical vapor deposition; forming a ferroelectric layer and a storage gate located on the ferroelectric layer on the buffer dielectric, and patterning them by reactive ion etching or wet etching; depositing an insulating layer material on the gate dielectric, and performing dry etching or reactive ion etching until the gate dielectric is exposed to form an insulating layer; depositing a control gate material on the insulating layer, and patterning it by dry etching or reactive ion etching until the substrate is exposed to form a control gate; forming source and drain epitaxy on the substrate by light doping implantation or oblique implantation, depositing sidewall isolation material on the source and drain epitaxy, and etching until the substrate is exposed to form the sidewall of the control gate; forming heavily doped source and drain regions on the substrate by ion implantation or diffusion. In some embodiments, before forming a gate dielectric and a buffer dielectric under the ferroelectric layer on the substrate by thermal oxidation or chemical vapor deposition, the method further comprises:

[0020] forming a doped substrate, and forming each memory cell by shallow trench isolation or field oxidation segmentation to form a memory array;

[0021] The gate dielectrics of the two control gates and the buffer layer under the ferroelectric layer are formed by thermal oxidation or chemical vapor deposition.

[0022] In some embodiments, forming the doped substrate includes:

[0023] The doped substrate is formed by diffusion or ion implantation.

[0024] In some embodiments, depositing a control gate material on the insulating layer includes:

[0025] The control gate material is deposited using chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0026] In some embodiments, patterning the substrate by dry etching or reactive ion etching to expose the substrate to form a control gate includes:

[0027] planarizing the control gate material using chemical mechanical polishing;

[0028] Using photolithography to define the control gate pattern on the photoresist, and using reactive ion etching to pattern it until the substrate is exposed;

[0029] The photoresist is removed to form the control gate.

[0030] In some embodiments, depositing a spacer isolation material on the source and drain epitaxy and etching until the substrate is exposed includes:

[0031] Depositing sidewall isolation materials using chemical vapor deposition or atomic layer deposition;

[0032] Etch using dry etching or reactive ion etching until the substrate is exposed.

[0033] To achieve the above and related purposes, one or more aspects of the present application include features that will be described in detail later. The following description and the accompanying drawings describe some exemplary aspects of the present application in detail. However, these aspects indicate only some of the various ways in which the principles of the present application can be used. In addition, the present application is intended to include all of these aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without any creative work.

[0035] FIG1 is a schematic structural diagram of a nonvolatile semiconductor memory according to an embodiment of the present application;

[0036] FIG2 is a structural diagram of a storage array according to an embodiment of the present application;

[0037] FIG3 is a schematic diagram of a write state of a nonvolatile semiconductor memory according to an embodiment of the present application;

[0038] 4 is a potential distribution diagram of various points on the channel surface of a nonvolatile semiconductor memory device in a write state according to an embodiment of the present application;

[0039] FIG5 is a schematic diagram of a semi-selected state of a nonvolatile semiconductor memory according to an embodiment of the present application;

[0040] 6 is a diagram showing potential distribution at various points on the channel surface of a half-selected memory cell of a nonvolatile semiconductor memory according to an embodiment of the present application;

[0041] FIG7 is a flow chart of a method for manufacturing a non-volatile semiconductor memory according to an embodiment of the present application.

[0042] The reference numerals include: substrate 1 , drain 2 , source 3 , ferroelectric layer 4 , storage gate 6 , and control gate 7 .

[0043] The same reference numerals throughout the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0045] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0046] To address the problems of limited storage density, low reliability, and high power consumption in existing memory solutions, the present application provides a non-volatile semiconductor memory and a preparation method thereof. A control gate and a storage gate are provided, and a ferroelectric layer is provided between the storage gate and the substrate. The polarization state of the ferroelectric layer is changed by the voltage between the control gate and the storage gate, thereby achieving cross-selection of a NOR array structure, eliminating write crosstalk, eliminating leakage current, reducing threshold voltage, operating voltage, and read voltage, improving storage density, enhancing the reliability and erase / write endurance of the memory, improving data retention time, increasing the storage window and erase / write speed, reducing leakage current and power consumption, and improving the overall performance and reliability of the memory.

[0047] To describe the non-volatile semiconductor memory and its manufacturing method in detail, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0048] FIG1 shows a schematic structure of a nonvolatile semiconductor memory according to an embodiment of the present application.

[0049] As shown in Figure 1, the non-volatile semiconductor memory of an embodiment of the present application includes a substrate 1, a control gate 7 and a storage gate 6 arranged in sequence above the substrate 1; wherein, a source 3 and a drain 2 are arranged on the substrate 1, and a region of the substrate 1 located between the source 3 and the drain 2 forms a channel that isolates the source 3 and the drain 2; a ferroelectric layer 4 is provided between the channel and the storage gate 6, and the storage gate 6 is used to apply a voltage to the upper surface of the ferroelectric layer 4 to change the polarization state of the ferroelectric layer 4; the control gate 7 is used to control whether the channel is turned on or off; and data writing, reading, and erasing are achieved by controlling the voltages of the storage gate 6, the source 3, the control gate 7, the drain 2, and the substrate 1.

[0050] Specifically, the memory may include five terminals: a substrate 1, a control gate 7 (CG), a memory gate 6 (MG), a source 3, and a drain 2. A ferroelectric layer 4 composed of materials with ferroelectric properties such as hafnium zirconium oxide and hafnium oxide is arranged under the memory gate 6. A buffer material such as silicon dioxide can be added between the ferroelectric layer 4 and the substrate 1 to form a buffer medium. An insulating medium is arranged between the memory gate 6 and the control gate 7. The insulating medium can be formed of an insulating layer made of insulating materials such as silicon nitride.

[0051] During use of a non-volatile semiconductor memory, the control gate 7 (CG) can be connected to a word line (WL), the drain 2 can be connected to a bit line (BL), the control gate 7 can be connected to the same voltage as the bit line, the source 3 can be grounded via a common source line (Common SL), and the substrate 1 can be grounded, forming a NOR-type crossbar array structure, thereby enabling random access, random writing, and block erasure of data. In some examples, during writing, the storage gate can be connected to the same voltage as the drain 2, or to a different voltage. For example, the storage gate can be connected to a voltage whose difference from the drain 2 is within a preset range.

[0052] As shown in FIG2 , a memory array structure diagram in one embodiment of the present application is shown. The memory array includes word lines (WL), bit lines (Bit Line), memory gate lines (Memory Line), and common source lines (Common Source Line). i 、WL i+1 ...etc. The word line connects the control gate of each memory cell and is used to select a row when writing or reading; the bit line includes BL j BL j+1 ...etc. The bit line connects the drain of each memory cell to avoid crosstalk during writing and to apply voltage to read the memory cell state during reading; the storage gate lead includes ML j ML j+1 ...etc., the storage gate lead connects the storage gate of each memory cell and is used to apply a write voltage and change the residual polarization direction of the ferroelectric layer during writing; the common source lead includes CSL j,j+1 The common source lead connects the source of each memory cell and can be grounded during use. i and j are used to indicate the row and column coordinates in the memory array, respectively, and can be any positive integer. The figure only shows an arbitrary 2*2 area in the memory array; the memory array can actually include more areas. Optionally, the memory array can use an independent source lead (SL) for each column, rather than a common source lead (CSL) for every two columns.

[0053] As shown in the table below, during data writing, the word line, bit line, and storage gate lead can be connected to the write voltage (Write Voltage) Vw, and the common source lead and well can be grounded. During data reading, the word line can be connected to the select voltage (Select Voltage) V sel , that is, the voltage applied to the control gate of the target cell to turn it on when data is read. The bit line can be connected to the drain voltage (Drain Voltage) V of the target cell when reading. d , the storage gate lead can be connected to the read voltage (Read Voltage) V r , that is, the storage gate voltage of the target cell during reading, the common source lead and the well can all be grounded. During the data erase process, the word line, bit line, common source lead and well can all be connected to the erase voltage (Erase Voltage) Ve, and the storage gate lead can be grounded.

[0054] In some examples, the above-mentioned access voltage may adopt different voltage values ​​when the specific device design is different. For example, these voltage values ​​may meet V w 、V e >V sel >V r >V d , making V w 、V e Satisfy the remanent polarization direction of the ferroelectric layer, V sel Greater than the control gate threshold voltage, V r It is greater than the threshold voltage of the storage gate in the memory cell's '1' state, but cannot approach or exceed the threshold voltage of the storage gate in the memory cell's '0' state, V d A voltage difference between the drain and source generates current, for example, V d Can be 0.1V or 0.2V.

[0055] In a specific embodiment of the present application, the substrate 1 is located at the bottom and has a first doping type; its upper part includes source and drain regions, and the source and drain regions are doped with a second doping type opposite to the doping type of the substrate 1; the area between the source 3 and the drain 2 forms a channel, and the channel includes a control gate under-channel and a storage gate under-channel; the material of the substrate 1 includes at least one of silicon, germanium, gallium nitride, gallium arsenide, indium arsenide, indium phosphide, silicon carbide, indium antimonide, IGZO (indium gallium zinc oxide), IAZO (indium aluminum zinc oxide), ITZO (indium tin zinc oxide), and ITO (indium tin oxide).

[0056] The substrate, which can be a silicon substrate, is located at the bottom and has P-type doping. Its upper portion contains the source and drain regions, which are N+ doped. The region between the source and drain is the channel. The gate dielectric, control gate, memory gate, ferroelectric layer, and various insulating layers are stacked on top of the substrate. Ion implantation is used to form a highly doped p-well in the substrate. Shallow trench isolation (STI) and field oxide processes are then used to isolate the memory cells.

[0057] Specifically, the gate dielectric, control gate 7, memory gate 6, ferroelectric layer 4, and various insulating dielectrics located between the lower surface of control gate 7 and the upper surface of substrate 1 are stacked above substrate 1. The vertically corresponding channels can be divided into a control gate lower channel and a memory gate lower channel. Available substrate 1 materials include elemental semiconductors such as silicon and germanium; compound semiconductors such as gallium nitride, gallium arsenide, indium arsenide, indium phosphide, silicon carbide, and indium antimonide; oxide semiconductors such as IGZO (indium gallium zinc oxide), IAZO (indium aluminum zinc oxide), ITZO (indium tin zinc oxide), and ITO (indium tin oxide); alloy compound semiconductors; organic materials; flexible materials; and combinations of these materials. Substrate 1 doping is achieved through diffusion, ion implantation, and other methods. Shallow trench isolation (STI) and field oxide isolation techniques are then used to separate the material into various substrate 1 regions. Furthermore, high-doping concentration regions can be further formed within substrate 1 through diffusion or ion implantation to enhance memory performance, such as p-well (n-well) and EPM implantation.

[0058] In the specific embodiment of the present application, ferroelectric layer 4 is a thin layer composed of a material having ferroelectric properties, located above substrate 1 and covering the central portion of the channel. The lower surface of ferroelectric layer 4 is in contact with substrate 1, and the upper surface is in contact with storage gate 6. A buffer dielectric or insulating layer may be added between the lower surface of ferroelectric layer 4 and substrate 1, and between the upper surface and storage gate 6, to improve the properties of the interface.

[0059] Furthermore, the material of the ferroelectric layer 4 has a remanent polarization in the absence of an electric field, and its polarization state is reversible. Suitable materials for the ferroelectric layer 4 may include metal oxides such as hafnium oxide, doped hafnium oxide, zirconium oxide, hafnium zirconium oxide (HZO), hafnium aluminum oxide (HAlO), and hafnium lanthanum oxide; and salts such as lead titanate, PZT, SBT, and BLT. The ferroelectric layer 4 may be formed on the substrate 1 by one or more of the following methods: atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), and plasma induced chemical vapor deposition (PECVD).

[0060] In addition, a buffer medium is provided on the upper and lower surfaces of the ferroelectric layer 4, respectively. The buffer medium comprises at least one layer of dielectric material of silicon dioxide, silicon carbide, aluminum oxide, hafnium oxide, HfAlO, HfSiO, Ta2O5 or TaSiO, and the buffer medium forms a dielectric layer.

[0061] For example, a thin layer of hafnium zirconium oxide (HZO) is used as the ferroelectric layer, located above the substrate and covering the right side of the channel. The ferroelectric layer's lower surface contacts the substrate, while its upper surface contacts the memory gate. A thin layer of silicon dioxide is placed between the lower surface and the substrate to improve interface properties. Furthermore, the ferroelectric layer can be formed using atomic layer deposition (ALD).

[0062] In a specific embodiment of the present application, storage gate 6 is located directly above ferroelectric layer 4, with its cross-section coinciding with ferroelectric layer 4. To the left of storage gate 6 and ferroelectric layer 4 (the side where the source electrode is located) is control gate 7, which is isolated from storage gate 6 by an insulating layer. Storage gate 6 serves as a gate electrode for applying a high voltage to the top surface of ferroelectric layer 4. Suitable materials for storage gate 6 include semiconductors, such as doped polysilicon; metals, such as tantalum and neodymium; metal nitrides and oxides, such as titanium nitride, tungsten nitride, and tantalum nitride; and metal silicides.

[0063] In addition, methods for forming the memory gate 6 on the ferroelectric layer 4 include low-pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD), etc. If a polysilicon gate is used, in-situ doping can be performed during deposition. After the ferroelectric layer 4 and the memory gate 6 are formed, both can be patterned. The patterning process includes wet etching (WE) after photolithography, reactive ion etching (RIE) after photolithography, etc. Furthermore, the materials that can be used for the insulating layer include one or more layers of insulating dielectrics such as silicon dioxide and silicon nitride, as well as common compounds and organic composite isolation materials. After the ferroelectric layer 4 and the memory gate 6 are formed, the insulating layer can be formed by forming a thin layer of insulating dielectric by chemical deposition methods such as LPCVD and PECVD, followed by a short etching time. The etching method can be dry etching, reactive ion etching (RIE), etc.

[0064] As a specific example, the memory gate can be an N+ polysilicon gate, located directly above the ferroelectric layer, with its cross-section overlapping the ferroelectric layer. To the left of the memory gate and the ferroelectric layer is the control gate, separated from the control gate by a silicon nitride insulating layer. Sidewall spacers are located to the right of the memory gate and the ferroelectric layer. During the fabrication process, a polysilicon thin film is first deposited using low-pressure chemical vapor deposition (LPCVD) technology, with N+ in-situ doping performed during deposition. The memory gate pattern is then defined on the photoresist using photolithography, followed by reactive ion etching (RIE), stopping when the silicon dioxide is exposed and removing the photoresist. Following this, a thin layer of silicon nitride is deposited using LPCVD and briefly etched using RIE until the silicon dioxide is exposed, forming an insulating layer. Sidewall spacers can be formed using the same method after the ferroelectric layer, memory gate, control gate, and insulating layer are all formed.

[0065] In a specific embodiment of the present application, the control gate is located above the substrate 1 and the gate dielectric, covering the remaining area at the edge of the channel and controlling the opening and closing of the channel below it. In the embodiment shown in the accompanying drawings, the control gate covers the left side of the channel. The gate dielectric is located between the lower surface of the control gate and the upper surface of the substrate 1. Side-wall spacers are located to the left of the control gate and to the right of the storage gate and ferroelectric layer. The control gate and storage gate are isolated by an insulating layer. Among them, the gate dielectric can be made of one or more layers of silicon dioxide; silicon nitride; and high-k metal oxide materials such as titanium dioxide, hafnium oxide, aluminum oxide, tantalum oxide, and lanthanum oxide.

[0066] In addition, the gate dielectric is formed before each gate is formed, using deposition techniques such as LPCVD, PECVD, HDP-CVD, and ALD. If silicon dioxide is used as the gate dielectric, thermal oxidation can be used to form a higher quality gate dielectric. The materials available for the control gate are similar to those for the storage gate 6, including polysilicon, metal, metal oxide, or nitride. The process flow for forming the control gate includes deposition, planarization, and patterning. Deposition can be performed using chemical vapor deposition such as LPCVD, PECVD, and HDP-CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), etc. Planarization can be performed using techniques such as chemical mechanical polishing (CMP), and patterning can be performed using etching techniques such as reactive ion etching (RIE) after photolithography masking.

[0067] Furthermore, the control gate can be formed after the memory gate 6 is formed and before the sidewall spacer is formed. The sidewall spacer can be formed using the same method after the ferroelectric layer 4, memory gate 6, control gate, and insulating layer are all formed. Available materials include one or more layers of insulating dielectrics such as silicon dioxide and silicon nitride, as well as common compounds and organic composite insulating materials. For details, please refer to the insulating materials mentioned above.

[0068] As a specific example, the control gate is also an N+ polysilicon gate, located above the substrate and the gate dielectric, covering the remaining area on the left side of the channel. A thin layer of silicon dioxide is placed between the lower surface of the control gate and the upper surface of the substrate, with a sidewall isolation on the left and a silicon nitride insulating layer on the right to isolate it from the storage gate. During the preparation process, a thin layer of silicon dioxide is first formed by thermal oxidation, and then a polysilicon film is deposited using LPCVD, with in-situ doping performed during the process. Thereafter, chemical mechanical polishing (CMP) technology is used for flattening, and the control gate pattern is defined by photolithography. After photolithography, RIE etching is used until the silicon substrate is exposed, and the photoresist is removed to form the control gate. The control gate can be formed after the storage gate is formed and before the sidewall isolation is formed. The materials and formation methods of the sidewall isolation and the inter-gate insulating layer have been described above.

[0069] In a specific embodiment of the present application, the source and drain regions are located on both sides of the channel of the substrate 1, with a high doping concentration and a doping type opposite to that of the channel. They can be formed using doping processes such as diffusion and ion implantation. The source and drain regions can be doped before or after the gate stack and sidewalls are formed. If doped after formation, self-aligned ion implantation can be used. Furthermore, short-time diffusion, low-concentration ion implantation, or oblique ion implantation can be performed after the gate stack is formed and before the sidewalls are formed to form source and drain epitaxy to reduce the short channel effect.

[0070] Specifically, the source and drain regions are located in the substrate, on either side of the channel, and are doped with N+. After the gate stack is formed, low-concentration ion implantation and halo implantation are first performed to form the source and drain epitaxy. After the sidewall isolation is formed, self-aligned ion implantation is used to form the source and drain dopants.

[0071] When writing data using the non-volatile semiconductor memory of the embodiment of the present application, a positive voltage greater than the polarization reversal threshold is applied to the storage gate and drain of the storage cell to be written, and a positive voltage greater than the threshold voltage is applied to the control gate; the channel of the storage cell is fully opened, the positive voltage of the drain drops at the drain end of the channel, and excluding the position intersecting with the drain, the surface potential of the channel is the source voltage 0V; the voltage of the upper surface of the ferroelectric layer is the positive voltage of the storage gate, and the voltage of the lower surface is the potential of the channel surface 0V. The positive voltage of the storage gate drops in the ferroelectric layer, and there is a downward electric field in the ferroelectric layer, and the polarization state changes; after the voltage is removed, the ferroelectric layer has a residual polarization in the downward direction, and the storage cell is written with "1".

[0072] Specifically, FIG3 shows the writing principle of the non-volatile semiconductor memory according to an embodiment of the present application, and FIG4 shows a corresponding potential distribution diagram of each point on the channel surface.

[0073] As shown in Figures 3 and 4, the horizontal axis represents various points on the channel surface, and the vertical axis represents the potential. For example, the ferroelectric layer, hafnium zirconium oxide (HZO), is used. A positive voltage greater than the polarization reversal threshold is applied to the MG and drain (BL) of the memory cell to be written, and a positive voltage greater than the threshold voltage is applied to the CG (WL), using a high voltage level. At this point, the channel of the selected memory cell is fully open, and the positive drain voltage is applied to the drain end of the channel. Excluding the junction with the drain, the surface potential of the majority of the channel is close to the source voltage, 0V. The upper surface voltage of the ferroelectric layer is the positive voltage of the MG, while the lower surface voltage is the channel surface potential, 0V. The large positive voltage applied to the MG is applied to the ferroelectric layer, creating a downward, strong electric field in the ferroelectric layer, causing the polarization state to change. After the voltage is removed, the ferroelectric layer retains a downward residual polarization, and the cell is written with "1."

[0074] In addition, FIG5 shows the principle of a half-selected state of a non-volatile semiconductor memory according to an embodiment of the present application; FIG6 shows the potential distribution of each point on the channel surface of the corresponding half-selected memory cell.

[0075] As shown in Figures 5 and 6, the horizontal axis represents various points on the channel surface, and the vertical axis represents the electric potential. For example, the ferroelectric layer is made of hafnium zirconium oxide (HZO). When the remaining memory cells sharing the BL with the programmed memory cell are half-selected, a positive voltage exceeding the polarization reversal threshold is applied to the MG and drain, and the CG voltage is zero. At this point, there is no inversion layer beneath the CG, but an inversion layer appears beneath the MG. The inversion layer beneath the MG is connected to the drain, and its potential approaches the positive drain voltage. The upper surface voltage of the ferroelectric layer is at the positive MG voltage, while the lower surface voltage is at the positive drain voltage. Because the voltages applied to the MG and drain are the same during operation, the electric field within the ferroelectric layer is very weak. The large positive voltage applied by the MG and drain is applied to the reverse-biased PN junction between the drain, the inversion layer, and the substrate. The ferroelectric layer is shielded by the inversion layer beneath it, and its polarization state remains unchanged. Therefore, the memory cells half-selected by BL are not affected. For the remaining memory cells, the MG, drain, and source voltages are all 0V. Therefore, regardless of whether a positive voltage is applied to CG, the upper and lower surface voltages of the ferroelectric layer are both 0V, the polarization state does not change, and the memory cells are not affected, thereby eliminating the crosstalk of the memory.

[0076] When erasing data using the nonvolatile semiconductor memory device of the present invention, a strong positive voltage with an amplitude greater than the polarization reversal threshold is applied to the substrate where the memory cell to be erased is located, causing the ferroelectric layer to experience a strong upward electric field. After the positive voltage is removed, the ferroelectric layer retains the upward remnant polarization, and the memory cell is erased to "0." All memory cells in the entire region are erased.

[0077] When reading data using the nonvolatile semiconductor memory of the present invention, the CG applies a voltage greater than the threshold voltage, and the MG applies a read voltage; the read voltage is between the threshold voltages corresponding to the two ferroelectric polarization states. If the ferroelectric layer is polarized downward, the MG voltage is greater than the threshold voltage, the channel is turned on, and a "1" is read. If the ferroelectric layer is polarized upward, the voltage on the memory gate is less than or equal to the threshold voltage, the channel is turned off, and a "0" is read.

[0078] Corresponding to the above-mentioned non-volatile semiconductor memory, the present application also provides a method for preparing a non-volatile semiconductor memory. Specifically, FIG6 shows the process of the method for preparing a non-volatile semiconductor memory according to an embodiment of the present application.

[0079] As shown in FIG6 , the method for preparing the non-volatile semiconductor memory according to an embodiment of the present application includes:

[0080] S100: forming a gate dielectric and a buffer dielectric under the ferroelectric layer on the substrate by thermal oxidation or chemical vapor deposition;

[0081] Before step A100, a doped substrate may be formed first, and each memory cell may be formed by shallow trench isolation or field oxidation segmentation to form a memory array; then, the gate dielectrics of the two control gates and the buffer layer under the ferroelectric layer may be formed by thermal oxidation or chemical vapor deposition.

[0082] S200: forming a ferroelectric layer and a storage gate located on the ferroelectric layer on the buffer dielectric, and patterning the layers by reactive ion etching or wet etching;

[0083] S300: depositing an insulating layer material on the gate dielectric, and performing dry etching or reactive ion etching until the gate dielectric is exposed to form an insulating layer;

[0084] S400: depositing a control gate material on the insulating layer and patterning the material until the substrate is exposed by dry etching or reactive ion etching to form a control gate;

[0085] S500: forming source and drain epitaxy on the substrate by lightly doped implantation or oblique implantation, depositing sidewall isolation material on the source and drain epitaxy, and etching until the substrate is exposed to form sidewalls of the control gate;

[0086] S600: forming heavily doped source and drain regions on the substrate by ion implantation or diffusion.

[0087] As a specific example, the method for preparing the non-volatile semiconductor memory according to the embodiment of the present application may include:

[0088] 1) Forming a doped substrate by diffusion or ion implantation, and dividing the material into individual memory cell substrates using isolation techniques such as shallow trench isolation (STI) and field oxide.

[0089] 2) Forming the control gate dielectric and the buffer layer under the ferroelectric layer using deposition techniques such as LPCVD, PECVD, HDP-CVD, and ALD;

[0090] 3) Depositing ferroelectric layer materials using techniques such as atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), or plasma assisted chemical deposition (PECVD);

[0091] 4) Depositing the storage gate material using techniques such as low pressure chemical vapor deposition (LPCVD) or plasma assisted chemical deposition (PECVD);

[0092] 5) Using photolithography to define the memory gate and ferroelectric layer patterns on the photoresist, patterning them using etching techniques such as wet etching (WE) or reactive ion etching (RIE), and then removing the photoresist;

[0093] 6) Depositing an insulating layer material by chemical deposition methods such as LPCVD or PECVD, followed by short-term etching using dry etching, reactive ion etching (RIE), or other techniques until the gate dielectric deposited in step 2 is exposed, forming an insulating layer between the control gate and the storage gate;

[0094] 7) Depositing control gate material using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) techniques such as LPCVD, PECVD, or HDP-CVD;

[0095] 8) Planarization using techniques such as chemical mechanical polishing (CMP);

[0096] 9) Using photolithography to define a control gate pattern on the photoresist, patterning it using etching techniques such as reactive ion etching (RIE), and then removing the photoresist to form a control gate;

[0097] 10) Depositing sidewall isolation material using CVD, ALD, or other techniques, followed by etching using dry etching, RIE, or other techniques until the substrate described in step 1 is exposed, thereby forming sidewall isolation;

[0098] 11) Use diffusion, ion implantation and other doping processes to perform heavy doping. The doping type is opposite to the type doped in the substrate doping process in step 1 to form source and drain regions.

[0099] Furthermore, a high doping concentration region may be formed in the substrate by diffusion or ion implantation to improve device performance, such as p-well (n-well) and EPM implantation.

[0100] It should be noted that the embodiments of the above-mentioned method for preparing the non-volatile semiconductor memory can refer to the description in the embodiment of the non-volatile semiconductor memory, and will not be described in detail here.

[0101] According to the above-mentioned scheme of the non-volatile semiconductor memory and preparation method of the present application, CG can be used to achieve cross-selection during programming, the storage density is improved compared with FeFETs with additional transistors or transmission gates, the write crosstalk is eliminated compared with FeFETs without additional transistors, the reliability is enhanced, and the leakage current is cut off by CG, a lower threshold voltage and read voltage can be used, the impact of the read operation on the data is reduced, so that the reliability is enhanced and the power consumption is reduced.

[0102] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0103] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A nonvolatile semiconductor memory, comprising a substrate, a control gate and a storage gate sequentially arranged above the substrate; wherein: A source electrode and a drain electrode are arranged on the substrate, and a substrate region between the source electrode and the drain electrode forms a channel isolating the source electrode and the drain electrode; A ferroelectric layer is provided between the channel and the storage gate, and the storage gate is used to apply a voltage to the upper surface of the ferroelectric layer to change the polarization state of the ferroelectric layer; The control gate is used to control the channel to be turned on or off, and to control the surface potential of the channel during the data writing process; Data writing, reading and erasing are achieved by controlling the voltages of the storage gate, the source, the control gate, the drain and the substrate.

2. The nonvolatile semiconductor memory according to claim 1, wherein: The substrate is of a first doping type, and the source and the drain are of a second doping type opposite to the first doping type.

3. The nonvolatile semiconductor memory according to claim 1, wherein: The channel includes a control gate lower channel and a storage gate lower channel; The material of the substrate includes at least one of silicon, germanium, gallium nitride, gallium arsenide, indium arsenide, indium phosphide, silicon carbide, indium antimonide, IGZO (indium gallium zinc oxide), IAZO (indium aluminum zinc oxide), ITZO (indium tin zinc oxide), and ITO (indium tin oxide); The channel is formed on the substrate in a manner including shallow trench isolation or field oxide isolation.

4. The nonvolatile semiconductor memory according to claim 1, wherein: The ferroelectric layer covers a part of the channel, and the material of the ferroelectric layer includes hafnium oxide, zirconium oxide, hafnium zirconium oxide, hafnium aluminum oxide, hafnium lanthanum oxide, lead titanate, PZT, SBT, BLT, and is composed of a single layer of any one of the above materials or a multilayer of a combination of multiple materials, and The ferroelectric layer is formed on the substrate by atomic layer deposition, physical vapor deposition, low pressure chemical vapor deposition and plasma chemical deposition.

5. The nonvolatile semiconductor memory according to claim 1 or 4, wherein: Buffer media are respectively arranged on the upper and lower surfaces of the ferroelectric layer; The buffer medium includes at least one dielectric layer of silicon dioxide or silicon carbide or aluminum oxide or hafnium oxide or HfAlO or HfSiO or Ta2O5 or TaSiO.

6. The nonvolatile semiconductor memory according to claim 1, wherein: The cross section of the storage gate is consistent with the ferroelectric layer, and the control gate covers the area of ​​the channel except the ferroelectric layer; The material of the storage gate includes: doped polysilicon, tantalum, neodymium, titanium nitride, tungsten nitride, tantalum nitride, and metal silicide; An insulating medium is arranged between the storage gate and the control gate.

7. The nonvolatile semiconductor memory according to claim 1, wherein: When implementing data writing, a positive voltage greater than the polarization reversal threshold is applied to the storage gate and drain of the storage unit to be written, and a positive voltage greater than the threshold voltage is applied to the control gate; The channel of the memory cell is fully opened, the positive voltage of the drain electrode drops at the drain end of the channel, and the surface potential of the channel is 0V, excluding the position intersecting with the drain electrode; The voltage on the upper surface of the ferroelectric layer is the positive voltage of the storage gate, and the voltage on the lower surface is the potential of the channel surface 0V. The positive voltage of the storage gate falls in the ferroelectric layer, and a downward electric field exists in the ferroelectric layer, and the polarization state changes; After the voltage is removed, the ferroelectric layer has a residual polarization in a downward direction, and the memory cell is written with "1".

8. The nonvolatile semiconductor memory according to claim 1, wherein: When erasing data, a positive voltage with an amplitude greater than a polarization reversal threshold is applied to the substrate where the storage unit to be erased is located, so that the ferroelectric layer is subjected to an upward electric field; After the positive voltage is removed, the ferroelectric layer retains the remnant polarization in the upward direction, and the memory cell is erased to "0".

9. The nonvolatile semiconductor memory according to claim 1, wherein: When data is read, a voltage greater than a threshold voltage is applied to the control gate, and a read voltage is applied to the storage gate, wherein the read voltage is between the threshold voltages corresponding to the two polarization states of the ferroelectric layer; If the polarization direction of the ferroelectric layer is downward, the voltage of the storage gate is greater than the threshold voltage, the channel is turned on, and "1" is read out; If the polarization direction of the ferroelectric layer is upward, the voltage of the storage gate is less than or equal to the threshold voltage, the channel is turned off, and "0" is read out.

10. A method for preparing a non-volatile semiconductor memory, the method comprising: Forming a gate dielectric and a buffer dielectric under the ferroelectric layer on the substrate by thermal oxidation or chemical vapor deposition; forming a ferroelectric layer and a storage gate located on the ferroelectric layer on the buffer medium, and patterning them by reactive ion etching or wet etching; Depositing an insulating layer material on the gate dielectric, and performing dry etching or reactive ion etching until the gate dielectric is exposed to form an insulating layer; Depositing a control gate material on the insulating layer, and patterning the layer by dry etching or reactive ion etching until the substrate is exposed to form a control gate; Forming source and drain epitaxy on the substrate by light doping implantation or oblique implantation, depositing sidewall isolation material on the source and drain epitaxy, and etching until the substrate is exposed to form the sidewall of the control gate; Heavily doped source and drain regions are formed on the substrate by ion implantation or diffusion.

11. The method for preparing a non-volatile memory according to claim 10, wherein: Before forming the gate dielectric and the buffer dielectric under the ferroelectric layer on the substrate by thermal oxidation or chemical vapor deposition, the method further includes: forming a doped substrate, and forming each memory cell by shallow trench isolation or field oxidation segmentation to form a memory array; The gate dielectrics of the two control gates and the buffer layer under the ferroelectric layer are formed by thermal oxidation or chemical vapor deposition.

12. The method for preparing a non-volatile memory according to claim 11, wherein: The forming of the doped substrate comprises: The doped substrate is formed by diffusion or ion implantation.

13. The method for preparing a non-volatile memory according to claim 10, wherein: The step of depositing a control gate material on the insulating layer comprises: The control gate material is deposited by chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

14. The method for preparing a non-volatile memory according to claim 13, wherein: The method of patterning the substrate by dry etching or reactive ion etching until the substrate is exposed to form a control gate comprises: planarizing the control gate material using chemical mechanical polishing; Defining a control gate pattern on the photoresist by photolithography, and patterning the pattern until the substrate is exposed by reactive ion etching; The photoresist is removed to form the control gate.

15. The method for preparing a non-volatile memory according to claim 10, wherein: Depositing a sidewall isolation material on the source and drain epitaxy and etching until the substrate is exposed, comprising: Depositing the sidewall isolation material by chemical vapor deposition or atomic layer deposition; The substrate is etched by dry etching or reactive ion etching until the substrate is exposed.

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