A semiconductor die and method of manufacturing the same

Abstract

The disclosure relates to a semiconductor die, comprising a transistor device in an active area of the die; an electrostatic discharge (ESD) protection structure electrically connected between a load contact and a gate contact; wherein an edge termination structure comprises a field dielectric made of a field dielectric material, the field dielectric material having a first thickness t1 in a first portion of the edge termination structure and a second thickness t2 in a second portion of the edge termination structure, wherein the second portion is arranged laterally between the first portion and the active area and t2 < t1, wherein the ESD protection structure at least partly overlaps the second portion.

Description

[0001] A SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING THE SAME

[0002] TECHNICAL FIELD

[0003] The present application relates to a semiconductor die.

[0004] BACKGROUND

[0005] The semiconductor die may comprise a semiconductor body and a semiconductor device in an active area of the semiconductor body.

[0006] SUMMARY

[0007] Examples of the present application are directed at an advantageous semiconductor die.

[0008] In an embodiment, the application relates to the semiconductor die of claim 1. It may comprise an electrostatic discharge (ESD) protection structure, which is electrically connected between a load contact and a gate contact of the device, e.g. transistor device. The ESD protection structure may be arranged in or with an overlap to an edge termination structure, the edge termination structure disposed laterally between an active area and a lateral edge of the die. The edge termination structure may comprise a field dielectric made of a field dielectric material. The field dielectric material may have a first thickness in a first portion of the edge termination structure and a second thickness in a second portion of the edge termination structure, wherein the second thickness is smaller than the first thickness and the second portion is arranged laterally between the first portion and the active area. In other words, the first portion is arranged further outward than the second portion and the dielectric material is thicker in the first portion.

[0009] The ESD protection structure may be arranged with an at least partial overlap in the second portion. As viewed in a vertical cross-section, the sectional plane lying perpendicular to the lateral edge of the semiconductor die or body, at least an outer part of the ESD protection structure may be arranged above the field dielectric or field dielectric material where it has the first thickness. Optionally, an inner part of the ESD protection structure may overlap the field dielectric or field dielectric material where it has the second thickness. Arranging the ESD protection structure at least partly overlapping the second portion may, for instance, allow for an area saving layout.

[0010] Particular and / or alternative embodiments are provided in the remaining claims and the following description. Therein, the individual features shall be disclosed independently of a specific claim category, the disclosure relates to apparatus and device aspects but also to method and use aspects. If for instance a die manufactured in a specific way is described, this is also a disclosure of a respective manufacturing process, and vice versa. Any embodiment may for instance relate to the die, or to a method or use.

[0011] The edge termination structure may be arranged between the lateral edge of the die or semiconductor body and an active area of the die. In the active area, a device structure may be formed in the semiconductor body, for instance a transistor device structure. Generally, when elements are discussed with respect to the relative position, e.g. when viewed in a vertical cross-section, these elements are for instance arranged on the same side of the active area, i. e. at the same lateral edge of the semiconductor die or body (“outwards” meaning for instance closer to / towards the respective lateral edge, and “inwards” meaning closer to / towards the active area).

[0012] "Vertical" or "vertically" may refer to a vertical direction which lies for instance perpendicular to a surface of the die, e. g. a surface of the semiconductor body. A first side and a second side of the semiconductor body may lie vertically opposite. "Above" may mean vertically aligned and closer to the first side of the semiconductor body or frontside of the die, "below" may mean vertically aligned and closer to the second side of the semiconductor body or the backside of the die. "Lateral" or "laterally" may refer to the lateral directions perpendicular to the vertical direction, in which for instance an area of the semiconductor body or die may be taken.

[0013] The semiconductor body may comprise a semiconductor substrate, for instance in combination with one or a plurality of epitaxial layers thereon. The semiconductor body may, for instance, be a silicon (Si), a silicon carbide (SiC), gallium nitride (GaN) or gallium arsenide (GaAs) semiconductor body.

[0014] A device structure or semiconductor device arranged in the active area may comprise a first load terminal arranged at a first side of the semiconductor body. In addition, it may comprise a second load terminal, which may be arranged at a vertically opposite second side of the semiconductor body. The device or device structure can for instance be a FET having a source terminal / region and a drain terminal / region in the semiconductor body, e.g. the source region at the first side of the semiconductor body and the drain region at the second side thereof.

[0015] In addition to the source region and the drain region, the device may comprise a body region to which a gate electrode capacitively couples. By way of example, the device may be a superjunction transistor device. In the semiconductor body, first regions made of a first doping type and second regions made of a second doping type may be formed. The first regions may be drift regions, and the second regions may be compensation regions. By way of example, the first doping type may be n-type and the second doping type may be p-type.

[0016] As discussed in further detail below, the ESD protection structure may comprise first and second doping type zones arranged alternately in succession. At each end of this diode chain, a respective contact region may be arranged, e.g. made of the second doping type. When reference is made to the ESD protection structure "at least partly overlapping" the second portion, this may read on at least a contact region and / or doping type zone being arranged above the field dielectric or field dielectric material where it has the first thickness. The ESD protection structure, e.g. first and second zones, may be formed in a material layer arranged above the field dielectric material, for instance in a polysilicon layer.

[0017] In an embodiment, the field dielectric of the edge termination structure is arranged recessed in a shallow trench in the semiconductor body. Therein, a first side of the field dielectric material, which faces away from the semiconductor body, may be planar. The vertically opposite second side of the field dielectric, which faces towards the semiconductor body, may have a topography. The planar first side may for instance be obtained in a planarization step, e.g. by chemical mechanical polishing (CMP). Independently of these details, the planar first side may be advantageous, for instance, in terms of a fabrication of the ESD protection structure. In other words, though the ESD protection structure is arranged with at least an overlap in the first portion, where the thickness is larger, it may be formed without a step.

[0018] In an embodiment, the shallow trench has an inclined side wall towards the active area. As viewed in a vertical cross-section perpendicular to the lateral edge, the inclined side wall may be arranged laterally between a bottom of the shallow trench and the active area. The ESD protection structure, e.g. a contact region and / or doping zone(s) thereof, overlaps the inclined side wall. By way of example, the ESD protection structure may overlap the entire inclined side wall, the ESD protection structure being arranged above the inclined side wall (covering it upwards).

[0019] As viewed in a vertical cross-section, at least some of the doping type zones of the ESD protection structure may be arranged above the inclined side wall. By way of example, an inner contact region of the ESD protection structure may be arranged laterally inside of the inclined side wall and / or an outer contact region of the ESD protection structure may be arranged laterally outside of the inclined side wall. Alternatively, one or both contact regions may be arranged above the inclined sidewall.

[0020] Generally, the shallow trench with field dielectric may form a shallow trench isolation, e.g. for a shielding of a device arranged in the active area from an electrical potential at the lateral edge of the die (which may reach up from the backside there, for instance). In other words, by arranging the ESD protection structure with at least an overlap to the shallow trench / field dielectric, an area used for an isolation structure may additionally be used for the ESD protection structure (at least partly).

[0021] In an embodiment, a well region made of a second doping type is arranged at the bottom of the shallow trench. The well region may for instance comprise a non-depletable doping zone and a depletable doping zone, the non-depletable doping zone being for instance arranged laterally inside of the depletable doping zone.

[0022] In an embodiment, the semiconductor die comprises a gate interconnection structure which electrically connects a gate terminal of a device arranged in the active area to a gate contact. In addition, the die may comprise an ESD protection structure electrically connected between a load contact of the device and the gate contact, see the description above for possible details. Therein, the gate interconnection structure may extend along a first length of a first side of the active area, and the ESD protection structure may extend along a second length of the first side of the active area, wherein the gate interconnection structure is completely interrupted along the second length. In other words, the gate interconnection structure may be interrupted to arrange the ESD protection structure laterally aside, which may for instance allow for a space-saving layout.

[0023] The first side of the active area may extend along a first lateral edge of the die. As viewed in a first vertical cross-section, the sectional plane running through the first length and lying perpendicular to the first lateral edge of the semiconductor die, the gate interconnection structure may extend laterally inwards from the gate contact. In a second vertical cross-section, the sectional plane running through the second length and lying perpendicular to the first lateral edge of the die, the ESD protection structure may extend laterally inwards from the gate contact.

[0024] The gate contact may for instance be a gate ring running along the active area and / or a gate pad. In other words, the gate contact may be provided for forming an electrical connection to a gate connection or pin in a package, e.g. via a bond wire or clip or the like. Independently of these details, the gate contact may be formed in a metallization arranged above the first side of the semiconductor body, e.g. deposited onto an insulating layer (interlayer dielectric).

[0025] In an embodiment, the gate interconnection structure and the ESD protection structure are formed in the same material layer, e.g. in a polysilicon layer. Along the first length, the respective portion of the poly silicon layer may form a low ohmic connection between the gate contact and the gate terminal of the device. Along the second length, the ESD protection structure may be formed in the respective portion of polysilicon layer (e.g. by alternating first and second doping zones).

[0026] In an embodiment, a second ESD protection structure is provided at a second side of the active area (which may extend along a second lateral edge of the die). Therein, the second ESD protection structure may extend along the entire second side of the active area. Alternatively or in addition, a further gate interconnection structure may be arranged at a third side of the active area (which may extend along a third lateral edge of the semiconductor die), wherein the further gate interconnection structure may extend along the entire third side of the active area. Alternatively or in addition, a third ESD protection structure may be provided at fourth side of the active area (which may extend along a fourth lateral edge of the die), wherein the third ESD protection structure may extend along the entire fourth side of the active area.

[0027] In an embodiment, the semiconductor die, in addition to the gate interconnection structure and the ESD protection structure, comprises an edge termination structure laterally between the active area and the lateral edge of the die. As to possible details of the edge termination structure, reference is also made to the description above. Referring to the field dielectric material having a first thickness in a first portion of the edge termination structure and a second thickness in a second portion of the edge termination structure, wherein the second portion is arranged laterally inside of a first portion and the second thickness is smaller than the first thickness, the ESD protection structure may overlap the first portion and the second portion along the second length. In other words, as viewed in the second vertical cross-section (see above), the ESD protection structure may be arranged partly in the first and in the second portion, for instance above the inclined side wall as discussed above.

[0028] Along the first length, the gate interconnection structure may overlap the first portion and the second portion. In other words, as viewed in the first vertical cross-section (see above), the gate interconnection structure may be arranged partly in the first and partly in the second portion, e.g. above an inclined side wall of a shallow trench.

[0029] In an embodiment, a semiconductor die comprises an ESD protection structure. The ESD protection structure may comprise first zones made of a first doping type and second zones made of a second doping type, the first and second zones being arranged alternately in succession. In an embodiment, a doping concentration of the second zones is higher than a doping concentration of the first zones. By way of example, the first type may be n-type and the second type may be p-type, e.g. a higher p doping being applied in the second zones compared to an n doping of the first zones. In an embodiment, the ESD protection structure, in addition to the first and second zones, comprises contact regions made of the second doping type. The first and second zones may be arranged alternately in succession between the contact regions. In an embodiment, a doping concentration in the contact regions is higher than a doping concentration in the first and / or second zones. The doping concentration in the first zones may be smaller than the doping concentration in the second zones, wherein a doping concentration in the contact regions may be equal two or even higher than the doping concentration in the second zones.

[0030] Via the contact regions, a diode chain formed by the first and second zones may be electrically connected, e.g. via one contact region to the gate contact and / or via the other contact region to the load contact. In detail, a respective contact may be formed by a respective contact plug which may vertically intersect an insulating layer (ILD) covering the ESD protection structure.

[0031] In an embodiment, the first and second zones are arranged alternately in succession in a length direction. The length direction may be a lateral direction, e.g. a lateral direction which lies perpendicular to the lateral edge of semiconductor die. Independently of these details, a respective contact region may have a larger extension in the length direction than a respective first and / or second zone.

[0032] In an embodiment, the first zones have basically the same extension in the length direction with respect to each other. Alternatively or in addition, the second zones may have basically the same extension in the length direction with respect to each other. Therein, a doping concentration of the second zones may be higher than a doping concentration of the first zones.

[0033] As discussed above, the ESD protection structure may be formed in a polysilicon layer. In detail, the first and second zones may be formed in the polysilicon layer, e.g. via a respective first and second doping type implantation. Optionally, the contact regions may be formed in the poly silicon layer as well.

[0034] In an embodiment, the polysilicon layer has a thickness of not more than 400 nm, further upper limits being for instance not more than 300 nm, 200 nm or 100 nm. Lower limits may be at least 50 nm or 80 nm, by way of example. In an embodiment, the ESD protection structure has a diode pitch of not more than 2.3 pm, further upper limits being for instance not more than 2 pm, 1.7 pm, 1.4 pm, 1.2 pm, 1 pm or 0.8 pm. Lower limits may be at least 0.6 pm or 0.7 pm, by way of example.

[0035] As discussed above, the ESD protection structure may be arranged on a field dielectric, e.g. with an additional layer in between or directly on the field dielectric. In an embodiment, the ESD protection structure is embedded into an interlayer dielectric, which may be an insulating layer made of one or a plurality of sublayers. Independently of these details, a metallization may be arranged on the interlayer dielectric, e.g. the load contact and / or gate contact being formed in the metallization.

[0036] The ESD protection structure embedded into the interlayer dielectric may be covered upwards and laterally by the interlayer dielectric. In other words, as viewed in a vertical crosssection perpendicular to the lateral edge of the die, the interlayer dielectric may not only cover an upper side of the ESD protection structure, e.g. respective portion of the polysilicon layer. Additionally, it may also cover an inner lateral end of the respective portion of the polysilicon layer inwards and / or may cover an outer lateral end of the respective portion of the polysilicon layer outwards.

[0037] In an embodiment, a superjunction transistor device is arranged in the active area. It may comprise a plurality of superjunction transistor cells, e.g. respectively having a drift region portion and a compensation region portion.

[0038] In an embodiment, a method of manufacturing a semiconductor die may comprise forming a transistor device in the active area and forming an ESD protection structure, e.g. electrically connected between a load contact (e.g. source pad) and a gate contact of the device.

[0039] In an embodiment, forming the ESD protection structure may comprise: providing a polysilicon layer doped with a first doping type; providing a structured mask on the doped polysilicon layer; implanting a second doping type through openings defined by the mask. The openings may define the second zones and / or the contact regions. In an embodiment, a respective opening defining a respective contact region is larger than a respective opening defining a respective second zone. Alternatively or in addition, a respective opening defining a respective second zone may be smaller than a respective coverage section in between. A respective coverage section may cover a first doping zone, e.g. be arranged laterally between two neighboring openings which respectively define a second zone.

[0040] In an embodiment, a respective opening defining a respective second zone is smaller than half a diode pitch, see the description above for possible values.

[0041] In an embodiment, a respective opening defining a respective second zone has, taken in a length direction, an extension of not more than 600 nm, possible upper limits being for instance not more than 500 nm, 400 nm, 300 nm or 200 nm. Possible lower limits may be at least 100 nm or 150 nm, by way of example.

[0042] BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Below, the die and further details are explained by means of exemplary embodiments. Therein, the individual features can also be relevant for the application in a different combination.

[0044] Figure 1 shows a vertical cross-section of a semiconductor die with an edge termination structure;

[0045] Figure 2 shows an enlarged view of figure 1;

[0046] Figures 3a-c illustrate an ESD protection structure and some manufacturing details;

[0047] Figure 4 shows a portion of a semiconductor die in a vertical top view;

[0048] Figure 5 shows a vertical top view of a semiconductor die;

[0049] Figure 6 shows a vertical cross-section in an active area of a semiconductor die.

[0050] PARTICULAR EMBODIMENT

[0051] Figure 1 shows a vertical cross-section of a semiconductor die 1, namely of an edge termination structure 10 arranged laterally between an active area 100 and a lateral edge 1.1 of the die 1. In the active area 100, a transistor device 110 may be formed, see below in further detail. A load contact 20 may electrically connect to a load terminal, for instance source region, of the transistor device. The load contact 20 may in particular be a source plate connecting to a source terminal or region. Further, a gate contact 30 is shown which may, in another sectional plane than illustrated in figure 1, connect to a gate terminal of the transistor device, see in detail below.

[0052] In the sectional view of figure 1, an electrostatic discharge (ESD) protection structure 40 is shown, it connects between the load contact 20 and the gate contact 30. The ESD protection structure 40 may protect the device, for instance a gate dielectric of the device, from an electrostatic discharge event that may occur during assembly or operation.

[0053] The edge termination structure 10 may comprise a field dielectric 11 made of a field dielectric material 12. The field dielectric 11 may isolate the active area 100 from an edge potential at a first side 2.1 (frontside) of the semiconductor body 2, for instance from a backside or drain potential reaching up to the frontside at the lateral edge 1.1. In particular, the field dielectric 11 may be recessed in a shallow trench 13, namely form a shallow trench isolation.

[0054] The field dielectric material 12 has a first thickness ti in a first portion 10.1 of the edge termination structure 10 and a second thickness t2in a second portion 10.2 of the edge termination structure 10. As illustrated in figure 1, the second thickness t2is smaller than the first thickness ti and the second portion 10.2 is arranged laterally inside of the first portion 10.1. The ESD protection structure 40 may at least partly overlap the second portion 10.2. Using the area above the second portion 10.2 may for example allow for an integration of the ESD protection structure 40 in an area saving manner, e. g. for a comparably narrow high-voltage edge termination structure.

[0055] Referring to the shallow trench 13, the first thickness ti may in particular be taken from a bottom 13b of the shallow trench 13. In a sense, the ESD protection structure 40 is placed in a transition between the active area 100 and the shallow trench isolation, it may in particular overlap in inclined sidewall 13a of the shallow trench 13, see below. The load contact, the gate contact and the field dielectric may be arranged on the first side of the semiconductor body, and the ESD protection structure may be integrated into the stack on the first side, for instance as a polysilicon diode chain. In the embodiments shown, a first or upper side 12.1 of the field dielectric material 12, which faces upwards (e. g. away from the semiconductor body 2), is planarized. In other words, the first or upper side 12.1 may lie in a horizontal plane. The planarization can for instance allow for a particularly narrow lithography, e. g. enable diodes with a comparably small spacing. As detailed below, a mask opening may only be around 0.5 pm or smaller and the spacing between two mask openings can be around 1.8 pm or even smaller in case of a higher doping, for instance higher n-doping.

[0056] Seen in a vertical cross-section perpendicular to the lateral edge 1.1 of the die 1 , the thickness of the dielectric material 11 above the inclined side wall 13a decreases towards the active area 100. The ESD protection structure may overlap the inclined sidewall 13a only partially, a laterally inner end or a laterally outer end of the ESD protection structure 40 arranged above the inclined sidewall 13a. In particular, however, the ESD protection structure 40 may overlap the entire inclined sidewall 13a. A laterally inner end of the ESD protection structure 40 can be arranged above a field dielectric portion having a constant thickness and a laterally outer end of the ESD protection structure can be arranged above the bottom 13b of shallow trench 13.

[0057] In addition to the field dielectric 11, the edge termination structure 10 may comprise a well region 15 at the bottom of the shallow trench 13 and extending towards the active region 100. The well region 15 may be made of a second doping type, in particular p-type. It may for instance comprise a non-depletable doping zone and a depletable doping zone, the latter arranged for instance laterally outside of the non-depletable doping zone (not referenced in further detail). Below the well region 15 first and second regions are shown, see figure 6 in further detail.

[0058] Figure 2 shows an enlarged view of figure 1. The ESD protection structure 40 is formed in a common material layer 50, in particular polysilicon layer 51. In the embodiment shown, the common material layer 50 is deposited onto the field dielectric 11 and the ESD protection structure 40 is embedded into an interlayer dielectric 70 arranged on the field dielectric 11. A thickness of the interlayer dielectric 70 may exceed a thickness of the ESD protection structure 40 which is embedded laterally and covered upwards by the interlayer dielectric 70. In the common material layer 50, also a gate interconnection structure 90 may be formed, see figure 4 for comparison. Figures 3a-c illustrate further the ESD protection structure 40 and some manufacturing details. Figure 3a illustrates a schematic cross-sectional view of a structured mask 80 on a polysilicon layer 51. Prior to the deposition and structuring of the mask 80, the polysilicon layer 51 may be doped with a first doping type, subsequently a second doping type may be introduced through the openings 82, 83 in the mask 80. Generally, in this disclosure, the first doping type may in particular be n-type and the second doping type p-type.

[0059] The ESD protection structure 40 may comprise first zones 41 made of a first doping type and second zones 42 made of a second doping type, the first and second zones 41, 42 arranged alternately in succession. Referring to a length direction 45, the first zones 41 may substantially have the same extension with respect to each other and / or the second zones 42 may substantially have the same extension with respect to each other. Compared to a respective first zone 41, a respective second zone 42 may have a greater extension in the length direction 45 (see figure 3b). A respective contact region 43 may have a larger extension than a respective first and / or second zone 41, 42.

[0060] Considering again the structured mask 80, a respective opening 83 defining a respective contact region 43 to contact the diode chain may be larger than a respective opening 82 defining a respective second zone 42. A respective opening 82 defining a respective second zone 42 may be smaller than a respective coverage section 81 in between. A respective opening 82 may in particular be smaller than half a diode pitch.

[0061] For illustration, in absolute values, a respective opening 82 may for instance have, taken in the length direction 45, an extension of not more than 600 nm, 500 nm, 400 nm, 300 nm or 200 nm, possible lower limits being for example 100 nm or 150 nm. In the length direction 45, the first and second zones may be arranged alternately or, in case of the structured mask 80, the coverage sections 81 openings 82 may be arranged alternately in succession.

[0062] Figure 3b illustrates a thickness tps of the polysilicon layer 51, which may for instance be not more than 400 nm, 300 nm, 200 nm or 100 nm, possible lower limits being for example 50 nm or 80 nm. In the ready-made ESD protection structure 40, first and second zones 41, 42 may be arranged with a diode pitch of not more than 2.3 pm, 2 pm, 1.7 pm, 1.4 pm, 1.2 pm, 1 pm or 0.8 pm. Possible lower limits may for instance be 0.6 pm or 0.7 pm. Figure 3c illustrates a doping profile or concentration along the contact regions and first / second zones 41, 42, 43. A doping concentration 62 of the second zones 42 may be higher than a doping concentration 61 of the first zones 41. A doping concentration 63 of the contact regions 43 may be higher than a doping concentration 61 of the first zones 41 and / or a doping concentration 62 of the second zones 42.

[0063] Figure 4 shows a portion of the die 1 in a vertical top view. Laterally between the active area 100 and the lateral edge 1.1 of the die 1, the ESD protection structure 40 is arranged. As detailed above, it may connect between a load contact (on the left) and a gate contact (on the right), wherein these contacts are not shown in figure 4. In addition to the ESD protection structure 40, a gate interconnection structure 90 is shown, which may be formed in the same common material layer, in particular polysilicon layer, see above.

[0064] Referring to a first side 101 of the active area 100, which is oriented towards the lateral edge 1.1, the gate interconnection structure 90 may extend along a first length 101.1 of the first side 101. Along a second length 101.2 of the first side 101, the gate interconnection structure 90 may be completely interrupted, the ESD protection structure 40 arranged along the second length 101.2. Along the first length 101.1, the gate interconnection structure 90 may overlap the first and second portion 10.1, 10.2 (see figure 1), in particular it may overlap the entire inclined sidewall 13a. Along the second length 101.2, the ESD protection structure 40 may overlap the first portion 10.1 and second portion 10.2 (see figure 1), in particular may overlap the entire inclined sidewall 13a.

[0065] Figure 5 shows a schematic vertical top view of the complete die, e.g. illustrates four lateral edges 1.1-1.4 of the die 1. As described with reference to figure 4, the ESD protection structure 40 and the gate interconnection structure 90 are both arranged at the first side 101. At a second side 102 of the active area 100, a second ESD protection structure 140 may be provided, for instance extending along the entire second side 102. Alternatively or in addition, a further gate interconnection structure 190 may be provided at a third side 103 of the active area 100, extending for instance along the entire third side 103 of the active area 100. Alternatively or in addition, a third ESD protection structure 240 may be provided at a fourth side 104 of the active area 100, extending for instance along the entire fourth side 104 of the active area 100. Figure 6 shows a schematic cross-section in the active area 100 and illustrates the semiconductor device 110 which may in particular be a superjunction transistor device. In the semiconductor body 2, first regions 211 made of a first doping type and second regions 212 made of a second doping type are formed, wherein the first regions 211 may be drift regions in this semiconductor device 110. The second regions 212 may be compensation regions. The numeral 110.1 indicates one superjunction transistor cell.

[0066] Above the first and second regions 211, 212, a body region 112 and source region 111 (load terminal 115) may be formed. The source region 111 is arranged at the first side 2.1 of the semiconductor body 2, a drain region 113 of the device 110 is arranged at the vertically opposite second side 2.2 (“backside”) of the semiconductor body 2. The source and drain region 111, 113 may be made of the first doping type, the body region 112 of the second doping type. The first doping type may in particular be n-type, the second doping type p-type. From the first side 2.1, a gate trench or trenches 215 extend into the semiconductor body, the gate electrode / terminal 116 arranged laterally aside the body region 112. In an embodiment not shown, the body region may be arranged aside the source region, for instance combined with a planar gate formed above.

Claims

Claims1. A semiconductor die (1) with a semiconductor body (2), comprising: a transistor device (110) in an active area (100) of the die (1); an edge termination structure (10) laterally between the active area (100) and a lateral edge (1.1) of the die (1); a load contact (20) electrically connected to a load terminal (115) of the transistor device (110); a gate contact (30) electrically connected to a gate terminal (116) of the transistor device (110); an electrostatic discharge (ESD) protection structure (40) electrically connected between the load contact (20) and the gate contact (30); the edge termination structure (10) comprising a field dielectric (11) made of a field dielectric material (12), the field dielectric material (12) having a first thickness ti in a first portion (10.1) of the edge termination structure (10) and a second thickness t2in a second portion (10.2) of the edge termination structure (10), wherein the second portion (10.2) is arranged laterally between the first portion(10.1) and the active area (100), the second thickness t2being smaller than the first thickness t wherein the ESD protection structure (40) at least partly overlaps the second portion(10.2).

2. The semiconductor die (1) of claim 1, wherein the field dielectric (11) of the edge termination structure (10) is arranged recessed in a shallow trench (13) in the semiconductor body (2).

3. The semiconductor die (1) of claim 2, wherein a first side (12.1) of the field dielectric material (12) facing away from the semiconductor body (2) is planar.

4. The semiconductor die (1) of claim 2 or 3, wherein the shallow trench (13) has an inclined sidewall (13a) towards the active area (100), the ESD protection structure (40) at least partially overlapping the inclined sidewall (13a).

5. The semiconductor die (1) of claim 4, wherein, seen in a vertical cross-section perpendicular to the lateral edge (1.1) of the die (1), the ESD protection structure (40) overlaps the entire inclined sidewall (13a).

6. The semiconductor die (1) of any one of claims 2 to 5, wherein a well region (15) made of a second doping type is arranged at the bottom of the shallow trench (13), the well region (15) particularly comprising a non-depletable doping zone and a depletable doping zone.

7. A semiconductor die (1), comprising: a transistor device (110) in an active area (100) of the die (1); a load contact (20) electrically connected to a load terminal (115) of the transistor device (110); a gate contact (30) electrically connected to a gate terminal (116) of the transistor device (110); a gate interconnection structure (90) connecting the gate terminal (116) of the transistor device (100) to the gate contact (30); an electrostatic discharge (ESD) protection structure (40) electrically connected between the load contact (20) and the gate contact (30); the gate interconnection structure (90) extending along a first length (101.1) of a first side (101) of the active area (100), the ESD protection structure (40) extending along a second length (101.2) of the first side (101) of the active area (100), wherein the gate interconnection structure (90) is completely interrupted along the second length (101.2) of the first side (101) of the active area (100).

8. The semiconductor die (1) of claim 7, wherein the gate interconnection structure (90) and the ESD protection structure (40) are formed in a common material layer (50), in a particular polysilicon layer (51).

9. The semiconductor die (1) of claim 7 or 8, comprising: a second electrostatic discharge (ESD) protection structure (140) electrically connected between the load contact (20) and the gate contact (30); wherein the second ESD protection structure (140) extends along an entire second side (102) of the active area (100).

10. The semiconductor die (1) of any one of claims 7 to 9, comprising: an edge termination structure (10) laterally between the active area (100) and a lateral edge (1.1) of the die (1); the edge termination structure (10) comprising a field dielectric (11) made of a field dielectric material (12), the field dielectric material (12) having a first thickness ti in a first portion (10.1) of the edge termination structure (10) and a second thickness t2in a second portion (10.2) of the edge termination structure (10), wherein the second portion (10.2) is arranged laterally between the first portion (10.1) and the active area (100), the second thickness t2being smaller than the first thickness t wherein along the first length (101.1) the gate interconnection structure (90) overlaps the first portion (10.1) and the second portion (10.2), and wherein along the second length (101.2) the ESD protection structure (40) overlaps the first portion (10.1) and the second portion (10.2).

11. The semiconductor die (1) of claim 10, wherein the field dielectric (11) of the edge termination structure (10) is arranged recessed in a shallow trench (13) in a semiconductor body (2), which has an inclined sidewall (13a) towards the active area (100), wherein along the first length (101.1) the gate interconnection structure (90) overlaps the entire inclined sidewall (13a), and wherein along the second length (101.2) the ESD protection structure (40) overlaps the entire inclined sidewall (13a).

12. A semiconductor die (1), comprising: a transistor device (110) in an active area (100) of the die (1); a load contact (20) electrically connected to load terminal (115) of the transistor device (110);a gate contact (30) electrically connected to a gate terminal (116) of the transistor device (110); an electrostatic discharge (ESD) protection structure (40) electrically connected between the load contact (20) and the gate contact (30); the ESD protection structure (40) comprising first zones (41) made of a first doping type and second zones (42) made of a second doping type, the first zones (41) and second zones (42) arranged alternately in succession, wherein a doping concentration (62) of the second zones (42) is higher than a doping concentration (61) of the first zones (41).

13. A semiconductor die (1), comprising: a transistor device (110) in an active area (100) of the die (1); a load contact (20) electrically connected to a load terminal (115) of the transistor device (110); a gate contact (30) electrically connected to a gate terminal (116) of the transistor device (110); an electrostatic discharge (ESD) protection structure (40) electrically connected between the load contact (20) and the gate contact (30); the ESD protection structure (40) comprising first zones (41) made of a first doping type and second zones (42) made of a second doping type and contact regions (43) made of the second doping type; the first zones (41) and second zones (42) arranged alternately in succession between the contact regions (43), wherein a doping concentration (63) in the contact regions (43) is higher than a doping concentration (61, 62) in the first and / or second zones (41, 42).

14. The semiconductor die (1) of claim 13, the first and second zones (41, 42) arranged alternately in succession in a length direction (45), wherein the contact regions (43) respectively have a larger extension in the length direction (45) than a respective first and / or second zone (41, 42).

15. The semiconductor die (1) of claim 13 or 14, the first and second zones (41, 42) arranged alternately in succession in a length direction (45), wherein the first zones (41) have substantially the same extension in the length direction (45) with respectto each other and / or the second zones (42) have substantially the same extension in the length direction (45) with respect to each other.

16. The semiconductor die (1) of claim 15, wherein a doping concentration (62) of the second zones (42) is higher than a doping concentration (61) of the first zones (41).

17. The semiconductor die (1) of any one of the preceding claims, wherein the ESD protection structure (40) is formed in a polysilicon layer (51), in particular first zones (41) and second zones (42) of the ESD protection structure (40) being formed in the polysilicon layer (51).

18. The semiconductor die (1) of claim 17, the poly silicon layer (51) having a thickness tpSof not more than 400 nm, 300 nm, 200 nm or 100 nm, possible lower limits being for instance 50 nm or 80 nm.

19. The semiconductor die (1) of any one of the preceding claims, wherein the ESD protection structure (40) has a diode pitch of not more than 2.3 pm, 2 pm, 1.7 pm, 1.4 pm, 1.2 pm, 1 pm, 0.8 pm, possible lower limits being for instance 0.6 pm or 0.7 pm.

20. The semiconductor die (1) of any one of the preceding claims, comprising: a field dielectric (11) on which the ESD protection structure (40) is arranged; wherein the ESD protection structure (40) is embedded into an interlayer dielectric (70) arranged on the field dielectric (11).

21. The semiconductor die (1) of any one of the preceding claims, the transistor device (110) comprising a plurality of superjunction transistor cells (110.1).

22. A method of manufacturing a semiconductor die (1), in particular the semiconductor die (1) of any one of the preceding claims, comprising the steps: forming a transistor device (110) in an active area (100) of the die (1); forming an electrostatic discharge (ESD) protection structure (40) electrically connected between a load contact (20) and a gate contact (30).

23. The method of claim 22, in particular for manufacturing the semiconductor die (1) of any one of claims 12 to 18, wherein forming the ESD protection structure (40) comprises: providing a poly silicon layer (51) doped with a first doping type; providing a structured mask (80) on the doped polysilicon layer, implanting the second doping type through openings (82) defined by the mask.

24. The method of claim 23, wherein a respective opening (83) defining a respective contact region (43) is larger than a respective opening (82) defining a respective second zone (42) and / or a respective opening (82) defining a respective second zone (42) is smaller than a respective coverage section (81) in between.

25. The method of claim 24, wherein a respective opening (82) defining a respective second zone (42) is smaller than half a diode pitch.

26. The method of claim 24 or 25, wherein a respective opening (82) defining a respective second zone (42) has, taken in a length direction (45), an extension of not more than 600 nm, 500 nm, 400 nm, 300 nm or 200 nm, possible lower limits being 100 nm or 150 nm.

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