Method for transmitting data

Abstract

One aspect of the invention relates to a method (4) for transmitting data between a first electronic device (30) with a discrete output (OUT_mult) and a second device (20) connected to the first device (30) via the discrete output (OUT_mult), comprising: the first device (30) defining (41) an expected output voltage level (Vcmd) from among the plurality of predefined voltage levels, a voltage regulation loop of the first device (30) regulating (42) the output voltage level, the regulation loop controlling (43) an output transistor (Q1) of the first device (30) so as to have the expected output voltage level (OUT_mult), the output of the output transistor being the discrete output (D, OUT_mult) connected to the second device (20), and the second device (20) reading (44) the voltage level of the discrete output.

Description

DESCRIPTION TITLE: Data transmission method TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of electronics.

[0002] The present invention relates to data transmission using a multi-information electronic device of the “DSO” (Discrete Signal Output) type with regulated voltage level. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0003] An aircraft has multiple electrical and electronic devices that must communicate with each other. Some of these devices must transmit at least one binary data, for example to indicate their status.

[0004] For this purpose, Figure 1 shows a block diagram of a binary data transmission device called a "DSO". The DSO 10 shown in Figure 1 comprises a CMD control, a GND ground, and an OUT output. The value of the OUT output is governed by the control of the transistor 11, the transistor 11 being controlled by the CMD control. When the block diagram of Figure 1 is used to transmit a discrete signal by information, the CMD control makes the transistor 11 conductive or blocked, for a sufficient duration for a device receiving the signal to be able to decode the status of the information (conductive or blocked). And this status remains unchanged as long as the transmitted information does not need to be modified. A DSO therefore makes it possible to transmit a single binary information per physical signal.

[0005] An electrical schematic representation of a DSO 10 is shown in Figure 2.

[0006] As shown in Figure 2, the DSO 10 is connected to a remote device 20, to which it transmits the binary information. The DSO 10 of Figure 2 includes the same CMD control signal as in Figure 1. The transistor 11 in Figure 2 is a MOSFET transistor and is controlled by the CMD control. The arrangement is of the "open drain" type, that is to say that the drain of the MOSFET 11 is connected to the remote device 20 and the source of the MOSFET 11 is connected to ground. To transmit the binary information, the MOSFET 11 is controlled to the on state or to the off state via its gate. The output voltage is determined by the remote device 20, which includes a power supply 21 and a resistor 22. The resistor 22 creates a pull-up resistor. When the MOSFET 11 is driven into the blocking state, its output voltage is 28 Volts, thanks to the power supply 21 and the pull-up resistor 22. The discrete output signal is then in the positive state (or "1"). When the MOSFT is driven into the on state, its output voltage is zero or close to 0V. The discrete output signal is then in the zero state (or "0").

[0007] To transmit multiple pieces of information in a simple and robust way, there are several solutions. One solution is to use a discrete signal per piece of information. Using a discrete signal per piece of information requires using a DSO per signal (such as those shown in Figures 1 and 2), which requires duplicating the number of components and wires in the harnesses. This multiplies the surface area required on the board, generates mass and cost, and leads to a loss of reliability.

[0008] Another solution is to use a discrete Pulse Width Modulated (PWM) signal. A pulse width modulated signal can transmit multiple pieces of information by encoding and decoding its duty cycle value. Figure 3 shows a schematic representation of the time-domain evolution of a pulse width modulated signal.

[0009] When the principle of the block diagram in Figure 1 is used to create a pulse width modulated signal, the CMD command turns transistor 11 on for a certain duration Ton, then turns it off for a duration Toff.

[0010] This cycle Ton and Toff is repetitive at a chosen fixed frequency F, of period T. We then have Ton + Toff = T, as shown in Figure 3.

[0011] It is then possible to choose by configuration several Ton values ​​which will correspond to the transmission of several pieces of information: Ton1, Ton2, etc.

[0012] This principle therefore makes it possible to transmit several binary information via the same physical DSO OUT output signal.

[0013] However, using a discrete Pulse Width Modulated (PWM) signal has disadvantages. In particular, it is difficult to filter such a signal. If no filtering is applied, the signal then has a significant susceptibility to external disturbances, particularly with regard to remote devices 20. On the contrary, by applying too much filtering, a loss of information can occur.

[0014] The compromise to be found on the level of filtering is key and generates numerous adjustments during equipment qualifications, before their commissioning.

[0015] Furthermore, using a fixed frequency modulated signal requires switching the output signal OUT at the frequency 1 / T, generating disturbances linked to these signal switchings.

[0016] It is therefore appropriate to propose an approach which does not have the drawbacks of the prior art. SUMMARY OF THE INVENTION

[0017] The invention provides a solution to the problems mentioned above, by proposing data transmission using a multi-level output DSO, allowing the DSO to have several possible voltage levels on its output and therefore several pieces of information.

[0018] Thus, one aspect of the invention relates to a method for transmitting data between at least one first electronic device with a discrete output and at least one second device connected to the first device via the discrete output, the discrete output having a voltage level from among a plurality of predefined voltage levels, the method comprising: defining, by a control of the first device, an expected output voltage level from among the plurality of predefined voltage levels, regulating the output voltage level by a voltage regulation loop of the first device, the regulation loop comprising a constant voltage at the input, the regulation comprising a modification of a voltage feedback gain of the voltage regulation loop to compensate for the difference between the output voltage and the expected output voltage, controlling, by the regulation loop, an output transistor of the first device,to present the expected output voltage level between an input of the output transistor and an output of the output transistor, the input, of the output transistor being connected to ground and the output of the output transistor being the discrete output connected to the second device, reading, by the second device, of the voltage level of the discrete output.

[0019] The invention makes it possible to propose data transmission via an electronic device with a multi-information discrete output, thanks to the voltage regulation loop. Indeed, for the first electronic device, the impedance of the second electronic device is unknown. When several second electronic devices are connected to the first electronic device to read its output, each second electronic device does not know the impedance of the other second electronic devices. Since the impedance of the second electronic circuit influences the output voltage of the first electronic device, when several second electronic devices are connected to the first electronic device, the second electronic devices cannot decode the output information of the first electronic device.The control loop makes it possible to solve this problem, by ensuring an output voltage equal to the voltage expected by the control of the first device, and therefore output information decodable by each second device connected to the first device, the voltage corresponding to a given information then always being the same at the output of the first device.

[0020] Thus, the principle of the invention adopted to realize this multi-level output DSO is that of using a regulation loop of the output voltage of the DSO. For example, an output voltage regulated to a first voltage V1 will correspond to a first binary information, an output voltage regulated to a second voltage V2 will correspond to a second binary information, etc.

[0021] The control of the first device of the system according to the invention remains simple and requires a reduced number of components. It is also compatible with the product environment, in particular lightning and EMC constraints.

[0022] Thanks to the invention, it is possible to reliably generate different output voltage levels of a DSO based on simple components.

[0023] At least one of the expected output voltage levels is a predefined point in the linear operating regime of the output transistor, the expected output voltage level being controlled by the control of the first device.

[0024] In addition to the characteristics which have just been mentioned in the preceding paragraphs, the method according to the invention may further comprise: Changing the expected voltage level by controlling the first device, regulating the output voltage level by the voltage regulation loop of the first device, controlling, by the regulation loop, the output transistor of the first device, to present the modified expected output voltage level.

[0025] Another aspect of the invention relates to a data transmission system comprising a first electronic device with a discrete output and a second device connected to the first device via the discrete output, the discrete output having a voltage level among a plurality of predefined voltage levels, the first device comprising: a control defining an expected output voltage level among the plurality of predefined voltage levels, the voltage regulation loop comprising a constant voltage at the input, configured to compare the expected output voltage level with the output voltage level to obtain a voltage level difference, and to modify the voltage feedback gain of the voltage regulation loop to compensate for the difference between the output voltage and the expected output voltage, an output transistor, the output transistor comprising a control,an input connected to ground and the discrete output connected to the second device, the control of the output transistor being controlled by the voltage regulation loop to present the expected output voltage level between the input of the output transistor and the output of the output transistor.,

[0026] In addition to the characteristics which have just been mentioned in the preceding paragraph, the system according to a second aspect of the invention may have one or more complementary characteristics among the following, considered individually or according to all technically possible combinations: the first device comprises an open-drain output, wherein the output transistor of the first device is a field-effect transistor comprising a gate, a drain and a source, the control of the output transistor being the gate, the input of the output transistor being the source and the output of the output transistor being the drain, and wherein the second device comprises at least one power supply and a resistor performing a pull-up resistor function, an output of the voltage regulation loop controls a gate of an intermediate transistor included in the first device, the intermediate transistor comprising a drain controlling the gate of the output transistor, The intermediate transistor adjusts the output control voltage according to a measurement of the difference between the control and the output voltage, The output transistor adjusts the output control voltage according to a difference measurement between the control and the output voltage, the regulation loop comprises a voltage reference providing the constant voltage. the voltage reference is a TL431 integrated circuit. each voltage level of the plurality of predefined voltage levels corresponds to a binary value of the discrete output. the control of the first device is carried out by a plurality of voltage divider bridges having a common control voltage output, each voltage divider bridge being associated with a switch, each switch defining the state of a bit of a sequence of bits forming a binary value of the discrete output, the common control voltage output being connected to a gain of the voltage regulation loop and defining the expected output voltage level. The system includes a plurality of second devices connected to the first device via the discrete output.

[0027] Another aspect of the invention relates to an aircraft comprising the system according to the invention, and in which the first device is a discrete output device of the DSO “Discrete Signal Output” type.

[0028] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0029] The figures are presented for information purposes only and in no way limit the invention. Figure 1 shows a block diagram of a DSO according to the prior art, Figure 2 shows a schematic representation of a DSO according to the prior art, Figure 3 shows a schematic representation of a pulse width modulated signal, Figure 4 shows a block diagram of a device according to the invention, Figure 5 shows a schematic representation of a system according to the invention, Figure 6 shows a schematic representation of a particular embodiment of a system according to the invention, Figure 7 shows a schematic representation of a method according to the invention. DETAILED DESCRIPTION

[0030] Unless otherwise specified, the same element appearing in different figures has a single reference.

[0031] Figure 4 shows a block diagram of at least part of a device according to the invention. The block diagram of Figure 4 shows a discrete output of the device 30 according to the invention.

[0032] The device 30 is an electronic device comprising a plurality of electronic components. The device 30 is for example a programmable logic circuit of the “FPGA” (Field-Programmable Gate Array) type, a wired electronic logic circuit, or a microcontroller.

[0033] The device 30 comprises a discrete multi-information output OUT_mult. An output is said to be “discrete” when it can take at least one finite value from among a plurality of predetermined values. The discrete output OUT_mult is said to be “multi-information” because it can take more than two different values. In other words, the discrete output OUT_mult provides more information than a binary output providing only two states. The discrete output OUT-mult can, for example, provide four different states.

[0034] The device 30 comprises a terminal supplied with constant voltage Vref, a CMD command of expected output voltage Vcmd, and a regulation loop. The regulation loop takes as input the constant voltage Vref, provides as output the output voltage Vout, and comprises a feedback gain G and a subtractor Diff. The feedback gain G receives as input the output voltage Vout and the expected output voltage Vcmd from the CMD command. The feedback gain G provides as output the voltage value to be subtracted from the constant voltage Vref to obtain the expected output voltage Vcmd as the actual output voltage Vout at the output OUT_mult.

[0035] Thanks to the invention, the output voltage Vout can take several voltage levels, depending on the voltage level Vcmd controlled by the CMD command. A device 20 connected to the device 30 can thus read on the output OUT_mult more than 2 different states, for example 4, 8 or 16 states, depending on the number of voltage values ​​that the CMD command can control and therefore that the output voltage Vout can take.

[0036] Figure 5 shows a schematic representation of a system according to the invention. Such a system comprises the device 30 and a device 20 connected by an electrical connection. The device 30 comprises several electronic components: resistors R1 to R9, a capacitor C5, switches K1 and K2, transistors Q1 and Q2, a diode D1 and a voltage reference U1. The regulation loop of the device 30 is formed by the voltage reference U1 and by the resistors R4, R3, R1, R2 and the RC circuit formed by the capacitor C5 and the resistor R5.

[0037] The internal components of the device 30 are supplied with electrical current via input terminals 31 and 32 at a voltage Vint, for example 12 Volts. This signal does not generate any voltage on the output OUT_mult, because it only serves to supply the internal components of the device 30.

[0038] The source of the output voltage is the voltage source Vtir supplying the device 20 connected to the device 30. This is achieved thanks to the presence of a pull-up resistor R10. A pull-up resistor is a conventional resistor whose position in a circuit gives it a pull-up function (also called "pull-up").

[0039] The discrete output OUT_mult is the output of a transistor Q1 of the device 30. The output of a transistor, when it is a field effect transistor as shown, is called the drain. When the transistor is a bipolar transistor, the output is called the collector. The device 30 is therefore "open drain" or "open collector", because the output of the transistor is connected to another device 20 and because its input (source or emitter) is connected to ground 0.

[0040] The CMD control of the device 30 is carried out by two voltage divider bridges: a first voltage divider bridge formed by the resistors R1 and R4 and a second voltage divider bridge formed by the resistors R2 and R4. Each voltage divider bridge is associated with a switch. The voltage divider bridge R1 and R4 is associated with the switch K1 while the voltage divider bridge R2 and R4 is associated with the switch K2. The switches K1 and K2 are used to control the expected output voltage Vcmd. The voltage divider bridges have a common output at point 32, making it possible to obtain several discrete levels of expected output voltage Vcmd. This control voltage Vcmd is at the input of the component U1.

[0041] It is possible to consider the state of each switch as the state of a bit in a sequence of bits corresponding to a sequence of bits in the OUT_mult output. Thus, when both switches K1 and K2 are open, the voltage Vcmd is worth a first voltage level, equivalent to the two bits in the sequence of output bits at 0, i.e. to an OUT_mult output at 00. When only K1 is closed, the sequence of bits in the OUT_mult output is worth, for example, 10. When only K2 is closed, the sequence of bits is worth, for example, 01. Finally, when both switches K1 and K2 are closed, the sequence of bits is worth 11. Each value in the sequence of bits corresponds to an output voltage value Vout. For example, 00 corresponds to 24 Volts, 01 corresponds to 12 Volts, 10 corresponds to 5 Volts, and 11 corresponds to 0 Volts. The device 20 will read the voltage Vout and deduce the value of the bits in the sequence of bits, thus deducing the state corresponding to each piece of information.For example, the first bit may correspond to one piece of information and the second bit to another. Alternatively, all four values ​​may. correspond to four values ​​of the same information. The intermediate voltage values ​​corresponding to 01 and 10 depend on the resistivity value of resistors R1, R2 and R4 via the voltage divider bridges they create and the value of the pull-up voltage Vtir. The voltage value corresponding to 00 (open switches) is for example Vtir, and the voltage value corresponding to 11 is for example close to 0 Volts depending on the value of resistors R1 and R2.

[0042] To add information levels, one or more other voltage divider bridges can be added to the voltage divider bridges on the left of the diagram in Figure 5. For example, it is possible to add at least one line connected to ground 0 and to the common output Vcmd, and to add to this line a switch K3 and another resistor. This makes it possible to add a bit to the sequence of bits on the output OUT_mult, and therefore to multiply by two the number of transmittable information. The important thing is then that the device 20 has a sensitivity such that it can differentiate the different voltage levels taken by Vout to obtain the corresponding information in bits.

[0043] The common output of the voltage divider bridges Vcmd is connected to a voltage reference U1 . The voltage reference U1 is for example of type TL431 , for example from Texas Instruments®. U1 is powered by Vint. The interest of U1 is that it has an internal constant voltage, thus forming the constant voltage Vref of the control loop. The interest of U1 is also that it realizes the difference function Diff of the control loop.

[0044] The programmable voltage reference U1 is used, in combination with other components, to perform the comparison Cmd between the reference voltage Vref and the difference between the control voltage Vcmd and the output voltage Vout, and generate an error to compensate for this difference. The feedback gain of the control loop is created by the resistor R4, which is preferably a set of resistors in series. This feedback gain is modified by the control according to the state of the switches K1 and K2, because the resistor R4 creates voltage divider bridges respectively with R1 and R2.

[0045] The comparison function is performed by the RC circuit composed of the resistor R5 and the capacitor C5 and by U1, associated with the resistor R6. This assembly makes it possible to generate the error, from the constant voltage Vref, between the control voltage Vcmd in reference to U1 and the voltage from the feedback gain at point 33, i.e. Vout.

[0046] The voltage reference 111 sees its operating point modified according to the state of switches K1 and K2 and according to the return of the output voltage OUT_mult.

[0047] The voltage reference LU controls transistor Q1. This control is preferably achieved via an intermediate transistor Q2. Indeed, directly controlling transistor Q1 would lead to a divergence.

[0048] The intermediate transistor Q2 is preferably of the same type as the output transistor Q1, for example a field effect transistor as shown in Figure 5, for example a MOSFET type transistor. The transistor Q2 makes it possible to "invert" the command from the programmable voltage regulator U1, to best control the output transistor Q1. Thus with a control voltage Vcmd set to 0V, LU will compensate to the maximum and therefore reach the voltage Vint on point 33. This voltage will control the intermediate transistor Q2 through the two bias resistors R7 and R8. The intermediate transistor Q2 will become conducting and put the drain of Q2 to ground. The gate of the output transistor Q1 will be connected to ground, and the output transistor Q1 will be in the open state and therefore the voltage OUT_mult will be at its maximum, i.e. Vtir. corresponding to a sequence of bits worth for example 00.Resistor R9 is a bias resistor for output transistor Q1.

[0049] The previous paragraph took the example of an expected output voltage (or "control") equal to Vtir. In such a case, and for an expected output voltage equal to the pull-up voltage Vtir, the output transistor Q1 behaves like an ON / OFF switch, i.e. its output is 0 Volts or Vtir. When the expected output voltage is an intermediate voltage determined by the voltage divider bridges formed by the resistors R1 and R2 respectively jointly with R4, the output voltage levels are predefined points of the linear operating regime of the output transistor Q1 (and the same for the intermediate transistor Q2), making it possible to obtain the desired voltage level at the drain of the output transistor Q1 and therefore at the output OUT_mult.

[0050] Finally, the device 30 comprises a protection diode D1.

[0051] Figure 6 shows a schematic representation of one embodiment of the system comprising device 30 and device 20. In this embodiment, resistor R4 performing the feedback gain function is implemented by three resistors R41, R42 and R43. In this embodiment, Vint has a value of 12 Volts, Vtir has a value of 28 Volts, and the pull-up resistor has a value of 20k Ohms. The first voltage divider bridge is implemented by switch K1 with resistor R4 (R41, R42 and R43) of 99k Ohms and a resistor R1 of 1k Ohms. The second voltage divider bridge is implemented by switch K2 with resistor R4 of 99k Ohms and resistor R2 of 22k Ohms.

[0052] With K1 and K2 open, Vcmd is obtained at its maximum, and with K1 and K2 closed, Vcmd is obtained at its minimum. The minimum and maximum values ​​of Vcmd are determined by the transmittance of the circuit, that is, by the different components of the device 10.

[0053] The invention also relates to a method for transmitting data between the first electronic device 30 with discrete output and the second remote device 20 connected to the first device 30 via the discrete output OUT_mult. Such a method according to the invention is shown in Figure 7 and comprises five steps 41 to 45, some of these steps being able to be repeated.

[0054] The method 40 according to the invention notably comprises two steps 42 and 43, carried out each time that the expected voltage level Vcmd by the CMD command is modified at a step 44.

[0055] The initialization of the method 40 comprises a first step 41 of defining, by the CMD command of the first device 30, an expected output voltage level Vcmd among the plurality of predefined voltage levels. This definition step is preferably carried out by the use of the switches K1 and K2 of the device 30 of Figure 5.

[0056] The method 40 then comprises a step 42 of regulating the output voltage level by the voltage regulation loop of the first device, as described previously. The regulation 42 notably comprises the modification of the voltage feedback gain, to compensate for the difference between the output voltage Vout and the expected output voltage Vcmd.

[0057] Then, a step 43 of control, by the regulation loop, of the output transistor Q1 of the first device 30 is carried out in the method 40, to present the expected output voltage level Vcmd between the input S of the output transistor Q1 and the output D of the output transistor Q1.

[0058] Then, the method 40 comprises a reading 44, by the second device 20, of the voltage level of the discrete output OUT_mult.

[0059] The method 40 further comprises a step 45 of modifying the expected voltage level Vcmd into a modified expected voltage level Vcmd' by the command of the first device 30, then steps 42, 43 and 44 are carried out again with the modified expected voltage level Vcmd', for a reading of the modified expected voltage level Vcmd' by the remote device 20.

Claims

CLAIMS

1. System comprising a first electronic device (30) with discrete output (OUT_mult) comprising an open drain output (D) and a second device (20) connected to the first device (30) via the discrete output (OUT_mult), the discrete output having a voltage level among a plurality of predefined voltage levels, the first device (30) comprising: - a command (CMD) defining an expected output voltage level among the plurality of predefined voltage levels, - a voltage regulation loop comprising a constant voltage (Vref) at the input, configured to compare the expected output voltage level (Vcmd) with the output voltage level (Vout) to obtain a voltage level difference, and to modify the voltage feedback gain of the voltage regulation loop to compensate for the difference between the output voltage (Vout) and the expected output voltage (Vcmd), - a field effect output transistor (Q1) comprising a gate (G), a drain (D) and a source (S), the input of the output transistor (Q1) being the source (S) connected to ground and the discrete output of the output transistor (Q1) connected to the second device (20) being the drain (D), the gate (G) of the output transistor being controlled by the voltage regulation loop to present the expected output voltage level (Vcmd) between the input (S) of the output transistor (Q1) and the output (D) of the output transistor (Q1), - an intermediate transistor (Q2), an output of the voltage regulation loop controlling a gate (G) of the intermediate transistor (Q2), the intermediate transistor (Q2) comprising a drain (D) controlling the gate (G) of the output transistor (Q1), - the second device (20) comprising at least one power supply (Vtir) and a resistor (R10) performing a pull-up resistor function.

2. System according to the preceding claim in which the regulation loop comprises a voltage reference (U1) providing the constant voltage.

3. System according to the preceding claim in which the voltage reference (U1) is a TL431 integrated circuit.

4. The system of one of claims 1 to 3 wherein each voltage level of the plurality of predefined voltage levels corresponds to a binary value of the discrete output.

5. System according to claim 4 wherein the control of the first device (30) is carried out by a plurality of voltage divider bridges having a common control voltage output (32), each voltage divider bridge being associated with a switch (K1, K2), each switch (K1, K2) defining the state of a bit of a sequence of bits forming a binary value of the discrete output (OUT_mult), the common control voltage output (32) being connected to a gain (G) of the voltage regulation loop and defining the expected output voltage level (Vcmd).

6. Method (4) for transmitting data in a system according to one of the preceding claims, between the first electronic device (30) with discrete output (OUT_mult) and the second device (20) connected to the first device (30) via the discrete output (OUT_mult), the discrete output having a voltage level among a plurality of predefined voltage levels, the method comprising: - definition (41), by the command (CMD) of the first device (30), of an expected output voltage level (Vcmd) among the plurality of predefined voltage levels, - regulation (42) of the output voltage level by the voltage regulation loop of the first device (30), the regulation loop comprising a constant voltage (Vref) at the input, the regulation (42) comprising the modification of a voltage feedback gain of the voltage regulation loop to compensate for the difference between the output voltage (Vout) and the expected output voltage (Vcmd) - control (43), by the regulation loop, of the output transistor (Q1) of the first device (30), to present the expected output voltage level (OUT_mult) between the input (S) of the output transistor (Q1) and the output (D) of the output transistor (Q1), the input (S) of the output transistor being connected to ground and the output of the output transistor being the discrete output (D, OUT_mult) connected to the second device (20), - reading (44), by the second device (20), of the voltage level of the discrete output.

7. Method (4) according to the preceding claim further comprising: - Modification (45) of the expected voltage level (Vcmd) by the control of the first device (30), then - regulation (42) of the output voltage level by the voltage regulation loop of the first device (30), - control (43), by the regulation loop, of the output transistor (Q1) of the first device (30), to present the modified expected output voltage level (OUT_mult).

8. Aircraft comprising the system according to one of claims 1 to 5, the first device (30) being a so-called DSO “Discrete Signal Output” device.

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