Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor which is capable of having improved deflection resistance.　This multilayer ceramic capacitor 1 includes an external electrode 40, and the external electrode 40 includes a base electrode layer 50, a conductive resin layer 60, and a plating layer 70. The film thickness of the conductive resin layer 60 on a ridge line part 10a of a multilayer body 10 is 0.8 μm to 8 μm inclusive. The conductive resin layer has a separated region P, which is separated from the multilayer body 10, in at least one extension part E. The separated region P is located in a region that extends from an end part of the conductive resin layer 60 on the multilayer body center side in the length direction L to the front of an end part of the base electrode layer 50 on the multilayer body center side in the length direction L, and the dimension of the separated region P in the length direction L is 5 μm or more.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] In recent years, multilayer ceramic capacitors have been required to be durable in harsh environments, such as those exposed to bending stress due to thermal expansion. To address this demand, a technique using a thermosetting conductive resin paste for the external electrodes of a multilayer ceramic capacitor has been known. Patent Document 1 (JP-A-2003-102666) describes this type of technique. Patent Document 1 describes a multilayer ceramic capacitor having external electrodes with a layered structure in which an electrode layer formed by applying a conductive paste by dipping and baking the paste, a conductive epoxy-based thermosetting resin layer, a nickel-plated layer, and a tin-based layer are sequentially laminated.

[0003] Japanese Patent Application Publication No. 11-162771

[0004] However, when a multilayer ceramic capacitor is mounted on a substrate, bending stress generated in the external electrodes is transmitted to the laminate, which may cause cracks or the like in the laminate, and therefore there is a need for improved bending resistance.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor that can improve resistance to bending.

[0006] The multilayer ceramic capacitor according to the present invention comprises a laminate including a plurality of laminated dielectric layers, the laminate having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and first and second end surfaces opposing each other in a length direction perpendicular to the height direction and the width direction; first internal electrode layers arranged on the plurality of dielectric layers and exposed at the first end surfaces; second internal electrode layers arranged on the plurality of dielectric layers and exposed at the second end surfaces; first external electrodes arranged on the first end surfaces; and second external electrodes arranged on the second end surfaces, wherein the first external electrodes and the second external electrodes each have a base electrode layer containing a metal component, a conductive resin layer arranged on the base electrode layer and containing a filler powder and a resin component, and a plating layer arranged on the conductive resin layer, the electrode and the second external electrode each have an extension portion that is arranged to extend to a part of the first main surface and a part of the second main surface, the laminate has ridge portions at a portion where the first end face and the first main surface intersect, a portion where the first end face and the second main surface intersect, a portion where the second end face and the first main surface intersect, and a portion where the second end face and the second main surface intersect, the conductive resin layer is arranged on the ridge portions of the laminate, and the film thickness of the conductive resin layer on the ridge portions is 0.8 μm or more and 8 μm or less, the conductive resin layer has a peeled region that is peeled off from the laminate in at least one of the extension portions, the peeled region being arranged in a region from the end of the conductive resin layer that is on the center side of the laminate in the length direction to just before the end of the base electrode layer that is on the center side of the laminate in the length direction, and the longitudinal dimension of the peeled region is 5 μm or more.

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor capable of improving the resistance to bending.

[0008] 1 is a perspective view of the appearance of a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown in FIG. 1; FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG. 2; FIG. 4 is a cross-sectional view taken along line IV-IV of the multilayer ceramic capacitor shown in FIG. 2; FIG. 5 is an enlarged view of a V portion of the multilayer ceramic capacitor shown in FIG. 2, and is a schematic diagram for explaining in detail the structure of a ridge line portion of the multilayer ceramic capacitor; FIG. 6 is a schematic diagram showing an example of the configuration of a multilayer ceramic capacitor with a double structure; FIG. 7 is a schematic diagram showing an example of the configuration of a multilayer ceramic capacitor with a triple structure; and FIG. 8 is a schematic diagram showing an example of the configuration of a multilayer ceramic capacitor with a quadruple structure.

[0009] <Embodiment> A multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to one embodiment of the present disclosure will now be described with reference to Figs. 1 to 4. Fig. 1 is an external perspective view of the multilayer ceramic capacitor 1 of this embodiment. Fig. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor 1 of Fig. 1. Fig. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor 1 of Fig. 2. Fig. 4 is a cross-sectional view taken along line IV-IV of the multilayer ceramic capacitor 1 of Fig. 2.

[0010] The multilayer ceramic capacitor 1 includes a laminate 10 and external electrodes 40 .

[0011] 1 to 4 show an XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T as the height direction of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in FIG. 2 is also referred to as the LT cross section. The cross section shown in FIG. 3 is also referred to as the WT cross section. The cross section shown in FIG. 4 is also referred to as the LW cross section.

[0012] As shown in Figures 1 to 4, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that face each other in a stacking direction T, a first side surface WS1 and a second side surface WS2 that face each other in a width direction W that is perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 that face each other in a length direction L that is perpendicular to the stacking direction T and the width direction W.

[0013] As shown in FIG. 1 , the laminate 10 has a substantially rectangular parallelepiped shape. The dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. The corners and ridges of the laminate 10 are preferably rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. Incidentally, unevenness or the like may be formed on part or all of the surfaces constituting the laminate 10.

[0014] The dimensions of the laminate 10 are not particularly limited, but if the dimension of the laminate 10 in the length direction L is defined as the L dimension, the L dimension is preferably 0.2 mm or more and 10 mm or less. If the dimension of the laminate 10 in the stacking direction T is defined as the T dimension, the T dimension is preferably 0.1 mm or more and 10 mm or less. If the dimension of the laminate 10 in the width direction W is defined as the W dimension, the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0015] As shown in Figures 2 and 3, the laminate 10 has an inner layer portion 11, and a first outer layer portion 12A as a first main surface side outer layer portion and a second outer layer portion 12B as a second outer layer portion arranged to sandwich the inner layer portion 11 in the stacking direction T.

[0016] The internal layer portion 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers. The internal layer portion 11 includes the internal electrode layer 30 located closest to the first main surface TS1 in the stacking direction T to the internal electrode layer 30 located closest to the second main surface TS2. In the internal layer portion 11, the multiple internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The internal layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0017] The dielectric layers 20 are made of a dielectric material, such as BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ The dielectric material may be a dielectric ceramic containing components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, etc., added to the above main components.

[0018] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 30 μm or less. The number of laminated dielectric layers 20 is preferably 10 or more and 1500 or less. Note that this number of dielectric layers 20 is the total number of the dielectric layers in the inner layer portion 11 and the dielectric layers in the first main surface side outer layer portion 12A and the second main surface side outer layer portion 12B.

[0019] The multiple internal electrode layers 30 include first internal electrode layers 31 as multiple first internal conductor layers and second internal electrode layers 32 as multiple second internal conductor layers. The multiple first internal electrode layers 31 are arranged on the multiple dielectric layers 20. The multiple second internal electrode layers 32 are arranged on the multiple dielectric layers 20. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10, with the dielectric layers 20 interposed between them. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layers 20 therebetween.

[0020] The first internal electrode layer 31 has a first opposing portion 31A opposing the second internal electrode layer 32, and a first lead portion 31B led from the first opposing portion 31A to the first end face LS1. The first lead portion 31B is exposed at the first end face LS1.

[0021] The second internal electrode layer 32 has a second opposing portion 32A opposing the first internal electrode layer 31 and a second lead portion 32B led from the second opposing portion 32A to the second end face LS2. The second lead portion 32B is exposed at the second end face LS2.

[0022] In this embodiment, the first opposing portion 31A and the second opposing portion 32A face each other with the dielectric layer 20 interposed therebetween, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0023] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle. The shapes of the first draw-out portion 31B and the second draw-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle.

[0024] The dimension in the width direction W of the first opposing portion 31A and the dimension in the width direction W of the first lead portion 31B may be the same dimension, or one of the dimensions may be smaller. The dimension in the width direction W of the second opposing portion 32A and the dimension in the width direction W of the second lead portion 32B may be the same dimension, or one of the dimensions may be smaller.

[0025] The first internal electrode layer 31 and the second internal electrode layer 32 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0026] The thickness of each of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably, for example, about 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 10 or more and 1500 or less.

[0027] The first main surface side outer layer portion 12A is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion 12A is an assembly of a plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layers 20 used in the first main surface side outer layer portion 12A may be the same as the dielectric layers 20 used in the internal layer portion 11, or may be dielectric layers made of a different material.

[0028] The second main surface side outer layer portion 12B is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 12B is an assembly of a plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the second main surface side outer layer portion 12B may be the same as the dielectric layers 20 used in the internal layer portion 11, or may be dielectric layers made of a different material.

[0029] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is a portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as a part of the inner layer portion 11. Fig. 4 shows the range of the counter electrode portion 11E in the width direction W and the length direction L. The counter electrode portion 11E is also called the effective portion of the capacitor.

[0030] The laminate 10 has side surface outer layer portions. The side surface outer layer portions include a first side surface outer layer portion WG1 and a second side surface outer layer portion WG2. The first side surface outer layer portion WG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first side surface WS1. The second side surface outer layer portion WG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second side surface WS2. Figures 3 and 4 show the ranges in the width direction W of the first side surface outer layer portion WG1 and the second side surface outer layer portion WG2. The side surface outer layer portions are also referred to as W gaps or side gaps.

[0031] The laminate 10 has an end surface side outer layer portion. The end surface side outer layer portion includes a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2. The first end surface side outer layer portion LG1 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the first end surface LS1. The second end surface side outer layer portion LG2 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the second end surface LS2. Figures 2 and 4 show the ranges in the length direction L of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2. The end surface side outer layer portion is also referred to as an L gap or end gap.

[0032] The external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side and a second external electrode 40B arranged on the second end face LS2 side.

[0033] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A is disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2. In this embodiment, the first external electrode 40A is formed to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0034] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B is disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2. In this embodiment, the second external electrode 40B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0035] As described above, in the laminate 10, capacitance is formed by the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 facing each other via the dielectric layer 20. Therefore, the characteristics of a capacitor are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0036] The first external electrode 40A has a first base electrode layer 50A containing a metal component, a first conductive resin layer 60A disposed on the first base electrode layer 50A, and a first plating layer 70A disposed on the first conductive resin layer 60A. The first plating layer 70A has a first Ni plating layer 71A as a lower plating layer and a first Sn plating layer 72A as an upper plating layer.

[0037] The second external electrode 40B has a second base electrode layer 50B containing a metal component, a second conductive resin layer 60B disposed on the second base electrode layer 50B, and a second plating layer 70B disposed on the second conductive resin layer 60B. The second plating layer 70B has a second Ni plating layer 71B as a lower plating layer and a second Sn plating layer 72B as an upper plating layer.

[0038] Here, the layers constituting the first external electrode 40A and the second external electrode 40B have the same basic configuration. The first external electrode 40A and the second external electrode 40B are generally symmetrical with respect to a cross section LW at the center of the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, when there is no need to distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrodes 40. When there is no need to distinguish between the first base electrode layer 50A and the second base electrode layer 50B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the base electrode layer 50. Furthermore, when it is not necessary to particularly distinguish between the first conductive resin layer 60A and the second conductive resin layer 60B, the first conductive resin layer 60A and the second conductive resin layer 60B may be collectively referred to as the conductive resin layer 60. Furthermore, when it is not necessary to particularly distinguish between the first plating layer 70A and the second plating layer 70B, the first plating layer 70A and the second plating layer 70B may be collectively referred to as the plating layer 70. Furthermore, when it is not necessary to particularly distinguish between the first Ni plating layer 71A and the second Ni plating layer 71B, the first Ni plating layer 71A and the second Ni plating layer 71B may be collectively referred to as the Ni plating layer 71. Furthermore, when it is not necessary to particularly distinguish between the first Sn plating layer 72A and the second Sn plating layer 72B, the first Sn plating layer 72A and the second Sn plating layer 72B may be collectively referred to as the Sn plating layer 72. When it is not necessary to particularly distinguish between the first main surface TS1 and the second main surface TS2, the first main surface TS1 and the second main surface TS2 may be collectively referred to as the main surface TS. When it is not necessary to particularly distinguish between the first side surface WS1 and the second side surface WS2, the first side surface WS1 and the second side surface WS2 may be collectively referred to as the side surface WS. When it is not necessary to particularly distinguish between the first end surface LS1 and the second end surface LS2, the first end surface LS1 and the second end surface LS2 may be collectively referred to as the end surface LS.

[0039] The base electrode layer 50 includes a first base electrode layer 50A and a second base electrode layer 50B.

[0040] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first internal electrode layer 31. In this embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0041] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is connected to the second internal electrode layer 32. In this embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0042] The first base electrode layer 50A and the second base electrode layer 50B of this embodiment are baked layers. The baked layers preferably contain a metal component and either a glass component or a ceramic component, or both. This improves the adhesion between the laminate 10 and the base electrode layers. The metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. The presence of a glass component can help sinter the metal component in the base electrode layer and promote sintering. The ceramic component may be the same type of ceramic material as that of the dielectric layer 20, or a different type of ceramic material. The ceramic component may be, for example, BaTiO ３ , CaTiO ３ , (Ba,Ca)TiO ３ , SrTiO ３ , CaZrO ３ It includes at least one selected from the following:

[0043] The baked layer is formed by, for example, applying a conductive paste containing glass and metal to the laminate and baking it. The baked layer may be formed by simultaneously firing a laminated chip having internal electrodes and a dielectric layer with a conductive paste applied to the laminated chip, or by simultaneously firing a laminated chip having internal electrodes and a dielectric layer to obtain a laminate and then applying a conductive paste to the laminate and baking it. When simultaneously firing a laminated chip having internal electrodes and a dielectric layer with a conductive paste applied to the laminated chip, it is preferable to form the baked layer by baking a layer containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may be formed in multiple layers.

[0044] The longitudinal thickness of the first base electrode layer 50A located on the first end surface LS1 is preferably, for example, approximately 2 μm or more and 220 μm or less at the center of the first base electrode layer 50A in the stacking direction T and width direction W.

[0045] The longitudinal thickness of the second base electrode layer 50B located on the second end surface LS2 is preferably, for example, approximately 2 μm or more and 220 μm or less at the center of the second base electrode layer 50B in the stacking direction T and width direction W.

[0046] When the first base electrode layer 50A is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness in the stacking direction of the first base electrode layer 50A provided on this portion is preferably, for example, approximately 4 μm or more and 40 μm or less at the center in the length direction L and width direction W of the first base electrode layer 50A provided on this portion.

[0047] When the first base electrode layer 50A is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the widthwise thickness of the first base electrode layer 50A provided on this portion is, for example, approximately 4 μm or more and 40 μm or less at the center of the length direction L and stacking direction T of the first base electrode layer 50A provided on this portion.

[0048] When the second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness in the stacking direction of the second base electrode layer 50B provided on this portion is preferably, for example, approximately 4 μm or more and 40 μm or less at the center in the length direction L and width direction W of the second base electrode layer 50B provided on this portion.

[0049] When the second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the widthwise thickness of the second base electrode layer 50B provided on this portion is, for example, approximately 4 μm or more and 40 μm or less at the center of the length direction L and stacking direction T of the second base electrode layer 50B provided on this portion.

[0050] The external electrode 40 has a conductive resin layer 60 that is disposed on the base electrode layer 50 and contains a resin component and a metal component.

[0051] The conductive resin layer 60 includes a first conductive resin layer 60A and a second conductive resin layer 60B.

[0052] The first conductive resin layer 60A is disposed so as to cover the first base electrode layer 50A. In this embodiment, the first conductive resin layer 60A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. The second conductive resin layer 60B is disposed so as to cover the second base electrode layer 50B. In this embodiment, the second conductive resin layer 60B is formed to extend from the second end face LS2 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. Here, the dimension in the length direction L on the first main surface TS1 and the second main surface TS2 of the first conductive resin layer 60A is longer than the dimension in the length direction L on the first main surface TS1 and the second main surface TS2 of the first base electrode layer 50A. Also, the dimension in the length direction L on the first main surface TS1 and the second main surface TS2 of the second conductive resin layer 60B is longer than the dimension in the length direction L on the first main surface TS1 and the second main surface TS2 of the second base electrode layer 50B.

[0053] The longitudinal thickness of the first conductive resin layer 60A located on the first end face LS1 side is preferably, for example, approximately 5 μm or more and 200 μm or less at the center of the stacking direction T and width direction W of the first conductive resin layer 60A.

[0054] The longitudinal thickness of the second conductive resin layer 60B located on the second end face LS2 side is preferably, for example, approximately 5 μm or more and 200 μm or less at the center of the stacking direction T and width direction W of the second conductive resin layer 60B.

[0055] When the first conductive resin layer 60A is provided on a portion of the first main surface TS1 side and a portion of the second main surface TS2 side, the thickness in the stacking direction of the first conductive resin layer 60A provided on this portion is preferably, for example, approximately 5 μm or more and 200 μm or less at the center in the length direction L and width direction W of the first conductive resin layer 60A provided on this portion.

[0056] When the first conductive resin layer 60A is provided on a portion of the first side surface WS1 side and a portion of the second side surface WS2 side, the widthwise thickness of the first conductive resin layer 60A provided on this portion is preferably, for example, approximately 5 μm or more and 200 μm or less at the center in the length direction L and stacking direction T of the first conductive resin layer 60A provided on this portion.

[0057] When the second conductive resin layer 60B is provided on a portion of the first main surface TS1 side and a portion of the second main surface TS2 side, the thickness in the stacking direction of the second conductive resin layer 60B provided on this portion is preferably, for example, approximately 5 μm or more and 200 μm or less at the center in the length direction L and width direction W of the second conductive resin layer 60B provided on this portion.

[0058] When the second conductive resin layer 60B is provided on a portion of the first side surface WS1 side and a portion of the second side surface WS2 side, the widthwise thickness of the second conductive resin layer 60B provided on this portion is preferably, for example, approximately 5 μm or more and 200 μm or less at the center in the length direction L and stacking direction T of the second conductive resin layer 60B provided on this portion.

[0059] The conductive resin layer 60 is disposed on the base electrode layer 50. Then, the plating layer 70 is disposed so as to cover the conductive resin layer 60. The plating layer 70 has a Ni plating layer 71 and a Sn plating layer 72.

[0060] The conductive resin layer 60 has a resin portion as a resin component and conductive filler as filler powder dispersed in the resin portion.

[0061] The resin portion of the conductive resin layer 60 may contain at least one selected from various known thermosetting resins, such as epoxy resin, phenoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin is one of the most suitable resins, due to its excellent heat resistance, moisture resistance, and adhesion. Furthermore, the resin portion of the conductive resin layer 60 preferably contains a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent for the epoxy resin may be any of various known compounds, such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0062] Because the conductive resin layer 60 contains such a resin portion, it is more flexible than the base electrode layer 50, which is made of, for example, a plating film or a fired product of a metal component and a glass component. Therefore, even when the multilayer ceramic capacitor 1 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer 60 functions as a buffer layer. Therefore, the conductive resin layer 60 suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0063] The conductive fillers are dispersed in a substantially uniform distribution within the resin portion, and are primarily responsible for the electrical conductivity of the conductive resin layer 60. Specifically, when multiple conductive fillers come into contact with each other, a conductive path is formed within the conductive resin layer 60, providing electrical continuity between the base electrode layer 50 and the plating layer 70.

[0064] The metal constituting the conductive filler may be Ag alone, an alloy containing Ag, or a metal powder with Ag coated on its surface. Ag has the lowest resistivity of all metals, making it suitable as an electrode material. Furthermore, since Ag is a noble metal, it is resistant to oxidation and highly weather-resistant. Therefore, Ag metal powder is suitable as a conductive filler. Furthermore, when using a metal powder with Ag coated on its surface, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder containing any of these metal powders.

[0065] Furthermore, the conductive filler may be Cu or Ni that has been subjected to an oxidation prevention treatment. The conductive filler may also be a metal powder in which the surface of the metal powder is coated with Sn, Ni, or Cu. When using a metal powder in which the surface of the metal powder is coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof. It is more preferable that the conductive filler has a Cu particle as a core. It is also more preferable that at least a portion of the surface of the Cu particle is coated with a Cu-Ag alloy of Cu and Ag. At least a portion of the surface of the Cu particle may be coated with Ag. This improves affinity with Ni plating and improves electrical properties.

[0066] The shape of the conductive filler is not particularly limited. The conductive filler may be spherical, flat, or the like. It is preferable to use a mixture of spherical metal powder and flat metal powder. In other words, the conductive filler as the filler powder includes flat powder or spherical powder.

[0067] The conductive filler may have an average particle size of, for example, 0.3 μm or more and 10 μm or less.

[0068] The average particle size of the conductive filler contained in the conductive resin layer 60 is measured by calculation using a laser diffraction particle size measurement method based on ISO 13320, regardless of the shape of the conductive filler.

[0069] The plating layer 70 includes a first plating layer 70A and a second plating layer 70B.

[0070] The first plating layer 70A is disposed so as to cover the first conductive resin layer 60A. In this embodiment, the first plating layer 70A is disposed so as to extend from the first end surface LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0071] The second plating layer 70B is disposed so as to cover the second conductive resin layer 60B. In this embodiment, the second plating layer 70B is disposed so as to extend from the first end surface LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0072] The plating layer 70 preferably has a two-layer structure of a Ni plating layer 71 and a Sn plating layer 72. A first Sn plating layer 72A is preferably disposed on the first Ni plating layer 71A, and a second Sn plating layer 72B is preferably disposed on the second Ni plating layer 71B. The Ni plating layer 71 prevents the base electrode layer 50 and the conductive resin layer 60 from being eroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer 72 improves the wettability of the solder when mounting the multilayer ceramic capacitor 1, thereby facilitating the mounting of the multilayer ceramic capacitor 1.

[0073] The thickness of each of the first Ni plating layer 71A and the first Sn plating layer 72A is preferably 5 μm or more and 15 μm or less.

[0074] The thickness of each of the second Ni plating layer 71B and the second Sn plating layer 72B is preferably 5 μm or more and 15 μm or less.

[0075] FIG. 5 is an enlarged view of the V portion of the multilayer ceramic capacitor 1 shown in FIG. 2, and is a schematic diagram for explaining in detail the structure of a ridge line portion 10a of the multilayer ceramic capacitor 1, which will be described later.

[0076] Here, the four ridge portions 10a1 to 10a4 of the laminate 10 shown in Figure 2 have the same basic configuration, and the four extension portions E1 to E4 of the external electrode 40 also have the same basic configuration. Therefore, the four regions will be explained using Figure 5 as a representative diagram. As mentioned above, the first external electrode 40A and the second external electrode 40B have the same basic configuration, and therefore in Figure 5 they are collectively shown as the external electrode 40. The same applies to the other layers that make up the first external electrode 40A and the second external electrode 40B.

[0077] 5 , the external electrode 40 has a base electrode layer 50, a conductive resin layer 60 disposed on the base electrode layer 50, and a plating layer 70 disposed on the conductive resin layer 60. The external electrode 40 has an extension portion E that extends to a part of the main surface TS. The laminate 10 has a ridge portion 10a at the intersection of the end surface LS and the main surface TS. The conductive resin layer 60 is disposed on the ridge portion 10a of the laminate 10.

[0078] The first external electrode 40A and the second external electrode 40B each have an extension E that is arranged to extend to a part of the first main surface TS1 and a part of the second main surface TS2. In this embodiment, the first external electrode 40A and the second external electrode 40B each further have an extension E that is arranged to extend to a part of the first side surface WS1 and a part of the second side surface WS2.

[0079] For example, the extension portion E of this embodiment has a first extension portion E1, a second extension portion E2, a third extension portion E3, a fourth extension portion E4, a fifth extension portion E5, a sixth extension portion E6, a seventh extension portion E7, and an eighth extension portion E8, as shown in Figures 2, 4, and 5.

[0080] The first extension E1 is a portion of the first external electrode 40A that extends to a part of the first main surface TS1 as shown in Figures 2 and 5. The second extension E2 is a portion of the first external electrode 40A that extends to a part of the second main surface TS2 as shown in Figures 2 and 5.

[0081] The third extension E3 is a portion of the second external electrode 40B that is disposed extending over a portion of the first main surface TS1, as shown in Figures 2 and 5. The fourth extension E4 is a portion of the second external electrode 40B that is disposed extending over a portion of the second main surface TS2, as shown in Figures 2 and 5.

[0082] The fifth extension E5 is a portion of the first external electrode 40A that extends to a part of the first side surface WS1 as shown in Fig. 4. The sixth extension E6 is a portion of the first external electrode 40A that extends to a part of the second side surface WS2 as shown in Fig. 4.

[0083] The seventh extension E7 is a portion of the second external electrode 40B that extends to a portion of the first side surface WS1 as shown in Fig. 4. The eighth extension E8 is a portion of the second external electrode 40B that extends to a portion of the second side surface WS2 as shown in Fig. 4.

[0084] The configuration of the extension portion E is not limited to this. For example, it is sufficient that the extension portion E is disposed on at least the first main surface TS1 and the second main surface TS2 of the first external electrode 40A and the second external electrode 40B.

[0085] The laminate 10 has ridge portions 10a at the intersections of the first end face LS1 and the first main face TS1, the intersections of the first end face LS1 and the second main face TS2, the intersections of the second end face LS2 and the first main face TS1, and the intersections of the second end face LS2 and the second main face TS2. In this embodiment, the laminate 10 also has ridge portions 10a at the intersections of the first end face LS1 and the first side face WS1, the intersections of the first end face LS1 and the second side face WS2, the intersections of the second end face LS2 and the first side face WS1, and the intersections of the second end face LS2 and the second side face WS2.

[0086] For example, the ridge portion 10a in this embodiment has a first ridge portion 10a1, a second ridge portion 10a2, a third ridge portion 10a3, a fourth ridge portion 10a4, a fifth ridge portion 10a5, a sixth ridge portion 10a6, a seventh ridge portion 10a7, and an eighth ridge portion 10a8.

[0087] 2 and 5, the first ridge portion 10a1 is the portion where the first end face LS1 and the first main surface TS1 intersect. The second ridge portion 10a2 is the portion where the first end face LS1 and the second main surface TS2 intersect.

[0088] 2 and 5, the third ridge portion 10a3 is the portion where the second end face LS2 and the first main surface TS1 intersect. The fourth ridge portion 10a4 is the portion where the second end face LS2 and the second main surface TS2 intersect.

[0089] As shown in Fig. 4, the fifth ridge 10a5 is an intersection between the first end face LS1 and the first side face WS1. As shown in Fig. 4, the sixth ridge 10a6 is an intersection between the first end face LS1 and the second side face WS2.

[0090] The seventh ridge portion 10a7 is the intersection of the second end face LS2 and the first side face WS1, as shown in Fig. 4. The eighth ridge portion 10a8 is the intersection of the second end face LS2 and the second side face WS2, as shown in Fig. 4.

[0091] A conductive resin layer 60 is disposed on the ridge line portion 10a of the laminate 10 via a base electrode layer 50. That is, the conductive resin layer 60 is disposed on the ridge line portion 10a of the laminate 10 so as to be sandwiched between the base electrode layer 50 and the plating layer 70. The thickness of the conductive resin layer 60 at the ridge line portion 10a of the laminate 10 is thinner than the thickness of the conductive resin layer 60 in other portions, i.e., the thickness of the conductive resin layer 60 at the end surface LS of the laminate 10, the main surface TS of the laminate 10, and the side surface WS of the laminate. The film thickness t of the conductive resin layer 60 on the ridge line portion 10a is preferably 0.8 μm or more and 8 μm or less.

[0092] When the plating layer 70 is disposed across the ridge line portion 10a, deflection occurring on the main surface TS or the side surface WS of the external electrode 40 may propagate to the end surface LS of the laminate 10. However, when the conductive resin layer 60 is disposed on the ridge line portion 10a, the flexibility of the conductive resin layer 60 can prevent deflection occurring on the main surface TS or the side surface WS of the external electrode 40 from propagating to the end surface LS of the laminate 10.

[0093] As shown in Figures 2 and 5, a first conductive resin layer 60A is disposed on the first ridge line portion 10a1 of the laminate 10 according to this embodiment. As shown in Figures 2 and 5, a first conductive resin layer 60A is disposed on the second ridge line portion 10a2 of the laminate 10 according to this embodiment. As shown in Figures 2 and 5, a second conductive resin layer 60B is disposed on the third ridge line portion 10a3 of the laminate 10 according to this embodiment. As shown in Figures 2 and 5, a second conductive resin layer 60B is disposed on the fourth ridge line portion 10a4 of the laminate 10 according to this embodiment.

[0094] As shown in Fig. 4, a first conductive resin layer 60A is disposed on the fifth ridge line portion 10a5 of the laminate 10 according to this embodiment. As shown in Fig. 4, a first conductive resin layer 60A is disposed on the sixth ridge line portion 10a6 of the laminate 10 according to this embodiment. As shown in Fig. 4, a second conductive resin layer 60B is disposed on the seventh ridge line portion 10a7 of the laminate 10 according to this embodiment. As shown in Fig. 4, a second conductive resin layer 60B is disposed on the eighth ridge line portion 10a8 of the laminate 10 according to this embodiment.

[0095] The conductive resin layer 60 has a peeled region P peeled from the laminate 10 in at least one extension E. The peeled region P is arranged in a region from the ends 60Aa, 60Ba of the conductive resin layer 60 on the central side of the laminate in the length direction L to just before the ends 50Aa, 50Ba of the underlying electrode layer 50 on the central side of the laminate in the length direction L. In other words, the peeled region P does not reach the ends 50Aa, 50Ba of the underlying electrode layer 50 on the central side of the laminate in the length direction L. The dimension of the peeled region P in the length direction L is preferably 5 μm or more. Note that, although a particularly high effect can be obtained by arranging the peeled region P on the mounting surface side, this is not limited thereto.

[0096] At least one of the first conductive resin layer 60A and the second conductive resin layer 60B has a peeled region P peeled off from the laminate 10 on either the first main surface TS1 or the second main surface TS2 that contacts the ridge portion 10a.

[0097] 2 and 5, the first conductive resin layer 60A according to this embodiment has a first peeled region P1 peeled from the laminate 10 on the first main surface TS1 that contacts the first ridge portion 10a1. The first conductive resin layer 60A according to this embodiment has a second peeled region P2 peeled from the laminate 10 on the second main surface TS2 that contacts the second ridge portion 10a2.

[0098] 2 and 5, the second conductive resin layer 60B according to this embodiment has a third peeled region P3 peeled from the laminate 10 on the first main surface TS1 in contact with the third ridge portion 10a3. The second conductive resin layer 60B according to this embodiment has a fourth peeled region P4 peeled from the laminate 10 on the second main surface TS2 in contact with the fourth ridge portion 10a4.

[0099] For example, as shown in Fig. 4, the first conductive resin layer 60A according to this embodiment has a fifth peeled region P5 peeled from the laminate 10 on the first side surface WS1 that contacts the fifth ridge portion 10a5. The first conductive resin layer 60A according to this embodiment has a sixth peeled region P6 peeled from the laminate 10 on the second side surface WS2 that contacts the sixth ridge portion 10a6.

[0100] 4, the second conductive resin layer 60B according to this embodiment has a seventh peeled region P7 on the first main surface TS1 that contacts the seventh ridge portion 10a7 and that is peeled from the laminate 10. The second conductive resin layer 60B according to this embodiment has an eighth peeled region P8 on the second main surface TS2 that contacts the eighth ridge portion 10a8 and that is peeled from the laminate 10.

[0101] That is, the peeling region P according to this embodiment includes a first peeling region P1, a second peeling region P2, a third peeling region P3, a fourth peeling region P4, a fifth peeling region P5, a sixth peeling region P6, a seventh peeling region P7, and an eighth peeling region P8. The configuration of the peeling region P is not limited to this. The peeling region P does not have to be disposed in all of the extension portions E where the first conductive resin layer 60A and the second conductive resin layer 60B extend onto the main surface TS and the side surface WS. For example, the peeling region P may be disposed only in the extension portions E extending onto the main surface TS.

[0102] For example, the peeling region P may be arranged in at least one of the first extension portion E1 on the first main surface TS1 side of the first external electrode 40A and the second extension portion E2 on the second main surface TS2 side, and in at least one of the third extension portion E3 on the first main surface TS1 side of the second external electrode 40B and the fourth extension portion E4 on the second main surface TS2 side.

[0103] In addition, the peeled region P may be arranged in the first extension portion E1 on the first main surface TS1 side of the first external electrode 40A and the third extension portion E3 on the first main surface TS1 side of the second external electrode 40B, or in the second extension portion E2 on the second main surface TS2 side of the first external electrode 40A and the fourth extension portion E4 on the second main surface TS2 side of the second external electrode 40B.

[0104] In addition, the peeled region P may be arranged in the first extension portion E1 on the first main surface TS1 side and the second extension portion E2 on the second main surface TS2 side of the first external electrode 40A, or in the third extension portion E3 on the first main surface TS1 side and the fourth extension portion E4 on the second main surface TS2 side of the second external electrode 40B.

[0105] In addition, the peeling region P may be arranged in the first extension portion E1 on the first main surface TS1 side of the first external electrode 40A and the second extension portion E2 on the second main surface TS2 side, and in the third extension portion E3 on the first main surface TS1 side of the second external electrode 40B and the fourth extension portion E4 on the second main surface TS2 side.

[0106] The thickness of the conductive resin layer on the ridge line 10a of the laminate 10, where the main surface TS and the end surface LS of the laminate 10 on which the extensions E having the peeled regions P are arranged, is preferably 0.8 μm or more and 8 μm or less. In this embodiment, all of the extensions E have the peeled regions P.

[0107] In this embodiment, the thickness of the first conductive resin layer 60A on the first ridge line portion 10a1 is 0.8 μm or more and 8 μm or less, and the thickness of the first conductive resin layer 60A on the second ridge line portion 10a2 is 0.8 μm or more and 8 μm or less.

[0108] In this embodiment, the thickness of the second conductive resin layer 60B on the third ridge portion 10a3 is 0.8 μm or more and 8 μm or less, and the thickness of the second conductive resin layer 60B on the fourth ridge portion 10a4 is 0.8 μm or more and 8 μm or less.

[0109] In this embodiment, the thickness of the first conductive resin layer 60A on the fifth ridge line portion 10a5 is 0.8 μm or more and 8 μm or less, and the thickness of the first conductive resin layer 60A on the sixth ridge line portion 10a6 is 0.8 μm or more and 8 μm or less.

[0110] In this embodiment, the thickness of the second conductive resin layer 60B on the seventh ridge line portion 10a7 is 0.8 μm or more and 8 μm or less, and the thickness of the second conductive resin layer 60B on the eighth ridge line portion 10a8 is 0.8 μm or more and 8 μm or less.

[0111] <Measurement of Film Thickness of Conductive Resin Layer on Ridge Line Portion> Hereinafter, measurement of the film thickness of the conductive resin layer 60 on the ridge line portion 10 a will be described with reference to Fig. 5. The film thickness of the conductive resin layer 60 on the ridge line portion 10 a is measured based on observation using a SEM (scanning electron microscope).

[0112] SEM observation for measuring the thickness of the conductive resin layer 60 on the ridge portion 10a is performed on the LT cross section approximately parallel to the first side surface WS1 and the second side surface WS2 at approximately the center position in the width direction W of the laminate 10.

[0113] First, the laminate 10 of the multilayer ceramic capacitor 1 is broken with nippers at approximately the center in the width direction W so that the LT cross section of the laminate 10 is exposed.

[0114] The fracture surface is then heat-treated at 1000°C for 30 minutes to facilitate observation of the conductive resin layer. After the treatment, the measurement area is photographed at a high magnification of 20,000 times using an SEM. The outer edge of the conductive resin layer is traced using analysis software to measure the thickness.

[0115] 5, a bisector is drawn so as to bisect the angle formed by the end face LS and the main surface TS at an angle θ. In this embodiment, since the angle formed by the end face LS and the main surface TS is approximately 90°, a bisector is drawn so as to bisect the angle at an angle θ = 45°. The thickness of the conductive resin layer 60 is measured in the direction of the drawn bisector.

[0116] The thickness of the conductive resin layer 60 on the ridge portion 10a is measured at four locations: the ridge portion 10a1 where the first end face LS1 and the first main surface TS1 intersect; the ridge portion 10a2 where the first end face LS1 and the second main surface TS2 intersect; the ridge portion 10a3 where the second end face LS2 and the first main surface TS1 intersect; and the ridge portion 10a4 where the second end face LS2 and the second main surface TS2 intersect. The average value of the measured thicknesses is defined as the film thickness t of the conductive resin layer 60 on the ridge portion 10a in the present disclosure.

[0117] The peeled region P is disposed in a region from the end (60Aa, 60Ba) of the conductive resin layer 60 on the side of the center of the laminate in the length direction L to just before the end (50Aa, 50Ba) of the base electrode layer 50 on the side of the center of the laminate in the length direction L. In other words, the peeled region P does not reach the end (50Aa, 50Ba) of the base electrode layer 50 on the side of the center of the laminate in the length direction L.

[0118] The first peeling region P1 in this embodiment is positioned in the longitudinal direction L between the end 60Aa of the first conductive resin layer 60A on the central side of the laminate in the longitudinal direction L and just before reaching the end 50Aa of the first underlying electrode layer 50A on the central side of the laminate in the longitudinal direction L.

[0119] The second peeling region P2 in this embodiment is positioned in the longitudinal direction L between the end 60Aa of the first conductive resin layer 60A on the central side of the laminate in the longitudinal direction L and just before reaching the end 50Aa of the first underlying electrode layer 50A on the central side of the laminate in the longitudinal direction L.

[0120] The third peeling region P3 in this embodiment is positioned in the longitudinal direction L between the end 60Ba of the second conductive resin layer 60B on the central side of the laminate in the longitudinal direction L and just before reaching the end 50Ba of the second base electrode layer 50B on the central side of the laminate in the longitudinal direction L.

[0121] The fourth peeling region P4 in this embodiment is positioned in the longitudinal direction L between the end 60Ba of the second conductive resin layer 60B on the central side of the laminate in the longitudinal direction L and just before reaching the end 50Ba of the second base electrode layer 50B on the central side of the laminate in the longitudinal direction L.

[0122] The fifth peeling region P5 in this embodiment is positioned in the longitudinal direction L between the end 60Aa of the first conductive resin layer 60A on the central side of the laminate in the longitudinal direction L and just before reaching the end 50Aa of the first underlying electrode layer 50A on the central side of the laminate in the longitudinal direction L.

[0123] The sixth peeling region P6 in this embodiment is positioned in the longitudinal direction L between the end 60Aa of the first conductive resin layer 60A on the central side of the laminate in the longitudinal direction L and just before reaching the end 50Aa of the first underlying electrode layer 50A on the central side of the laminate in the longitudinal direction L.

[0124] The seventh peeling region P7 in this embodiment is positioned in the longitudinal direction L between the end 60Ba of the second conductive resin layer 60B on the central side of the laminate in the longitudinal direction L and just before reaching the end 50Ba of the second base electrode layer 50B on the central side of the laminate in the longitudinal direction L.

[0125] The eighth peeling region P8 in this embodiment is positioned in the longitudinal direction L between the end 60Ba of the second conductive resin layer 60B on the central side of the laminate in the longitudinal direction L and just before reaching the end 50Ba of the second base electrode layer 50B on the central side of the laminate in the longitudinal direction L.

[0126] An inner end 50Aa of the first base electrode layer 50A in the longitudinal direction L of the laminate 10 is positioned further outward in the longitudinal direction L than any of the first peeled region P1, the second peeled region P2, the fifth peeled region P5, and the sixth peeled region P6. In other words, none of the first peeled region P1, the second peeled region P2, the fifth peeled region P5, and the sixth peeled region P6 reaches the inner end of the laminate 10 of the first base electrode layer 50A in the longitudinal direction L.

[0127] The inner end 50Ba of the second base electrode layer 50B in the longitudinal direction L of the laminate 10 is positioned further outward in the longitudinal direction L than any of the third peeling region P3, the fourth peeling region P4, the seventh peeling region P7, and the eighth peeling region P8 of the laminate 10. In other words, none of the third peeling region P3, the fourth peeling region P4, the seventh peeling region P7, and the eighth peeling region P8 reaches the inner end of the laminate 10 of the second base electrode layer 50B in the longitudinal direction L.

[0128] The dimension d in the length direction L of the peeled region P is 5 μm or more. The dimension d1 in the length direction L of the first peeled region P1 according to this embodiment is 5 μm or more. The dimension d2 in the length direction L of the second peeled region P2 according to this embodiment is 5 μm or more.

[0129] The dimension d3 of the third peeling region P3 in the length direction L according to this embodiment is 5 μm or more. The dimension d4 of the fourth peeling region P4 in the length direction L according to this embodiment is 5 μm or more.

[0130] The fifth separation region P5 according to this embodiment has a dimension d5 of 5 μm or more in the length direction L. The sixth separation region P6 according to this embodiment has a dimension d6 of 5 μm or more in the length direction L.

[0131] The dimension d7 of the seventh separation region P7 in the length direction L according to this embodiment is 5 μm or more. The dimension d8 of the eighth separation region P8 in the length direction L according to this embodiment is 5 μm or more.

[0132] <Measurement of Lengthwise Dimension of Separation Area> Hereinafter, a method for measuring the lengthwise dimension L of the separation area P in this embodiment will be described. The lengthwise dimension L of the separation area P is measured based on observation using a SEM (scanning electron microscope).

[0133] SEM observation for measuring the dimension of the peeled region P in the length direction L is performed on the LT cross section approximately parallel to the first side surface WS1 and the second side surface WS2 at approximately the center position in the width direction W of the laminate 10.

[0134] First, the laminate 10 is polished at a position approximately at the center in the width direction W so that the LT cross section of the laminate 10 of the multilayer ceramic capacitor 1 is exposed.

[0135] The measurement target area is photographed with an SEM at a magnification of 20,000 times. The outer edges of the extension portion E and the laminate 10 are traced on the photographed image using analysis software to identify the peeled area P, and the dimension d of the identified peeled area P in the length direction L is measured.

[0136] The first Ni plating layer 71A is formed so that tensile stress is uniformly generated throughout the first Ni plating layer 70A in a direction intersecting the thickness direction of the first Ni plating layer 70A. In other words, tensile stress remains as internal stress within the first Ni plating layer 71A. The portion of the first Ni plating layer 71A included in the extension portion E experiences tensile stress in a direction intersecting the thickness direction of the first Ni plating layer 70A, and therefore tends to shrink in a direction intersecting the thickness direction of the plating layer 70A. The first conductive resin layer 60A, which is fixed in contact with the portion of the first Ni plating layer 71A included in the extension portion E, receives a force in the shrinking direction from the portion of the first Ni plating layer 71A included in the extension portion E, resulting in compressive stress. Therefore, in the extension portion E shown in FIG. 5, the first Ni plating layer 71A in the extension portion E and the first conductive resin layer 60A fixed in contact with the first Ni plating layer 71A are subjected to a bending moment that causes the first plating layer 70A to warp toward the surface side due to the resultant force of these internal stresses, which promotes peeling in the peeling region P of the extension portion E and further improves the bending resistance.

[0137] In the extension E having the peeled region P where the conductive resin layer 60 has peeled off from the laminate 10, the end of the Ni plating layer 71 and the end of the Sn plating layer 72 are also peeled off from the laminate 10, and it is preferable that tensile stress remains as internal stress inside the Ni plating layer 71. This promotes peeling in the peeled region P of the extension E, and further improves the bending resistance.

[0138] If the lengthwise dimension of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 40 is defined as L, then the L dimension is preferably 0.2 mm or more and 10 mm or less. If the lengthwise dimension of the multilayer ceramic capacitor 1 in the stacking direction is defined as T, then the T dimension is preferably 0.1 mm or more and 10 mm or less. The widthwise dimension of the multilayer ceramic capacitor 1 is defined as W. The W dimension is preferably 0.1 mm or more and 10 mm or less.

[0139] Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. The method for manufacturing the multilayer ceramic capacitor 1 of this embodiment is not limited as long as it satisfies the above-mentioned requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.

[0140] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known.

[0141] On the dielectric sheets, the conductive paste for the internal electrode layers 30 is printed in a predetermined pattern by, for example, screen printing, gravure printing, etc. In this way, a dielectric sheet on which the pattern of the first internal electrode layer 31 is formed and a dielectric sheet on which the pattern of the second internal electrode layer 32 is formed are prepared.

[0142] A predetermined number of dielectric sheets on which no pattern of internal electrode layers is printed are stacked to form a portion that will become the first main surface side outer layer portion 12A on the first main surface TS1 side. A dielectric sheet on which the pattern of the first internal electrode layer 31 and a dielectric sheet on which the pattern of the second internal electrode layer 32 are printed are stacked in order on top of that to form a portion that will become the internal layer portion 11. A predetermined number of dielectric sheets on which the pattern of the internal electrode layers is not printed are stacked on top of this portion that will become the internal layer portion 11 to form a portion that will become the second main surface side outer layer portion 12B on the second main surface TS2 side. In this way, a laminated sheet is produced.

[0143] The laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0144] The laminated block is cut to a predetermined size to cut out laminated chips, and at this time, corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0145] The laminated chip is fired to produce the laminate 10. The firing temperature depends on the materials of the dielectric layers 20 and the internal electrode layers 30, but is preferably 900°C or higher and 1400°C or lower.

[0146] A conductive paste that will become the base electrode layer 50 is applied to both end surfaces of the laminate 10. In this embodiment, the base electrode layer 50 is a baked layer. A conductive paste containing a glass component and a metal is applied to the laminate 10 by a method such as dipping. A baking process is then performed to form the base electrode layer 50. The temperature of the baking process at this time is preferably 700°C or higher and 950°C or lower.

[0147] Next, the conductive resin layer 60 is formed. The conductive resin layer 60 may be formed on the surface of the base electrode layer 50, or may be formed directly on the laminate 10. In this embodiment, the conductive resin layer 60 is formed on the surface of the base electrode layer 50.

[0148] First, a conductive resin paste is prepared by dispersing conductive fillers in a thermosetting resin as a base resin for the resin portion. This conductive resin paste is produced by stirring and mixing the thermosetting resin and the conductive fillers. Therefore, the conductive fillers are uniformly dispersed within the conductive resin paste. Here, the thermosetting resin is, for example, an epoxy resin. The conductive filler is, for example, Ag metal powder.

[0149] Thereafter, a conductive resin paste is applied onto the base electrode layer 50 by a dipping method, and a heat treatment is performed at a temperature of 200° C. to 550° C. This causes the resin portion to be thermally hardened, forming the conductive resin layer 60. The atmosphere during this heat treatment is N ２ In order to prevent the resin from scattering and the various metal components from being oxidized, it is preferable that the oxygen concentration be kept at 100 ppm or less.

[0150] The thickness of the conductive resin layer on the ridge line can be controlled by adjusting the viscosity of the resin electrode and the application conditions. The peeling area can be controlled by adjusting the thickness of the conductive resin layer or the thickness of the Ni plating with residual tensile stress (described below).

[0151] Thereafter, a plating layer 70 is formed on the surface of the conductive resin layer 60. In this embodiment, a Ni plating layer 71 and a Sn plating layer 72 are formed on the conductive resin layer 60. The Ni plating layer 71 and the Sn plating layer 72 are formed sequentially using an electrolytic plating method. As the plating method, for example, barrel plating is preferably used.

[0152] The stress generated throughout the first Ni plating layer 71A and the second Ni plating layer 71B of the present invention can be controlled by the following method.

[0153] It is known that the stress generated in the plating varies depending on the current density applied during film formation. The current density applied to the multilayer ceramic capacitor 1 is random. At the tip portions of the Ni plating layer located on the first main surface TS1, the second main surface TS2, the first side surface WS1, or the second side surface WS2, the average current density applied to each tip portion from the initial stage of Ni plating film formation until the Ni plating reaches a thickness of, for example, 3 μm is the same for all surfaces of the tip portions of the Ni plating layer located on the first main surface TS1, the second main surface TS2, the first side surface WS1, or the second side surface WS2. Therefore, the same stress is applied to all surfaces of the Ni plating layer 71 on the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2.

[0154] The first Ni plating layer 71A and the second Ni plating layer 71B can be formed with a plating solution containing an adjusted amount of stress relaxation agent, for example, to form Ni plating with residual tensile stress as internal stress within the Ni plating layer. This residual stress generates a bending moment that warps the surface of the plating layer 70, promoting peeling in the peeled region P of the extension E and further improving the bending resistance.

[0155] In this embodiment, an Sn plating layer 72 is further formed on the Ni plating layer 71, with a first Sn plating layer 72A formed on the first Ni plating layer 71A and a second Sn plating layer 72B formed on the second Ni plating layer 71B. Electrolytic plating is used to form the Sn plating layer 72. Barrel plating is preferably used as the plating method. This improves the wettability of the solder used for mounting when mounting the multilayer ceramic capacitor 1, facilitating mounting. The multilayer ceramic capacitor 1 is manufactured by the above manufacturing method.

[0156] The multilayer ceramic capacitor 1 of this embodiment has the following advantages.

[0157] (1) The multilayer ceramic capacitor 1 according to this embodiment includes a laminate 10 including a plurality of laminated dielectric layers 20, and having a first main surface TS1 and a second main surface TS2 facing each other in a height direction T, a first side surface WS1 and a second side surface WS2 facing each other in a width direction W perpendicular to the height direction T, and a first end surface LS1 and a second end surface LS2 facing each other in a length direction L perpendicular to the height direction T and the width direction W; and a first internal electrode layer 3 disposed on the plurality of dielectric layers 20 and exposed at the first end surface LS1. In the multilayer ceramic capacitor 1 having a first internal electrode layer 32 disposed on a plurality of dielectric layers 20 and exposed at a second end face LS2, a first external electrode 40A disposed on the first end face LS1, and a second external electrode 40B disposed on the second end face LS2, the first external electrode 40A and the second external electrode 40B are formed by a base electrode layer 50 containing a metal component, a conductive resin layer 60 containing a filler powder and a resin component disposed on the base electrode layer 50, and a conductive resin layer 60 containing a filler powder and a resin component disposed on the conductive resin layer 60. The first external electrode 40A and the second external electrode 40B each have an extension E that is arranged to extend to a part of the first main surface TS1 and a part of the second main surface TS2, and the laminate 10 has ridge portions 10a at a portion where the first end face LS1 and the first main surface TS1 intersect, a portion where the first end face LS1 and the second main surface TS2 intersect, a portion where the second end face LS2 and the first main surface TS1 intersect, and a portion where the second end face LS2 and the second main surface TS2 intersect, and the ridge portions 10a of the laminate 10 A conductive resin layer 60 is arranged on the ridge portion 10a, and the film thickness of the conductive resin layer 60 on the ridge portion 10a is 0.8 μm or more and 8 μm or less. The conductive resin layer 60 has a peeled region P in at least one extension portion E where it is peeled off from the laminate 10, and the peeled region P is arranged in a region from the end of the conductive resin layer 60 on the center side of the laminate in the longitudinal direction L to just before the end of the underlying electrode layer 50 on the center side of the laminate in the longitudinal direction, and the longitudinal dimension of the peeled region P is 5 μm or more.

[0158] As a result, the presence of conductive resin layer 60 with a film thickness of 0.8 μm or more and 8 μm or less at ridge line portion 10a of laminate 10 makes it difficult for flexural stress to be transmitted to laminate 10 at ridge line portion 10a, thereby improving flexural resistance. Furthermore, the presence of peeled region P, which has a dimension of 5 μm or more in the length direction L and does not reach base electrode layer 50, makes it difficult for flexural stress to be transmitted to laminate 10, thereby improving flexural resistance.

[0159] (2) In the multilayer ceramic capacitor 1 of this embodiment, the conductive filler has Cu particles as cores, and at least a portion of the surface of the Cu particles is coated with a Cu—Ag alloy of Cu and Ag.

[0160] This improves the electrical properties of the conductive resin layer 60, improves the affinity with Ni plating, and improves the bending resistance.

[0161] (3) The conductive filler includes flat powder or spherical powder.

[0162] This improves the electrical properties of the conductive resin layer 60, improves the affinity with Ni plating, and improves the bending resistance.

[0163] (4) The plating layer 70 has a Ni plating layer 71 and a Sn plating layer 72 on the Ni plating layer 71, and tensile stress remains inside the Ni plating layer 71 as internal stress.

[0164] This applies tensile stress to the conductive resin layer 60, promoting peeling in the peeling region P and further improving the bending resistance.

[0165] 1 to 5 were fabricated as samples of experimental examples and comparative examples using the manufacturing method according to the above embodiment. For the experimental examples and comparative examples, experiments were conducted to confirm the resistance to deflection by varying the corner thickness, which is the thickness of the conductive resin layer on the ridge line portion, and the peel distance, which is the dimension in the longitudinal direction of the peeled region, while keeping the peel distance fixed, and by varying the peel distance, while keeping the corner thickness fixed, to confirm the resistance to deflection.

[0166] The peel distance was the distance from the tip of the external electrode 40 on the central side of the laminate 10 in the length direction L. Specifically, experiments in which the corner thickness was changed while the peel distance was fixed were conducted under seven conditions in which the corner thickness was changed while the peel distance was fixed at 5 μm, as shown in Table 1. Experiments in which the corner thickness was changed while the peel distance was fixed were conducted under seven conditions in which the corner thickness was changed while the peel distance was fixed at 0.8 μm, as shown in Table 2.

[0167] The number of evaluation samples was 20, randomly selected from the same lot for each of the above conditions, and the corner thickness and peel distance were measured using the above-mentioned measurement method, and the average values ​​were obtained. To check the deflection resistance, another 20 samples were selected from the same lot as the samples used to measure the corner thickness and peel distance for each of the above conditions, and each was measured and evaluated for cracks.

[0168] The samples were prepared by controlling the corner thickness and peel distance using the method described above so that the corner thickness and peel distance met the conditions shown in Tables 1 and 2. The specifications of the multilayer ceramic capacitor were as follows: Dimensions of multilayer ceramic capacitor: 1.5 mm (length direction L) x 0.5 mm (width direction W) x 0.5 mm (stacking direction T) Ceramic material: BaTiO ３Electrostatic capacitance: 0.01 μF Rated voltage: 50 V Structure of external electrodes (1) Base electrode layer: electrode containing conductive metal (Cu) and glass component Thickness of base electrode layer at the center in the height direction located on the first end face and the second end face: 20 μm Thickness of base electrode layer at the center in the length direction located on the first main face and the second main face, the first side face and the second side face: 4 μm (2) Conductive resin layer Conductive resin layer portion: conductive filler: Cu particles coated with Cu—Ag alloy Resin: thermosetting system Thickness of first conductive resin layer portion at the center in the height direction located on the first end face and the second end face: 20 μm Thickness of base electrode layer at the center in the length direction located on the first main face and the second main face, the first side face and the second side face: 20 μm (3) Ni plating layer Ni plating layer thickness: The thickness of the Ni plating layer at the center in the height direction of the Ni plating layer located on the first end face and the second end face: 3.0 μm The thickness of the Ni plating layer at the center in the length direction of the Ni plating layer located on the first main face and the second main face, the first side face and the second side face: 4.0 μm (4) Sn plating layer Sn plating layer thickness: The thickness of the Sn plating layer at the center in the height direction of the Sn plating layer located on the first end face and the second end face: 4.0 μm The thickness of the Sn plating layer at the center in the length direction of the Sn plating layer located on the first main face and the second main face, the first side face and the second side face: 4.0 μm

[0169] Next, a deflection test was conducted on the samples of the experimental examples and comparative examples using the following method. The prepared multilayer ceramic capacitors were subjected to a deflection test using the method of JIS C 6484, and the presence or absence of cracks in the dielectric layers was evaluated when the deflection amount was fixed at 5 mm. If cracks occurred during the deflection test, the result was evaluated as "X", and if no cracks occurred, the result was evaluated as "O". The results of the deflection test are shown in Tables 1 and 2.

[0170]

[0171]

[0172] As shown in Table 1, no cracks occurred in the laminated ceramic capacitor having a corner thickness of 0.8 μm as the experimental example, whereas cracks occurred in the laminated body of the laminated ceramic capacitor having a corner thickness of 0.5 μm as the comparative example.

[0173] As shown in Table 1, no cracks occurred in the experimental multilayer ceramic capacitor with a corner thickness of 8 μm, whereas cracks occurred in the comparative examples, the multilayer ceramic capacitor without a conductive resin layer on the ridge line portion and the multilayer ceramic capacitor with a corner thickness of 10 μm.

[0174] It is believed that when the corner thickness is thin, stress concentration occurs inside the base electrode layer 50, causing cracks to occur that originate inside the base electrode layer 50. When the corner thickness is thick, stress does not concentrate inside the base electrode layer 50, but stress is applied to the edge of the base electrode layer 50, causing stress concentration, resulting in cracks. The experimental results confirmed that when the corner thickness is 0.8 μm or more and 8 μm or less, propagation of flexural stress to the laminate 10 is suppressed, and flexural resistance is improved.

[0175] As shown in Table 2, no cracks occurred in the multilayer ceramic capacitor with a peeling distance of 5 μm, which was an experimental example, whereas cracks occurred in the laminate in the multilayer ceramic capacitor with no peeling area and the multilayer ceramic capacitor with a corner thickness of 2 μm, which were comparative examples.

[0176] As shown in Table 2, no cracks occurred in the multilayer ceramic capacitor of the experimental example, whereas cracks occurred in the laminate of the comparative example multilayer ceramic capacitor in which the peeled region reached the edge of the base electrode layer.

[0177] When the peeled region is small at the end of the base electrode layer 50, it is believed that stress concentration at the end of the base electrode layer 50 cannot be alleviated, and cracks originating from the end of the base electrode layer 50 occur. When the peeled region reaches the base electrode layer 50, stress concentrates at the end of the base electrode layer 50, and cracks originating from the end of the base electrode layer 50 occur. From the experimental results, it was confirmed that when the peeled distance is 5 μm or more and the peeled region does not reach the end of the base electrode, propagation of flexural stress to the laminate 10 is suppressed, and flexural resistance is improved.

[0178] The configuration of the multilayer ceramic capacitor 1 is not limited to the configuration shown in Figures 1 to 4. For example, the multilayer ceramic capacitor 1 may be a multilayer ceramic capacitor having a double structure, a triple structure, or a quadruple structure as shown in Figures 6, 7, and 8.

[0179] The multilayer ceramic capacitor 1 shown in FIG. 6 is a double-structure multilayer ceramic capacitor 1, and includes, as the internal electrode layers 30, a first internal electrode layer 33, a second internal electrode layer 34, and a floating internal electrode layer 35 that is not extended to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in FIG. 7 is a triple-structure multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as the floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in FIG. 8 is a quadruple-structure multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as the floating internal electrode layers 35. By providing the floating internal electrode layers 35 as the internal electrode layers 30 in this way, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. This reduces the voltage applied to each capacitor component, thereby achieving a high withstand voltage for the multilayer ceramic capacitor 1. It goes without saying that the multilayer ceramic capacitor 1 of this embodiment may have a multi-row structure of four or more rows.

[0180] The multilayer ceramic capacitor 1 may be a two-terminal type having two external electrodes, or may be a multi-terminal type having many external electrodes.

[0181] The present invention is not limited to the configurations of the above-described embodiments, and can be applied by making appropriate modifications within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-described embodiments.

[0182] <1> A multilayer ceramic capacitor comprising: a laminate including a plurality of dielectric layers stacked together, the laminate having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and first and second end surfaces opposing each other in a length direction perpendicular to the height and width directions; first internal electrode layers arranged on the plurality of dielectric layers and exposed at the first end surfaces; second internal electrode layers arranged on the plurality of dielectric layers and exposed at the second end surfaces; a first external electrode arranged on the first end surfaces; and a second external electrode arranged on the second end surfaces, wherein the first external electrode and the second external electrode have a base electrode layer containing a metal component, a conductive resin layer arranged on the base electrode layer and containing a filler powder and a resin component, and a plating layer arranged on the conductive resin layer, and the first external electrode and the second external electrode each have an extension portion arranged to extend to a part of the first main surface and a part of the second main surface, a conductive resin layer disposed on the ridgeline portions of the laminate, the conductive resin layer having a thickness of 0.8 μm or more and 8 μm or less, the conductive resin layer having a peeled region in at least one of the extension portions where the conductive resin layer has peeled off from the laminate, the peeled region being disposed in a region from an end of the conductive resin layer toward the center of the laminate in the length direction to just before an end of the base electrode layer toward the center of the laminate in the length direction, and the peeled region having a lengthwise dimension of 5 μm or more. <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the filler powder includes a flat powder or a spherical powder.<4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the plating layer includes a Ni plating layer and a Sn plating layer disposed on the Ni plating layer, and a tensile stress remains inside the Ni plating layer as an internal stress.

[0183] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 10 Laminate 10a Ridge portion 20 Dielectric layer 31 First internal electrode layer 32 Second internal electrode layer 40A First external electrode 40Aa End 40B Second external electrode 40Ba End 50A First base electrode layer 50Aa End 50B Second base electrode layer 50Ba End 60A First conductive resin layer 60B Second conductive resin layer 70A First plating layer 70B Second plating layer d Average length dimension of peeled region P Peeled region t Average film thickness T Height direction TS1 First main surface TS2 Second main surface W Width direction WS1 First side surface WS2 Second side surface L Length direction LS1 First end face LS2 Second end face

Claims

1. A laminate including a plurality of dielectric layers stacked together, the laminate having a first main surface and a second main surface opposed to each other in a height direction, a first side surface and a second side surface opposed to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposed to each other in a length direction perpendicular to the height direction and the width direction; a first internal electrode layer disposed on the plurality of dielectric layers and exposed to the first end surface; a second internal electrode layer disposed on the plurality of dielectric layers and exposed to the second end surface; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface, wherein the first external electrode and the second external electrode have a base electrode layer containing a metal component, a conductive resin layer containing a filler powder and a resin component and disposed on the base electrode layer, and a plating layer disposed on the conductive resin layer, the first external electrode and the second external electrode each have an extension portion extending to a portion of the first main surface and a portion of the second main surface, the laminate has ridge portions at a portion where the first end face and the first main surface intersect, a portion where the first end face and the second main surface intersect, a portion where the second end face and the first main surface intersect, and a portion where the second end face and the second main surface intersect, the conductive resin layer is disposed on the ridge portions of the laminate, and a film thickness of the conductive resin layer on the ridge portion is 0.8 μm or more and 8 μm or less, the conductive resin layer has a peeled region in at least one of the extension portions where it has peeled off from the laminate, the peeled region being disposed in a region from an end of the conductive resin layer on the center side of the laminate in the length direction to just before an end of the base electrode layer on the center side of the laminate in the length direction, and a longitudinal dimension of the peeled region is 5 μm or more.

2. The multilayer ceramic capacitor according to claim 1, wherein the filler powder has a Cu particle as a core, and at least a portion of the surface of the Cu particle is coated with a Cu-Ag alloy of Cu and Ag.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the filler powder includes flat powder or spherical powder.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the plating layer comprises a Ni plating layer and a Sn plating layer disposed on the Ni plating layer, and tensile stress remains inside the Ni plating layer as internal stress.

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