Multilayer ceramic capacitor

Abstract

The purpose of the present invention is to provide a multilayer ceramic capacitor in which sufficient mechanical strength is secured while maintaining electrical characteristics. In a multilayer ceramic capacitor 1, in a surface layer region 400, a side margin part 16 includes a first segregated object 133 containing silicon as a main component and having a major axis of 10-50 nm, and a second segregated object 135 containing silicon as a main component and having a major axis of 1 μm or more. A plurality of second segregated objects 135 are present in a cross section, and an additive component is included in the surface layer region 400. The additive component is composed of at least one of zirconium, aluminum, titanium, and calcium, and the concentration of the additive component of the surface layer region 400 is higher than the concentration of the additive component of the inner region 402.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Various techniques for coating the surface of a multilayer ceramic capacitor have been proposed as a means for improving the mechanical strength of the capacitor. Patent Document 1 discloses an example of a technique for forming a coating layer on the body of a ceramic electronic component.

[0003] JP 2016-105488 A

[0004] One possible way to improve the mechanical strength of multilayer ceramic capacitors is to increase the temperature rise rate during firing to densify the dielectric portion at or near the periphery of the multilayer ceramic capacitor (hereinafter referred to as the peripheral portion). However, increasing the temperature rise rate during firing to densify the peripheral portion can result in silicon dioxide not being discharged and segregating to the peripheral portion. The segregated silicon dioxide can reduce the mechanical strength of the multilayer ceramic capacitor. Silicon dioxide may contain barium, rare earth elements, zirconium, aluminum, titanium, etc. Furthermore, the peripheral portion can be composed of a side margin portion, a dead portion, an outer layer portion, etc., depending on the configuration of the multilayer ceramic capacitor.

[0005] If the sintering of ceramics is advanced in order to sufficiently remove silicon dioxide, there is a risk that grain growth will proceed excessively, resulting in defects.

[0006] When a multilayer ceramic capacitor is subjected to a coating treatment, structural defects may occur due to handling during the coating treatment.

[0007] Furthermore, if the coating layer is too thick, the connectivity of the terminal electrodes may be reduced. Furthermore, if a dip-type slurry is used in the coating process, the thickness of the coating layer may be less uniform. As a result, the dimensions of the multilayer ceramic capacitor may fall outside the tolerance range.

[0008] An object of the present invention is to provide a multilayer ceramic capacitor that ensures sufficient mechanical strength while maintaining electrical properties.

[0009] The multilayer ceramic capacitor of the present invention comprises an effective portion in which first internal electrode layers and second internal electrode layers are alternately stacked with dielectric layers formed of a ceramic dielectric interposed therebetween, the effective portion having a first effective portion main surface which is a surface in the stacking direction, a second effective portion main surface which is a surface opposite to the first effective portion main surface, a first effective portion side surface which is a surface in the width direction perpendicular to the first effective portion main surface and the second effective portion main surface and from which the first internal electrode layers and the second internal electrode layers are drawn, a second effective portion side surface which is a surface opposite to the first effective portion side surface and from which the first internal electrode layers and the second internal electrode layers are drawn, a first effective portion end surface which is a surface in the length direction perpendicular to the first effective portion main surface, the second effective portion main surface, the first effective portion side surface, and the second effective portion side surface and from which the first internal electrode layers are drawn, and a second effective portion end surface which is a surface opposite to the first effective portion end surface and from which the second internal electrode layers are drawn, and a side margin portion covering the effective portion and the invalid portion from the width direction; a first terminal electrode covering the first effective portion end face and electrically connected to the first internal electrode layer; and a second terminal electrode covering the second effective portion end face and electrically connected to the second internal electrode layer, wherein the side margin portion constitutes a ridge portion and in a surface layer region The side margin portion includes first segregates having silicon as a main component and having a major axis of 10 nm or more and 50 nm or less, and second segregates having silicon as a main component and having a major axis of 1 μm or more, and there are a plurality of the second segregates. The surface region includes an additive component consisting of at least one of zirconium, aluminum, titanium, and calcium, and the concentration of the additive component in the surface region is higher than the concentration of the additive component in the inner region.

[0010] According to the present invention, it is possible to provide a multilayer ceramic capacitor that ensures sufficient mechanical strength.

[0011] 19 is a perspective view of a multilayer ceramic capacitor according to a first embodiment. FIG. 19 is a cross-sectional view taken along line 201-201 in FIG. 1. FIG. 19 is a cross-sectional view taken along line 202-202 in FIG. 1. FIG. 19 is a cross-sectional view taken along line 204-204 in FIG. 19. FIG. 19 is a cross-sectional view taken along line 204-204 in FIG. 19. FIG. 19 is a cross-sectional view taken along line 204-204 in FIG. 19. 20. A cross-sectional view taken along line 205-205 in FIG. 19. A cross-sectional view of the multilayer ceramic capacitor at a second position. A view showing an enlarged view of the box 350 in FIG. 9. A view showing an enlarged view of the box 350 in FIG.

[0012] First Embodiment An overview of a multilayer ceramic capacitor 1 according to a first embodiment will be described with reference to Fig. 1. (Multilayer Ceramic Capacitor) Fig. 1 is a perspective view of the multilayer ceramic capacitor 1 according to the first embodiment. The multilayer ceramic capacitor 1 includes a ceramic body 2 and terminal electrodes 50. The terminal electrodes 50 include a first terminal electrode 51 and a second terminal electrode 52.

[0013] (Ceramic Element) The ceramic element 2 includes a laminate 3 and a side margin 16. The side margin 16 includes a first side margin 17 and a second side margin 18. The laminate 3 includes internal electrode layers 30 and dielectric layers 40.

[0014] (Directions of the ceramic body) The shape of the ceramic body 2 is approximately a rectangular parallelepiped. The direction in which the internal electrode layers 30 and the dielectric layers 40 are stacked is called the stacking direction 100. One of the directions perpendicular to the stacking direction 100 is called the length direction 101. The direction perpendicular to the stacking direction 100 and the length direction 101 is called the width direction 102.

[0015] (Surfaces of the ceramic body) The two surfaces that face each other in the stacking direction 100 are called the first element body main surface 4 and the second element body main surface 5. The two surfaces that face each other in the width direction 102 are called the first element body side surface 6 and the second element body side surface 7. The two surfaces that face each other in the length direction 101 are called the first element body end surface 8 and the second element body end surface 9.

[0016] (Ridge and Corner Portions) The portion where two surfaces intersect among the first element body main surface 4 , the second element body main surface 5 , the first element body side surface 6 and the second element body side surface 7 is called a ridge portion 60 .

[0017] (Laminate) The structure of the laminate 3 will be described with reference to Fig. 2. Fig. 2 is a cross-sectional view taken along line 201-201 in Fig. 1. The laminate 3 includes a plurality of internal electrode layers 30 and a plurality of dielectric layers 40 that are stacked.

[0018] (Internal electrode layers) The internal electrode layers 30 include a first internal electrode layer 31 and a second internal electrode layer 32. The first internal electrode layer 31 is an internal electrode layer 30 that is extended to the first element body end face 8. The second internal electrode layer 32 is an internal electrode layer 30 that is extended to the second element body end face 9.

[0019] (Effective portion, ineffective portion) The laminate 3 includes an effective portion 10 and an ineffective portion 12. The effective portion 10 and the ineffective portion 12 are the respective portions when the laminate 3 is divided in the stacking direction 100. The effective portion 10 is the portion where the internal electrode layers 30 and the dielectric layers 40 are stacked. The ineffective portions 12 sandwich the effective portion 10 in the stacking direction 100. In the effective portion 10, the portion where the first internal electrode layer 31 and the second internal electrode layer face each other is the portion where capacitance is formed. On the other hand, the ineffective portion 12 is the portion where capacitance is not formed.

[0020] (Invalid portion) The invalid portion 12 includes a first invalid portion 13 and a second invalid portion 14. The first invalid portion 13 is a portion between the valid portion 10 and the first element body main surface 4. The second invalid portion 14 is a portion between the valid portion 10 and the second element body main surface 5. The invalid portion 12 sandwiches the valid portion 10 in the stacking direction 100 between the first invalid portion 13 and the second invalid portion 14. The invalid portion 12 may be formed from a dielectric sheet of the same material as the dielectric layer 40, or may be formed from a different dielectric sheet.

[0021] (Surface of Effective Portion) One of the surfaces of the effective portion 10 perpendicular to the stacking direction 100 is called a first effective portion main surface 21. The surface of the effective portion 10 opposite to the first effective portion main surface 21 is called a second effective portion main surface 22.

[0022] One of the surfaces of the effective portion 10 perpendicular to the width direction 102 is called the first effective portion side surface 23. The surface of the effective portion 10 opposite the first effective portion side surface 23 is called the second effective portion side surface 24. The first effective portion side surface 23 and the second effective portion side surface 24 are not shown in Figure 2. The first effective portion side surface 23 and the second effective portion side surface 24 are shown in Figure 3 and other figures. Internal electrode layers 30 are drawn out from the first effective portion side surface 23 and the second effective portion side surface 24.

[0023] One of the surfaces of the effective portion 10 perpendicular to the longitudinal direction 101 is called a first effective portion end face 25. The surface of the effective portion 10 opposite to the first effective portion end face 25 is called a second effective portion end face 26. A first internal electrode layer 31 is drawn from the first effective portion end face 25. A second internal electrode layer 32 is drawn from the second effective portion end face 26.

[0024] The effective portion 10 is surrounded by a first effective portion main surface 21 , a second effective portion main surface 22 , a first effective portion side surface 23 , a second effective portion side surface 24 , a first effective portion end surface 25 and a second effective portion end surface 26 .

[0025] The first invalid portion 13 is the portion between the first effective portion main surface 21 and the first element body main surface 4. The second invalid portion 14 is the portion between the second effective portion main surface 22 and the second element body main surface 5.

[0026] (Materials of the Internal Electrode Layers, etc.) Examples of materials for the internal electrode layers 30 are metals such as nickel, copper, silver, palladium, and gold, and alloys containing at least one of the above-mentioned metals, such as a silver-palladium alloy. The components of the internal electrode layers 30 are not particularly limited as long as they are conductive materials.

[0027] The preferred thickness of the internal electrode layer 30 is 0.2 μm or more and 2.0 μm or less.

[0028] The total number of layers of the internal electrode layers 30, which is the sum of the number of the first internal electrode layers 31 and the number of the second internal electrode layers 32, is preferably 15 or more and 2000 or less.

[0029] (Materials of the Dielectric Layer, etc.) The ceramic dielectric that forms the dielectric layer 40 will be described. Examples of the main component of the ceramic dielectric are barium titanate, calcium titanate, strontium titanate, calcium zirconate, and strontium zirconate. The ceramic dielectric may contain a minor component. Examples of the minor component are rare earth oxides, silicon compounds, aluminum compounds, magnesium compounds, manganese compounds, iron compounds, chromium compounds, cobalt compounds, vanadium compounds, and nickel compounds. The ceramic dielectric is a perovskite-type oxide. In the perovskite-type atomic configuration, the element that is preferably contained most abundantly in the B site is titanium.

[0030] The thickness of each of the dielectric layers 40 is preferably 0.3 μm to 10 μm, and the total number of the dielectric layers 40 is preferably 15 to 2000.

[0031] (Ceramic Element Body) The structure of the ceramic element body 2 in the width direction 102 will be described with reference to Figure 3. Figure 3 is a cross-sectional view taken along line 202-202 in Figure 1. As described above, the ceramic element body 2 includes the laminate 3 and the side margin portion 16. The side margin portion 16 includes a first side margin portion 17 and a second side margin portion 18.

[0032] (Side Margin Portion) As shown in Fig. 3, the laminate 3 has a side margin portion 16. The side margin portion 16 is a portion that covers the valid portion 10 and the invalid portion 12 in the width direction 102. In other words, the side margin portion 16 is a portion that covers the laminate 3 in the width direction 102. The ceramic body 2 is formed by arranging the side margin portion 16 in the laminate 3. The side margin portion 16 may be formed from a dielectric sheet made of the same material as the dielectric layer 40, or from a different dielectric sheet.

[0033] The side margin portion 16 includes a first side margin portion 17 and a second side margin portion 18. The first side margin portion 17 is the side margin portion 16 that is arranged so that a portion thereof contacts the first effective portion side surface 23. The first side margin portion 17 constitutes the first element body side surface 6.

[0034] The second side margin 18 is the side margin 16 that is arranged so that a portion thereof contacts the second effective portion side surface 24. The second side margin 18 constitutes the second element body side surface 7. The side margin 16 constitutes the ridge portion 60.

[0035] (Size of ceramic element body) The size of the ceramic element body 2 is not particularly limited. The length of the ceramic element body 2 in the longitudinal direction 101 is preferably 0.2 mm or more and 10 mm or less. The length of the ceramic element body 2 in the width direction 102 is preferably 0.1 mm or more and 5 mm or less. The length of the ceramic element body 2 in the stacking direction 100 is preferably 0.1 mm or more and 5 mm or less.

[0036] (Terminal Electrodes) The terminal electrodes 50 will be described. As shown in Fig. 1 , the terminal electrodes 50 include a first terminal electrode 51 and a second terminal electrode 52. The first terminal electrode 51 is the terminal electrode 50 connected to the first internal electrode layer 31. The second terminal electrode 52 is the terminal electrode 50 connected to the second internal electrode layer 32.

[0037] The first terminal electrode 51 is arranged on the first element body end face 8, part of the first element body main surface 4, part of the second element body main surface 5, part of the first element body side surface 6, and part of the second element body side surface 7. The second terminal electrode 52 is arranged on the second element body end face 9, part of the first element body main surface 4, part of the second element body main surface 5, part of the first element body side surface 6, and part of the second element body side surface 7.

[0038] The terminal electrode 50 includes a base electrode layer 53, a nickel plating layer 56, and a tin plating layer 57. These are arranged in this order from the end face of the ceramic body 2: base electrode layer 53, nickel plating layer 56, tin plating layer 57.

[0039] The base electrode layer 53 is disposed on and covers the end face of the ceramic body 2. The base electrode layer 53 extends from the end face to a part of the main surface and a part of the side face.

[0040] The base electrode layer 53 includes a metal and glass. The metal includes, for example, at least one selected from copper, nickel, silver, palladium, a silver-palladium alloy, and gold. The glass includes, for example, boron and silicon. The base electrode layer 53 is formed by applying a conductive paste to the ceramic body 2 and firing the paste. This conductive paste includes a metal and glass. The preferred thickness of the base electrode layer 53 is, for example, 3 μm or more and 100 μm or less.

[0041] The nickel plating layer 56 is disposed so as to cover the base electrode layer 53. The tin plating layer 57 is disposed so as to cover the nickel plating layer 56.

[0042] Solder is used when mounting the multilayer ceramic capacitor 1 on a substrate, etc. The nickel plating layer 56 prevents the base electrode layer 53 from being corroded by the solder.

[0043] The tin plating layer 57 improves the wettability of the solder to the multilayer ceramic capacitor 1. As a result, the multilayer ceramic capacitor 1 can be easily mounted on a substrate or the like.

[0044] (Size of Multilayer Ceramic Capacitor) The size of the multilayer ceramic capacitor 1 is not particularly limited. The length in the longitudinal direction 101 of the multilayer ceramic capacitor 1 including the ceramic body 2 and the terminal electrodes 50 is preferably 0.2 mm or more and 10 mm or less. The length in the lamination direction 100 of the multilayer ceramic capacitor 1 including the ceramic body 2 and the terminal electrodes 50 is preferably 0.1 mm or more and 5 mm or less. The length in the width direction 102 of the multilayer ceramic capacitor 1 including the ceramic body 2 and the terminal electrodes 50 is preferably 0.1 mm or more and 10 mm or less.

[0045] (Segregation in Side Margin) The segregation 130 in the side margin 16 will be described. A portion where silicon is segregated to a predetermined size is called a segregation 130. The segregation of silicon occurs due to the segregation of silicon oxides, for example, silicon dioxide.

[0046] The segregation material 130 contains silicon as a main component, but also contains other additives such as magnesium and aluminum during the firing process. The main component here refers to a component that is contained in an amount of more than 50 wt %.

[0047] Segregated materials are elements contained in the main components of ceramics or additive elements that solidify in the ceramic during the sintering process, and include amorphous and crystalline materials. Segregated materials also include silicon, magnesium, aluminum, etc.

[0048] The segregation will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view of the side margin portion 16, taken along a plane parallel to the width direction 102 and the stacking direction 100. Fig. 4 shows a cross-section of the side margin portion 16 along a plane parallel to the stacking direction 100 and the width direction 102.

[0049] The cross section can be observed using a SEM (scanning electron microscope) or a TEM (transmission electron microscope) / STEM (scanning transmission electron microscope).

[0050] As shown in Fig. 4, the side margin portion 16 includes dielectric particles 120 and grain boundaries 122. The grain boundaries 122 are the outer peripheries of the dielectric particles 120. Segregations 130 are mainly present in portions where three or more grain boundaries 122 are about to intersect. Fig. 4 illustrates two segregations 130. The two segregations 130 are segregations 131 and 132.

[0051] Both the segregation object 131 and the segregation object 132 are present at the portion where three grain boundaries 122 intersect. The shape of the segregation object 131 in a cross-sectional view is approximately triangular. The shape of the segregation object 132 in a cross-sectional view is approximately rectangular. The shape of the segregation object 130 can be various, as shown by the segregation objects 131 and 132.

[0052] A double-headed arrow 141 shown in Fig. 4 indicates the major axis 141 of the segregated material 131. A double-headed arrow 142 shown in Fig. 4 indicates the major axis 142 of the segregated material 132. The major axis will be described later with reference to Fig. 8 .

[0053] The shape and size of the segregation 130 are not limited to the example shown in Fig. 4. Figs. 5, 6 and 7 are cross-sectional views of the side margin portion 16 taken along a plane parallel to the stacking direction 100 and the width direction 102.

[0054] 5 are present in most of the areas where the grain boundaries 122 intersect with each other. The segregations 133 are mainly present in the areas where three grain boundaries 122 intersect with each other.

[0055] The segregation 135 shown in Fig. 6 exists in a part where the grain boundaries 122 are about to intersect. The segregation 135 exists in a part where four or more grain boundaries 122 are about to intersect. The size of the segregation 135 is larger than the size of the segregation 133 shown in Fig. 5. The density of the segregation 135 is lower than the density of the segregation 133 shown in Fig. 5.

[0056] (First Segregates and Second Segregates) The segregates 130 are classified according to their major diameters. Segregates 130 with a major diameter of 10 nm or more and 50 nm or less are called first segregates 133. Segregates 130 with a major diameter of 1 μm or more are called second segregates 135. FIG. 5 illustrates an example of the state of the first segregates 133. FIG. 6 illustrates an example of the state of the second segregates 135.

[0057] The first segregated material 133 and the second segregated material 135 may be present together. Fig. 7 illustrates an example in which the first segregated material 133 and the second segregated material 135 are present together.

[0058] (Major Diameter) The major diameter and a method for measuring the major diameter will be described with reference to FIG. 8 . FIG. 8 is a cross-sectional view of the side margin portion 16 taken along a plane parallel to the stacking direction 100 and the width direction 102. The major diameter is the longest distance between two points around the segregation 130 in the cross-sectional view. Length 143 in FIG. 8 indicates the major diameter 143 of the segregation 136. Length 144 in FIG. 8 indicates the major diameter 144 of the segregation 137.

[0059] 8 has a rectangular cross-sectional shape. The segregation object 137 has a roughly J-shaped cross-sectional shape. The shape of the segregation object 130 can be various shapes, as shown by the segregation objects 136 and 137.

[0060] Whatever the shape of the segregation 130, the major axis can be determined by determining two points on the periphery of the segregation 130 that are the longest distance apart.

[0061] Note that segregates present at the interfaces between the dielectric particles 120 and portions extending from the segregates 130 along the grain boundaries are not included in the measurement of the major axis of the segregates 130. An example of the dielectric particles 120 is barium titanate particles.

[0062] (Evaluation Position) The following describes the position and range for evaluating the segregates 130. The evaluation of the segregates 130 includes measuring the major axis of the segregates 130, counting the number of segregates 130 present, and calculating the probability of the presence of the segregates 130.

[0063] 2 shows a first position 301, a second position 302, and a third position 303. The first position 301, the second position 302, and the third position 303 are boundary positions when the ceramic body 2 is divided into four equal parts in the longitudinal direction 101. The lengths 311, 312, 313, and 314 are all the same.

[0064] 9 is a diagram showing a cross section of the multilayer ceramic capacitor 1 taken along a plane parallel to the lamination direction 100 and the width direction 102 at the second position 302. The cross sections of the multilayer ceramic capacitor 1 at the first position 301 and the third position 303 are also similar to those shown in FIG.

[0065] The evaluation of the segregation 130 is performed at three locations: a first location 301, a second location 302, and a third location 303. The average of the evaluation results at the three locations, the first location 301, the second location 302, and the third location 303, is used as the evaluation result of the multilayer ceramic capacitor 1. The multilayer ceramic capacitor 1 includes a first segregation 133 containing silicon as the main component and having a major axis of 10 nm to 50 nm, and a second segregation 135 containing silicon as the main component and having a major axis of 1 μm or more, and whether a plurality of second segregations 135 are present in the cross section can be determined at the second location 302. The following description will be given using the second location 302 as an example.

[0066] 9 shows the fourth position 324. The fourth position 324 is the boundary position when dividing the side margin portion 16 into two equal parts in the width direction 102. The length 321 and the length 322 are the same.

[0067] (Evaluation Area) Figures 10 and 11 are enlarged views of box 330 in Figure 9. Box 331 in Figure 10 indicates a first evaluation area 331. Box 332 in Figure 11 indicates a second evaluation area 332. The first evaluation area 331 and the second evaluation area 332 are fields of view when evaluating segregated substances such as silicon dioxide. The first evaluation area 331 and the second evaluation area 332 are square in shape.

[0068] The probability of the presence of the first segregation material 133 is calculated from the observation results of the first evaluation region 331. The numbers of the first segregation material 133 and the second segregation material 135 are determined from the observation results of the second evaluation region 332.

[0069] (Surface Region) The surface region 400 will now be described. The region extending 5 μm or less from the element body main surface toward the interior of the ceramic element body 2 is referred to as the surface region 400. In FIG. 10 , the distance between the first element body main surface 4 and line 412 is indicated by length 341. In FIG. 11 , the distance between the first element body main surface 4 and line 414 is indicated by length 342. In FIG. 10 , length 341 is 5 μm. In FIG. 11 , length 342 is 5 μm. In FIG. 10 , the region between the first element body main surface 4 and line 412 is the surface region 400. In FIG. 10 , the region between the first element body main surface 4 and line 414 is the surface region 400.

[0070] As will be described below, line 412 in Fig. 10 also indicates the side that is farther from the first element body main surface 4 of the two sides that are parallel to the width direction 102 and that define the first evaluation region 331. Line 414 in Fig. 11 also indicates the side that is farther from the first element body main surface 4 of the two sides that are parallel to the width direction 102 and that define the second evaluation region 332.

[0071] (First Evaluation Area) The first evaluation area 331 will be described with reference to Fig. 10. In Fig. 10, the length of one side of the first evaluation area 331 is indicated by length 343. Length 343 is 2 µm. The size of the first evaluation area 331 is 2 µm x 2 µm. The field of view of the first evaluation area 331 is 4 µm squared.

[0072] The center position of the first evaluation area 331 in the width direction 102 is at the fourth position 324. The length 334 and the length 335 are the same.

[0073] The first evaluation region 331 is positioned within a range of 4 μm from the first element body main surface 4. Of the four sides defining the first evaluation region 331, two sides parallel to the width direction 102 are farther from the first element body main surface 4, and the distance between the first element body main surface 4 and the side is indicated by length 341. Length 341 is 4 μm.

[0074] (Second Evaluation Area) The second evaluation area 332 will be described with reference to Figure 11. In Figure 11, the length of one side of the second evaluation area 332 is indicated by length 344. Length 344 is 3 µm. The second evaluation area 332 is 3 µm x 3 µm in size. The field of view of the second evaluation area 332 is 9 µm squared.

[0075] The center position of the second evaluation area 332 in the width direction 102 is at the fourth position 324. The length 337 and the length 338 are the same.

[0076] The second evaluation region 332 is positioned within a range of 4 μm from the first element body main surface 4. Of the four sides defining the second evaluation region 332, the distance between the first element body main surface 4 and the side farther from the first element body main surface 4 of the two sides parallel to the width direction 102 is indicated by length 342. Length 342 is 4 μm.

[0077] The first evaluation area 331 and the second evaluation area 332 are both located in the surface area 400 .

[0078] The first evaluation area 331 is an evaluation area used when evaluating the first segregate. The second evaluation area 332 is an evaluation area used when evaluating the second segregate. The first evaluation area 331 is mainly used when evaluating the first segregate 133. The second evaluation area 332 is used when evaluating the second segregate 135.

[0079] As described above, the segregation particles 130 are evaluated in the vicinity of the ridge line 60 of the ceramic body 2 at three locations when the ceramic body 2 is divided into four equal parts in the longitudinal direction 101 .

[0080] As described above, the main content of the evaluation is how many first segregates 133 are contained in the first evaluation region 331, and how many first segregates 133 and second segregates 135 are contained in the second evaluation region 332.

[0081] In each evaluation, the major axis of the segregated matter 130 is measured. The segregated matter 130 is classified into a first segregated matter 133, a second segregated matter 135, and a segregated matter 130 that does not fall into either of the above categories, depending on the major axis.

[0082] The distribution of segregates 130 is likely to vary in the vicinity of the main surface of the ceramic body 2. This is because silicon dioxide is likely to be expelled from the main surface of the ceramic body 2 to the outside of the ceramic body 2. Therefore, an evaluation region is set at a predetermined distance from the main surface of the ceramic body 2. This makes it possible to suppress variation in the evaluation results of the segregates 130.

[0083] In the multilayer ceramic capacitor 1 of this embodiment, the first segregation and the second segregation are present in the second evaluation region 332, and there are two or more second segregation objects.

[0084] Furthermore, in the multilayer ceramic capacitor 1 of this embodiment, the number of first segregates present in the first evaluation region 331 is 32 or less. In other words, the abundance ratio of the first segregates in the first evaluation region 331 is 8 or less per 1 μm 2 .

[0085] This makes it possible to provide a multilayer ceramic capacitor 1 that has sufficient mechanical strength.

[0086] 5, when the first segregation particles 133 are present at a high abundance ratio, the strength of the side margin portion 16 is likely to decrease. This is because chipping or cracking may occur starting from the first segregation particles 133.

[0087] The portion where the segregation 130 exists is a portion in the dielectric where mechanical properties (Young's modulus, Poisson's ratio, etc.) are different. Portions where mechanical properties (Young's modulus, Poisson's ratio, etc.) are different become stress concentration points. The portion where the segregation 130 exists can be said to be a defect in fracture mechanics. Stress concentration increases when a defect is adjacent to another defect. Therefore, a state where the portion where the segregation 130 exists at high density across the grain boundary can be said to be a state where it is weak against external forces. Therefore, chipping and the like are likely to occur starting from the first segregation 133.

[0088] In contrast, as shown in Figures 6 and 7 , when the segregates 130 with short major axes are gathered together, the number of segregates 130 with short major axes is reduced, and when the segregates 130 with short major axes are aggregated into segregates 130 with long major axes, the number of segregates 130 is reduced, and a decrease in the strength of the side margin portion 16 is suppressed. In other words, when a plurality of first segregates 133 gather together to form second segregates 135, a decrease in the strength of the side margin portion 16 is suppressed. This effect is particularly noticeable in the surface layer region. Here, the surface layer region refers to a region 5 µm inward from the surface of the ceramic body 2.

[0089] In order to suppress a decrease in the strength of the side margin portion 16, it is not necessary for the number of first segregates 133 to be zero. For example, as shown in Fig. 7 , the first segregates 133 may remain. In that case, as shown in Fig. 7 , it is preferable that the first segregates 133 and the second segregates 135 are not adjacent to each other.

[0090] The length of the side margin portion 16 in the width direction 102 is preferably 50 μm or less, and more preferably 40 μm or less.

[0091] The length of the ineffective portion 12 in the stacking direction 100 is preferably 60 μm or less, and more preferably 35 μm or less.

[0092] The thickness of the dielectric layer 40 is preferably 0.6 μm or less.

[0093] In the multilayer ceramic capacitor 1 of this embodiment, even if the capacitor is thin and the length in the width direction 102 of the side margin portion 16 that constitutes the ridge portion 60 is short, i.e., even if the capacitor is thin, the mechanical strength of the multilayer ceramic capacitor 1 can be ensured.

[0094] The major axis of the second segregation matter 135 is preferably at least twice the particle diameter of the dielectric particle 120. The major axis of the first segregation matter 133 is preferably at most half the particle diameter of the dielectric particle 120. This can further improve the mechanical strength of the multilayer ceramic capacitor 1.

[0095] (Method for Evaluating Mechanical Strength) A method for evaluating mechanical strength will be described with reference to Fig. 12. Fig. 12 is a diagram showing two multilayer ceramic capacitors 1 colliding with each other. The mechanical strength of the multilayer ceramic capacitors 1 is evaluated by colliding the multilayer ceramic capacitors 1 with each other. After the collision, the multilayer ceramic capacitors 1 are observed under a microscope. Multilayer ceramic capacitors 1 that are found to have structural defects as a result of the observation are deemed defective.

[0096] Specifically, of the two multilayer ceramic capacitors 1, one multilayer ceramic capacitor 151 is inclined at 45 degrees relative to the other multilayer ceramic capacitor 152. The angle formed between the ridge line 60 of the multilayer ceramic capacitor 151 and the ridge line 60 of the other multilayer ceramic capacitor 152 is indicated by angle 164. The angle 164 is 45 degrees.

[0097] With the capacitors tilted at 45 degrees, the multilayer ceramic capacitor 151 is moved in the direction of the arrow 161, and the multilayer ceramic capacitor 152 is moved in the direction of the arrow 162. Then, the ridges 60 of the multilayer ceramic capacitor 151 in the longitudinal direction collide with the ridges 60 of the multilayer ceramic capacitor 152 in the longitudinal direction. The collision speed is set to 2.4 m / s. Twenty sets of multilayer ceramic capacitors 1 are collided, and the presence or absence of structural defects is observed.

[0098] (Mechanical Strength Evaluation Results) The mechanical strength evaluation results will be described with reference to Fig. 13. Fig. 13 is a graph showing the relationship between the abundance ratio of the first segregates 133 and the incidence of defects in the evaluation of mechanical strength. The X axis of the graph in Fig. 13 represents the abundance ratio of the first segregates 133. The Y axis of the graph in Fig. 13 represents the incidence of defects. The incidence of defects refers to the rate of defects among 20 sets of tests.

[0099] 13 , in the first evaluation region 331, when the abundance ratio of the first segregates 133 is 20 particles / μm 2 or more, the defect rate is 30% or more. On the other hand, when the abundance ratio of the first segregates 133 is 10 particles / μm 2 or less, the defect rate is 20% or less. Thus, when the abundance ratio of the first segregates 133 is 10 particles / μm 2 or less, preferably when the abundance ratio of the first segregates 133 is 8 particles / μm 2 or less, the defect rate can be reduced.

[0100] Similarly, in the second evaluation region 332, when the first segregation material 133 and the second segregation material 135 are included and there are a plurality of second segregation materials 135, the defect rate can be reduced compared to when a large number of first segregation materials 133 are included and no second segregation materials 135 are included.

[0101] (Additive Component) In the multilayer ceramic capacitor 1 of this embodiment, the additive component is contained in the surface region 400. The additive component is not limited to the surface region 400 but is contained throughout the entire ceramic body 2. In this embodiment, because a coating material is applied to the ceramic body 2 by coating, the additive component is contained in a particularly large amount in the surface region 400. Examples of the additive component include zirconium, aluminum, titanium, and calcium. The additive component may be at least one of zirconium, aluminum, and titanium. The additive component is a portion of the components contained in the coating material. The additive component exists in the same form as a compound in the surface region 400 and inside the ceramic body 2, but the element amount differs. The additive component derived from the coating material dissolves in the ceramic during the sintering process or dissolves in a sintering aid (such as silicon dioxide) originally added. Specifically, for example, when an aluminum oxide coating is applied, the amount of aluminum is higher in the surface region 400. The coating material is applied to the multilayer chip before firing. The coating process and coating materials will be described later.

[0102] (Zirconium Distribution) FIGS. 14 and 15 are cross-sectional views of the outer layer portion 72 taken along a plane parallel to the stacking direction 100 and the width direction 102. FIGS. 14 and 15 show the distribution of zirconium 176 in STEM (Scanning Transmission Electron Microscopy)-EDX (Energy Dispersive X-ray Fluorescence Spectroscopy) images in the surface layer region 400. FIG. 14 shows the outer layer portion 72 of a multilayer ceramic capacitor 1 that has been fired after a coating treatment has been applied to the laminated chip. FIG. 15 shows the outer layer portion 72 of a multilayer ceramic capacitor 1 that has been fired without a coating treatment being applied to the laminated chip.

[0103] 14 and 15, zirconium 176 is diffused within a range of several μm from the first element body main surface 4. In the coated multilayer ceramic capacitor 1, zirconium 176 is distributed in larger chunks than in the uncoated multilayer ceramic capacitor 1.

[0104] (Inner Region) The concentration of the additive component in the surface region 400 is higher than the concentration of the additive component in the inner region 402. The inner region 402 will be described with reference to Figure 9. Line 404 in Figure 9 indicates the center of the ceramic body 2 in the stacking direction 100. Length 406 and length 408 are the same. With line 404 as the center, the range of 2 µm from line 404 in the direction toward the first element body main surface 4 and 2 µm from line 404 in the direction toward the second element body main surface 5, totaling 4 µm, is referred to as the inner region 402.

[0105] (Third Evaluation Region) A frame 410 in Fig. 9 indicates the third evaluation region 410. The shape of the third evaluation region 410 is square. The length of one side of the third evaluation region 410 is 3 µm. The center position of the third evaluation region 410 in the width direction 102 is at the fourth position 324. The center position of the third evaluation region 410 in the stacking direction 100 is on the center line 404.

[0106] The concentration of the additive component in the inner region 402 is the concentration of the additive component in the third evaluation region 410. The concentration of the additive component in the surface region 400 is the concentration of the additive component in the second evaluation region 332 described above. More specifically, the average of the results of the evaluation of the third evaluation region 410 at the three locations, the first position 301, the second position 302, and the third position 303, is the concentration of the additive component in the inner region 402. Furthermore, the average of the results of the evaluation of the second evaluation region 332 at the three locations, the first position 301, the second position 302, and the third position 303, is the concentration of the additive component in the surface region 400.

[0107] When the concentration of the additive component is evaluated by the above method, the concentration of the additive component in the surface region 400 is higher than the concentration of the additive component in the inner region 402. Here, examples of the additive component are zirconium, aluminum, titanium, and calcium, as described above.

[0108] In the coated multilayer ceramic capacitor 1, more zirconium is distributed in the surface layer region 400. In the coated multilayer ceramic capacitor 1, the voids 172 in the outer layer portion 72 are reduced and the segregation of silicon dioxide is greater than in the uncoated multilayer ceramic capacitor 1. This will be described with reference to FIGS.

[0109] (Distribution of voids and silicon dioxide) Figures 16 and 17 are both cross-sectional views of the outer layer portion 72 taken along a plane parallel to the stacking direction 100 and the width direction 102. Figures 16 and 17 both show FE-SEM (field emission scanning electron microscope) images of the surface layer region 400. Figure 16 shows the outer layer portion 72 of a multilayer ceramic capacitor 1 that has been fired after the laminated chip has been coated. Figure 17 shows the outer layer portion 72 of a multilayer ceramic capacitor 1 that has been fired without the laminated chip being coated.

[0110] As shown in Figures 16 and 17, the coated multilayer ceramic capacitor 1 has fewer voids 172 and larger silicon dioxide segregations 170 than the uncoated multilayer ceramic capacitor 1.

[0111] The relationship between the presence or absence of coating treatment and mechanical strength will be explained with reference to Figure 18. Figure 18 is a diagram showing the results of evaluation of mechanical strength. Figure 18 shows the evaluation of surface strength using a spherical indenter with a sphere of 10 μm radius. There is no significant difference in the composite modulus of elasticity depending on whether or not the coating treatment is performed. However, when the coating treatment is performed, the yield contact pressure at which plastic deformation occurs is approximately 1.5 times higher than when the coating treatment is not performed. As shown in Figure 18, mechanical strength is improved by applying the coating treatment.

[0112] By carrying out the coating process as described above, the periphery (the invalid portion 12 and the side margin portion 16) is densified, voids are reduced, and silicon dioxide at the grain boundaries is expelled. This allows large segregated silicon dioxide particles to be generated in the periphery.

[0113] The coating treatment is performed on the surface of the ceramic body 2, and therefore has little effect on the electrical characteristics of the multilayer ceramic capacitor 1. This is because there is a difference in the concentration of the additive components between the ineffective portion 12 and the effective portion 10. Furthermore, because the coating is thin, it has little effect on the connectivity of the terminal electrodes 50.

[0114] (Method for Producing the Multilayer Ceramic Capacitor of the First Embodiment) A method for producing the multilayer ceramic capacitor 1 will be described. (1) A precursor of the laminate 3 is prepared. The precursor means a precursor before firing. The precursor of the laminate 3 is a precursor before the dielectric sheets for the side margin portions 16 are arranged.

[0115] A dielectric sheet for the laminate 3 and a conductive paste for the internal electrode layers 30 are prepared. The conductive paste for the dielectric sheet and the internal electrode layers 30 contains a binder and a solvent. The binder and the solvent may be known organic binders and organic solvents.

[0116] (2) A conductive paste for the internal electrode layer 30 is printed in a predetermined pattern on the dielectric sheet. This forms an internal electrode layer pattern on the dielectric sheet. Examples of printing methods include screen printing and gravure printing.

[0117] (3) A predetermined number of dielectric sheets on which no internal electrode layer patterns are printed are stacked. The stacked layers become layers that include the ineffective portion 12 on one side. Dielectric sheets on which internal electrode layer patterns are printed are stacked in sequence on top of these. The stacked layers become layers that include the effective portion 10. A predetermined number of dielectric sheets on which no internal electrode layer patterns are printed are stacked on top of these. The stacked layers become layers that include the ineffective portion 12 on the other side.

[0118] (4) The stacked sheets are pressed in the stacking direction to produce a stacked block. An example of the pressing method is isostatic pressing.

[0119] (5) The laminated block is cut. When cutting, the conductive paste corresponding to the internal electrode layers 30 is exposed on both sides in the width direction 102. Dielectric sheets for forming side margin portions 16 are arranged on both sides in the width direction 102 of the cut block. After that, the ceramic body 2 is formed through firing and cutting. The steps will be described in order below.

[0120] (6) A dielectric sheet for the side margin portion 16 is prepared. The dielectric material of the dielectric sheet may be the same as the dielectric material for the effective portion 10 and the ineffective portion 12. Additives may be added to the dielectric powder obtained from this dielectric material.

[0121] (7) The dielectric sheet for the side margin portion 16 is pressed against the precursor of the laminate 3. Then, by punching, a layer that will become the side margin portion 16 is formed. Next, the dielectric sheet for the side margin portion 16 is pressed against the other side of the precursor of the laminate 3 in the same manner. Then, by punching, a layer that will become the side margin portion on the other side is formed. Note that punching may be performed after the dielectric sheets for the side margin portions have been pressed against both sides of the precursor of the laminate 3.

[0122] (11) The laminated chip on which the layer that will become the side margin portion 16 is formed is degreased under predetermined conditions in a nitrogen atmosphere. Thereafter, the laminated chip is fired at a predetermined temperature in a nitrogen-hydrogen-water vapor mixed atmosphere to obtain a sintered ceramic body 2.

[0123] (Coating Treatment) In this embodiment, the laminated chips are subjected to a coating treatment at the stage of raw chips before firing. The coating treatment is a treatment for thinly and uniformly coating the surface of the laminated chips with an additive.

[0124] Specifically, the surface of the laminated chip is covered with a coating material in a thin film of 100 nm or less. The coating material includes at least one of zirconium, aluminum, titanium, and calcium. The coating material functions as an additive. When the surface of the laminated chip is coated with the additive, the sinterability near the surface is changed by firing, resulting in the desired mechanical strength.

[0125] Typical examples of thin film coating techniques include liquid phase deposition and mist CVD (chemical vapor deposition).

[0126] An example of the procedure when using liquid phase precipitation is described below. 1. Prepare an aqueous solution of ammonium hexafluorozirconate (Zr solution) and an aqueous solution of boric acid dissolved in pure water at a concentration of 5 wt% to 10 wt%. 2. While heating and stirring, add the raw chip layered chips to the Zr solution, then add the aqueous solution of boric acid. 3. Continue stirring and immersion for at least 1 hour to allow the reaction to proceed. 4. Separate the reaction solution from the layered chips using a sieve, and wash the layered chips with pure water. 5. Thoroughly dry in an oven at 100°C or higher.

[0127] When coating is performed after firing, there is a concern that structural defects may occur during handling. However, by performing the process at the raw chip stage, when the chip is still in a composite state of resin and particles, structural defects can be suppressed. Furthermore, by achieving a film thickness of 100 nm or less, the connectivity of the terminal electrodes can be ensured without any problems. Furthermore, the coating process promotes the growth of particles near the surface, thereby facilitating the migration of segregated particles. As a result, it becomes easier to obtain a multilayer ceramic capacitor 1 having second segregated particles 135 formed therein. Furthermore, by densifying the peripheral portion (the invalid portion 12 and the side margin portion 16) and reducing voids, the occurrence of cracks due to external impacts can be suppressed, and the mechanical strength of the surface layer can be improved. Furthermore, because the coating process only affects the surface layer, the impact on electrical characteristics can be minimized. Furthermore, even when the length of the invalid portion 12 in the stacking direction 100, i.e., its thickness, is as thin as 35 μm or less, the occurrence of cracks due to external impacts can be suppressed, and the mechanical strength of the surface layer can be improved. Furthermore, even if the length in the width direction 102 of the side margin portion 16 that constitutes the ridge portion 60, i.e., the thickness, is thin, such as 40 μm or less, the occurrence of cracks due to external impact can be suppressed, and the mechanical strength of the surface layer can be improved.

[0128] After the above-mentioned coating process, the laminated chip is fired under the conditions of a temperature rise rate of 100° C. / min or more and a maximum temperature of 1200° C. or more.

[0129] (12) Terminal electrodes 50 are formed on each of two end faces of the sintered ceramic body 2, the first end face 8 and the second end face 9. In this manner, the multilayer ceramic capacitor 1 is fabricated. The terminal electrodes 50 may be formed by a known method. For example, a conductive paste containing a conductive component such as copper or nickel as a main component is applied and baked to the end faces exposed by drawing out the internal electrode layers of the body portion to form the base electrode layer 54. The base electrode layer 54 may also be formed by applying a conductive paste to both end faces of a precursor of the ceramic body 2 before firing, followed by firing. After the base electrode layer 53 is formed, electrolytic plating is performed to form a nickel plating layer 56 and a tin plating layer 57 on the surface of the base electrode layer 53. This completes the fabrication of the multilayer ceramic capacitor.

[0130] (Modification of First Embodiment) In the multilayer ceramic capacitor 1 of this embodiment, annealing may be performed at a high temperature after firing. This will be described with reference to FIG. 19. FIG. 19 is a diagram showing an outline of annealing conditions. The X axis of the graph shown in FIG. 19 represents time. The Y axis of the graph shown in FIG. 19 represents temperature.

[0131] As described above, the laminated chip is fired under the conditions of a temperature rise rate of 100°C / min or more and a maximum temperature of 1200°C or more. Annealing is then performed. Although the laminated chip that has undergone the firing process described above is densified, the removal of silicon dioxide may not be sufficient. Therefore, an annealing process is performed at a high temperature.

[0132] In the annealing treatment, the ceramic body is held at 950°C or higher for 120 minutes or longer. Then, the ceramic body is further held at 1000°C or higher for 60 minutes or longer. This annealing treatment promotes the removal of silicon dioxide. Furthermore, it promotes the aggregation of minute silicon dioxide segregations, which leads to the formation of large silicon dioxide segregations. That is, in addition to the surface region, the first segregates 133 are aggregated from the surface region toward the interior of the ceramic body, which promotes the formation of second segregates 135. By this firing and annealing treatment, a sintered ceramic body 2 is obtained.

[0133] Second Embodiment An overview of a multilayer ceramic capacitor 1 according to a second embodiment will be described with reference to FIG. 20 . Differences from the first embodiment will be mainly described below. Items not otherwise specifically described are the same as those in the first embodiment. Multilayer Ceramic Capacitor FIG. 20 is a perspective view of a multilayer ceramic capacitor 1 according to a second embodiment. The ceramic body 2 according to the first embodiment is composed of a laminate 3 and a side margin portion 16. The ceramic body 2 according to the second embodiment is composed of an inner layer portion 70 and an outer layer portion 72. The inner layer portion 70 and the outer layer portion 72 are not shown in FIG. 20 . The inner layer portion 70 and the outer layer portion 72 are illustrated in FIGS. 21 and 22 . In the first embodiment, the internal structure of the ceramic body 2 was described using the terms effective portion and ineffective portion. In the second embodiment, the internal structure of the ceramic body 2 will be described using the terms inner layer portion and outer layer portion. The effective portion and inner layer portion, and the ineffective portion and outer layer portion refer to different areas.

[0134] (Inner layer portion and outer layer portion) The inner layer portion 70 and outer layer portion 72 will be described with reference to Figures 21 and 22. Figure 21 is a cross-sectional view taken along line 204-204 in Figure 20. Figure 22 is a cross-sectional view taken along line 205-205 in Figure 20. As shown in Figures 21 and 22, the ceramic body 2 includes an inner layer portion 70 and an outer layer portion 72. The inner layer portion 70 and the outer layer portion 72 are portions when the ceramic body 2 is sectioned in the stacking direction 100.

[0135] 22 , each of the inner layer portions 70 and the outer layer portions 72 is continuous in the width direction 102 from the first element body side surface 6 to the second element body side surface 7. On the other hand, as shown in FIG. 3 , the valid portion 10 and the invalid portion 12 in the first embodiment are not continuous in the width direction 102 from the first element body side surface 6 to the second element body side surface 7. This is because, in the multilayer ceramic capacitor 1 of the first embodiment, the first element body side surface 6 and the second element body side surface 7 are formed by the side margin portion 16.

[0136] The inner layer portion 70 is a portion where the internal electrode layer 30 and the dielectric layer 40 are laminated. The outer layer portion 72 may be formed from a dielectric sheet made of the same material as the dielectric layer 40, or may be formed from a different dielectric sheet.

[0137] (Outer Layer Portion) The outer layer portion 72 includes a first outer layer portion 73 and a second outer layer portion 74. The first outer layer portion 73 is the portion between the inner layer portion 70 and the first element body main surface 4. The second outer layer portion 74 is the portion between the inner layer portion 70 and the second element body main surface 5. The outer layer portion 72 sandwiches the inner layer portion 70 between the first outer layer portion 73 and the second outer layer portion 74 in the stacking direction 100. In the second embodiment, the outer layer portion 72 forms a ridge portion 60. The length of the outer layer portion 72 in the stacking direction 100 is preferably 60 μm or less, and more preferably 35 μm or less.

[0138] (Surface of Inner Layer Portion) One of the surfaces of the inner layer portion 70 perpendicular to the stacking direction 100 is called a first inner layer portion main surface 81. The surface of the inner layer portion 70 opposite to the first inner layer portion main surface 81 is called a second inner layer portion main surface 82.

[0139] One of the faces of the inner layer portion 70 perpendicular to the width direction 102 is referred to as the first inner layer portion side surface 83. The face of the inner layer portion 70 opposite the first inner layer portion side surface 83 is referred to as the second inner layer portion side surface 84. The first inner layer portion side surface 83 and the second inner layer portion side surface 84 are not shown in FIG. 21 . The first inner layer portion side surface 83 and the second inner layer portion side surface 84 are shown in FIG. 22 . The first inner layer portion side surface 83 constitutes a part of the first element body side surface 6. The second inner layer portion side surface 84 constitutes a part of the second element body side surface 7.

[0140] One of the faces of the inner layer portion 70 perpendicular to the length direction 101 is called the first inner layer portion end face 85. The face of the inner layer portion 70 opposite to the first inner layer portion end face 85 is called the second inner layer portion end face 86. The first internal electrode layer 31 is drawn from the first inner layer portion end face 85. The second internal electrode layer 32 is drawn from the second inner layer portion end face 86. The first inner layer portion end face 85 constitutes a part of the first element body end face 8. The second inner layer portion end face 86 constitutes a part of the second element body end face 9.

[0141] The inner layer portion 70 is surrounded by a first inner layer portion main surface 81 , a second inner layer portion main surface 82 , a first inner layer portion side surface 83 , a second inner layer portion side surface 84 , a first inner layer portion end surface 85 and a second inner layer portion end surface 86 .

[0142] The first outer layer portion 73 is the portion between the first inner layer portion main surface 81 and the first element body main surface 4. The second outer layer portion 74 is the portion between the second inner layer portion main surface 82 and the second element body main surface 5.

[0143] The dielectric layer 40 is disposed in the inner layer portion 70. The composition of the ceramic dielectric forming the dielectric layer 40 and the composition of the ceramic dielectric forming the outer layer portion 72 may be the same or different.

[0144] The total number of dielectric layers 40 is preferably 15 or more and 2000 or less.

[0145] (Ceramic Body) As described above, the multilayer ceramic capacitor 1 of the second embodiment does not include the side margin portion 16. The ceramic body 2 of the multilayer ceramic capacitor 1 of the second embodiment is composed of the inner layer portion 70 and the outer layer portion 72 described above.

[0146] (Terminal Electrodes) The ceramic body 2 is provided with terminal electrodes 50 to form the multilayer ceramic capacitor 1. The terminal electrodes 50 are the same as those in the first embodiment.

[0147] (Segregation in Outer Layer Portion) The segregation 130 in the outer layer portion 72 will be described. The description will focus on differences from the segregation 130 in the side margin portion 16 in the first embodiment. In the first embodiment, the segregation 130 in the side margin portion 16 is evaluated. In the second embodiment, the segregation 130 in the outer layer portion 72 is evaluated.

[0148] Fig. 23 is a diagram showing a cross section of the multilayer ceramic capacitor 1 taken along a plane parallel to the lamination direction 100 and the width direction 102 at the second position 302 in Fig. 21. The cross sections of the multilayer ceramic capacitor 1 at the first position 301 and the third position 303 are also similar to those shown in Fig. 23.

[0149] 23 shows a fifth position 352. The fifth position 352 is the boundary position when the outer layer portion 72 is divided into two equal parts in the width direction 102. The lengths 354 and 356 are the same.

[0150] (Evaluation Area) Figures 24 and 25 are enlarged views of the box 350 in Figure 23. The box 331 in Figure 24 indicates the first evaluation area 331. The box 332 in Figure 25 indicates the second evaluation area 332.

[0151] As shown in Fig. 24, the center position of the first evaluation area 331 in the width direction 102 is at the fifth position 352. As shown in Fig. 25, the center position of the second evaluation area 332 in the width direction 102 is at the fifth position 352. As shown in Fig. 23, the center position of the third evaluation area 410 in the width direction 102 is also at the fifth position 352.

[0152] In the first embodiment, the center position in the width direction 102 of the first evaluation area 331 and the center position in the width direction 102 of the second evaluation area 332 are both at the fourth position 324. The positions of the evaluation areas in the width direction 102 are different between the first embodiment and the second embodiment.

[0153] In the multilayer ceramic capacitor 1 of the first embodiment, the second evaluation region 332 of the outer layer portion 72 includes a first segregation 133 and a second segregation 135, and there are a plurality of second segregations 135. The abundance ratio of the first segregations 133 in the first evaluation region 331 of the outer layer portion 72 is 8 or less per μm 2 .

[0154] In the multilayer ceramic capacitor 1 of the second embodiment, as with the multilayer ceramic capacitor 1 of the first embodiment, the decrease in mechanical strength of the multilayer ceramic capacitor 1 was suppressed. Furthermore, the mechanical strength due to the coating treatment was also improved, as with the multilayer ceramic capacitor 1 of the first embodiment. Furthermore, even when the length in the lamination direction 100 of the outer layer portion 72 constituting the ridge line portion 60, i.e., the thickness, was thin, being 35 μm or less, the decrease in mechanical strength of the multilayer ceramic capacitor 1 was suppressed, as with the multilayer ceramic capacitor 1 of the first embodiment. Furthermore, the mechanical strength due to the coating treatment was also improved, as with the multilayer ceramic capacitor 1 of the first embodiment.

[0155] (Method for Producing the Multilayer Ceramic Capacitor of the Second Embodiment) A method for producing the multilayer ceramic capacitor 1 of the second embodiment will be described. (1) A precursor for the ceramic body 2 is prepared. Dielectric sheets for the ceramic body 2 and conductive pastes for the internal electrode layers 30 are prepared. The dielectric sheets and conductive pastes for the internal electrode layers 30 contain a binder and a solvent. The binder and solvent may be known organic binders and organic solvents.

[0156] (2) A conductive paste for the internal electrode layer 30 is printed in a predetermined pattern on the dielectric sheet. This forms an internal electrode layer pattern on the dielectric sheet. Examples of printing methods include screen printing and gravure printing.

[0157] (3) A predetermined number of dielectric sheets on which no internal electrode layer patterns are printed are stacked. The stacked layers become layers that include the outer layer portion 72 on one side. Dielectric sheets on which internal electrode layer patterns are printed are stacked in sequence on top of that. The stacked layers become layers that include the inner layer portion 70. A predetermined number of dielectric sheets on which no internal electrode layer patterns are printed are stacked on top of that. The stacked layers become layers that include the outer layer portion 72 on the other side.

[0158] (4) The stacked sheets are pressed in the stacking direction to produce a stacked block. An example of the pressing method is isostatic pressing.

[0159] (5) The laminated block is cut into laminated chips. In this embodiment, the laminated chips are then coated. After that, the ceramic body 2 is formed through firing and other processes. Specifically, the laminated chips are degreased under predetermined conditions in a nitrogen atmosphere. The laminated chips are then fired at a predetermined temperature in a nitrogen-hydrogen-water vapor mixed atmosphere to obtain the sintered ceramic body 2.

[0160] The firing conditions are the same as those in the first embodiment.

[0161] (6) Thereafter, in the same manner as in the multilayer ceramic capacitor 1 of the first embodiment, terminal electrodes 50 are formed on each of the two end faces of the ceramic body 2, the first body end face 8 and the second body end face 9. In this way, a multilayer ceramic capacitor is produced.

[0162] (Modification of Second Embodiment) In the second embodiment, an annealing treatment may be performed after firing, similar to the modification of the first embodiment. By performing the annealing treatment similar to the modification of the first embodiment, the first segregated particles 133 are gathered in the surface layer region and the second segregated particles 135 are promoted to be formed not only in the surface layer region but also from the surface layer region toward the interior of the ceramic body.

[0163] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various changes and modifications are possible.

[0164] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Ceramic element body 3 Laminate 4 First element body main surface 5 Second element body main surface 6 First element body side surface 7 Second element body side surface 8 First element body end surface 9 Second element body end surface 10 Effective portion 12 Ineffective portion 30 Internal electrode layer 40 Dielectric layer 50 Terminal electrode 60 Ridge line portion 70 Inner layer portion 72 Outer layer portion 100 Stacking direction 101 Length direction 102 Width direction 133 First segregation 135 Second segregation

Claims

1. An effective section in which first internal electrode layers and second internal electrode layers are alternately stacked with dielectric layers formed of ceramic dielectrics interposed therebetween, the effective section having a first effective section main surface which is a surface in the stacking direction, a second effective section main surface which is a surface opposite to the first effective section main surface, a first effective section side surface which is a widthwise surface perpendicular to the first effective section main surface and the second effective section main surface, and from which the first internal electrode layer and the second internal electrode layer are drawn out, a second effective section side surface which is a surface opposite to the first effective section side surface, and from which the first internal electrode layer and the second internal electrode layer are drawn out, a first effective section end surface which is a lengthwise surface perpendicular to the first effective section main surface, the second effective section main surface, the first effective section side surface and the second effective section side surface, and from which the first internal electrode layer is drawn out, and a second effective section end surface which is a surface opposite to the first effective section end surface and from which the second internal electrode layer is drawn out; a laminate including: an ineffective portion formed of a ceramic dielectric and covering the first effective portion main surface and the second effective portion main surface in the lamination direction; a side margin portion covering the effective portion and the ineffective portion in the width direction; a first terminal electrode covering the first effective portion end face and electrically connected to the first internal electrode layer; and a second terminal electrode covering the second effective portion end face and electrically connected to the second internal electrode layer, wherein the side margin portion constitutes a ridge portion, and in a surface layer region, the side margin portion includes first segregated objects having silicon as a main component and a major axis of 10 nm or more and 50 nm or less, and second segregated objects having silicon as a main component and a major axis of 1 μm or more, a plurality of the second segregated objects are present, the surface layer region includes an additive component, and the additive component is at least one of zirconium, aluminum, titanium, and calcium, A multilayer ceramic capacitor, wherein a concentration of the additive component in the surface region is higher than a concentration of the additive component in an inner region.

2. The multilayer ceramic capacitor according to claim 1, wherein the first segregation particles are present in a density of 8 particles or less per square micrometer in the surface layer region.

3. An inner layer portion in which first internal electrode layers and second internal electrode layers are alternately stacked with dielectric layers formed of ceramic dielectrics interposed therebetween, the inner layer portion having a first inner layer portion main surface which is a surface in the stacking direction, a second inner layer portion main surface which is a surface opposite to the first inner layer portion main surface, a first inner layer portion side surface which is a widthwise surface perpendicular to the first inner layer portion main surface and the second inner layer portion main surface, a second inner layer portion side surface which is a surface opposite to the first inner layer portion side surface, a first inner layer portion end surface which is a lengthwise surface perpendicular to the first inner layer portion main surface, the second inner layer portion main surface, the first inner layer portion side surface and the second inner layer portion side surface, and from which the first internal electrode layer is drawn out, and a second inner layer portion end surface which is a surface opposite to the first inner layer portion end surface and from which the second internal electrode layer is drawn out; 1. A multilayer ceramic capacitor comprising: a ceramic body having an outer layer portion formed of a ceramic dielectric and covering a main surface of the first inner layer portion and a main surface of the second inner layer portion in the stacking direction; a first terminal electrode covering an end face of the first inner layer portion and electrically connected to the first internal electrode layer; and a second terminal electrode covering an end face of the second inner layer portion and electrically connected to the second internal electrode layer, wherein the outer layer portion constitutes a ridge portion, and in a surface layer region, the outer layer portion includes first segregated objects having a major axis of 10 nm or more and 50 nm or less, and second segregated objects having a major axis of 1 μm or more, the surface layer region including an additive component, the additive component being at least one of zirconium, aluminum, titanium, and calcium, and a concentration of the additive component in the surface layer region being higher than a concentration of the additive component in an inner region.

4. The multilayer ceramic capacitor according to claim 3, wherein the first segregation particles are present in the surface region at a rate of 8 particles or less per square micrometer.

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