Multilayer ceramic electronic component and method for manufacturing same

Abstract

This multilayer ceramic electronic component includes: an element which has a generally rectangular cuboidal shape and includes a capacitor part that is formed by alternately stacking a first internal electrode layer and a second internal electrode layer with a dielectric layer being interposed therebetween, and a protective part that is provided outside the capacitor part; and external electrodes which are formed on the surface of the element so as to be separated from each other, and in each of which the first internal electrode layer and the second internal electrode layer are led out. Each of the dielectric layer and the protective part contains a dielectric ceramic as a main component, and the protective part includes a first layer that is adjacent to the capacitor part, a second layer that is adjacent to the first layer, and a third layer that is adjacent to the second layer. The atomic content ratio of Mn in the second layer is larger than the atomic content ratio of Mn in the first layer, and the content of a glass component in the second layer is larger than the content of the glass component in the first layer and the content of the glass component in the third layer.

Description

Multilayer ceramic electronic component and its manufacturing method

[0001] The present invention relates to a multilayer ceramic electronic component and a method for manufacturing the same.

[0002] Recently, multilayer ceramic electronic components have been known that have a laminate (capacitive portion) in which internal electrodes and dielectric layers are alternately stacked, and a protective portion surrounding the laminate. The protective portion includes side margin portions formed on the side surfaces of the laminate, and cover portions provided on the main surfaces located at both ends of the internal electrodes and dielectric layers that form the laminate in the stacking direction. The side margin portions are sometimes referred to as side layer(s). The cover portions are sometimes referred to as main surface layer(s). Previously, proposals have been made in which the main surface layer(s) and the side surface layer(s) are composed of multiple layers (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2021-072356

[0004] The protective portion has the function of protecting the laminate. When the protective portion is provided around the laminate, an element that suppresses grain growth of the protective portion may be added to ensure the reliability of the protective portion. However, adding an element that suppresses grain growth may also inhibit grain growth of the dielectric of the capacitive portion. If the grain growth of the dielectric of the capacitive portion is inhibited, the dielectric constant of the laminate that becomes the capacitive portion will decrease, and the effective capacitance will also decrease. For this reason, the protective portion is required to improve the reliability of the ceramic electronic component while ensuring the effective capacitance of the ceramic electronic component. The proposal in Patent Document 1 left room for improvement in terms of the above-mentioned requirements for the protective portion.

[0005] SUMMARY OF THE INVENTION It is therefore an object of the present invention to improve the reliability of a ceramic electronic component while ensuring the effective capacitance of the ceramic electronic component.

[0006] In one aspect, the above object can be achieved by a multilayer ceramic electronic component comprising: an element body having a substantially rectangular parallelepiped shape, the element body including a capacitive section formed by alternately stacking first internal electrode layers and second internal electrode layers with a dielectric layer sandwiched therebetween; and a protective section provided outside the capacitive section; and external electrodes formed on a surface of the element body so as to be spaced apart from each other, and from which the first internal electrode layers and the second internal electrode layers are extended, respectively; the dielectric layer and the protective section each contain a dielectric ceramic as a main component; the protective section includes a first layer adjacent to the capacitive section, a second layer adjacent to the first layer, and a third layer adjacent to the second layer; an atomic ratio of Mn contained in the second layer is higher than an atomic ratio of Mn contained in the first layer; and a glass component content of the second layer is higher than a glass component content of the first layer and a glass component content of the third layer.

[0007] In one aspect, the above-mentioned object is achieved by a method for manufacturing a multilayer ceramic electronic component, the method comprising the steps of: forming a laminate to serve as a capacitance section in which first internal electrode layers and second internal electrode layers are alternately stacked with dielectric layers sandwiched therebetween; providing a first layer adjacent to a surface in the laminate where the first internal electrode layer and the second internal electrode layer are exposed, a second layer adjacent to the first layer, and a third layer adjacent to the second layer to form a protective section, thereby producing an unfired element body; firing the element body; and forming external electrodes on the fired element body, wherein the dielectric layer and the protective section each contain a dielectric ceramic as a main component, and the second layer has a higher atomic ratio of Mn than the first layer, and the second layer has a higher content of glass component than the first layer and the third layer.

[0008] According to the present invention, it is possible to improve the reliability of a ceramic electronic component while ensuring the effective capacitance of the ceramic electronic component.

[0009] FIG. 1 is a perspective view of a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line A-A' in FIG. 1. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor taken along line B-B' in FIG. 1. FIG. 4 is an enlarged cross-sectional view of a portion of a side margin provided in the multilayer ceramic capacitor according to the embodiment. FIG. 5 is a flowchart showing an example of a method for manufacturing the multilayer ceramic capacitor according to the embodiment. FIG. 6 is a perspective view showing the manufacturing process of the multilayer ceramic capacitor according to the embodiment. FIG. 7 is a perspective view showing the manufacturing process of the multilayer ceramic capacitor according to the embodiment. FIGS. 8A to 8C are schematic cross-sectional views showing the manufacturing process of the multilayer ceramic capacitor according to the embodiment. FIG. 9 is a perspective view showing the manufacturing process of the multilayer ceramic capacitor according to the embodiment. FIG. 10 is a cross-sectional view of a multilayer ceramic capacitor according to a second embodiment taken along a cutting line corresponding to line A-A' in FIG. 1. FIG. 11 is a schematic cross-sectional view showing the manufacturing process of the multilayer ceramic capacitor according to the second embodiment.

[0010] First Embodiment A first embodiment of the present invention will be described below with reference to the drawings. The drawings show X-, Y-, and Z-axes that are orthogonal to each other as appropriate. The X-, Y-, and Z-axes are common to all the drawings.

[0011] [Overall Configuration of Multilayer Ceramic Capacitor 10] Figures 1 to 4 are diagrams showing a multilayer ceramic capacitor 10 according to a first embodiment of the present invention. Figure 1 is a perspective view of the multilayer ceramic capacitor 10. Figure 2 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along line A-A' in Figure 1. Figure 3 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along line B-B' in Figure 1. Figure 4 is an enlarged cross-sectional view of a portion of a side margin portion 19 included in the multilayer ceramic capacitor 10.

[0012] As illustrated in FIGS. 1 to 4 , the multilayer ceramic capacitor 10 includes an element body 11 having a substantially rectangular parallelepiped shape. The four surfaces of the element body 11 other than the top and bottom surfaces in the stacking direction are referred to as side surfaces. A first external electrode 14a and a second external electrode 14b are provided on two opposing side surfaces (a first side surface and a second side surface) of the element body 11. The first external electrode 14a extends from the first side surface to the four adjacent surfaces. The second external electrode 14b extends from the second side surface to the four adjacent surfaces. However, the first external electrode 14a and the second external electrode 14b are spaced apart from each other.

[0013] 1 to 3, the Z-axis direction (first direction) is the stacking direction, and is the direction in which the internal electrode layers face each other. The X-axis direction (second direction) is the length direction of the element body 11, and is the direction in which the first side surface and the second side surface of the element body 11 face each other, and is the direction in which the first external electrode 14a and the second external electrode 14b face each other. The Y-axis direction (third direction) is the width direction of the internal electrode layers, and is the direction in which two side surfaces (third and fourth side surfaces) other than the first and second side surfaces of the four side surfaces of the element body 11 face each other. The X-axis direction, Y-axis direction, and Z-axis direction are perpendicular to each other.

[0014] The element body 11 has a configuration in which dielectric layers 15 containing a ceramic material that functions as a dielectric and internal electrode layers are alternately stacked. The internal electrode layers include a plurality of first internal electrode layers 12 and a plurality of second internal electrode layers 13. The first internal electrode layers 12 and the second internal electrode layers 13 are alternately stacked with the dielectric layer 15 sandwiched therebetween. Edges of the first internal electrode layers 12 extend to a first side surface of the element body 11 on which a first external electrode 14a is provided. Edges of the second internal electrode layers 13 extend to a second side surface of the element body 11 on which a second external electrode 14b is provided. As a result, the first internal electrode layers 12 and the second internal electrode layers 13 are alternately electrically connected to the first external electrode 14a and the second external electrode 14b. As a result, the multilayer ceramic capacitor 10 has a configuration in which capacitor units are stacked. In addition, in a laminate of dielectric layers 15 and internal electrode layers, the internal electrode layers are arranged on the outermost layers in the lamination direction, and the upper and lower surfaces of the laminate are covered with cover portions 18. The cover portions 18 are mainly composed of a ceramic material. Note that the multilayer ceramic capacitor is not limited to the configurations shown in FIGS. 1 to 3 as long as the first internal electrode layers 12 and the second internal electrode layers 13 are exposed in different regions on the surface of the laminate and are electrically connected to different external electrodes. The different regions on the surface of the laminate may be respective surface regions on opposing faces of the laminate, respective surface regions on adjacent faces of the laminate, or different surface regions on the same face of the laminate. As long as the different external electrodes are spaced apart from each other, the first internal electrode layers 12 and the second internal electrode layers 13 may extend from the faces exposed in the surface region of the laminate to other faces.

[0015] The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes. The size of the multilayer ceramic capacitor 100 may be, for example, length > width ≥ height, width > length ≥ height, height > length ≥ width, or height > width ≥ length.

[0016] The element body 11 has a dielectric layer 15, a capacitance section 16 which is a laminate of first internal electrode layers 12 and second internal electrode layers 13, and a protective section 17. The protective section 17 forms the peripheral edge of the element body 11 and has two side surfaces opposing each other in the X-axis direction, two side surfaces 11b opposing each other in the Y-axis direction, and two main surfaces 11c opposing each other in the Z-axis direction. The two side surfaces opposing each other in the X-axis direction are sometimes called end faces 11a. The side surfaces 11b and the main surfaces 11c form multiple peripheral surfaces. The end faces 11a, the side surfaces 11b, and the main surfaces 11c are, for example, substantially flat surfaces, but may also be rounded.

[0017] The protective section 17 has a cover section 18, a side margin section 19, and an end margin section 20. The cover section 18 is a region on the outer side in the stacking direction with respect to the capacitance section 16. The side margin section 19 is a region on the outer side perpendicular to the stacking direction with respect to the capacitance section 16, where the first internal electrode layers 12 and the second internal electrode layers 13 are not drawn to the surface of the element body 11. The end margin section 20 is a region on the outer side perpendicular to the stacking direction with respect to the capacitance section 16, where at least one of the first internal electrode layers 12 and the second internal electrode layers 13 is drawn to the surface of the element body 11.

[0018] 1 to 3, the cover portion 18 is located outside the capacitive portion 16 in the Z-axis direction. The side margin portion 19 is located outside the capacitive portion 16 in the Y-axis direction. The end margin portion 20 is located outside the capacitive portion 16 in the X-axis direction. In FIGS. 1 to 3, the stacking direction is the Z-direction of the element body 11. Naturally, even if the stacking direction is the X-direction or the Y-direction, the cover portion 18, side margin portion 19, and end margin portion 20 included in the protective portion 17 can be defined appropriately.

[0019] The capacitance section 16 is disposed inside the protection section 17 and constitutes a functional section. The capacitance section 16 is formed by stacking a plurality of first internal electrode layers 12 and a plurality of second internal electrode layers 13 with dielectric layers 15 (see FIG. 2) interposed therebetween. In the configurations of FIGS. 1 to 3, the capacitance section 16 is stacked in the Z-axis direction. The internal electrode layers 12, 13 are both sheet-shaped extending in a direction perpendicular to the stacking direction, i.e., along the X-Y plane in the configurations of FIGS. 1 to 3, and are alternately arranged along the Z-axis direction. The configuration of the dielectric layers 15 will be described in detail later.

[0020] The first internal electrode layer 12 and the second internal electrode layer 13 are mainly composed of base metals such as nickel (Ni), copper (Cu), and tin (Sn), or alloys containing these. Precious metals such as platinum (Pt), palladium (Pd), silver (Ag), and gold (Au), or alloys containing these, may also be used as the main component of the first internal electrode layer 12 and the second internal electrode layer 13. The main component of the first internal electrode layer 12 and the main component of the second internal electrode layer 13 may be the same or different. When there is no particular need to distinguish between them, the first internal electrode layer 12 and the second internal electrode layer 13 may collectively be referred to as internal electrodes.

[0021] The dielectric layer 15 is, for example, a compound represented by the general formula ABO ３ The main phase is a ceramic material having a perovskite structure represented by the formula: ３－α (0≦α≦1: α represents an amount that deviates from the stoichiometric composition; hereinafter, α will be omitted.) For example, the ceramic material includes barium titanate (BaTiO ３ ), calcium zirconate (CaZrO３ ), calcium titanate (CaTiO ３ ), strontium titanate (SrTiO ３ ), magnesium titanate (MgTiO ３ ), Ba that forms a perovskite structure １-ｘ－ｙ Ca ｘ Sr ｙ Ti １－ｚ Zr ｚ O ３ (0≦x≦1, 0≦y≦1, 0≦z≦1) and the like. １-ｘ－ｙ Ca ｘ Sr ｙ Ti １－ｚ Zr ｚ O ３ Examples of the ceramic material include barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate, and barium calcium titanate zirconate. For example, the dielectric layer 15 contains 50 at% or more of the main component ceramic, e.g., 90 at% or more. The thickness of the dielectric layer 15 is, for example, 5.0 μm or less, 3.0 μm or less, 1.0 μm or less, 0.5 μm or less, 0.4 μm or less, 0.3 μm or less, or 0.2 μm or less. The thickness of the dielectric layer 15 can be measured by observing the cross section of the multilayer ceramic capacitor 100 with a scanning electron microscope (SEM), measuring the thickness at 10 points for each of 10 different dielectric layers 15, and deriving the average value of all the measurement points.

[0022] An additive may be added to the dielectric layer 15. Examples of additives to the dielectric layer 15 include oxides of zirconium (Zr), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (scandium (Sc), cerium (Ce), neodymium (Nd), yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0023] The protective portion 17 is also made of a dielectric ceramic. From the viewpoint of suppressing internal stress, it is preferable that the end margin portion 20 of the protective portion 17 has the same main component composition as the dielectric layer 15. In this embodiment, the cover portion 18 also has the same main component composition as the dielectric layer 15. This improves manufacturing efficiency.

[0024] Typically, the cover portion 18 and side margin portion 19 of the protective portion 17 do not contain internal electrodes, and therefore tend to have a lower density after compression bonding than the capacitance portion 16. Furthermore, the cover portion 18 and side margin portion 19 are hardly affected by the sintering of the metal elements contained in the internal electrodes during firing. The end margin portion 20 of the protective portion 17 includes the internal electrode layers 12 and 13 in part, but this proportion is smaller than that of the capacitance portion 16, and therefore tends to have a lower density after compression bonding than the capacitance portion 16. Furthermore, the effect of the metal elements contained in the internal electrode lead portions during firing is limited to the capacitance portion 16. In any case, the density of the protective portion 17 is unlikely to increase during firing, resulting in a difference in density between the capacitance portion 16 and the protective portion 17 after firing. As a result, the protective portion 17 tends to have low mechanical strength, which makes it prone to peeling and cracking. Furthermore, its lack of density allows moisture to penetrate from the outside, resulting in a shortened lifespan. To prevent such a deterioration in reliability, an element that promotes firing is added to the protective portion 17 .

[0025] In the protective section 17, the side margin section 19 has the same main component as the dielectric layer 15. However, unlike usual, in the present invention, the side margin section 19 includes a first layer 19a, a second layer 19b, and a third layer 19c, as shown in Figures 3 and 4. The first layer 19a is adjacent to the side surface 16b of the capacitance section 16 facing the Y-axis direction. The second layer 19b is adjacent to the first layer 19a. The third layer 19c is adjacent to the second layer 19b.

[0026] The first layer 19a is formed so that the difference in density between it and the dielectric layer 15 is small, and the first layer 19a is a layer that has the function of not affecting the grain growth of the dielectric material of the dielectric layer 15 on the first layer 19a side.

[0027] The second layer 19b is an intermediate layer that has the function of seamlessly connecting the layer that suppresses the grain growth of the dielectric on the first layer 19a side and the layer that promotes the grain growth of the dielectric on the first layer 19a side.

[0028] The third layer 19c is a layer that promotes grain growth of the dielectric material and also has the function of improving moisture resistance.

[0029] To achieve such a function, the first layer 19a, the second layer 19b, and the third layer 19c have the same main component as the dielectric layer of the capacitance section 16, but have different subcomponents or additive components.

[0030] Specifically, the first layer 19a can be defined as a layer in which the total concentration (atomic %) of magnesium (Mg), ytterbium (Yb), and erbium (Er) is greater than the concentration (atomic %) of Mn. Alternatively, specifically, the first layer 19a can be defined as a layer in which, when the ratio of the number of atoms in the A site to the number of atoms in the B site of the perovskite structure in the dielectric, i.e., the A / B ratio, is ((Ba+Sr+Ca) / (Ti+Zr+Hf)), the ratio ((Ba+Sr+Ca) / (Ti+Zr+Hf)) is either less than 0.96 or 1.02 or greater.

[0031] The second layer 19b can be defined as a layer in which the concentration (atomic %) of Mn is greater than the total concentration (atomic %) of Mg, Yb, and Er, and the concentration (atomic %) of Mn is greater than the total concentration (atomic %) of Mo, B, and Li.

[0032] The third layer 19c can be defined as a layer in which the total concentration (atomic %) of Mo, B, and Li is greater than the concentration (atomic %) of Mn.

[0033] The second layer 19b and the third layer 19c may contain glass components, and the concentration of the glass components (concentration of the portion where Si and B exist simultaneously: atomic %) may be second layer 19b > third layer 19c > first layer 19a.

[0034] The first layer 19a is a layer that is formed to have a small density difference with the dielectric layer 15 and has the function of not affecting the grain growth of the dielectric on the first layer 19a side of the dielectric layer 15. To achieve this function, in a first embodiment of the present invention, the first layer 19a can contain, in addition to the same main components as the dielectric layer 15, an element that promotes the densification of the first layer 19a while diffusing little into the dielectric layer 15 during firing. The element that promotes the densification of the first layer 19a while not affecting the grain growth of the dielectric layer 15 is an element that promotes the formation of a fine particle shape without causing large grain growth when sintering the first layer 19a, thereby increasing the density of the first layer 19a and eliminating the density difference with the dielectric layer 15, and that is also difficult to diffuse during firing. The low diffusion into the dielectric layer 15 during firing suppresses the effect of element diffusion toward the first layer 19a side of the dielectric layer 15 on the grain growth of the dielectric layer 15, which previously occurred.

[0035] Examples of such elements include elements selected from Mg, Yb, and Er, but other elements may also be used, and one or more of these elements may be added as appropriate. In a second embodiment of the present invention, such a function can be achieved by setting the ratio of the number of atoms in the A site and the B site of the perovskite structure in the dielectric of the first layer 19a, i.e., the A / B ratio, to be ((Ba + Sr + Ca) / (Ti + Zr + Hf)), such that ((Ba + Sr + Ca) / (Ti + Zr + Hf)) is less than 0.96 or 1.02 or greater. In the case of a dielectric with a perovskite structure having such an A / B ratio, the first layer 19a is sintered without undergoing significant grain growth, resulting in a fine particle form, thereby increasing the density of the first layer 19a and eliminating the density difference with the dielectric layer 15. In this second embodiment, it is preferable not to add elements that promote grain growth to the first layer 19a. By setting this A / B ratio when firing the first layer 19a, excessive grain growth can be suppressed, and as a result, dense grains can be formed, increasing the density of the first layer 19a and eliminating the density difference with the dielectric layer 15. Furthermore, since there are no elements present in the first layer 19a that promote grain growth, and elements do not diffuse into the dielectric layer 15 in the first place, the inhibition of grain growth caused by elements diffusing into the first layer 19a of the dielectric layer 15, which has conventionally occurred, is suppressed.

[0036] The ratio of the number of atoms in the A site to the number of atoms in the B site of the perovskite structure in the dielectric, i.e., the A / B ratio, can be observed by mapping the elements to be measured using, for example, TEM-EDS (Transmission Electron Microscope-Energy Dispersive X-ray Spectroscopy). For observation, a JEOL JEM-ARM200 or the like can be used.

[0037] The first layer 19a may contain a Cu component. It is believed that the inclusion of a Cu component in the first layer 19a improves the life of the multilayer ceramic capacitor 10. As will be described in detail later, the first layer 19a is formed by firing an unfired first layer 119a (see FIG. 9 , etc.). When the Cu component diffuses into the internal electrode layers 12, 13 in contact with the unfired first layer 119a, the interface between the Ni contained in the internal electrode layers 12, 13 and the dielectric of the capacitance section 16 is strengthened, thereby improving the IR (insulation resistance). This is believed to improve the life of the multilayer ceramic capacitor 10. The Cu component can be, for example, CuO.

[0038] The first layer 19a is a dense layer, and therefore the average particle size of the particles forming the first layer 19a is smaller than the average particle size of the particles forming the second layer 19b, which is also smaller than the average particle size of the particles forming the third layer 19c.

[0039] Regardless of the external size of the multilayer ceramic capacitor 10, the average grain size of the first layer 19a can be greater than 0 μm and not greater than 5 μm. The average grain size of the second layer 19b can be greater than 0 μm and not greater than 15 μm. The average grain size of the third layer 19c can be greater than 0 μm and not greater than 30 μm. Furthermore, when the multilayer ceramic capacitor 10 is larger than the 0603 size, for example, the average grain size of the first layer 19a can be greater than 0 μm and not greater than 7 μm, the average grain size of the second layer 19b can be greater than 0 μm and not greater than 15 μm, and the average grain size of the third layer 19c can be greater than 0 μm and not greater than 45 μm. Furthermore, for example, the average grain size of the first layer 19a can be greater than 0 μm and not greater than 10 μm, the average grain size of the second layer 19b can be greater than 0 μm and not greater than 20 μm, and the average grain size of the third layer 19c can be greater than 0 μm and not greater than 60 μm.

[0040] In either case, it is desirable that the average particle diameter of each layer be such that the average particle diameter of the first layer 19 a is smaller than the average particle diameter of the second layer 19 b and smaller than the average particle diameter of the third layer 19 c. This relationship in average particle diameter allows for close contact with the capacitance section, prevents peeling between the layers, and provides a highly reliable structure.

[0041] The average particle diameter of each layer can be measured as follows. First, a cross section of the multilayer ceramic capacitor 10 is polished so that a plane including the axis of the stacking direction (first direction) can be observed. The multilayer ceramic capacitor 10 is observed using a field-emission scanning secondary electron microscope (FE-SEM) equipped with an energy-dispersive X-ray spectrometer (EDS). Regions that appear bright due to contrast differences in the SEM image are identified as internal electrodes (first internal electrode portion 12 or second internal electrode portion 13). This identifies the region of the capacitance portion, and the area outside of this is identified as the protective portion. An observation region is set in the dielectric region of the protective portion, which is the outer portion perpendicular to the stacking direction of the capacitance portion. EDS mapping is performed on this observation region to measure the presence of Ni, Ba, Ti, O, Mn, Mo, Yb, Er, Mg, Si, and, if necessary, other elements. The amounts of these elements are calculated as atomic percent relative to the overall composition at each point. The definitions of the first, second, and third layers allow the boundaries of each layer to be identified. For the measurements, a Hitachi High-Technologies FE-SEM (SU7000) was used as a field emission scanning secondary electron microscope, and a Quantax manufactured by BRUKER Corporation was used as an EDS detector.

[0042] The average grain size of the first layer 19a, the second layer 19b, and the third layer 19c was measured using secondary electron images. The observation area of ​​the portion of the protective layer closest to the capacitance section 16 was designated the observation area for the first layer 19a, and the observation area of ​​the outermost portion was designated the observation area for the third layer 19c. For the second layer 19b, the observation area was selected to be the portion with the highest Mn content and designated the second layer 19b as the observation area. Three observation areas were photographed for each layer. The average grain size was measured by measuring the area of ​​each grain within the field of view using image processing measurement software, calculating the diameter of a circle with the same area (Heywood diameter), and then calculating the average value from these. The average value of the measurements of the three observation areas photographed by SEM for each layer can be used to determine the average grain size for each layer of the sample. Note that the method for calculating the average grain size described here is merely an example, and other methods may also be used.

[0043] The first layer 19 a forms a dense film, which increases the contact area between the capacitor 16 and the dielectric layer 15 , making it easier to adhere to the capacitor 16 .

[0044] The second layer 19b is an intermediate layer that seamlessly connects the layer that suppresses dielectric grain growth on the first layer 19a side with the layer that promotes dielectric grain growth on the first layer 19a side. The second layer 19b is characterized by containing the same main components as the dielectric layer 15, as well as manganese (Mn) and glass components. First, let us explain the Mn component contained in the second layer 19b. The Mn component suppresses grain growth and densifies the sintering process, and is more effective than Mg, Yb, and Er, which have similar effects. However, because Mn diffuses over a wide area during sintering, adding it to the first layer 19a would also diffuse into the adjacent dielectric layer 15, suppressing the grain growth of the dielectric on the first layer 19a side of the dielectric layer 15 and resulting in a decrease in capacitance. For this reason, Mn is not suitable as an element to be added to the first layer 19a.

[0045] The present invention is characterized in that Mn is added to the second layer 19b sandwiching the first layer 19a between the dielectric layers 15. Even if the Mn diffuses during firing, the first layer 19a, which did not contain the Mn before firing, exerts a buffer effect, preventing the Mn from reaching the dielectric on the first layer 19a side of the dielectric layer 15. This prevents grain growth in this area from being suppressed, and therefore does not cause a decrease in capacitance. The second layer 19b, to which the Mn, which has a densifying effect, is added, becomes a dense layer. Furthermore, the first layer 19a, into which the Mn has diffused by firing, can be made denser by combining it with magnesium (Mg), ytterbium (Yb), and erbium (Er) than a layer without the Mn diffused. As will be described later, the sinterability is improved due to the effect of the glass component contained in the second layer 19b, and the density of the second layer 19b increases due to excessive grain growth of the dielectric. In order to reduce the density difference with the dielectric layer 15, the density difference with the first layer 19a, which suppresses grain growth, is prevented from increasing, and it is possible to prevent discontinuity in mechanical strength and the occurrence of peeling, cracks, etc.

[0046] The Mn content of the second layer 19b is higher than that of the first layer 19a. The Mn content can be compared based on the atomic ratio of Mn in each layer. That is, the Mn atomic ratio in the second layer 19b is higher than that in the first layer 19a. The first layer 19a may contain Mn, but the Mn content of the first layer 19a is 0% or more and 100% or less of the Mn content of the second layer 19b. Since the Mn content of the first layer 19a is 0% or more of the Mn content of the second layer 19b, the first layer 19a may not contain Mn. The content comparison may be expressed by the concentration distribution of each component.

[0047] The content and concentration of each elemental component were measured as follows. The multilayer ceramic capacitor 10 was cross-sectionally polished to expose a surface including the axis of the stacking direction (first direction). The surface was then observed using a field-emission scanning secondary electron microscope (FE-SEM) equipped with an energy-dispersive X-ray spectrometer (EDS). Regions that appeared bright due to contrast differences in the SEM image were identified as the internal electrodes (first internal electrode portion 12 or second internal electrode portion 13). This identified the region of the capacitance portion 16, and the area outside of this was identified as the protective portion. An observation region was set in the dielectric region of the protective portion, which is the outer portion perpendicular to the stacking direction of the capacitance portion. EDS mapping was performed on this observation region to measure the presence of Ni, Ba, Ti, O, Mn, Mo, Yb, Er, Mg, Si, and, if necessary, other elements. The amounts of these elements were calculated as atomic percent relative to the overall composition at each point. The definitions of the first, second, and third layers allow the boundaries of each layer to be identified. The average of the observation areas in three locations in each layer can be used to determine the average content and average concentration of that layer. The observation area may be the same as the observation area set when measuring the average particle size. For the measurements, a Hitachi High-Technologies FE-SEM (SU7000) was used as the field emission scanning secondary electron microscope. A Quantax EDS detector from BRUKER Corporation was used.

[0048] In the first layer 19a, there is a concern that the diffusion of Mn into the element body 11 will reduce the grain size of the dielectric ceramic in the element body 11, thereby reducing the effective capacitance. Therefore, it is desirable to reduce the Mn content in the first layer 19a so that the Mn content does not diffuse into the element body 11. On the other hand, it is expected that grain growth near the element body 11 will result in a reduction in lifespan, for example, as confirmed by the results of a Highly Accelerated Limit Test (HALT) test. Therefore, it is desirable to include an appropriate amount of Mn in the second layer 19b to a degree that does not contribute to the grain growth of the dielectric ceramic in the element body 11, i.e., to diffuse Mn only from the second layer 19b to the first layer 19a and prevent Mn from diffusing into the element body 11. In other words, it is desirable to set the concentration gradient of the Mn content in the first layer 19a to be smaller than the concentration in the second layer 19b. The Mn content of the first layer 19a is preferably 80% or less of the Mn content of the second layer 19b, more preferably 60% or less, and even more preferably 30% or less.

[0049] Next, the glass component contained in the second layer 19b will be described. The glass component may be any low-melting-point component that forms a liquid phase when the element body 11 is fired, and may include, for example, silicon or boron. The presence and concentration of each element component can be identified and measured using the same method as for the Mn component. A portion where silicon and boron, elements contained in glass, are simultaneously observed at the same observation point is considered to be a portion where glass is present. The combined concentration of silicon and boron is considered to be the concentration of the glass component. In the second layer 19b, a liquid phase composed of the glass component is expelled from the crystal grains during firing, resulting in a fine structure in which the glass phase segregates at the grain boundaries.

[0050] Furthermore, in the second layer 19b in which a glass phase is precipitated at the grain boundaries, the generation of a liquid phase during firing results in high sinterability and a structure with few voids between particles. The simultaneous presence of Mn and glass in the second layer 19b results in particles with suppressed grain growth arranged densely, resulting in a layer with few voids between particles. This results in a highly reliable structure that prevents the intrusion of moisture, etc.

[0051] The third layer 19c is a layer that promotes grain growth of the dielectric. Because the first layer 19a and the second layer 19b are sandwiched between the third layer 19c and the dielectric layer 15, grain growth of the dielectric within the third layer 19c can occur without affecting the dielectric of the dielectric layer 15. The third layer 19c functions to improve moisture resistance. The third layer 19c also contains a glass component. The glass component contained in the third layer 19c may be a low-melting-point component that forms a liquid phase when the element body 11 is fired, and may include, for example, silicon or boron. The glass component content of the second layer 19b is higher than the glass component content of the third layer 19c. By making the glass component content of the second layer 19b higher than the glass component content of the third layer 19c, the glass component that diffuses from the second layer 19b during firing diffuses into the third layer 19c. The third layer 19c may already contain a small amount of glass component before firing. The glass component contained in the third layer 19c may be the same as or different from the glass component contained in the second layer 19b. The glass component liquefies during firing to form a dielectric layer with few voids (pores). Furthermore, the glass component liquefies and diffuses into any small voids (pores) that may have formed. After firing, the glass component fills the voids (pores) in the third layer 19c upon cooling. This improves the moisture resistance of the third layer 19c. Because the third layer 19c is located as the outermost layer of the side margin portion 19, the improved moisture resistance of the third layer 19c improves the moisture resistance of the multilayer ceramic capacitor 10.

[0052] The third layer 19c can contain an element that promotes grain growth. The element that promotes grain growth refers to an element that promotes sintering, but not an element that promotes densification, that causes grain growth, such that multiple particles grow into integrated particles. Examples of elements that promote grain growth include molybdenum (Mo), B (boron), and Li (lithium). It is desirable that elements that cause grain growth are not contained in the first layer 19a and the second layer 19b before sintering. This is because even if elements that cause grain growth diffuse during sintering, the first layer 19a and the second layer 19b act as a buffer, preventing diffusion into the dielectric layer 15 and thus not affecting capacitance. The content of elements that promote grain growth in each layer after sintering is in the following order: first layer 19a < second layer 19b < third layer 19c. The element that promotes grain growth added to the third layer 19c can improve reliability, similar to glass components.

[0053] For example, when the size of the multilayer ceramic capacitor 10 is 0603 size (0.6 mm × 0.3 mm × 0.3 mm), the thickness of each layer can be as follows: The thickness t[19a] of the first layer 19a can be greater than 0 μm and less than 10 μm. The thickness t[19b] of the second layer 19b can be greater than 0 μm and less than 20 μm. The thickness t[19c] of the third layer 19c can be greater than 0 μm and less than 60 μm. Note that the thickness of each layer is measured along the Y-axis direction. The thickness of each layer can be changed as appropriate depending on the size of the multilayer ceramic capacitor 10, but the thickness of each layer can be such that the thickness t[19a] of the first layer 19a < the thickness t[19b] of the second layer 19b < the thickness t[19c] of the third layer 19c. The thickness of each layer can be compared by comparing the maximum thicknesses or the average thicknesses. The relationship between the thickness of each layer can be derived from the average particle size of the particles constituting each layer and the number of particles required for each layer. If each layer is composed of a single particle, it tends to be a layer with many paths for moisture and other substances to penetrate. For this reason, it is desirable that each layer be composed of 2 to 5 particles in the thickness direction of the layer, and when considering the continuity of mechanical strength such as peeling between each layer, it is even more desirable that each layer be composed of 3 to 5 particles in the thickness direction of the layer.

[0054] The external electrodes 14a, 14b have an undercoat film 21 formed to cover the surface of the protective portion 17 drawn out from the internal electrode, and a plating film 22 formed on the undercoat film 21. In the cases of FIGS. 1 to 3 , the undercoat film 21 is formed to cover the end face 11a, and the plating film 22 is formed on the undercoat film 21. The undercoat film 21 is formed, for example, by baking a conductive paste or by sputtering. The plating film 22 is formed by electrolytic plating. Each film of the external electrodes 14a, 14b is formed of a metal or alloy containing, for example, nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), or the like as a main component.

[0055] [Method of Manufacturing Multilayer Ceramic Capacitor 10] Fig. 5 is a flowchart showing a method of manufacturing the multilayer ceramic capacitor 10. Figs. 6 to 9 are diagrams schematically showing the manufacturing process of the multilayer ceramic capacitor 10. The method of manufacturing the multilayer ceramic capacitor 10 will be described below in accordance with the flowchart shown in Fig. 5, with appropriate reference to Figs. 6 to 9.

[0056] (Step S01: Fabrication of ceramic laminated chip C) In step S01, ceramic sheets 101 and 102 for forming the capacitance section 16 and ceramic sheet 103 for forming the cover section 18 are stacked and cut to fabricate an unfired ceramic laminated chip (laminated chip) C.

[0057] Prior to fabricating the ceramic laminated chip C, a dielectric material is prepared. The A-site elements and B-site elements contained in the dielectric layer 15 are usually ABO ３The dielectric layer 15 contains barium titanate in the form of a sintered body of particles. For example, barium titanate is a tetragonal compound with a perovskite structure and exhibits a high relative dielectric constant. This barium titanate can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known for synthesizing the ceramic that is the main component of the dielectric layer 15, including the solid-phase method, the sol-gel method, and the hydrothermal method. Any of these methods can be used in this embodiment.

[0058] A predetermined additive compound is added to the obtained ceramic raw material powder depending on the purpose. Examples of the additive compound include oxides of zirconium (Zr), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (scandium (Sc), cerium (Ce), neodymium (Nd), yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), and glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0059] For example, a ceramic material is prepared by wet-mixing a ceramic raw material powder with a compound containing an additive compound, followed by drying and pulverization. For example, the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. A dielectric material is obtained by the above process.

[0060] The ceramic sheets 101, 102, and 103 shown in FIG. 6 are unsintered dielectric green sheets containing a dielectric material made of a dielectric ceramic, an organic binder, and other additives. An unsintered first internal electrode pattern 112 corresponding to the first internal electrode layer 12 is formed on the ceramic sheet 101. An unsintered second internal electrode pattern 113 corresponding to the second internal electrode layer 13 is formed on the ceramic sheet 102. No internal electrodes are formed on the ceramic sheet 103. The ceramic sheets 101, 102, and 103 can be obtained as follows: A binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained raw material powder and wet-mixed. The obtained slurry is used to coat a ceramic green sheet 51 on a substrate, for example, by a die coater method or a doctor blade method, and then dried. The substrate is, for example, a polyethylene terephthalate (PET) film.

[0061] The first internal electrode layer 12 and the second internal electrode layer 13 are primarily composed of base metals such as nickel (Ni), copper (Cu), and tin (Sn), or alloys containing these metals. Precious metals such as platinum (Pt), palladium (Pd), silver (Ag), and gold (Au), or alloys containing these metals, may also be used. Therefore, a metal conductive paste for forming the internal electrodes is prepared containing these materials and an organic binder. The internal electrode patterns 112 and 113 have multiple strip-shaped electrode patterns that cross a cutting line Lx parallel to the X-axis direction and extend along a cutting line Ly parallel to the Y-axis direction. These internal electrode patterns 112 and 113 are formed by printing the metal conductive paste using screen printing, gravure printing, or the like. The internal electrode formation method is not limited to printing; plating, vacuum deposition, sputtering, and CVD may also be used.

[0062] As shown in Fig. 6, the ceramic sheets 101 and 102 are alternately stacked in the Z-axis direction. The stack of ceramic sheets 101 and 102 corresponds to the capacitance section 16 and the end margin section 20. The ceramic sheet 103 is stacked on the upper and lower surfaces in the Z-axis direction of the unfired stack of ceramic sheets 101 and 102. The stack of ceramic sheets 103 corresponds to the cover section 18. The number of stacked ceramic sheets 101, 102, and 103 can be adjusted as appropriate.

[0063] Next, the laminate of the ceramic sheets 101, 102, and 103 is pressed together in the Z-axis direction and cut along the cutting lines Lx and Ly, thereby producing the laminated chip C shown in FIG.

[0064] The laminated chip C has an unsintered capacitance portion 116 on which unsintered internal electrode patterns 112, 113 are formed, an unsintered cover portion 118, and an unsintered end margin portion 120. The laminated chip C has a side surface Cb which is a cut surface corresponding to the cutting line Lx, and an end surface Ca which is a cut surface corresponding to the cutting line Ly. Ends of the unsintered internal electrode patterns 112, 113 are exposed from the side surface Cb.

[0065] (Step 02: Forming Side Margins 119) In step S02, side margins 119 are formed on the side surfaces Cb of the stacked chips C. An example of a forming method will be described below.

[0066] The side margin portion 119 includes an unfired first layer 119a, a second layer 119b, and a third layer 119c. In this embodiment, the first layer 119a, the second layer 119b, and the third layer 119c are formed in that order on each side surface Cb using a paste dip method. Note that, in this embodiment, the laminated chip C can be debindered before the side margin portion 119 is formed. By completing the debindering process, a sheet or paste that serves as a protective portion can fill the binder-free areas. This improves the adhesive strength of each layer. The debindering process can be performed before (Step S03: Firing), which will be described later, or simultaneously with the process (Step S03: Firing).

[0067] First, as shown in Fig. 8A, a first layer 119a is formed on one side surface Cb. Next, as shown in Fig. 8B, a second layer 119b is formed to cover the first layer 119a. Then, as shown in Fig. 8C, a third layer 119c is formed to cover the second layer 119b.

[0068] After the first layer 119 a, the second layer 119 b, and the third layer 119 c are formed on one side surface Cb, the first layer 119 a, the second layer 119 b, and the third layer 119 c are formed on the other side surface Cb in the same manner, thereby producing the unsintered ceramic body 111 shown in FIG.

[0069] The first layer 119a, the second layer 119b, and the third layer 119c may each be formed by attaching a ceramic sheet.

[0070] The first layer 119a is primarily composed of a ceramic material made of dielectric ceramics, and contains one or more elements selected from Mg, Yb, and Er, as well as other additives, but does not contain Mn. The second layer 119b is primarily composed of a ceramic material made of dielectric ceramics, and contains a Mn component, a glass component, and other additives. The third layer 119c is primarily composed of a ceramic material made of dielectric ceramics, and contains a glass component and other additives such as Mo, BN, and Si. All of the first layer 119a, the second layer 119b, and the third layer 119c contain a binder. The first layer 119a does not contain a Mn component before firing. In this case, the concentration gradient of the Mn component after firing is first layer 119a < second layer 119b.

[0071] (Step S03: Firing) In step S03, the ceramic body 111 obtained in step S02 is fired to produce the ceramic body 11 of the multilayer ceramic capacitor 10 shown in FIG. 1. The firing temperature in step S03 can be determined based on the sintering temperature of the ceramic body 111. Firing can be performed, for example, in a reducing atmosphere or a low-oxygen partial pressure atmosphere. For example, in an atmosphere where the oxygen partial pressure is 10 －５ ~10 －８ The mixture is baked in a reducing atmosphere at a pressure of 1000 to 1300° C. for 5 minutes to 10 hours.

[0072] One or more elements of Mg, Yb, and Er contained in the first layer 119a promote densification, but are difficult to diffuse during firing and therefore are unlikely to affect the grain growth of the dielectric within the laminated chip C. Furthermore, Mn is a densification component that is easily diffused during firing, but since the first layer 119a does not contain Mn, it does not affect the grain growth of the dielectric within the laminated chip C. As a result, the grain growth of the dielectric of the laminated chip C adjacent to the first layer 119a is not inhibited. As a result, the effective capacitance of the capacitive section 16 formed after firing is ensured.

[0073] The second layer 119b contains Mn. Mn diffuses toward the stacked chip C, but because the first layer 19a is interposed between the stacked chip C and the second layer 119b, Mn is less likely to reach the stacked chip C. As a result, the effective capacitance of the capacitor 16 formed after firing is ensured. The second layer 119b also contains a glass component. The glass component is less likely to diffuse into the first layer 119a, which is a dense layer. Therefore, the glass component diffuses mainly into the third layer 119c. The glass component diffused into the third layer 119c fills voids (pores) in the third layer 119c. This densifies the third layer 119c and improves moisture resistance.

[0074] (Step S04: Formation of Base Film) In step S04, a conductive base film 21 is formed on the end faces 11a, side faces 11b, and main surface 11c shown in FIGS.

[0075] The undercoat film 21 is formed by applying unfired electrode material to the end surface 11a, the side surface 11b, and the main surface 11c. The application method is, for example, a dipping method, but other conventionally known methods such as printing and sputtering, or a combination of these, may also be used. The unfired electrode material is then baked. The baking can be performed, for example, in a reducing atmosphere or a low oxygen partial pressure atmosphere.

[0076] (Step S05: Plating Film Formation) In step S05, electrolytic plating is performed by immersing the multilayer ceramic capacitor 10 on which the base film 21 has been formed in a plating solution for forming the plating film 22. In this way, the plating film 22 is formed.

[0077] In this manner, the multilayer ceramic capacitor 10 shown in FIGS. 1 to 3 is manufactured.

[0078] In forming the side margin portion 119 in step S02, when preparing the ceramic material made of dielectric ceramic for the first layer 119a, a dielectric material that does not contain one or more elements selected from Mg, Yb, and Er and does not contain Mn may be prepared and used. The other steps can be the same as when one or more elements selected from Mg, Yb, and Er are included. That is, when the ratio of the number of atoms in the A site and the B site of the perovskite structure in the first layer 119a, i.e., the A / B ratio, is ((Ba + Sr + Ca) / (Ti + Zr + Hf)), the first layer 119a can be prepared in such a ratio that the layer satisfies either ((Ba + Sr + Ca) / (Ti + Zr + Hf)) is less than 0.96 or 1.02 or greater. In this case, too, the influence of Mn contained in the second layer 119b on the capacitance portion can be eliminated, and the dense first layer 119a can provide a multilayer ceramic capacitor 10 with excellent adhesion to the capacitance portion.

[0079] Second Embodiment Next, a multilayer ceramic capacitor 50 according to a second embodiment will be described. Fig. 10 is a cross-sectional view of the multilayer ceramic capacitor 50 according to the second embodiment taken along a cutting line corresponding to line A-A' in Fig. 1. Fig. 11 is a schematic cross-sectional view showing a manufacturing process for the multilayer ceramic capacitor 50 according to the second embodiment.

[0080] 10 , the cover portion 18 included in the protective portion 17 includes a first layer 18a, a second layer 18b, and a third layer 18c. That is, the multilayer ceramic capacitor 50 of the second embodiment includes a cover portion 18 having a three-layer structure, similar to the side margin portion 19. The components forming the first layer 18a, the second layer 18b, and the third layer 18c included in the cover portion 18 are the same as the components forming the first layer 19a, the second layer 19b, and the third layer 19c included in the side margin portion 19, respectively. Therefore, the first layer 18a, the second layer 18b, and the third layer 18c included in the cover portion 18 have the same functions as the first layer 19a, the second layer 19b, and the third layer 19c included in the side margin portion 19.

[0081] 11, the first layer 18a, the second layer 18b, and the third layer 18c are formed by laminating ceramic sheets 103a, 103b, and 103c as the ceramic sheet 103. The ceramic sheet 103a corresponds to the first layer 18a. The ceramic sheet 103b corresponds to the second layer 18b. The ceramic sheet 103c corresponds to the third layer 18c.

[0082] Thereafter, the multilayer ceramic capacitor 50 of the second embodiment can be obtained through the same steps as those of the first embodiment.

[0083] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

[0084] In the above embodiment, the multilayer ceramic capacitor 10 has been described as an example of a multilayer ceramic electronic component, but the present invention is applicable to all multilayer ceramic electronic components in which dielectric layers and internal electrodes are stacked. Examples of such multilayer ceramic electronic components include chip varistors and chip thermistors.

[0085] REFERENCE SIGNS LIST 10, 50... Multilayer ceramic capacitor 11... Ceramic body 11a... End face 11b... Side face 11c... Main surface 12, 13... Internal electrode 14... External electrode 17... Protective portion 18... Cover portion 18a... First layer 18b... Second layer 18c... Third layer 19... Side margin portion 19a... First layer 19b... Second layer 19c... Third layer 21... Undercoat film 22... Plating film

Claims

1. A multilayer ceramic electronic component comprising: a substantially rectangular parallelepiped element body including a capacitive section formed by alternately stacking first and second internal electrode layers with a dielectric layer therebetween, and a protective section provided on the outside of the capacitive section; and external electrodes formed on a surface of the element body so as to be spaced apart from each other, to which the first internal electrode layer and the second internal electrode layer are respectively extended, wherein the dielectric layer and the protective section are each primarily composed of dielectric ceramics, and the protective section includes a first layer adjacent to the capacitive section, a second layer adjacent to the first layer, and a third layer adjacent to the second layer, wherein the Mn atomic ratio in the second layer is higher than the Mn atomic ratio in the first layer, and the glass component content of the second layer is higher than the glass component content of the first layer and the glass component content of the third layer.

2. The multilayer ceramic electronic component according to claim 1, wherein the first layer contains at least one element selected from the group consisting of Mg, Yb and Er, and the total content of said elements is greater than the Mn content in the first layer.

3. The multilayer ceramic electronic component according to claim 1 or 2, wherein the Mn content in the second layer is greater than the total content of Mg, Yb, and Er.

4. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the third layer contains at least one element selected from the group consisting of Mo, B and Si, and the total content of the elements Mo, B and Si in the third layer is greater than the Mn content.

5. The multilayer ceramic electronic component according to claim 1, wherein the content of the component in said first layer is 0% or more and 100% or less of the content of the component in said second layer.

6. The multilayer ceramic electronic component according to claim 1, wherein the first layer contains a Cu component.

7. The multilayer ceramic electronic component according to claim 1, wherein when the A / B ratio, which is the ratio of the number of atoms at the A site and the B site of the perovskite structure in the first layer is ((Ba+Sr+Ca) / (Ti+Zr+Hf)), is less than 0.96 or is 1.02 or greater.

8. The monolithic ceramic electronic component according to claim 1, wherein the protective portion comprises at least one of a side margin portion and a cover portion.

9. A method for manufacturing a multilayer ceramic electronic component, comprising: a step of forming a laminate to serve as a capacitive section in which first internal electrode layers and second internal electrode layers are alternately stacked with a dielectric layer therebetween; a step of forming a protective section by providing a first layer adjacent to a surface of the laminate where the first internal electrode layer and the second internal electrode layer are exposed, a second layer adjacent to the first layer, and a third layer adjacent to the second layer in order to produce an unsintered element body; a step of firing the element body; and a step of forming an external electrode on the sintered element body, wherein the dielectric layer and the protective section are each primarily composed of dielectric ceramics, the atomic ratio of Mn in the second layer is higher than the atomic ratio of Mn in the first layer, and the glass component content of the second layer is higher than the glass component content of the first layer and the glass component content of the third layer.

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