Audio clock adjustment for multi-channel audio data output in network-based public address

Abstract

A method for audio clock adjustment in a network-based public address (PA) is disclosed. The disclosed method comprises the steps of: generating an audio clock signal on the basis of the occupancy level of an audio buffer in which digital audio data received through a network is buffered; and providing the digital audio data from the audio buffer according to the generated audio clock signal, wherein the step of generating the audio clock signal includes the steps of: generating a first audio clock signal as an audio clock signal from an oscillating clock signal if the occupancy level indicates that a first amount of digital audio data remains in the audio buffer; and setting a clock divisor on the basis of the occupancy level if the occupancy level indicates that a second amount differing from the first amount of the digital audio data remains in the audio buffer, and generating a second audio clock signal as the audio clock signal from a finite state machine (FSM) clock signal.

Description

Audio clock adjustment for multi-channel audio data output in network-based public address broadcasting.

[0001] The present disclosure relates to audio clock adjustment in a network-based public address (PA), and more particularly, to audio clock adjustment for multi-channel audio data output in a network-based PA.

[0002] A public address (PA) system is installed in a building or complex, such as an apartment complex, school, government office, large building, airport, shopping mall, etc., and is configured to transmit sounds (e.g., announcements, background music, etc.) at a volume level that can be heard by people over a wide area. Sometimes, this system is also equipped with the function of performing emergency broadcasts to notify people of an emergency situation (e.g., fire, explosion, flood, power outage, earthquake, etc.) that has occurred in or around the environment in which it is installed. Various devices are installed in each desired area (e.g., a company branch) for these PA broadcasts.

[0003] Recently, many PA systems have been implemented on a large scale, with multiple regional facilities connected via a network. In such systems, audio data for the PA may not be received at a uniform rate across the network, potentially resulting in latency at the receiving end.

[0004] In this regard, the applicant has proposed an audio clock adjustment in a network-based PA in Korean Patent No. 10-2400936. The proposed method involves outputting audio data in accordance with an audio clock signal whose clock rate is adjusted based on how much digital audio data received over the network remains in the audio buffer, thereby preventing data loss and suppressing the occurrence of latency. The inventors have recognized that there is room for introducing several improved configurations to help implement such a method in hardware, such as a programmable logic device such as a Field Programmable Gate Array (FPGA), or other types of logic circuits, without excessive manufacturing cost.

[0005] Audio clock adjustment in network-based public address broadcasting is disclosed in this document.

[0006] In an example, a device for audio clock adjustment in a network-based public address (PA) broadcasting system includes an audio clock adjustment unit for generating an audio clock signal based on an occupancy level of an audio buffer in which digital audio data received through a network is buffered, and an audio data formatting unit for providing digital audio data from the audio buffer according to the generated audio clock signal, wherein the generating of the audio clock signal comprises: generating a first audio clock signal as the audio clock signal from an oscillating clock signal having an oscillating clock frequency, when the occupancy level indicates that a first amount of digital audio data remains in the audio buffer, the first audio clock signal having a specific clock rate less than or equal to the oscillating clock frequency; and, when the occupancy level indicates that a second amount different from the first amount of digital audio data remains in the audio buffer, setting a clock divisor greater than 1 based on the occupancy level and a given sample of the digital audio data. Setting a sample rate to one of a plurality of integers determined for the rate (sample rate) and generating a second audio clock signal as an audio clock signal from a finite state machine (FSM) clock signal having a FSM clock frequency (the second audio clock signal having a different clock rate corresponding to the determined clock divisor).

[0007] The foregoing Summary is provided to introduce some aspects in a simplified form that are further described in the Detailed Description. This Summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to determine the scope of the claimed subject matter. Furthermore, the claimed subject matter is not limited to implementations that provide any or all of the advantages discussed herein.

[0008] According to the present disclosure, by buffering audio data received through a network and subsequently outputting the audio data in accordance with an audio clock signal having a variable clock rate, loss of original audio data, such as data discarding due to excessive buffering or data insertion due to insufficient buffering, can be prevented, and occurrence of latency can also be suppressed.

[0009] According to the present disclosure, a clock signal for outputting audio data can be generated in a cost-effective manner with a less complex hardware design, without a network switch supporting a transmission protocol such as Precision Time Protocol.

[0010] According to the present disclosure, in a network-based PA, even if the number of channels carried on audio data is relatively large and the FSM clock frequency available in the underlying hardware for audio clock adjustment is limited, the difference between two adjacent clock rates among the possible clock rates of an audio clock signal may not change abruptly, and thus excessively frequent switching of clock rates and unsmooth audio reproduction may be suppressed.

[0011] Figure 1 shows an example of audio communication for a public address (PA) in a networked environment.

[0012] FIG. 2 is a block diagram showing an example of a network-based PA system in which the network-based PA receiver of FIG. 1 is implemented.

[0013] Figure 3 is a block diagram showing an example of the local PA subsystem of Figure 2.

[0014] FIG. 4 is a block diagram showing an example of the network-based PA receiver of FIG. 1.

[0015] FIG. 5 is a diagram showing an example of a finite state machine (FSM) driven by the exemplary operation of the audio clock adjustment unit of FIG. 4.

[0016] Figure 6 is a diagram showing an example of a bit clock pulse generated by driving the FSM of Figure 5.

[0017] Figure 7 is a flowchart showing an example of a process for audio clock adjustment in a network-based PA.

[0018] The various terms used in this disclosure are selected from common terminology, taking into account their functions in this document. However, their meanings may vary depending on the intent of those skilled in the art, prevailing practices, or the emergence of new technologies. In certain instances, some terms may have meanings as described in the detailed description. Therefore, the terms used in this document should be defined consistently with their meaning within the context of this disclosure, rather than simply by their name.

[0019] In this document, the terms "comprise," "include," and "have" are used to specify the presence of elements listed later, such as certain features, numbers, steps, operations, components, information, or combinations thereof. Unless otherwise indicated, these terms and variations thereof are not intended to exclude the presence or addition of other elements.

[0020] As used herein, the terms "first," "second," and the like are intended to identify several similar elements. Unless otherwise specified, such terms are not intended to impose limitations, such as a specific order of use of these elements, but are merely used to refer to multiple elements separately. For example, an element may be referred to in one instance by the term "first," while the same element may be referred to in another instance by a different ordinal number, such as "second" or "third." In such instances, these terms do not limit the scope of the present disclosure. Furthermore, the use of the term "and / or" in a list of multiple elements includes any one or more of the listed items, as well as all possible combinations of those items. Furthermore, the singular form "a," "an," and the like include the plural unless the context clearly dictates otherwise.

[0021] Certain examples of the present disclosure will now be described in detail with reference to the attached drawings. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the examples set forth herein. Rather, these examples are provided to provide a better understanding of the scope of the present disclosure.

[0022] Figure 1 shows an example of audio communication for public address (PA) in a networked environment.

[0023] In the illustrated example, a network-based PA transmitter (105) transmits audio data to a network-based PA receiver (110) via a network (108). In some exemplary implementations, the network-based PA transmitter (105) may transmit digital audio data having a predetermined sample rate and a predetermined bit depth in a predetermined data transmission method, e.g., a multicast method, with a predetermined transmission period. The network-based PA receiver (110) may receive such digital audio data, e.g., by joining a multicast group. In addition, the network-based PA receiver (110) may write the received audio data to a buffer (e.g., a First-In-First-Out (FIFO) buffer) and read out the buffered audio data and provide it according to a clock signal having a variably set clock rate. In this way, the network-based PA receiver (110) can reduce latency that may occur in the network-based receiver (110) even if audio data does not enter the network-based PA receiver (110) in its transmission cycle under certain circumstances in the network (108).

[0024] For example, a network-based PA transmitter (105) may transmit more-than-two channel audio data over a network (108) to a network-based PA receiver (110) at predetermined transmission periods of 1 ms. For example, this audio data may have a sample rate of 48 kHz and a bit depth of 24 bits for each of the eight channels, and thus may amount to (1 / 1000) x 8 x 48 x 1000 x 24 = 9216 bits (i.e., 1152 bytes). The network-based PA receiver (110) may receive the eight channel audio data and buffer it into a buffer, for example, periodically, in a non-Operating System (non-OS) design, and ultimately without using any device drivers. When audio data is accumulated in the buffer to a certain extent, the network-based PA receiver (110) can output it in a predetermined internal interface format, for example, an 8-channel Time-Division Multiplexing (TDM) interface format. In order to maintain the amount of audio data remaining in the buffer or the buffer occupancy level representing the amount of audio data without significant fluctuation, the network-based PA receiver (110) can adjust the rate of the clock signal for outputting the audio data. For example, this clock rate is a reference rate (which is, for example, 8×48×1000×32 = 12.288×10 per second based on a sample rate of 48 kHz of audio data per channel in the case of providing output audio data with a width of 32 bits for each channel according to an 8-channel TDM interface format). 6 The bit rate can be adjusted around the reference rate based on the current buffer occupancy level, while being targeted at a bit rate of 12.288 MHz.

[0025] To this end, as depicted in FIG. 1, a network-based PA receiver (110) can be implemented including an audio clock adjustment unit (114) and an audio data formatting unit (115), wherein the audio clock adjustment unit (114) generates an audio clock signal based on an occupancy level of an audio buffer in which digital audio data received through a network (108) is buffered, and the audio data formatting unit (115) provides digital audio data from the audio buffer according to the generated audio clock signal, wherein the generation of the audio clock signal includes: generating a first audio clock signal as such an audio clock signal from an oscillating clock signal having an oscillating clock frequency, when the occupancy level of the audio buffer indicates that a certain amount of digital audio data remains in the audio buffer, the first audio clock signal having a specific clock rate that is less than or equal to the oscillating clock frequency; And if the occupancy level of the audio buffer indicates that some other amount different from that amount of digital audio data remains in the audio buffer, based on the occupancy level, setting a clock divisor to one of a plurality of integers greater than 1 and determined for a given sample rate of the digital audio data, and generating a second audio clock signal as such audio clock signal from a finite state machine (FSM) clock signal having a FSM clock frequency, the second audio clock signal having a different clock rate corresponding to the set clock divisor.

[0026] In a specific example, the network (108) may be an Internet Protocol (IP)-based network. Additionally, the network-based PA transmitter (105) and the network-based PA receiver (110) may not include a network switch that supports the Precision Time Protocol (PTP) used for clock synchronization on the network (108), and thus the network (108) may be a non-PTP network.

[0027] FIG. 2 is a block diagram illustrating an example of a network-based PA system (200) in which a network-based PA receiver (110) is implemented. The network-based PA system (200) can provide PA throughout a target environment (e.g., a complex comprising multiple buildings, a collection of local offices distributed across multiple remote locations, indoor and / or outdoor environments of at least a portion of a building, a building structure, or the like). For example, the target environment may be divided into multiple zones, and performing PA via the PA system (200) may include announcing the same or different messages across several zones. An exemplary implementation of the network-based PA system (200) is discussed in more detail below.

[0028] In the illustrated example, the network-based PA system (200) includes at least one local PA subsystem (210-1, 210-2, ..., 210-k) (which may be individually or collectively referred to hereinafter by the reference numeral "210"). For example, each local PA subsystem (210) may be constructed or installed within a corresponding area (e.g., a desired region or building) within the target environment to enable PA in that area. Referring to FIG. 3, an exemplary implementation of each local PA subsystem (210) will be described below.

[0029] In the example of FIG. 2, the local PA subsystem (210) is communicatively coupled to an external entity (e.g., another local PA subsystem (210) of a network-based PA system (200)) via a network (280). Examples of the network (280) include the Internet, a Wide Area Network (WAN), a Metropolitan Area Network (MAN), a Local Area Network (LAN), and the like.

[0030] As illustrated in FIG. 2, the network-based PA system (200) may further include a management subsystem (220). The management subsystem (220) may be communicatively coupled to the local PA subsystem (210) via a network (280). The management subsystem (220) may include a computing device operable to receive and process input from a user (e.g., an administrator of the network-based PA system (200)) and provide output representing certain information. For example, the memory of such a computing device may store program code that, when executed by a processor, provides a graphical user interface (GUI). The GUI may be displayed on a display device coupled to the computing device and may include, for example, a control GUI that assists a user in controlling at least a portion of the network-based PA system (200) (e.g., a particular device within one of the local PA subsystems (210-1, 210-2, ..., 210-k) of the network-based PA system (200), a schematic GUI that assists a user in monitoring at least a portion of the network-based PA system (200) (e.g., a particular device within one of the local PA subsystems (210-1, 210-2, ..., 210-k) of the network-based PA system (200), and / or other GUIs.

[0031] Additionally, in some exemplary implementations, the local PA subsystem (210) may be communicatively coupled to an external service system (270) via a network (280). For example, the external service system (270) may include a platform operated by the provider or operator of the network-based PA system (200) or by a third party. This platform may provide PA-related services (e.g., audio streaming services, PA status / flow monitoring services, failover / remote monitoring services, system management services, and / or other services) (e.g., based on a cloud computing system).

[0032] Figure 3 is a block diagram showing an example of a local PA subsystem (210).

[0033] In the example of FIG. 3, the local PA subsystem (210) includes a control device (310), a source device (320), an amplifier (330), a relay device (340), and speakers (350-1, 350-2, ..., 350-m) (which may be individually or collectively referred to hereinafter by the reference numeral "350").

[0034] In the illustrated example, certain of the components of the local PA subsystem (210) (e.g., components (310, 320, 330, 340, 350)) are communicatively coupled to other components within the local PA subsystem (210). Examples of such communication between devices within the local PA subsystem (210) include communication over a network such as a LAN that is confined to the area in which the local PA subsystem (210) is installed, digital serial communication, communication over contact lines, and various other analog or digital methods of communication.

[0035] In the illustrated example, certain of the components of the local PA subsystem (210) (e.g., components (310, 320, 330, 340, 350)) are communicatively coupled via the network (280) to an external entity (e.g., another local PA subsystem (210) of the network-based PA system (200) (which may be referred to hereinafter with the reference numeral "210'" and its components, e.g., the control device (310) and the source device (320), may also be referred to hereinafter with the reference numerals "310'" and "320'", respectively). For example, if the control device (310) of the local PA subsystem (210) is capable of communication via the network (280), other certain components within the local PA subsystem (210) may communicate with the control device (310), and / or without going through the control device (310). It can communicate with another local PA subsystem (210') of the system (200) (e.g., a control device (310') of the local PA subsystem (210')).

[0036] In the illustrated example, the local PA subsystem (210) is operable under the control of the control device (310). To this end, the control device (310) may operate and provide control signals under the control of a source inside or outside the local PA subsystem (210) to which it belongs (e.g., a management subsystem (220) as illustrated in FIG. 2 or a computing device included therein). For example, the control device (310) may provide control signals based on signals input to the control device (310) from a sensing device (e.g., a microphone, a camera, or another type of sensor) coupled to the control device (310) or from another local PA subsystem (210') or the management subsystem (220) of the network-based PA system (200) (e.g., a computing device providing a control GUI in the management subsystem (220), for example, the control device (310) may use the input signal as the control signal or may generate and output the control signal based on the input signal. Such control signals may be used to control a local PA subsystem (210) to which the control device (310) belongs (e.g., a specific device within the local PA subsystem (210)), or may be provided thereto for control of another local PA subsystem (210') of the network-based PA system (200) (e.g., a specific device within the local PA subsystem (210')).

[0037] In some exemplary implementations, a control device (310) disposed within a local PA subsystem (210) may perform the following operations: receiving audio signals for the PA from another device disposed within the local PA subsystem (210) (e.g., a source device (320)) and / or from another local PA subsystem (210') of a network-based PA system (200) (e.g., a particular device therein) via a network (280); providing the received audio signals to another device disposed within the local PA subsystem (210) (e.g., an amplifier (330), a relay device (340), or an additional device of some type) and / or transmitting the received audio signals to another local PA subsystem (210') of the network-based PA system (200) (e.g., a particular device therein) via a network (280); Providing a control signal to a predetermined device (e.g., a relay device (340)) disposed within a local PA subsystem (210) to cause such audio signal to be transmitted to a specific speaker (e.g., at least some of the speakers (350-1, 350-2, ..., 350-m) coupled to the relay device (340)) within the local PA subsystem (210) for reproduction; and / or the like.

[0038] In the illustrated example, the source device (320) is a device from which an audio signal in some format originates. For example, the source device (320) may include a sound player (e.g., a Compact Disc Player (CDP), an MP3 player, an FM / AM radio tuner, an Internet streaming receiver, a cassette deck, another sound player, etc.), a Text-To-Speech (TTS) synthesizer, a microphone (e.g., a Remote Microphone (RM)), etc. As described above, the audio signal from the source device (320) of the local PA subsystem (210) may be provided to the control device (310) of that local PA subsystem (210), and then to another local PA subsystem (210') (e.g., the control device (310') of the local PA subsystem (210')) via the network (280).

[0039] In the illustrated example, the relay device (340) is connectable to a line (which may be referred to herein as an "audio line") that can propagate an audio signal of a given level (e.g., an amplifier or speaker level such as about 50 V to 100 V or a line level such as about 1 V to 10 V). Accordingly, the relay device (340) can receive an audio signal through such an audio line. For example, the relay device (340) can be input with an audio signal provided from a control device (310). Such an audio signal can originate from within the local PA subsystem (210) to which the relay device (340) belongs (e.g., a source device (320)) or from outside (e.g., a source device (320') within another local PA subsystem (210') of a network-based PA system (200), an external service system (270), etc.). In some exemplary implementations, the input audio signal of the relay device (340) may be an audio signal output from the control device (310) that is amplified through a corresponding amplifier (330) interposed between the relay device (340) and the control device (310) and then provided to the relay device (340) via a corresponding audio line. For example, the control device (310) may output an audio signal at line level (e.g., about 1 V) to an audio line connected between the control device (310) and the amplifier (330), and the amplifier (330) may receive the audio signal output from the control device (310), amplify it to speaker level (e.g., about 100 V), and output it to an audio line connected between the amplifier (330) and the relay device (340). In some other exemplary implementations, the output audio signal of the control device (310) may be provided to the relay device (340) via a corresponding audio line without passing through the amplifier (330).

[0040] Additionally, in the illustrated example, the relay device (340) is capable of relaying the received audio signal to at least one of the speakers (350-1, 350-2, ..., 350-m) coupled thereto. Relaying of the audio signal to each speaker (350) can be enabled or disabled according to a control signal provided to the relay device (340) from the control device (310). For example, in response to receiving a particular control signal from the control device (310), the relay device (340) can enable or disable relaying of, for example, one of several input audio signals of the relay device (340) to at least one of the speakers (350-1, 350-2, ..., 350-m) coupled to the relay device (340) according to the received control signal. Then, when an input audio signal is relayed to the speaker (350), the speaker (350) can be driven to emit sound according to such audio signal.

[0041] In some exemplary implementations, such audio signal relay control may be considered to involve on / off control of contacts corresponding to channels between input audio signals and given speakers (350). For example, a relay device (340) may be coupled to 16 speakers corresponding to 16 channels, and the relay device (340) may be provided with one or more input audio signals and may enable or disable relaying of one of the input audio signals for playback to each of the 16 speakers based on a control signal (i.e., may turn on or off a contact for each channel in response to the control signal). In such an example, the relay device (340) may receive a control signal for controlling the audio signal relay from the control device (310) via a line connected between the control device (310) and the relay device (340), which may be, for example, a contact line that is a separate line from the audio line.

[0042] Referring to FIGS. 2 and 3, a network-based PA receiver (110) is illustrated as being disposed in a local PA subsystem (210) of a network-based PA system (200) and included in a control device (310) of the local PA subsystem (210). Additionally, although not shown, a network-based PA transmitter (105) may be disposed in the network-based PA system (200), for example, may be included in a source device (320) of a specific one of the local PA subsystems (210-1, 210-2, ..., 210-k).

[0043] Figure 4 is a block diagram showing an example of a network-based PA receiver (110).

[0044] In the example of FIG. 4, the network-based PA receiver (110) includes an audio data receiver (410), an audio buffer (420), an audio clock adjustment unit (440), and an audio data formatter (450). The audio clock adjustment unit (440) and the audio data formatter (450) may be implemented as the audio clock adjustment unit (114) and the audio data formatter (115) of FIG. 1, respectively. Other exemplary implementations of the network-based PA receiver (110) are also contemplated. For example, the network-based PA receiver (110) may also include additional components not shown, and / or may include some but not all of the components listed with respect to FIG. 4.

[0045] In the illustrated example, the audio data receiving unit (410) includes an external interface (415). For example, the external interface (415) may be a modem, an Ethernet interface, a network interface card (NIC), or the like, and may receive digital audio data (e.g., 8 channel audio data samples) from a network-based PA transmitter (105) via a network (e.g., network (280)).

[0046] In the illustrated example, the received digital audio data is buffered within an audio buffer (420) for later retrieval. For example, the audio buffer (420) may be a circular FIFO buffer or another type of FIFO buffer.

[0047] In the illustrated example, the audio clock adjustment unit (440) generates a variable rate audio clock signal having a variable clock rate based on an occupancy level indicating the amount of digital audio data currently remaining within the audio buffer (420). To this end, the audio clock adjustment unit (440) may use a finite state machine (FSM) clock signal generated to have a specific Finite State Machine (FSM) clock frequency (e.g., 251.904 MHz) or an oscillation clock signal generated to have a specific oscillation frequency (e.g., 24.576 MHz). As an example, the FSM clock signal may be generated (e.g., from an output signal of an active oscillator or other type of oscillator circuit) by an FSM clock generation unit (not shown) implemented as logic together with an audio clock conditioning unit (440) and an audio data formatting unit (450) on a programmable logic device (e.g., an FPGA) provided within a network-based PA receiver (110), and the oscillating clock signal may be generated (e.g., by such an oscillator or oscillator circuit or by a separate oscillator such as a crystal oscillator external to the programmable logic device).

[0048] Specifically, when the occupancy level of the audio buffer (420) indicates that a first amount of digital audio data remains within the audio buffer (420), the audio clock adjustment unit (440) can generate a first audio clock signal as a variable-rate audio clock signal from the oscillation clock signal, and the first audio clock signal can have a specific clock rate that is less than or equal to the oscillation clock frequency. For example, the first audio clock signal can be a frequency-division signal of the oscillation clock signal.

[0049] Additionally, when the occupancy level of the audio buffer (420) indicates that a second amount different from the first amount of digital audio data remains in the audio buffer (420), the audio clock adjustment unit (440) can, based on such occupancy level, set a clock divisor to one of a plurality of integers greater than 1 and defined for a given sample rate of the digital audio data (e.g., a predefined sample rate such as 48 kHz, 44.1 kHz, 32 kHz, or 16 kHz), and generate a second audio clock signal (which has a different clock rate corresponding to the set clock divisor) as a variable rate audio clock signal from the FSM clock signal. These integers may be several (e.g., two) candidate divisors (each integer greater than 1) that depend, for example, on the reference rate (which depends on the sample rate of the digital audio data) and the FSM clock frequency (see, in particular, Tables 2 and 3 and the related descriptions below).

[0050] Similarly, if the occupancy level of the audio buffer (420) indicates that a third amount different from the first and second amounts of digital audio data remains within the audio buffer (420), the clock divisor can be set to another of the aforementioned plurality of integers, and a third audio clock signal (which has another clock rate corresponding to the clock divisor set to another integer) can be generated as a variable rate audio clock signal from the FSM clock signal.

[0051] As an example, the first amount of digital audio data may be a value falling within a numerical range representing a “normal” buffer occupancy level, such as: a range of amounts of remaining audio data within the audio buffer (420) that satisfies that such amounts have a relatively small difference from a reference amount (e.g., a range from a value obtained by subtracting a predetermined fraction (e.g., 1 / 5) of the reference amount from the reference amount to a value obtained by adding this fraction to the reference amount). In addition, one of the second amount and the third amount of digital audio data may be a value belonging to a numerical range indicating an “abnormally reduced” buffer occupancy level, that is, a range of the amount of remaining audio data within the audio buffer (420) that satisfies that such amount is less than a reference amount and has a relatively large difference from the reference amount (e.g., a range less than a value obtained by subtracting an upper fraction of the reference amount from the reference amount), while the other of the second amount and the third amount of digital audio data may be a value belonging to a numerical range indicating an “abnormally increased” buffer occupancy level, that is, a range of the amount of remaining audio data within the audio buffer (420) that satisfies that such amount is greater than a reference amount and has a relatively large difference from the reference amount (e.g., a range exceeding a value obtained by adding an upper fraction of the reference amount to the reference amount).

[0052] In some exemplary implementations, the reference amount may be determined based on the amount of digital audio data expected to be received by the audio data receiver (410) over the network. For example, if 8 channel audio data having a 48 kHz sample rate and 24 sample bits for each channel as described above is transmitted from the network-based PA transmitter (105) and the predetermined period of such transmission is 1 ms, the network-based PA receiver (110) may want to maintain at least the following reference amount of audio data in the audio buffer (420) as much as possible to prevent the PA from being disconnected: (1.5 / 1000) x 8 x 48 x 1000 x 24 = 13824 bits (i.e., 1728 bytes), which is the amount of such audio data expected to be received every 1.5 ms plus a margin of 0.5 ms.

[0053] Hereinafter, in the design of a network-based PA receiver (110) (particularly, an audio clock adjustment unit (440)), (i) how the clock rate of a variable-rate audio clock signal (i.e., a first audio clock signal) generated from an oscillation clock signal is determined, (ii) how the FSM clock frequency is determined, and (iii) how a candidate divisor used in setting the clock rate of a variable-rate audio clock signal (i.e., a second or third audio clock signal) generated from the FSM clock signal is determined are discussed in detail. For convenience of explanation, an exemplary scenario is assumed in which, in a network-based PA receiver (110), an oscillation clock frequency is 24.576 MHz, 8-channel digital audio data having a 48 kHz sample rate and 32-bit width for each channel is output, and the maximum allowable value of the ratio of the difference between two adjacent possible clock rates of a variable-rate audio clock signal generated from an FSM clock signal to a reference rate (8×48×1000×32 = 12.288 MHz) (i.e., a targeted ratio of the difference between such clock rates to the reference rate) is 5%.

[0054] The clock rate of the audio clock signal generated from the oscillating clock signal can be the oscillating clock frequency or the oscillating clock frequency divided by a frequency-division factor greater than 1, and in particular can be determined as the smallest difference from a reference rate among the oscillating clock frequency / J (where J = 1, 2, ...). In this scenario, since the reference rate is 8×48×1000×32 = 12.288 MHz, a variable rate audio clock signal can be generated from the oscillating clock signal to have a clock rate of 24.576 / 2 = 12.288 MHz.

[0055] The FSM clock frequency may be set to be less than or equal to the maximum clock frequency available (e.g., on a programmable logic device in which several components, such as the audio clock adjustment unit (440) and the audio data formatting unit (450) of the network-based PA receiver (110), are implemented). For example, if a clock frequency of up to 300 MHz is available, a candidate value for the FSM clock frequency may be initially set to 245.768 MHz, with some margin. It will be appreciated that programmable logic devices, such as FPGAs, typically have a unit cost that increases almost exponentially with the maximum clock frequency they allow, so it is not cost-effective to increase the FSM clock frequency as desired (e.g., unless the number of required logic elements is very large).

[0056] Now, we know the highest candidate divisor, which is an integer that satisfies the following condition: Multiplying the reference rate 12.288 MHz by the highest candidate divisor results in a value closest to the candidate value of the FSM clock frequency. In this example, the highest candidate divisor is 20, since among several integer multiples of the reference rate, 12.288 × 20 = 245.760 MHz is closest to the candidate value of the FSM clock frequency 245.768 MHz. Table 1 shows the highest candidate divisor and three candidate divisors that include two adjacent integers, and the three corresponding possible clock rates.

[0057] Candidate Divisor Clock Rate (MHz) = FSM Clock Frequency / Candidate Divisor Clock Rate - Reference Rate (MHz) Error Rate (%) = (Clock Rate - Reference Rate) / Reference Rate 1912.935 20.647 25.267% 2012.288 40.000 40.003% 2111.7032 - 0.5848 - 4.759%

[0058] As can be seen in Table 1, the ratio of the difference between the two given clock rates 12.9352 MHz and 12.2884 MHz for candidate divisors 19 and 20, respectively, to the reference rate 12.288 MHz is equal to the difference between the two given error rates 5.267% and 0.003% for candidate divisors 19 and 20, respectively. This error rate difference is larger than the targeted rate of 5%. In this regard, the following is noteworthy: When the reference rate is high due to the large number of channels carried in the digital audio data, while the FSM clock frequency is limited as described above, the closer the possible clock rates are to the reference rate, the smaller integers are determined as candidate divisors, and the larger the difference between the two given error rates for two adjacent candidate divisors becomes.

[0059] In this situation, if a variable-rate audio clock signal is generated using an FSM clock signal without using an oscillation clock signal, and its clock rate is adjusted by switching between the clock rates presented in Table 1, excessively frequent clock rate switching may occur due to a large error rate difference, and as a result, audio data output according to this audio clock signal may have difficulty in being played back smoothly.

[0060] On the other hand, using the FSM clock signal as presented in Table 1 in addition to using the oscillating clock signal as described above may result in unnecessary switching between the nearly identical clock rates of the two signals: an audio clock signal generated from the oscillating clock signal to have a clock rate of 12.288 MHz and an audio clock signal generated from the FSM clock signal to have a clock rate of 12.2884 MHz.

[0061] Therefore, the aforementioned candidate value of 245.768 MHz is only used to determine the highest candidate divisor and may not be used as the FSM clock frequency. Instead, the FSM clock frequency may be determined based on the reference rate of 12.288 MHz, the highest candidate divisor of 20, and the targeted ratio of 5%. Then, based on the occupancy level of the audio buffer (420), switching between generating a variable rate audio clock signal from such FSM clock frequency and generating a variable rate audio clock signal from the aforementioned oscillation clock signal may be performed.

[0062] For example, the FSM clock frequency may be the product of a reference rate and a scaling factor multiplied by the highest candidate divisor or a candidate divisor adjacent to the highest candidate divisor, where the scaling factor is calculated from the targeted rate. The scaling factor may be, for example, one half of the targeted rate plus one, or one half of the targeted rate minus one.

[0063] Table 2 illustrates two candidate divisors and two corresponding possible clock rates for the case where the FSM clock frequency is determined as (reference rate) × (1 + (targeted rate) / 2) × (highest candidate divisor) = 12.288 × (1 + 0.05 / 2) × 20 = 251.904 MHz. The ratio of the difference between the two clock rates in Table 2 to the reference rate is less than 5% of the targeted rate.

[0064] Candidate Divisor Clock Rate (MHz) = FSM Clock Frequency / Candidate Divisor Clock Rate - Reference Rate (MHz) Error Rate (%) = (Clock Rate - Reference Rate) / Reference Rate 2012.59520.30722.500% 2111.9954-0.2926-2.381%

[0065] Then, when the occupancy level of the audio buffer (420) is “abnormally increased,” the audio clock adjustment unit (440) can operate in a “fast mode” to allow the remaining data in the audio buffer (420) to be read out more quickly by generating a variable rate audio clock signal from the FSM clock signal to have a clock rate of 12.5952 MHz corresponding to the small candidate divisor 20 in Table 2, i.e., by generating an audio clock signal with a higher clock rate. Furthermore, when the occupancy level of the audio buffer (420) is “abnormally decreased,” the audio clock adjustment unit (440) can operate in a “slow mode” to allow the remaining data in the audio buffer (420) to be read out more slowly by generating a variable rate audio clock signal from the FSM clock signal to have a clock rate of 11.9954 MHz corresponding to the large candidate divisor 21 in Table 2. Meanwhile, when the occupancy level of the audio buffer (420) is “normal” (e.g., indicating that a first amount of digital audio data remains within the audio buffer (420), the audio clock adjustment unit (440) may operate in a “normal mode” by generating a variable rate audio clock signal from the oscillating clock signal to have a clock rate of 24.576 / 2 = 12.288 MHz, i.e., by generating an audio clock signal having a clock rate that is between the two clock rates in Table 2 and is spaced from the reference rate by a smaller interval than these clock rates, thereby causing the remaining data within the audio buffer (420) to be read out at a normal pace.

[0066] Table 3 illustrates two candidate divisors and two corresponding possible clock rates for the case where the FSM clock frequency is determined as (reference rate) × (1 - (targeted rate) / 2) × (highest candidate divisor + 1) = 12.288 × (1 - 0.05 / 2) × 21 = 251.5968 MHz. The ratio of the difference between the two clock rates in Table 3 to the reference rate is less than 5% of the targeted rate.

[0067] Candidate Divisor Clock Rate (MHz) = FSM Clock Frequency / Candidate Divisor Clock Rate - Reference Rate (MHz) Error Rate (%) = (Clock Rate - Reference Rate) / Reference Rate 2012.57980.29182.375% 2111.9808-0.3072-2.500%

[0068] Then, when the occupancy level of the audio buffer (420) is “abnormally increased”, the audio clock adjustment unit (440) can operate in “fast mode” by generating a variable rate audio clock signal from the FSM clock signal to have a clock rate of 12.5798 MHz corresponding to the small candidate divisor 20 in Table 3. Also, when the occupancy level of the audio buffer (420) is “abnormally decreased”, the audio clock adjustment unit (440) can operate in “slow mode” by generating a variable rate audio clock signal from the FSM clock signal to have a clock rate of 11.9808 MHz corresponding to the large candidate divisor 21 in Table 3. Meanwhile, when the occupancy level of the audio buffer (420) is “normal,” the audio clock adjustment unit (440) can operate in “normal mode” by generating a variable rate audio clock signal from the oscillation clock signal to have a clock rate of 24.576 / 2 = 12.288 MHz.

[0069] In some exemplary implementations, the audio clock signal generated from the FSM clock signal by the audio clock adjustment unit (440) may include a bit clock pulse having a high level portion and a low level portion (e.g., one bit clock pulse (600) of the audio clock signal illustrated in FIG. 6). For example, the time width of the high level portion of the audio clock signal may be the time width spanned by successive pulses of a first count number of the FSM clock signal, and the time width of the low level portion of the audio clock signal may be the time width spanned by successive pulses of a second count number of the FSM clock, wherein the first count number plus the second count number is equal to a clock divisor set by the audio clock adjustment unit (440).

[0070] Additionally, at least one of the first count number and the second count number may be the largest integer less than or equal to half of the clock divisor (e.g., when the clock divisor N is even, both the first count number and the second count number may be N / 2, and when the clock divisor N is odd, the first count number may be [N / 2]+1 and the second count number may be [N / 2] or vice versa, where the symbol [x] represents the largest integer less than or equal to x). Then, the duty ratio of the audio clock signal may not deviate significantly from 50%, for example, in the cases of Tables 2 and 3, the candidate divisor 21 may result in the worst-case duty ratio, which is only 10 / 21, i.e., approximately 47.6%.

[0071] In the example of FIG. 4, the audio data formatting unit (450) fetches digital audio data from the audio buffer (420) and provides it through the internal interface (455) according to an audio clock signal generated by the audio clock adjusting unit (440). In some exemplary implementations, the internal interface (455) may be a TDM interface, another serial bus interface for audio data transmission, or another type of interface, and the audio data formatting unit (450) may output the fetched digital audio data in a specific format suitable for the internal interface (455) in accordance with the audio clock signal. For example, the audio data formatting unit (450) may format the fetched digital audio data to conform to the internal interface (455) and provide one bit of the formatted digital audio data for each bit clock pulse of the audio clock signal.

[0072] FIG. 5 is a diagram showing an example of an FSM (500) driven in an exemplary operation of an audio clock adjustment unit (440).

[0073] In the example of Fig. 5, to generate an audio clock signal from an FSM clock signal, an audio clock adjustment unit (440) drives an FSM (500) with the FSM clock signal and counts pulses of the FSM clock signal as a clock count while driving the FSM (500). In this example, the FSM (500) has an initial state S0, a first state S1, a second state S2, and a third state S3.

[0074] In some example implementations, the FSM (500) may increment the clock count by 1 in response to detecting an edge of the FSM clock signal (e.g., a rising edge of a pulse).

[0075] In the example of FIG. 5, the FSM (500) starts with an initial state S0. In the initial state S0, the clock count may be initialized to 0, and the maximum possible value of the clock count may be set to a clock divisor N set by the audio clock adjustment unit (440). Additionally, during the initial state S0, the audio clock signal may be generated to assume a first binary level (e.g., a high level, as illustrated in FIG. 6).

[0076] In the illustrated example, the FSM (500) transitions from an initial state S0 to a first state S1 when the clock count is incremented to 1 (e.g., in response to a rising edge of the FSM clock signal). If the clock count is less than [N / 2], the FSM (500) remains in the first state S1. During the first state S1, the audio clock signal may still be generated to assume the first binary level (e.g., a high level, as illustrated in FIG. 6).

[0077] In the illustrated example, the FSM (500) transitions from the first state S1 to the second state S2 when the clock count reaches [N / 2] (e.g., in response to ([N / 2]-1) additional rising edges of the FSM clock signal). If the clock count is less than [N / 2]×2, the FSM (500) remains in the second state S2. During the second state S2, the audio clock signal can be generated to assume a second binary level (e.g., a low level, as illustrated in FIG. 6).

[0078] In the illustrated example, the FSM (500) transitions from the second state S2 when the clock count reaches [N / 2]×2 (e.g., in response to [N / 2] additional rising edges of the FSM clock signal). If the clock divisor N is even (i.e., the remainder N%2 of N divided by 2 is 0) and the clock count is [N / 2]×2, the FSM (500) transitions from the second state S2 to the initial state S0. If the clock divisor N is odd (i.e., the remainder N%2 of N divided by 2 is 1) and the clock count is [N / 2]×2, the FSM (500) transitions from the second state S2 to a third state S3. During the third state S3, the audio clock signal may still be generated to assume a second binary level (e.g., a low level, as illustrated in FIG. 6). Afterwards (e.g., in response to one additional rising edge of the FSM clock signal), when the clock counter reaches the clock divisor N, the FSM (500) transitions from the third state S3 to the initial state S0.

[0079] FIG. 7 is a flowchart illustrating an example of a process (700) for audio clock adjustment in a network-based PA. For example, the process (700) of FIG. 7 may be performed by a network-based PA receiver (110) (e.g., an audio clock adjustment unit (440) and an audio data formatting unit (450)). Other exemplary flows of the process (700) are also contemplated. For example, the process (700) may include additional operations not illustrated in FIG. 7, may include some but not all of the operations listed with respect to FIG. 7, and / or may be performed in a different order than the order illustrated in FIG. 7.

[0080] In operation (710), digital audio data is buffered within an audio buffer for later retrieval. The digital audio data may be samples received over a network (e.g., an IP-based non-PTP network).

[0081] In operation (720), it is determined whether the occupancy level, which indicates the amount of digital audio data currently remaining in the audio buffer, is normal.

[0082] If it is determined that the occupancy level of the audio buffer is normal, in operation (730), a first audio clock signal is generated from the oscillation clock signal. The first audio clock signal may be a frequency division signal of the oscillation clock signal.

[0083] If it is determined that the occupancy level of the audio buffer is abnormal, in operation (740), based on the occupancy level, the clock divisor is set to one of a plurality of candidate divisors (which are integers greater than 1 and determined for a given sample rate of the digital audio data). The clock divisor may be set lower if the occupancy level of the audio buffer abnormally increases, and may be set higher if the occupancy level of the audio buffer abnormally decreases.

[0084] In operation (750), a second audio clock signal having a clock rate equal to the FSM clock frequency divided by a set clock divisor is generated from an FSM clock signal having an FSM clock frequency.

[0085] In some exemplary implementations, the generation of the second audio clock signal may include driving the FSM with the FSM clock signal and, during driving of the FSM, counting pulses of the FSM clock signal as a clock count. For example, the FSM may be characterized by the initial state S0, the first state S1, and the second state S2 as described above, such that when the clock count is initialized in the initial state S0 and reaches 1, a transition may be made from the initial state S0 to the first state S1, the first state S1 may be maintained until the clock count reaches [N / 2], and then a transition may be made from the first state S1 to the second state S2, and the second state S2 may be maintained until the clock count reaches [N / 2]×2. The second audio clock signal may exhibit a high level during the initial state S0 and the first state S1, and a low level during the second state S2. Also, a transition from the second state S2 to the initial state S0 can be performed when the clock divisor N is even and the clock count reaches [N / 2]×2=N. The FSM can also be characterized by a third state S3, in which a transition from the second state S2 to the third state S3 can be performed when the clock divisor N is odd and the clock count reaches [N / 2]×2=N. During the third state S3, the second audio clock signal can indicate a low level. Afterwards, a transition from the third state S3 to the initial state S0 can be performed when the clock count reaches [N / 2]×2+1=N.

[0086] In operation (760), digital audio data is provided according to a first or second audio clock signal generated by fetching from an audio buffer. The fetched digital audio data may be provided in synchronization with the audio clock signal in a specific format (e.g., a format conforming to the TDM protocol).

[0087] Below are various examples of audio clock adjustment in a network-based PA.

[0088] In Example 1, a device for audio clock adjustment in a network-based public address (PA) broadcasting system includes an audio clock adjustment unit for generating an audio clock signal based on an occupancy level of an audio buffer in which digital audio data received through a network is buffered, and an audio data formatting unit for providing the digital audio data from the audio buffer according to the generated audio clock signal, wherein generating the audio clock signal comprises: generating a first audio clock signal as the audio clock signal from an oscillating clock signal having an oscillating clock frequency when the occupancy level indicates that a first amount of the digital audio data remains in the audio buffer, the first audio clock signal having a specific clock rate less than or equal to the oscillating clock frequency; and, when the occupancy level indicates that a second amount different from the first amount of the digital audio data remains in the audio buffer, generating a clock divisor based on the occupancy level. The method further comprises setting a divisor to be greater than 1 and one of a plurality of integers determined for a given sample rate of the digital audio data, and generating a second audio clock signal as the audio clock signal from a finite state machine (FSM) clock signal having a FSM clock frequency (the second audio clock signal having a different clock rate corresponding to the set clock divisor).

[0089] Example 2 includes the subject matter of Example 1, except that the particular clock rate is the oscillation clock frequency divided by a frequency-division factor greater than 1.

[0090] Example 3 includes the subject matter of Example 1 or Example 2, wherein generating the audio clock signal further includes, when the occupancy level indicates that a third amount different from the first amount and the second amount of the digital audio data remains in the audio buffer, setting the clock divisor to an adjacent one of the plurality of integers based on the occupancy level, and generating a third audio clock signal from the FSM clock signal as the audio clock signal, the third audio clock signal having another clock rate corresponding to the clock divisor set to the adjacent integer, wherein the particular clock rate is less than one of the other clock rate and the other clock rate and greater than the remainder of the other clock rate and the other clock rate.

[0091] Example 4 includes the subject matter of Example 3, wherein the particular clock rate is spaced from a reference rate by a smaller interval than the other clock rates and the other clock rates, and the reference rate is determined based on a given sample rate as a targeted bitrate at which the digital audio data is to be provided from the audio buffer.

[0092] Example 5 includes the subject matter of Example 3 or Example 4, wherein the first amount of the digital audio data falls within a numerical range representing a normal occupancy level of the audio buffer, one of the second amount and the third amount of the digital audio data falls within a numerical range representing an abnormally increased occupancy level of the audio buffer, and the other of the second amount and the third amount of the digital audio data falls within a numerical range representing an abnormally decreased occupancy level of the audio buffer.

[0093] Example 6 includes the subject matter of any of Examples 1 through 5, wherein the audio buffer is a First-In-First-Out (FIFO) buffer.

[0094] Example 7 includes the subject matter of any of Examples 1 through 6, wherein the clock divisor is further set based on a predetermined transmission period during which the digital audio data is transmitted to the device via the network.

[0095] Example 8 includes the subject matter of any of Examples 1 to 7, wherein the device further comprises an audio data receiving unit for receiving the digital audio data via the network.

[0096] Example 9 includes the subject matter of any of Examples 1 through 8, wherein the network is an Internet Protocol (IP) based network.

[0097] Example 10 includes the subject matter of any of Examples 1 through 9, wherein the network is a non-Precision Time Protocol (non-PTP) network.

[0098] Example 11 includes the subject matter of any of Examples 1 to 10, wherein the second audio clock signal generated above comprises a bit clock pulse having a high level portion and a low level portion, wherein a time width of the high level portion is a time width spanned by successive pulses of a first count number of the FSM clock signal, and wherein a time width of the low level portion is a time width spanned by successive pulses of a second count number of the FSM clock, and wherein the first count number plus the second count number is a clock divisor.

[0099] Example 12 includes the subject matter of Example 11, wherein at least one of the first count number and the second count number is the largest integer less than or equal to half of the clock divisor.

[0100] Example 13 includes the subject matter of any of Examples 1 through 12, wherein all of the above plural integers are consecutive.

[0101] Example 14 includes the subject matter of any of Examples 1 through 13, wherein the digital audio data is buffered within the audio buffer without using any device driver to control the buffering.

[0102] Example 15 includes the subject matter of any of Examples 1 to 14, wherein the digital audio data is provided via a more-than-two channel Time-Division Multiplexing (TDM) interface according to an audio clock signal generated from the audio buffer by the audio data formatting unit.

[0103] Example 16 includes the subject matter of any of Examples 1 to 15, wherein the audio clock adjustment unit and the audio data formatting unit are implemented as logic on a programmable logic device.

[0104] Example 17 includes the subject matter of Example 16, wherein the audio clock adjustment unit receives the oscillation clock signal from an oscillator external to the programmable logic device to generate the first audio clock signal.

[0105] Example 18 includes the subject matter of Example 16 or Example 17, wherein the audio buffer is implemented within the programmable logic device or on memory external to the programmable logic device.

[0106] In Example 19, a method for adjusting an audio clock in a network-based public address (PA) broadcasting system includes generating an audio clock signal based on an occupancy level of an audio buffer in which digital audio data received through a network is buffered, and providing the digital audio data from the audio buffer according to the generated audio clock signal, wherein generating the audio clock signal comprises: generating a first audio clock signal as the audio clock signal from an oscillating clock signal having an oscillating clock frequency, when the occupancy level indicates that a first amount of the digital audio data remains in the audio buffer, the first audio clock signal having a specific clock rate less than or equal to the oscillating clock frequency; and setting a clock divisor to one of a plurality of integers greater than 1 and determined for a given sample rate of the digital audio data, based on the occupancy level, when the occupancy level indicates that a second amount different from the first amount of the digital audio data remains in the audio buffer, and providing a second audio clock signal as the audio clock signal, using a finite state machine (Finite State Machine): FSM) generating from an FSM clock signal having a clock frequency (the second audio clock signal has a different clock rate corresponding to the clock divisor set above).

[0107] Example 20 includes the subject matter of Example 19, wherein the particular clock rate is the above oscillation clock frequency divided by a division factor greater than 1.

[0108] Example 21 includes the subject matter of Example 19 or Example 20, wherein generating the audio clock signal further includes, when the occupancy level indicates that a third amount different from the first amount and the second amount of the digital audio data remains in the audio buffer, setting the clock divisor to an adjacent one of the plurality of integers based on the occupancy level, and generating a third audio clock signal from the FSM clock signal as the audio clock signal, the third audio clock signal having another clock rate corresponding to the clock divisor set to the adjacent integer, wherein the particular clock rate is less than one of the other clock rate and the other clock rate and greater than the remainder of the other clock rate and the other clock rate.

[0109] Example 22 includes the subject matter of Example 21, wherein the particular clock rate is spaced from a reference rate by a smaller interval than the other clock rates, and than the further clock rates, and wherein the reference rate is determined based on a given sample rate as a bitrate at which the digital audio data is targeted to be provided from the audio buffer.

[0110] Example 23 includes the subject matter of Example 21 or Example 22, wherein the first amount of the digital audio data falls within a numerical range representing a normal occupancy level of the audio buffer, one of the second amount and the third amount of the digital audio data falls within a numerical range representing an abnormally increased occupancy level of the audio buffer, and the remainder of the second amount and the third amount of the digital audio data falls within a numerical range representing an abnormally decreased occupancy level of the audio buffer.

[0111] Example 24 includes the subject matter of any of Examples 19 through 23, wherein the audio buffer is a First-In-First-Out (FIFO) buffer.

[0112] Example 25 includes the subject matter of any of Examples 19 to 24, wherein the clock divisor is further set based on a predetermined transmission period, and wherein the digital audio data is transmitted to a device including the audio buffer over the network with the predetermined transmission period and is buffered within the audio buffer.

[0113] Example 26 includes the subject matter of any of Examples 19 to 25, wherein the method further comprises receiving the digital audio data via the network.

[0114] Example 27 includes the subject matter of any of Examples 19 through 26, wherein the network is an Internet Protocol (IP) based network.

[0115] Example 28 includes the subject matter of any of Examples 19 to 27, wherein the network is a non-Precision Time Protocol (non-PTP) network.

[0116] Example 29 includes the subject matter of any of Examples 19 to 28, wherein the generated second audio clock signal comprises a bit clock pulse having a high level portion and a low level portion, wherein a time width of the high level portion is a time width spanned by successive pulses of a first count number of the FSM clock signal, a time width of the low level portion is a time width spanned by successive pulses of a second count number of the FSM clock, and wherein the first count number plus the second count number is a clock divisor.

[0117] Example 30 includes the subject matter of Example 29, wherein at least one of the first count number and the second count number is the largest integer less than or equal to half of the clock divisor.

[0118] Example 31 includes the subject matter of any of Examples 19 to 30, wherein all of the above plural integers are consecutive.

[0119] Example 32 includes the subject matter of any of Examples 19 through 31, wherein the digital audio data is buffered within the audio buffer without using any device driver to control the buffering.

[0120] Example 33 includes the subject matter of any of Examples 19 to 32, wherein the digital audio data is provided from the audio buffer via a 2+ channel Time-Division Multiplexing (TDM) interface according to the generated audio clock signal.

[0121] Example 34 includes the subject matter of any of Examples 19 through 33, wherein the method is performed by programmed logic within a programmable logic device.

[0122] Example 35 includes the subject matter of Example 34, wherein the method further comprises receiving the above oscillation clock signal from an oscillator external to the above programmable logic device to generate the above first audio clock signal.

[0123] Example 36 includes the subject matter of Example 34 or Example 35, wherein the audio buffer is implemented within the programmable logic device or on memory external to the programmable logic device.

[0124] In Example 37, a computer-readable storage medium has computer-executable instructions stored therein, wherein the computer-executable instructions, when executed by a computer processor, cause the computer processor to perform a method as described in any of Examples 19 to 36.

[0125] In example 38, the computing device includes a processor and a computer-readable storage medium, wherein the computer-readable storage medium has stored thereon computer-executable instructions that, when executed by the processor, cause the computing device to perform the method described in any one of examples 19 to 36.

[0126] In Example 39, a programmable logic device for audio clock adjustment in a network-based public address (PA) broadcast comprises programmable logic, wherein the programmable logic is programmed to perform a method as described in any of Examples 19 to 36.

[0127] In Example 40, a network-based public address (PA) system includes a network-based PA receiver including the programmable logic device of Example 39.

[0128] In certain instances, the apparatus, device, system, machine, and the like referred to herein may be, include, or be implemented in any suitable type of computing device. The computing device may include a processor and a computer-readable storage medium readable by the processor. The processor may execute one or more instructions stored in the computer-readable storage medium. The processor may also read other information stored in the computer-readable storage medium. Additionally, the processor may store new information in the computer-readable storage medium and update any information stored in the computer-readable storage medium. The processor may include, for example, a Central Processing Unit (CPU), a Digital Signal Processor (DSP), a Graphics Processing Unit (GPU), a processor core, a microprocessor, a microcontroller, a Field-Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), other hardware and logic circuitry, or any suitable combination thereof. A computer-readable storage medium may be encoded with various information, such as a set of processor-executable instructions that can be performed by a processor and / or other information. For example, a computer-readable storage medium may have stored therein computer program instructions that, when executed by a processor, cause a computing device (e.g., a processor) to perform some of the operations disclosed herein and / or information, data, variables, constants, data structures, and the like used in such operations.The computer-readable storage medium may include, for example, read-only memory (ROM), random-access memory (RAM), volatile memory, non-volatile memory, removable memory, non-removable memory, flash memory, solid-state memory, other types of memory devices, magnetic media such as hard disks, floppy disks, and magnetic tapes, optical recording media such as CD-ROMs, DVDs, magneto-optical media such as floptical disks, other types of storage devices and storage media, or any suitable combination thereof.

[0129] In certain instances, the operations, techniques, processes, or any aspect or portion thereof described herein may be embodied in a computer program product. Such a computer program may be implemented in any type of computer-executable programming language (e.g., compiled or interpreted), such as assembly, machine language, procedural language, object-oriented language, etc., and may be combined with a hardware implementation. The computer program product may be distributed in the form of a computer-readable storage medium or may be distributed online. For online distribution, part or all of the computer program product may be temporarily stored or temporarily generated on a server (e.g., on the server's computer-readable storage medium).

[0130] The above description has been presented to illustrate and describe a few examples in detail. Those skilled in the art will readily appreciate that many modifications and variations are possible in light of the above teachings without departing from the scope of the present disclosure. In various instances, suitable results may still be achieved even if the described techniques are performed in different sequences, and / or some of the components of the described systems, architectures, devices, circuits, and the like are combined or combined in different ways, or replaced or substituted with other components or their equivalents.

[0131] Therefore, the scope of the present disclosure should not be limited to the form disclosed, but should be defined by the claims set forth below and their equivalents.

Claims

1. As a device for adjusting the audio clock in network-based public address (PA) broadcasting, An audio clock adjustment unit that generates an audio clock signal based on the occupancy level of an audio buffer in which digital audio data received through a network is buffered; Including an audio data formatting unit that provides the digital audio data from the audio buffer according to the generated audio clock signal, Generating the above audio clock signal is: When the occupancy level indicates that a first amount of the digital audio data remains in the audio buffer, generating a first audio clock signal as the audio clock signal from an oscillation clock signal having an oscillation clock frequency, wherein the first audio clock signal has a specific clock rate that is less than or equal to the oscillation clock frequency; and If the occupancy level indicates that a second amount different from the first amount of the digital audio data remains in the audio buffer, based on the occupancy level, setting a clock divisor to one of a plurality of integers greater than 1 and determined for a given sample rate of the digital audio data, and generating a second audio clock signal as the audio clock signal from a finite state machine (FSM) clock signal having a FSM clock frequency, wherein the second audio clock signal has a different clock rate corresponding to the set clock divisor. Device.

2. In paragraph 1, The above specific clock rate is the oscillation clock frequency divided by a frequency-division factor greater than 1. Device.

3. In paragraph 1, Generating the above audio clock signal is: If the occupancy level indicates that a third amount different from the first amount and the second amount of the digital audio data remains in the audio buffer, based on the occupancy level, setting the clock divisor to an adjacent one of the plurality of integers, and generating a third audio clock signal as the audio clock signal from the FSM clock signal, wherein the third audio clock signal has another clock rate corresponding to the clock divisor set to the adjacent integer, wherein said particular clock rate is less than one of said other clock rate and said other clock rate and greater than the remaining one of said other clock rate and said other clock rate, Device.

4. In paragraph 1, The digital audio data is provided according to the generated audio clock signal through a more-than-two channel Time-Division Multiplexing (TDM) interface from the audio buffer by the audio data formatting unit. Device.

5. In paragraph 1, The audio clock adjustment unit and the audio data formatting unit are implemented as logic on a programmable logic device, and the audio clock adjustment unit receives the oscillation clock signal from an oscillator external to the programmable logic device to generate the first audio clock signal. Device.

6. A method for adjusting the audio clock in a network-based public address (PA) broadcast, A step of generating an audio clock signal based on the occupancy level of an audio buffer in which digital audio data received through a network is buffered, Including a step of providing the digital audio data from the audio buffer according to the generated audio clock signal, The step of generating the above audio clock signal comprises: When the occupancy level indicates that a first amount of the digital audio data remains in the audio buffer, generating a first audio clock signal as the audio clock signal from an oscillation clock signal having an oscillation clock frequency, wherein the first audio clock signal has a specific clock rate that is less than or equal to the oscillation clock frequency; and A step of setting a clock divisor to one of a plurality of integers greater than 1 and determined for a given sample rate of the digital audio data, based on the occupancy level, when the occupancy level indicates that a second amount different from the first amount of the digital audio data remains in the audio buffer, and generating a second audio clock signal as the audio clock signal from a finite state machine (FSM) clock signal having a FSM clock frequency, wherein the second audio clock signal has a different clock rate corresponding to the set clock divisor. method.

7. In paragraph 6, The above specific clock rate is the oscillation clock frequency divided by a frequency division factor greater than 1. method.

8. In paragraph 6, The step of generating the above audio clock signal comprises: If the occupancy level indicates that a third amount different from the first amount and the second amount of the digital audio data remains in the audio buffer, the step of setting the clock divisor to an adjacent one of the plurality of integers based on the occupancy level and generating a third audio clock signal as the audio clock signal from the FSM clock signal, wherein the third audio clock signal has another clock rate corresponding to the clock divisor set to the adjacent integer, wherein said particular clock rate is less than one of said other clock rate and said other clock rate and greater than the remaining one of said other clock rate and said other clock rate, method.

9. In paragraph 6, The step of providing the digital audio data includes the step of providing the digital audio data from the audio buffer through a 2-plus channel time-division multiplexing (TDM) interface according to the generated audio clock signal. method.

10. A programmable logic device for audio clock adjustment in network-based public address (PA) broadcasting, Including programmable logic, wherein said programmable logic comprises: Generating an audio clock signal based on the occupancy level of an audio buffer in which digital audio data received through a network is buffered, Programmed to perform the above-mentioned digital audio data providing from the above-mentioned audio buffer according to the above-mentioned generated audio clock signal, Generating the above audio clock signal is: When the occupancy level indicates that a first amount of the digital audio data remains in the audio buffer, generating a first audio clock signal as the audio clock signal from an oscillation clock signal having an oscillation clock frequency, wherein the first audio clock signal has a specific clock rate that is less than or equal to the oscillation clock frequency; and In a case where the occupancy level indicates that a second amount different from the first amount of the digital audio data remains in the audio buffer, based on the occupancy level, setting a clock divisor to one of a plurality of integers greater than 1 and determined for a given sample rate of the digital audio data, and generating a second audio clock signal as the audio clock signal from a finite state machine (FSM) clock signal having a FSM clock frequency, wherein the second audio clock signal has a different clock rate corresponding to the set clock divisor. Programmable logic device.

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