System and method for synchronizing and aligning several modules on a same clock

Abstract

System and method for synchronizing a module A (110) with each module Bj (120) of a set S of modules, wherein j=1 M ≥ 1, and S={B1,...,BM}, wherein the module A (110) is configured for operating in synchronicity with a clock signal CK_A (210) of period T and the module Bj (120) is configured for operating in synchronicity with a clock signal CK Bj of said period T, the method comprising: - adjusting or controlling, by a phase adjustment circuit, for each couple of modules formed by the module A (110) and one of said modules Bj (120) and in function of a total adjustment time TT_ Dj calculated for each couple, a relative time between an arrival time of signal S_Aj data at the sampling location of the sampling component of the module Bj (120) and a sampling time of said data by the sampling component of module Bj, wherein said sampling time is temporally directly adjacent to the arrival time; wherein said total adjustment time TT_Dj is configured for increasing, for both a sampling by a sampling component of module A (110) of data values of a signal S_Bj sent by the module Bj (120) to the module A and the sampling by the sampling component of module Bj (120) of data values of the signal S_Aj, a time separation between data arrival at a sampling location of the concerned sampling component and data sampling by said concerned sampling component, wherein the time at which said data sampling takes place is temporally directly adjacent to the time at which the data arrive at said sampling location of the concerned sampling component.

Description

SYSTEM AND METHOD FOR SYNCHRONIZING AND ALIGNING SEVERAL MODULES ON A SAME CLOCK

[0001] The present invention concerns the synchronization and alignment of several modules on a common clock. Aspects of the present invention are notably directed to emulation, and more precisely to clock latency in an emulation system comprising several modules, for instance several integrated circuits or integrated circuit chips (together referred to hereafter as “IC”).BACKGROUND ART

[0002] Clock latency is a parameter that is particularly important in emulation systems, notably when high accuracy is required. Indeed, such systems comprise ICs that need to communicate with each other at relatively high rate, wherein signals or data are sent and received in synchronicity with a clock. Typically, a reference clock signal is used by the ICs for synchronizing their operations or actions, e.g. the sampling of data values from an incoming signal, or the change or retain of a data value in an output signal. Said reference clock signal might be received by an IC from a global source clock signal distributed centrally to all ICs of a same emulation system or might be generated internally (e.g. by means of an internal electronic oscillator) by an IC and distributed to one or several other ICs.

[0003] Consequently, the respective clock signals used by ICs of a set or network of ICs that need to work synchronously with each other have all the same constant frequency, however, and unfortunately, said respective clock signals might be slightly out-of-phase or delayed due to the different amounts of time required by the reference clock signal to travel and reach each ICs of the set. This might then prevent the ICs of said set to act or operate all together synchronously. In other words, the respective clocks of two ICs of said set that need to exchange data or to act synchronously might be at a slightly differenttime, wherein the delay between the clock of the IC that sends data and the clock of the IC that receives said data is usually called “clock skew”. More generally, clock skew refers to the instantaneous difference between the time of a clock of a first IC and the time of a clock of a second IC in communication with the first IC.

[0004] Clock skew is problematic. Indeed, when data is received by an IC whose clock is not synchronous with the clock of the IC which sent said data, then there is a risk that said data be lost or distorted due to an incorrect sampling of the latter.

[0005] In order to solve this problem, it was known to link ICs in a daisy chain and to propagate a start signal from the first IC in said daisy chain to the last IC in said chain. Then, from a determination of the time latency of the transmission of said start signal in said chain, it was possible to wait for the arrival of the start signal to the last IC in said chain for starting synchronous actions of the ICs. However, such solution is not appropriate for new network configurations of ICs wherein the ICs are typically distributed in star, wherein all ICs of an emulator system are for instance directly connected with one another for bidirectionally exchanging data. Typically, in a daisy chain, the first IC is not directly connected to the last IC, but via the series of interconnected ICs in between, using thus short connection cables. At the opposite, according to said new configuration, the first IC will be directly connected to the last IC, increasing thus notably the length of cables and consequently propagation time of data. Consequently, making a synchronous signal exchange is not anymore possible in such a configuration. Indeed, the clock skew together with the latency resulting from the propagation time of the start signal through the length of the cables (typically, several tens of meters) make it impossible to synchronously exchange signals.

[0006] Therefore, despite the existing solutions, there is still a need to improve the synchronicity of ICs having to work together, notably in order to improve the sampling accuracy.SUMMARY OF THE INVENTION

[0007] An objective of the present invention is to propose a method and system for synchronizing several modules on a clock signal in order to enable a synchronized sampling of exchanged data.

[0008] This objective is achieved by the measures taken in accordance with the independent claims. Further advantageous embodiments are proposed by the dependent claims.

[0009] According to an aspect of the invention, a method for synchronizing a module A with each module Bj of a set S is proposed, wherein j=1 ,...,M, M > 1 , and S={BI ,...,BM}, said set S comprising therefore at least one module, for instance the module Bi. The module A is usually called “master module”, while the modules Bj are usually called “slave modules”. The module A is configured for operating in synchronicity with a clock signal CK_A of period T, notably for triggering actions in synchronicity with said clock signal CK_A, like outputting or generating or sending a signal S_Aj to the module Bj in synchronicity with said clock signal CK_A, or for reading (e.g. sampling data in) an incoming signal S_Bj received from the module Bj, wherein said reading can be performed in synchronicity with said clock signal CK_A. Each module Bj is configured for operating in synchronicity with a clock signal CK Bj of said period T, notably for triggering actions in synchronicity with said clock signal CK Bj, like reading incoming signal S_Aj (e.g. for sampling data of signal S_Aj) in synchronicity with clock signal CK Bj, or generating or outputting or sending a signal S_Bj in synchronicity with clock signal CK Bj. Furthermore, each module Bj comprises a sampling component configured for sampling, at a sampling location, data values of the signal S_Aj sent by module A to module Bj. The sampling component is typically a flip-flop configured for sampling data at said sampling signal. In particular, a clock A of module A may acquire or generate said clock signal CK_A and a clock Bj of module Bj may acquire or generate said clock signal CK Bj of period T. In particular, according to the present invention, a skewbetween clock A and clock Bj, i.e. between clock signal CK_A and clock signal CK Bj, is preferentially smaller or equal to T / 2.

[0010] According to the present invention, the module A and module Bj are preferentially connected with one another by connecting means, e.g. by one or several cables, configured for ensuring an identical or substantially identical propagation time of data between said module A and said module Bj whatever the direction of propagation of said data is, i.e. from module A to module Bj or from module Bj to module A. For instance, the module A might be connected to the module Bj by a single cable enabling a bidirectional exchange of data, so that, via said cable, module A may send a signal S_Aj to module Bj and module Bj may send a signal S_Bj to module A. Alternatively, a first cable may connect module A to module Bj for enabling the sending, by module A, of said signal S_Aj to module Bj, and a second cable may connect said module A to module Bj for enabling the sending, by module Bj, of a signal S_Bj to module A, wherein the first and second cables are configured for ensuring said identical time of propagation of signal data between the module A and the module Bj whatever the direction of propagation is by having for instance the same length and data propagation characteristics.

[0011] The method according to the invention comprises an adjustment or a control, by a phase adjustment circuit, for each couple of modules formed by the module A and one module Bj of the set S, and in function of a total adjustment time TT Dj calculated for each couple, of a relative time between an arrival time of signal S _Aj data at the sampling location of the sampling component of the module Bj and a sampling time of said data by the sampling component of module Bj, wherein said sampling time is temporally directly adjacent to the arrival time; and wherein said total adjustment time TT Dj is configured for increasing, e.g. maximizing or optimizing, for both a sampling by a sampling component of module A of data values of a signal S_Bj sent by the module Bj to the module A and the sampling by the sampling component of module Bj of data values of the signal S_Aj, a time separation between data arrival at a sampling location of theconcerned sampling component and data sampling by said concerned sampling component, wherein the time at which said data sampling takes place is temporally directly adjacent to the time at which the data arrive at said sampling location of the concerned sampling component.

[0012] In other words, the present invention proposes a method that can automatically determine a total adjustment time TT Dj, e.g. that can automatically set a value for said total adjustment time, that increases (e.g. optimizes or maximizes) the time separation between data arrival at the sampling location of the sampling component and any one of the temporally adjacent sampling times at said sampling component for both the module A and the module Bj, i.e. for the sampling by the sampling component of module A and, at the same time, for the sampling by the sampling component of module Bj. The total adjustment time TT Dj is thus a common phase adjustment value, i.e. which is used for both module A and module Bj, the method resulting in an equivalent phase adjustment value (i.e. the value of said TT Dj) for both paths, i.e. to be applied by the system for a signal sent by module A to module Bj, as well as for a signal sent by module Bj to module A, the total phase adjustment value being a right balance for avoiding a sampling of data at a time at which a data change takes place within an incoming signal, and this for said both paths.

[0013] According to another aspect of the present invention, a system for synchronizing several modules is disclosed. Said system is notably able to synchronize the module A with each module Bj of said set S of modules, wherein j=1 ,...,M, M > 1 , and S={BI , ... ,BM}. Said system comprises: the module A configured for operating in synchronicity with the clock signal CK_A of period T; said set S of modules Bj, wherein each module Bj is configured for operating in synchronicity with said clock signal CK Bj of said period T, each module Bj comprising a sampling component configured for sampling data values of a signal S_Aj sent by module A to module Bj at a sampling location;characterized in that said system further comprises at least one phase adjustment circuit, wherein said phase adjustment circuit is configured for: adjusting or controlling , for each couple of modules formed by the module A and one of said modules Bj and in function of a total adjustment time TT Dj calculated for each couple, a relative time between an arrival time of signal S_Aj data at the sampling location of the sampling component of the module Bj and a sampling time of said data by the sampling component of module Bj, wherein said sampling time is temporally directly adjacent to the arrival time. Said sampling time can be any of the adjacent sampling times of said arrival time. Preferably, said total adjustment time TT Dj enables the system to adjust or control the relative time between said arrival time and the adjacent sampling times of said data by the sampling component of module Bj; wherein said total adjustment time TT Dj is configured for increasing, e.g. maximizing or optimizing, for both a sampling, by a sampling component of module A, of data values of a signal S_Bj sent by the module Bj to the module A and the sampling, by the sampling component of module Bj, of data values of the signal S_Aj, a time separation between data arrival at the sampling location of their respective sampling component and data sampling by their respective sampling component, wherein the time at which said data sampling takes place is temporally directly adjacent to the time at which the data arrive at said sampling location of the concerned respective sampling component. By “optimizing” said time separation, it has to be understood that the claimed invention is seeking a value for the total adjustment time TT Dj that is able to prevent that a sampling takes place at the same time as an arrival time of a data change at a sampling location for both the sampling component of module A and the sampling component of module Bj. For instance, the system may comprise, stored in a memory, a threshold, wherein the system is then configured for determining for which value of said total adjustment time TT Dj, said time separation is greater than said threshold with respect to adjacent sampling times for both the sampling by the sampling component of module A and the sampling by the sampling component of module Bj, automatically choosing then the value of TT Dj, or one of the values of TT Dj (e.g. the lowest value), for which saidtime separation is greater than said threshold. In particular, the total adjustment time TT Dj “maximizes” said time separation, if the value of said time separation resulting from the value of the total adjustment time TT_Dj is above a maximum threshold with respect to any directly adjacent sampling time for both the sampling by the sampling component of module A and the sampling by the sampling component of module Bj. In particular, said time separation can be considered as increased, resp. maximized, when the value of the total adjustment time TT_Dj results in jointly (i.e. at the same time for both module A and module Bj) increasing, resp. maximizing, a minimum value for the separation time between data arrival time and adjacent data sampling times for the sampling by the sampling component of module A and the sampling by the sampling component of module Bj.

[0014] According to the present invention, the total adjustment time TT Dj is preferentially automatically determined by the system during a calibration phase, wherein the module Bj is configured for automatically returning, e.g. looping back, to the module A a calibration signal S’_Aj received from the module A. Preferably, said calibration phase comprises a repetition loop configured for automatically determining a value of said total adjustment time TT Dj by iteratively changing a value of an adjustable time T_Di j used for iteratively modifying said time separation, and setting the value of the total adjustment time TT Dj equal to the value of the adjustable time that results in a separation time that prevents a sampling of data at a time at which a data change takes place for both said sampling by the sampling component of module A and said sampling by the sampling component of module Bj. Preferably, a value of the total adjustment time TT Dj that optimizes or maximizes said time separation is automatically selected or determined during said calibration phase.

[0015] Preferably, the adjustable time is defined as T_Di,j = (i-1 )■ T ine, wherein TJnc is a time increment with TJnc < T, and i is an integer, wherein 0<i<imax, with imax’Tinc > T, and wherein, during said repetition loop, the value of T Dij is changed by iteratively taking different values for the integer i. For instance, one may have N-T inc > T and (N-1 ) T ine < T, N being a positiveinteger which is preferentially greater or equal to 3, and i max = N. In particular, the time increment T ine might be acquired or received or automatically determined by module A, for instance by dividing the period T by said number N, wherein said number N might be a parameter stored in a memory of module A or inputted by an operator. In particular, N > n + 3, with n being a positive integer or a positive real number satisfying n-T inc > maximum skew between module A and module Bj, said maximum skew comprising for instance the skew between the clock signals CK_A and CK_Bj, and optionally any latency resulting from data propagation in said connecting means between module A and module Bj and / or data processing in any intern components (e.g. buffer, FPGA, etc.) of module A and / or Bj.

[0016] The repetition loop for determining said total adjustment time TT Dj may then comprise, for i=1 ,...,N, the following steps:- step A: during an initial clock cycle CKOJJ of clock signal CK_A, outputting, by module A, the calibration signal S’_Aj, the latter comprising a change CJJ from a first data value to a second data value, and applying, to a relative time between an arrival time of signal S’_Aj data at the sampling location of the sampling component of the module Bj and a sampling time of said data by the sampling component of module Bj, a time adjustment T_Di,j (typically expressed in ns), with T_Di,j = (i-1 )-T_inc, for sampling the signal S’_Aj with said sampling component of module Bj, and starting a counter configured for counting clock signal CK_A cycles. Optionally, the system might be configured for maintaining or retaining said second data value in the calibration signal S’_Aj at the output of module A during a period of time T_Mj extending at least until the time at which the calibration signal S'_Aj comprising said data change C_i,j is received back from module Bj by module A (e.g. extending until a detection by module A of said change in the calibration signal S’_Aj sent back by module Bj);- step B: counting, by means of said counter and from said initial clock cycle CKOJJ, a number Lij of clock signal CK_A cycles until a final clock cycle CKF i,j, wherein said final clock cycle CKF JJ is a clock cycle of clock signalCK_A at which said counter receives a stop signal configured for stopping said counting by said counter, wherein said stop signal is generated upon detection, by the module A, of said change in the signal S’_Aj received back from module Bj, wherein the latter is configured for sending back to module A the received signal S’_Aj during said repetition loop, using for instance a loop back mode, and wherein, for sending, by the module Bj, the signal S’_Aj back to module A, the system is configured for applying said time adjustment T_Di,j to another relative time, wherein said another relative time is a relative time between an arrival time of the signal S’_Aj data at a sampling location of the sampling component of the module A and a sampling time of said data by the sampling component of module A when sampling the signal S’_Aj with said sampling component of module A. Said number Lij is for instance the number of clock signal OK A cycles between a time T_Si,j at which said transition or change C_i,j took place and a time T_Ri,j at which said stop signal, indicating that module A detected said transition in the calibration signal S’_Aj received back from module Bj, is received by the counter. During said repetition loop, module Bj is thus configured for automatically sending back to module A the received calibration signal S’_Aj. Preferably, after detection by module A of said change C_i,j in said calibration signal S’_Aj sent back by module Bj, the method comprises outputting, by module A, a change from said second data value to said first data value in the calibration signal S’_Aj to be sent to the module Bj, and preferentially keeping the calibration signal S’_Aj at said first data value until starting again step A;- step C: storing for the time adjustment T_Di j the corresponding number Lij of counted clock signal CK_A cycles and, if i<N, repeating steps A-C for i=i+1 , otherwise stopping the repetition loop; and after stopping the repetition loop, the system is configured for automatically choosing, among the set of time adjustments {T_Di j,...,T_DNJ}, a time adjustment T_Ds,j, with s e{1 , ... , N}, characterized by an even number Lsj of cycles, and for which, for both the sampling component of module A and the sampling component of module Bj, an arrival of the change C_s,j at the sampling location of the considered sampling component is temporally located thefarthest, or among the farthest ones, from adjacent times of sampling by the considered sampling component, the system being further configured for setting TT_Dj = T_Ds,j = (s-1 ) TJnc. In other words, the system is configured for choosing a time adjustment T_Ds,j that jointly increases or maximizes or optimizes the minimum time separation between the change C_s,j arrival time at the sampling location and adjacent sampling times at said sampling location for both the module A and the module Bj.

[0017] According to the present invention, a set {LI ,...,LN } of numbers of counted clock signal CK_A cycles corresponds to a set of time adjustments {T_Di ,j,...,T_DNJ}: for each time adjustment T_Dij, a corresponding number Lij of cycles has been counted. In particular, such a set {Lij,..., LNJ} might be obtained for time increments which cumulatively cover one clock period T. Preferably, the system might be configured for automatically determining a larger set {Li , ... , LNJ,LN+I , ... ,LN+N } that corresponds to successively adding the time increment so that cumulatively two successive clock periods are covered. Such a larger set is thus associated to a larger set of time adjustments {T_Di ,...,T_DN,j,T+T_Di ,...,T+T_DNj} (see in particular Fig. 6 as illustration of cumulatively incrementing the time increment so that a first and a second clock period be covered, in the specific case of Fig. 6, with T ine = T / N, N=8, and T = 10ns). Preferably, the system according to the invention is configured for automatically determining such a larger set {Lij,..., LNJ,LN+I J,.. .,LN+NJ} of numbers of counted clock signal OK A cycles for cumulated time increments covering two successive clock periods, and for automatically selecting, within said larger set, a subset comprising the largest number of consecutive identical even number of cycles, and within said selected subset, the system is configured for selecting the midpoint in said selected subset if it comprises an odd number of numbers of counted cycles and for assigning to TT Dj the time adjustment value corresponding to said midpoint, and if it comprises an even number of numbers of counted cycles, it is configured for selecting one of the two central points of the subset, preferentially the central point corresponding to the lowest time adjustment value, and for assigning to TT Dj the time adjustment value corresponding to the selected central point. In particular, if there are two subsetsthat are equivalently the largest, then the previously described steps for assigning to TT Dj a time adjustment value are repeated for both subsets, and at the end, the system is configured for automatically selecting the lowest time adjustment value.

[0018] According to the present invention, said adjusting or controlling might be achieved according to different ways. For instance, it can be performed by adjusting the sampling time of the sampling component of module Bj and / or the time of data arrival at said sampling location of the sampling component of module Bj. In particular, when adjusting the time of data arrival, said phase adjustment circuit comprises at least one adjustable delay component, i.e. a component for adjusting a delay, configured for delaying, with respect to the clock signal CK_A, a time at which the signal S_Aj is sent by module A to module Bj and / or for delaying, after reception of said signal S_Aj by module Bj, the time at which said signal S_Aj arrives at said sampling location of the sampling component of module Bj with respect to the time at which the module Bj received the signal S_Aj.

[0019] Preferably, the total adjustment time TT Dj might be defined as TT Dj = TD Aj + TD Bj, wherein TD Aj and TD Bj are delay times implemented by said phase adjustment circuit so that any change between a first data value and a second data value in a signal S_Aj outputted by module A and configured for being sent to module Bj has been delayed by the delay time TD Aj with respect to an active transition edge of clock signal OK A and an arrival of said change at said sampling location has been delayed by the delay time TD Bj with respect to its reception by the module Bj. The total adjustment time TT Dj can therefore be split between the module A and the module Bj according to the respective value of TD Aj and TD Bj. For instance, we may have T DAj = TT Dj and T DBj = 0, or T DBj = TT Dj and T DAj = 0, or T DAj = TT_Dj / 2 = T DBj. Of course, another splitting is possible. In order to achieve this, the system preferentially comprises, if TD Aj + 0, a first adjustable delay component installed within module A that is configured for applying said delay time TD Aj to the sending of signal S_Aj to module Bj, and, if TD Bj 0, a second adjustable delaycomponent installed within module Bj and that is configured for implementing the delay time TD Bj. Of course, if TD Aj = 0, or resp. TD Bj = 0, then said first adjustable delay component, resp. second adjustable component, is not required. Said first adjustable delay component is for instance a flip-flop whose clock can be controlled in function of the clock signal CK_A, or a programmable delay component, or a tapped delay line enabling to control the time at which a signal is outputted from module A. Preferably, the second adjustable delay component is a programmable delay component or a tapped delay line.

[0020] Preferably, the system according to the invention is configured for implementing a latency adjustment in order to synchronize several or all modules Bj of the set. For instance, the system, e.g. module A, might be configured for: determining, for each module Bj, a number Lj of cycles of clock signal CK_A or CK Bj between a time at which a signal S_Aj data is outputted by module A and the time at which said data is sampled by the sampling component of module Bj. Preferably, the system automatically sets Lj as Lj = Ls.j / 2; determining, among all numbers Lj, the greatest number called hereafter LMax, wherein Lwax = Lq> Lr, V q,r e{1 ,...,M], with q r; simultaneously sending to each module Bj a start signal using S_Aj that is configured for synchronously starting all modules Bj, the module Bj being configured for adjusting said relative time between the arrival time of signal S_Aj data at the sampling location of the sampling component of the module Bj and the sampling time of said data by the sampling component of module Bj by the delay time TD_Bj with respect to its reception time by module Bj before its sampling by the sampling component of module Bj takes place and the system is further configured to apply a further delay to the signal S_Aj of LMax - Lj cycles applied as a first further delay of 0 or more clock signal CK_A cycles of delay at module A before transmission of the signal S_Aj and a second further delay of 0 or more clock signal CK_Bj cycles of delay at module Bj after sampling the signal S_Aj such that a sum of said first further delay and second further delay totals LMax - Lj cycles.

[0021] In particular, the sampling component of module Bj may comprise a flip-flop with adjustable clock which can be adjusted with respect to the clock signal CK_Bj in order to adjust or control the sampling time in function of said total adjustment time TT_Dj time. In such a case, the phase adjustment circuit preferentially comprises a retiming element, e.g. a flip-flop, installed within module Bj, said retiming element being configured for retiming the signal sampled by said flip-flop of the sampling component of module Bj to the clock signal CK_Bj. For instance, the module Bj might be configured for adjusting said relative time between the arrival time of signal S_Aj data at the sampling location of the sampling component of the module Bj and the sampling time of said data by the sampling component of module Bj by applying a sampling delay TDS_Bj with respect to the clock signal CK_Bj for delaying the sampling of signal S_Aj data. In such a case, during latency adjustment, the module Bj is configured for applying the sampling delay TDS_Bj when sampling the signal S_Aj, and the system is further configured for applying said further delay of Lwax - Lj cycles to the signal S_Aj, wherein, as explained earlier, said further delay can be applied as a combination of said first further delay and said second further delay.

[0022] According to the present invention, the total adjustment time TT_Dj might be used for synchronizing module A and the module Bj when their roles are reversed, i.e. when module Bj is sending a signal S_Bj to module A and the latter is reading said signal S_Bj. In such a case, the phase adjustment circuit is preferentially further configured for adjusting or controlling for each couple of modules formed by the module A and one of said modules Bj and in function of said total adjustment time TT Dj calculated for the concerned couple, another relative time that is the relative time between an arrival time of signal S_Bj data at a sampling location of the sampling component of the module A and a sampling time of said data by the sampling component of module A, wherein said sampling time is temporally directly adjacent to said arrival time. In particular, said adjusting or controlling of said another relative time might be performed by adjusting the sampling time of the sampling component of module A and / or the time of arrival at said sampling location of the sampling component of module A. For instance, the phase adjustment circuit might be configured forapplying, for the module Bj , a delay time TD’ Bj to the sending of the signal S_Bj to module A, and, within the module A, for delaying the arrival of the signal S_Bj at the sampling location of the module A by a delay time TD’_Aj with respect to the time at which the signal S_Bj is received by module A, wherein TT Dj = TD’ Aj + TD’ Bj. In other words, in this specific case of delaying an arrival time of signal S_Bj data at the sampling location of module A, the output, by module Bj of a change or transition between a first data value and a second data value in the signal S_Bj outputted by module Bj and configured for being sent to module A would be delayed within module Bj and with respect to its clock signal CK Bj by an amount of time equal to said delay time TD’ Bj, and the arrival time of said change at the sampling location of module A would be delayed, within module A, by the delay time TD’_Aj with respect to its reception time by module A. Preferentially TD’ Aj = TD Aj and TD’ Bj = TD Bj.

[0023] Finally, the system according to the invention is preferentially configured for implementing the previously described and claimed method at each of its power-on. Therefore, at each power-on of the system, and for each couple formed by the module A and one of said modules Bj, a total adjustment time TT Dj, that is specific to this couple and which depends notably on a link (or connection means) connecting the module A to the concerned module Bj, is calculated by the system, for instance by module A, the system further performing as well and preferentially said latency adjustment for all modules Bj connected to module A, in order to synchronize all modules that are interconnected, i.e. the modules A, BI ,...,BM.BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0024] Further aspects of the present invention will be better understood through the following drawings, wherein like numbers designate like objects:

[0025] Fig. 1 is a schematic illustration of a system according to the invention;

[0026] Fig. 2 is a schematic illustration of a propagation of a signal delayed by a first time increment.

[0027] Fig. 3 is a flowchart of a preferred embodiment of a method according to the invention.

[0028] Fig. 4 is a schematic illustration of a propagation of a signal delayed by another time increment.

[0029] Fig. 5 is a table showing examples of results of an iteration process according to the invention.

[0030] Fig. 6 is a table showing examples of results of an iteration process according to the invention for two successive clock periods.DESCRIPTION OF EMBODIMENTS OF THE INVENTION

[0031] Figure 1 shows a schematic illustration of a system 100 according to the invention. Said system 100 comprises typically several modules, namely a master module called module A 110 and one or several slave modules Bj with j=1 ,...,M. In order to illustrate the present invention, the synchronization of the module A with a module Bj 120 belonging to the set S={BI ,...,BM} will be taken as example. Even if module A is a master module, module A and module Bj might be identical. They are typically electrical arrangements, e.g. ICs, configured for operating or acting in synchronicity with a clock signal.

[0032] Preferably, module A 110 comprises: a counter 11 1 for counting a number of clock cycles with respect to a clock signal CK_A; a signal emitter 112, comprising for instance a flip-flop, for outputting a signal S_Aj 220 in function of, e.g. in synchronicity with, the clock signal CK_A, wherein the clock signal CK_A might be received or generated by the module A;a signal receiver 114 for receiving a signal S_Bj from module Bj 120. Said signal receiver 114 typically comprises a sampling component, e.g. a flip-flop, through which the signal S_Aj passes, and data are sampled. For the present invention, one considers that said sampling component is configured for sampling at a sampling location. As explained afterwards, said signal receiver 114 might be connected to the counter 111 for triggering a stopping of said counting of the number of clock cycles when a calibration signal S’_Aj is received back from module Bj. The signal receiver 114 comprises thus typically a sampling component configured for sampling incoming data of an incoming signal (e.g. of the signal S'_Aj sent back by module Bj, or, more generally speaking, of a signal S_Bj sent by said module Bj), notably via its flip-flop, in function of, e.g. in synchronicity with, the clock signal CK_A. Said signal receiver 114 and signal emitter 112 of module A might be connected with one another; a processor unit 115 for determining a total adjustment time TT Dj that is notably configured for acting as a latency adjustment parameter for adjusting a latency of a communication link between module A and module Bj with respect to the clock signal CK_A and the clock signal CK Bj. Said communication link might be embodied as a cable connecting module A to module Bj. Preferably, the cable length that has to be covered by a signal S_Aj outputted by module A and sent to module Bj is the same as the cable length that has to be covered by a signal S_Bj outputted by module Bj and sent to module A.

[0033] Preferably, module Bj 120 comprises: a signal receiver 124 for receiving said signal S_Aj 220 sent by module A, said signal receiver 124 typically comprises a sampling component, e.g. a flipflop, through which said signal S_Aj passes. The signal receiver 124 is typically configured for sampling, via its sampling component and at a given sampling location, the incoming data of signal S_Aj in function of, e.g. in synchronicity with, a clock signal CK Bj, which might be received or generated by the module Bj; a signal emitter 122, comprising for instance a flip-flop, for sending a signal S_Bj to module A in function of, e.g. in synchronicity with, the clock signal Bj. The signal emitter 124 and the signal receiver 124 of module Bj are typicallyconnected with one another for enabling the reception and notably the transmission back to module A of said calibration signal S'_Aj.

[0034] The module Bj typically works in loopback mode for sending back to module A the calibration signal S’_Aj. In other words, the calibration signal S’_Aj is sent back to the module A free of any processing or modification. Practically speaking, module A and module Bj may each comprise an FPGA comprising said signal emitter, said signal receiver, the processing unit, and the counter.

[0035] In particular, module A and / or module Bj might comprise an internal local clock for generating their clock signal, i.e. clock signal CK_A for module A and clock signal CK_Bj for module Bj. According to another embodiment, and Preferably, module A and module Bj are connected to a global clock CK 130 configured for generating a global clock signal 131 that is distributed to all modules of the system, i.e. to module A and all modules BI ,...,BM, notably to their respective signal emitter 1 12, 122 and signal receiver 1 14, 124. Typically, the flip-flops of the respective signal emitters and signal receivers of module A and module Bj are configured for being connected to the global clock CK 130 in order to receive said global clock signal 131 . However, as known in the art, due to a difference in propagation times for the global clock signal to cover on one hand the distance separating the global clock CK 130 from the module A and on the other hand the distance separating the global clock CK 130 from the module B, the clock signal according to which the module A effectively operates (i.e. said clock signal CK_A), and respectively the clock signal according to which the module Bj effectively operates (i.e. said clock signal CK Bj) might be each slightly out of phase with respect to the global clock signal as outputted by the global clock CK 130. Therefore, the clock signal CK_A and the clock signal CK Bj might be out of phase. The present invention proposes a new way for synchronizing module A and module Bj so that they can operate synchronously, overcoming therefore the skew problem of their respective clock.

[0036] A clock signal according to the invention, e.g. the clock signal CK_A 210 as illustrated in Fig. 2 or the clock signal CK Bj, is typically a signalperiodically oscillating between two values, namely a low value and a high value. It is usually a square wave. Each cycle or period T of such a clock signal comprises a rising edge 211 and a falling edge 212. Said rising edge and / or said falling edge are typically used for triggering some actions or operations of the module according to the invention, e.g. of the module A or the module Bj, like sampling data in synchronicity with said rising or falling edge, and / or generating a data transition on said rising or falling edge. For instance, module B 120 may sample data of incoming signal S_Aj 220 on the rising edges of clock signal CK Bj. Alternatively or additionally, it can sample data of signal S_Aj on the falling edge of clock signal CK Bj. Preferably, both module A and module Bj operate in synchronicity with rising edges of their respective clock signal.Alternatively, or additionally, they both operate in synchronicity with falling edges of their respective clock signal. According to another embodiment, module A may operate in synchronicity with rising edges of clock signal CK_A and module B may operate in synchronicity with falling edges of clock signal CK Bj. Inversely, module Bj may operate in synchronicity with rising edges of clock signal CK Bj and module A may operate in synchronicity with falling edges of clock signal CK_A. Other situations may occur with respect to operating in synchronicity with falling and / or rising edges of their respective clock signals, as long as it ensures that, for data, the propagation time from the module A to the module Bj (i.e. for a signal S_Aj) and the propagation time from the module Bj to the module A (i.e. for a signal S_Bj) are identical (or substantially identical). Hereafter, rising and falling edges will be generically referred to as “transition edges”. A transition edge can therefore be a rising or a falling edge of a clock signal. Additionally, the transition edge of a clock signal on which a module operates, e.g. for generating a change from a first value to a second value, or vice versa, in an outputted signal, or for sampling data of an incoming signal, will be referred to as the active transition edge, the other transition edge being then referred to as the inactive transition edge if any (i.e. only if both transition edges are not used for triggering an operation of the concerned module).

[0037] According to the present invention, the signal S_Aj might be represented as a series or sequence of data having discrete values being eithera first value or a second value. It is typically a binary signal (also called logic signal), wherein said first value is for instance zero and said second value is for instance one. Module A, in particular its signal emitter 112, is configured, notably in a nominal working mode, for outputting any data transition in said signal S_A from said first value to said second value and vice versa (e.g. 0->1 or 1->0) in synchronicity with its clock signal CK_A. More precisely, any data transition takes place on an active transition edge of said clock signal CK_A. Said data transition from a first value to a second value is thus synchronized on active transition edges of the clock signal CK_A. The same applies mutatis mutandis to module Bj for any signal S_Bj outputted by module B, i.e. outputted by its signal emitter 122: in its nominal working mode, any transition between a first and second value is realized synchronously with active transition edges of its clock signal CK Bj. This is also thus true for the signal S_Aj sent back by module Bj to module A.

[0038] Figure 2 is an illustration of a latency within the system 100 according to the invention. More precisely, it illustrates the time, counted in number of module A clock cycles, that is needed for a signal S_Aj 220 outputted by the signal emitter 112 of module A and sent to module Bj for looping back to module A. As explained earlier, the clock signal CK_A 210 and clock signal CK Bj have the same frequency, and thus the same period T. The signal emitter 1 12 and signal receiver 114 of module A operate, according to their respective nominal working mode, in synchronicity with clock signal CK_A while the signal emitter 122 and the signal receiver 124 of module Bj operate, according to their respective nominal working mode, in synchronicity with the clock signal CK Bj. Figure 2, together with Figure 1 will now be used for explaining the method according to the invention as illustrated in Figure 3.

[0039] The method according to the invention comprises a control or adjustment, for each couple of modules formed by the module A 110 and one of said modules Bj 120, and in function of a total adjustment time TT Dj calculated for each couple, of a relative time between an arrival time of signal S_Aj data at the sampling location of the sampling component of the module Bj 120 and anadjacent sampling time, e.g. each of the adjacent sampling times, of said data by the sampling component of module Bj. By controlling or adjusting said relative time, the system is able to control the time separation between an arrival time of data at said sampling location and each of the adjacent sampling times at which data are sampled by said sampling component aiming to optimize said time separation so that no sampling takes place at the moment a data change would arrive at the sampling location. According to the presently claimed method, the total adjustment time TT_Dj is automatically determined by the system 100. For this purpose, the method comprises a calibration phase whose preferred embodiment is described hereafter in more details.

[0040] Said calibration phase comprises the following steps:

[0041] At step 301 , a time increment T ine < T is set within module A 1 10. Different values might be assigned to T ine. However, the value chosen for T ine should verify N-T_inc > T and (N-1 ) T ine < T with N being a positive integer. Preferably, T ine = T / N, with N > 3. For instance, said time increment T ine might be received or acquired or determined by module A. In particular, the time increment T ine can be automatically calculated by said module A, or by the system 100, by dividing the period T by the number N, wherein N might be a parameter stored in module A. The typical order of magnitude of the period T is several to tens of nanoseconds, e.g. T = 10 ns. Preferably, N is comprised between 5 and 15. For instance, N = 8, T = 10ns, and T ine = 1 .25 ns, as illustrated in Fig. 5 and Fig. 6. In particular, the processor unit 115 of module A is configured for automatically calculating said time increment T ine. Preferably, the processor unit 115 is further configured for automatically determining said number N in function of said cable length and a propagation speed of signal S_Aj in said cable, notably by setting N > n+3 wherein n can take any value verifying that a maximum skew < n-TJnc and preferentially keeping N < 2- (n+3). Of course, values greater than 2-(n+3) might also be taken for N, which will increase the precision of the total adjustment time TT Dj, but also the time required for the determination of TT Dj. The proposed values are a compromise between precision while keeping the required processing time for said calibrationphase sufficiently low . Alternatively, said number N might be a parameter inputted within module A by an operator and stored in a memory of said processor unit 115. Said period T might be measured by the processor unit 115 or be a predefined parameter, e.g. stored in module A, that is used by said processor unit 115 for calculating T ine. Alternatively, said time increment T ine can be calculated by an external system and sent to module A.

[0042] At step 302, the module A is configured for determining said total adjustment time TT_Dj. As said earlier, said total adjustment time enables the system to adjust the relative time between an arrival of data at the sampling location of module Bj and adjacent sampling times (with respect to the time of arrival) of the sampling component of said module Bj when considering a sending of the signal S_Aj to module Bj, and optionally, also to adjust another relative time that is the relative time between an arrival of data at the sampling location of module A and adjacent sampling times (with respect to the time of arrival) of the sampling component of said module A when considering a sending of a signal S_Bj to module A. . It acts thus as a latency adjustment parameter, taking into account the amount of time (measured in number of clock cycles) taken by said data outputted by module A to reach module Bj, with the assumption, according to the present invention, that said amount of time would be the same for a data sent by module Bj to module A, and aiming that a sampling of said data within module Bj takes place “as far as possible” from an active transition edge of a sampling clock signal which can be for instance the clock signal CK Bj itself, or an adjustable sampling clock signal of the sampling component of module Bj.

[0043] In particular, for determining the total adjustment time TT Dj, the system, or preferentially said module A, is configured for implementing a repetition loop 303 that is configured for searching for a value of the total adjustment time TT_Dj that prevents a sampling, for both the sampling component of module A and the sampling component of the module Bj, at a sampling time at which a data change in the signal to be sampled would reach, or arrive at, the sampling location of the concerned sampling component. Inparticular, the system, or preferentially said module A, is configured for choosing a value of said total adjustment time that increases, or optimizes, or maximizes, for both the module A and the module Bj, the time separation between data change arrival time at a sampling location of a considered sampling component and each of the sampling times adjacent to said arrival time at the considered sampling component. The chosen total adjustment time is thus a compromise for improving such time separation for both the module A and the module Bj: it is a common adjustment time that optimizes said time separation at the same time for the sampling of data by module A and the sampling of data by module Bj.

[0044] According to said repetition loop 303, the system, notably the module A, is configured for iteratively increasing an adjustable time T_Di j and for counting, at each iteration, a number of clock signal CK_A cycles needed for a data change comprised in the calibration signal S’_Aj sent by module A to module Bj to loop back to module A, wherein at each iteration, the relative time between the data change arrival at the sampling location of module Bj and an adjacent sampling time (i.e. the time at which an active transition edge of a sampling clock signal, i.e. a clock signal used for the sampling (e.g. clock signal CK Bj or another clock signal of the sampling component), takes place) of the sampling component is changed by the amount of time T ine. This might be implemented by delaying the arrival time of data at the sampling location of module Bj and / or by delaying the time at which the sampling itself takes place with respect to the clock signal CK Bj. For instance, a time delay between outputting, by the signal emitter 1 12, a transition between a first value and a second value and an occurrence of an active transition edge in the clock signal CK_A might be iteratively increased by T ine until said delay equal N-T_inc, at which stage the process stops. For instance, if T ine = 1 .25 ns and N = 8, then said time delay can for instance take iteratively the following values: 0 ns, 1 .25 ns, 2.5 ns, 3.75 ns, 5 ns, 6.25 ns, 7.5 ns, 8.75 ns (see also the table of Fig. 5).

[0045] More precisely, when considering a couple formed by the module A and a module Bj, the repetition loop 303 comprises preferentially the following steps for i = 1 ,...,N, the iteration starting with i=1 :

[0046] Step A: The signal emitter 112 of module A is configured for outputting, during an initial clock cycle CK0_1 ,j 213, of clock signal CK_A, a calibration signal S’_Aj comprising a data transition or change C_1 ,j 221 from a first data value 222 (e.g. 0) to a second data value 223 (e.g. 1 ) and the system, e.g. module A and / or module Bj, applies, to the relative time between an arrival time of calibration signal S’_Aj data at the sampling location of the sampling component of the module Bj 120 and an adjacent time of sampling by the sampling component of module Bj, a time adjustment T_Di,j, with T_Dij = (1 - 1 )-T_inc = 0, for sampling the signal S’_Aj with said sampling component of module Bj. During said initial clock cycle CK0_1 ,j 213, the system, preferentially module A, starts a counter configured for counting clock signal CK_A cycles.

[0047] For instance, said data change C_1 221 may take place simultaneously with the occurrence of an active transition edge in the initial clock cycle CK0_1 ,j 213 of the clock signal OK A. In such a case, the change C_1 ,j is outputted by the signal emitter 112 at a time T_Si synchronously with the active transition edge of the initial clock cycle CK0_1 ,j 213. Preferably, after said change C_1 ,j 221 , the calibration signal S’_Aj is kept to said second value until reception, by the signal receiver 114 of module A, of the calibration signal S’_Aj sent back by module Bj.

[0048] During said initial clock cycle CK0_1 ,j 213, the counter 1 1 starts its counting of cycles of clock signal CK_A. For instance, both the signal emitter 112 and the counter 111 may receive an initialization signal, sent for instance by the processing unit 115, and which, on one side, will initiate the outputting, by the signal emitter 112, of said change C_1 ,j, and on the other side, said counting by the counter. Alternatively, such an initialization signal might be generated by the signal emitter 112 upon generation of said change C_1 ,j and transmitted to the counter 111 for starting said counting. Preferably, the module A simultaneously starts counting the clock cycles of clock signal CK_A and outputs said change C_1 ,j in the calibration signal S’_Aj. Of course, other embodiments are possiblefor starting counting in the same clock cycle as the one in which the change C_1 ,j takes place. This applies mutatis mutandis to any other change C_i ,j.

[0049] Step B: the counter counts a number Lij of cycles until a final clock cycle CKF 1 ,j at which said counting will stop, for instance at a time T_Ri. Indeed, at each new period T or cycle of the clock signal CK_A, the counter 1 1 1 automatically increments its counting by one unit as shown in Fig. 2. This is a counting of the time, expressed in number of clock cycles, that is used for a data outputted by module A to loop back after having been received by module Bj. The propagation of the calibration signal S’_Aj comprising said change C_1 ,j 221 in function of the time is shown at different positions a-e in the system 100 of Fig. 1 (see the positions a-e in Fig. 1 ), wherein position “a” is located at the output of the signal emitter 1 12 of module A, position “b” is located at the input of the sampling component of the signal receiver 122 of module Bj, position “c” is located at the output of the signal emitter 124 of module Bj, position “d” is located at the input of a sampling component of the signal receiver 1 14 of module A, and finally, position “e” is located at an input of the counter 1 11 . As shown in Fig. 2, said data transition or change C_1 ,j 221 will reach position b after n cycles of clock signal CK_A since the initial clock cycle CK0_1 ,j. Module Bj, working for instance in said loopback mode, will send back the received calibration signal S’_Aj to the module A notably without modifying and / or processing said calibration signal S’_Aj. According to the present invention, the system 100, notably module Bj is configured for applying said time adjustment T_Di,j to another relative time that is the relative time between an arrival time of calibration signal S’ Aj data at the sampling location of the sampling component of the module A 1 10 and an adjacent time (in particular, the adjacent times of said arrival time) of sampling said calibration signal S'_Aj data by the sampling component of module A. The technique previously described for the relative time applies mutatis mutandis to said another relative time.

[0050] As illustrated in Fig. 2, the output of said change C_1 ,j 221 in the calibration signal S’_Aj by the signal emitter 122 of module Bj may take place n+1 cycles of clock signal CK_A after said initial clock cycle CK0_1 ,j. Afterwards,the calibration signal S'_Aj is received as input to the sampling component, e.g. flip-flop, of signal receiver 114 at 2n-1 cycles after said initial clock cycle CK0_1 ,j. At this time, the signal receiver 1 14 detects said change CK0_1 ,j and typically sends a stop signal to the counter 1 1 1 which stops counting the clock cycles Li = 2n cycles after having started its counting. The clock cycle at which said counting stops is the so-called final clock cycle CKF 1 . For instance, said stop signal, which might be the calibration signal S’_Aj forwarded to the counter 111 by the signal receiver 1 14, reaches position e 2n clock cycles after said initial clock cycle CK0_1 ,j. Preferably, the detection of said change C_1 ,j by the signal receiver 114 automatically triggers, within the signal emitter 112 a transition from said second value back to the first value in the calibration signal S’_Aj it outputs. Alternatively, said transition back to the first value may take place later on, but in any case before a new iteration.

[0051] Step C: the processing unit 1 15 stores, for the time delay T Di , the number Li j of cycles that has been taken for said change C_1 ,j to loop back to module A in order to trigger the stopping of the counter 1 1 1.

[0052] Then, the value of i is incremented by one unit: i = i+1 = 2 and the steps A-C are repeated for a change C_2,j from said first value 222 to said second value 223 outputted, during an initial clock cycle CK0_2,j of clock signal CK_A, wherein the system, for instance module A and / or module Bj, applies a time adjustment T_D2,j = (2-1 )-T_inc = 1 T ine to said relative time. For instance, said change C_2,j might be delayed by the time adjustment T_D2j = T ine with respect to the time at which an active transition edge in the initial clock cycle CK0_2,j of the clock signal CK_A takes place.

[0053] The iteration continues, and for each i, a change C_i,j 224 is generated and outputted within the calibration signal S’_Aj while applying a time adjustment T_Dij = (i-1 )-T_inc 214 to said relative time between data arrival and data sampling, and a number Lij of clock signal CK_A cycles until a final clock cycle CKFJJ is counted, wherein said final clock cycle CKFJ ,j is a clock cycle of clock signal CK_A at which said counter receives said stop signal generatedupon detection of said change CJJ by the module A in the signal S’_Aj received back from module Bj. For instance, the time at which said change CJJ is outputted by module A might be successively delayed by said adjustment time T_Di,j = (i-1 ) T ine 214 (see Fig. 4) by the signal emitter 114 with respect to an active transition edge of the clock signal CK_A, and a corresponding number Lij 225 of cycles be counted from an initial clock cycle CKOJJ 226 at which said change CJJ is outputted by the signal emitter until the final clock cycle CKF JJ 227 at which the detection of said change CJJ received back from module Bj by the signal receiver 114 is communicated to the counter 1 1 1 . At the end of each iteration, a number Lij of cycles is thus associated to a corresponding time adjustment T_Dij, and the couple (Li,j,T_Dij) is preferentially stored in a memory of the module A, e.g. in a memory of its processing unit 115. Finally, after completing the step A-C for i=N, the repetition loop 303 stops. Optionally, as shown in Fig. 6, such iteration may take place for i = 1 ,...,2N, wherein the above- mentioned steps take place mutatis mutandis.

[0054] Figure 5 shows possible results of such an iteration process for i = 1 ,...,N. The different columns A-H show the time adjustment T_Di,j = (i-1 ) T ine with T ine = 1 .25 ns and i=1 ,...,8 that has been applied, in this example, for delaying the output of the change CJJ, each line showing the numbers Lij of cycles (e.g. 2n, 2n+1 , 2n+2,...) that have been counted during a same repetition loop. Each line represents thus a different case that might occur during a same repetition loop. For instance, for the case of line 1 of the table, whatever the value of the time adjustment T_Dij, the number Lij of clock cycles counted until receiving the stop signal by the counter is always the same and equal to 2n. In another case illustrated by line 10 of the table, 2n+1 cycles will be counted for the time adjustment 0 ns and 1 .25 ns, then, then 2n+2 cycles will be counted for the time adjustments 2.5 ns, 3.75 ns, 5 ns, 6.25 ns, and 7.5 ns, and finally, 2n+3 cycles will be counted for a time adjustment equal to 8.75 ns.

[0055] At step 304, the system 100, preferentially the module A, for instance its processing unit 115, is configured for automatically choosing, among the couples (Li,T_Di)j determined for the module Bj, the couple ( Ls,T_Ds)j, with sG{1 ,...,N}, characterized by an even number Lsof cycles, and Preferably, for which an arrival of the corresponding change C_s at the sampling location of the sampling component of module A is temporally located the farthest, or among the farthest ones, from any adjacent sampling times of the sampling component of module A. This is better illustrated by means of Fig. 5. For instance, when considering the line 10 of the table, one can see that the number Lij of cycles is the same for different sets of time adjustments: it is 2n+1 cycles when applying the time adjustments 0 ns and 1 .25 ns, 2n+2 cycles when applying the time adjustments 2.5 ns, 3.75 ns, 5 ns, 6.25 ns, and 7.5 ns, and 2n+3 cycles when applying the time adjustment 8.75 ns. In such a case, the time adjustment E (5 ns) results in an arrival time of a change comprised within the calibration signal S’_Aj outputted by the signal emitter 112 at the sampling location of module A that will be temporally the farthest one from any adjacent sampling times at the sampling component of module A, which is also true with respect to the sampling by module Bj. Typically, the time at which said change reaches the sampling location of module A is the farthest from any active transition edge of the sampling clock signal, e.g. the clock signal CK_A, used for sampling the incoming signal in module A. Indeed, one wants to avoid the situation of having said change taking place at the instant of sampling, which might lead to an uncertainty of the sampled value. For instance, according to line 18 of the table, when one increases the time adjustment from 0 to 1 .25 ns and then from 7.5 ns to 8.75 ns, the number of counted cycles increases respectively from 2n+1 to 2n+2 and from 2n+2 to 2n+3. This means that it exists a time adjustment D_T 1 with 0<D_T1 <1 .25 ns and a time adjustment D_T2 with 7.5 ns <D_T2< 8.75 ns for which the corresponding outputted change will reach the module Bj and be sampled substantially at the time an active transition edge of a sampling clock signal occurs. And this is actually the situation to be avoided. For this reason, according to the present invention, one of the time adjustments D or E will be automatically chosen by the processing unit, since said time adjustments result, for both the module A and the module Bj, in an arrival time of said change at their respective sampling location that will be temporally located among the farthest ones from any adjacent sampling times at their respective sampling component, i.e. as far away as possible from any active transition edge of asampling clock signal used by their respective sampling component for sampling the incoming signal. By “temporally located among the farthest ones”, it has to be understood that the chosen time adjustment is a compromise between i) increasing, resp. maximizing, the temporal separation between the arrival time of a change at a sampling location of module A and any of the adjacent sampling times performed by the sampling component of module A, and ii) increasing, resp. maximizing, the temporal separation between the arrival time of a change at a sampling location of module Bj and any of the adjacent sampling times for the module Bj. In other words, the chosen time adjustment is a jointly optimized time adjustment value that increases, or resp. maximizes, said time separation for both module A and module Bj, i.e. when considering both paths (i.e. for a signal sent from module A to module B and vice versa), but it might be possible that it is not an optimized time adjustment value when considering a single path (e.g. only from module A to module B). Indeed, according to the present invention, the chosen time adjustment preferentially results in the largest value for the minimum time separation of any data arrival time relative to any adjacent sampling time. Indeed, the method enables to increase or maximize a minimum value of the time separation between data arrival at a sampling location and an adjacent sampling time jointly for both module A and module Bj, i.e. it increases or maximizes or optimizes jointly the time separation between data arrival time at the sampling location of module Bj and a directly preceding sampling time at said sampling location, the time separation between data arrival time at said sampling location of module Bj and a directly following sampling time at said sampling location, the time separation between data arrival time at the sampling location of module A and a directly preceding sampling time at said sampling location of module A, and the time separation between data arrival time at the sampling location of module A and a directly following sampling time at said sampling location of module A.

[0056] The system thus jointly optimizes or maximizes said time separation by optimizing or maximizing said minimum value of the time separation whenconsidering the samplings that take place in both the module A and the module Bj.

[0057] Preferably, the processing unit 115 stores a table, like the table of Fig. 5, defining for the set of time adjustments {T_Di,...,T_DN}j all sets of numbers of cycles {Li,..., l_N}physicaiiy possible that are physically possible given the physical configuration of the link between module A and module Bj, e.g. length of cable, propagation speed, etc., and wherein, within said table, a time adjustment T_Dsj to be applied is predefined for each set of numbers of cycles {Li , ... , l_N}physicaiiy possible. In such a case, the processing unit is then configured for determining which set {L-i . . ,l_N}physicaiiy possible of the table matches the set {LI ,...,LN}J obtained via the repetition loop 303, and then for automatically choosing the time adjustment T_Ds,j that has been predefined for the set {Li , ... ,LN}physicaiiy possible matching the set {LI,...,LN}J obtained via the repetition loop.

[0058] At step 305, the module A, for instance its processing unit 115, sets TT Dj = (T_Ds)j, i.e. it sets the value of the total adjustment time to be used with respect to the module Bj equal to the value of said time adjustment T_Ds,j previously selected at step 304 for module Bj. Said total adjustment time TT_Dj= T_Ds,j might be split between the module A and the module Bj as a delay time TD_Aj and a delay time TD_Bj.

[0059] According to the present invention, different techniques might be implemented for applying the time adjustment T_Dij or adjusting / controlling the relative time in function of the total adjustment time TT Dj. Indeed, both said time adjustment and said total adjustment time enable to adjust the relative time between data arrival at a sampling location and data sampling at said sampling location. It is therefore possible to act on the time of arrival of data at said sampling location and / or on the sampling time at said sampling location when applying the time adjustment T_Dij or when adjusting / controlling the relative time in function of the total adjustment time TT Dj.

[0060] In particular, applying the total adjustment time or the time adjustment T_Di ,j to a relative time means for instance delaying the arrival time of data at the sampling location and / or delaying the time of sampling of said data at said sampling location with respect to the local clock, i.e. clock signal CK Bj when considering the module Bj or clock signal CK_A when considering the module A.

[0061] For instance, the relative time between data arrival at the sampling location and data sampling at said sampling location might be adjusted by acting on the sampling time, wherein the phase adjustment circuit comprises in this case a flip-flop with adjustable clock installed within the sampling component and a retiming element connected to an output of said sampling component. The system is then configured for controlling or adjusting, by means of said adjustable clock, a sampling clock signal used by said flip-flop for sampling an inputted signal (e.g. the incoming signal S_Aj or S’_Aj or S_Bj depending on the considered module), so that, for instance, said sampling be delayed, with respect to the “local” clock signal (i.e. the clock signal CK_A in case of a sampling by module A, or the clock signal CK Bj when considering a sampling by module Bj) by an amount of time equal to said total adjustment time TT Dj after said calibration phase, and respectively, that is equal to said time adjustment T_Dij during the calibration phase. The signal outputted by said flip-flop having done the “delayed” sampling passes then through said retiming element for retiming the outputted signal to the local clock of the considered module. For instance, both the receiver of the module A and of the module Bj might be equipped with said flip-flop with adjustable clock and said retiming element, wherein the signal outputted by the flip-flop passes then through the retiming element for being resynchronized with the local clock. Typically, after calibration, both said flipflops with adjustable clock are configured for delaying their respective sampling time with respect to the local clock by an amount of time equal to TT Dj.

[0062] In order to act on the time of arrival, the phase adjustment circuit may delay the time at which a signal is leaving a module (e.g. module A or module Bj) and / or increase the time spent by an incoming signal between its arrival at a module until its arrival at the sampling location of said module. For delaying thetime at which a signal is leaving a module, the system may act on the time at which data are generated with respect to the local clock of the concerned module (e.g. by using a flip-flop with adjustable clock for delaying the generation of data with respect to the local clock) and / or the time spent by generated data for travelling from their creation / generation location to the output of the concerned module (e.g. by using adjustable delay component, like a tapped line, for delaying the signal of a predefined amount of time). Also, such adjustable delay component might be used for increasing said time spent by an incoming signal between its arrival at a module, i.e. its input to the module, until its arrival at the sampling location of said module.

[0063] For instance, instead of generating data transitions between a first value and a second value synchronously with active transition edges of the clock signal CK_A of module A and directly outputting the generated signal comprising said data transitions (which corresponds to a nominal working mode), the signal emitter 1 12 may output, after determination of said total adjustment , data transitions that are delayed by the value of the total adjustment time with respect to said clock signal CK_A, i.e. with respect to active transition edges of said clock signal CK_A. Said delay might be implemented either by generating a signal S_A0 for which said transitions took place synchronously with active transition edges of said clock signal CK_A, and instead of directly outputting said signal S_A0, delaying its outputting by signal emitter 112 by a delay equal to T DAj, or by delaying the time at which said transition is generated with respect to an active transition edge of the clock signal OK A and outputting without delay the generated signal comprising said transition. In both cases, transitions between a first value and a second value are at the end outputted by the signal emitter delayed with respect to the clock signal of the module A. The same would apply mutatis mutandis to the module Bj when sending a signal S_Bj to module A. Therefore, after completion of the determination of the total adjustment time, any data transition in signals sent by module A to module Bj might be outputted by the signal emitter of module A delayed by T DAj with respect to an active transition edge of the clock signal CK_A, and thus slightlyout-of-phase with respect to the cycles of clock signal CK_A, the same applying mutatis mutandis for data transition in signals sent by the module Bj to module A.

[0064] Similarly, if the total adjustment time is for instance only implemented within the receiving module, then, for delaying the reading or sampling of the signal S_Aj by module Bj, the signal receiver 124 might be configured, instead of sampling incoming data in synchronicity with transition edges of clock signal CK_Bj, and once the total adjustment time TT_Dj has been determined, for delaying said sampling with respect to active transition edges of the clock signal CK Bj by an amount of time equal to the total adjustment time TT_Dj. Therefore, after completion of the determination of the total adjustment time, any sampling of data in the signals received by module Bj from module A will be slightly out-of- phase of the value of TT_Dj with respect to the cycles of clock signal CK Bj, i.e. with respect to transition edges (e.g. either the rising edges or the falling edges depending on how the synchronization with the clock signal CK Bj has been set up within module Bj) of the clock signal CK Bj. The same applies mutatis mutandis to the signal S_Bj received by module A.

[0065] Indeed, and Preferably, said total adjustment time TT Dj is not only used for adjusting the relative time between data arrival at a sampling location and data sampling at said sampling location for the signal S_Aj, i.e. for the sending of data from module A to module Bj and their reading with module Bj, but the same total adjustment time TT Dj might also be used for adjusting the relative time between data arrival at a sampling location and data sampling at said sampling location for the signal S Bj, i.e. for the sending of data from the module Bj to module A and their reading by module A. For instance, once said determination of the total adjustment time is completed, then the module Bj might be configured for delaying the sending of a signal S_Bj to the module A by a delay time TD’ Bj, and the module A might be configured for delaying the arrival time of said signal S_Bj at its sampling location by a delay time TD’_Aj with respect to its arrival time at module A (i.e. its reception at an input of module A), wherein TT Dj = TD’ Aj + TD’ Bj.

[0066] At step 306, the system 100 might be configured for implementing a latency adjustment with respect to each of its modules. This enables to adapt the system to the “worst” case, i.e. to the module, among all modules Bj connected to module A, for which the greatest latency, expressed in number of clock cycles Lmax, is measured, and to adjust the time at which the sampling will start in function of said Lmax. Such an adjustment of the latency which takes into account the worst case is known in the art and does not need further explanations here. However, contrary to existing techniques, the present invention proposes to synchronize the clock cycles of all modules by waiting not only LMax - Lj cycles for module Bj before starting the operation of module Bj, but by further adjusting the relative time between the arrival time of data at the sampling location of module Bj and the adjacent sampling times at said sampling location in function of the value determined for the total adjustment time, , wherein module A has to wait Lwiax cycles for operating synchronously with the other modules.

[0067] To conclude, the present invention proposes a new way of synchronizing modules with one another, which provides several advantages: it makes it possible to align modules which are totally independent and without any constraint of interconnections (as daisy chain according to previous solutions); it makes it possible to start the system with a minimum of latency (just due to physical propagation time of a start signal) and avoids losing any clock cycles due to required elastic buffers mechanism used for managing asynchronism between the modules; it enables a check, at each power-on of the system, of a correct connectivity of all modules by measuring respective latencies, and to guaranty an expected programmed latency, defined and / or stored in the system (e.g. in module A) for instance in function of a length of a cable connecting module A with module Bj, and which might be reused at each power-on in a software of the system configured for implementing the claimed method, e.g. via instructions comprised within the processing unit of module A; it can be easily implemented inside an FPGA;it avoids a use of complex mechanism as Data Phase Alignment or Oversampling for data sampling; it enables to immediately detects any error in the cabling of the modules of the system (bad cable length for example).

Claims

CLAIMS1 . System (100) for synchronizing a module A (1 10) with each module Bj (120) of a set S of modules, wherein jsaid system comprising:- the module A (110) configured for operating in synchronicity with a clock signal CK_A (210) of period T;- said set S of modules Bj (120), wherein each module Bj (120) is configured for operating in synchronicity with a clock signal CK Bj of said period T, each module Bj comprising a sampling component configured for sampling data values of a signal S_Aj sent by module A to module Bj at a sampling location; characterized in that said system (100) further comprises at least one phase adjustment circuit, wherein said phase adjustment circuit is configured for: adjusting or controlling, for each couple of modules formed by the module A (1 10) and one module Bj (120) of the set S and in function of a total adjustment time TT Dj calculated for each couple, a relative time between an arrival time of signal S_Aj data at the sampling location of the sampling component of the module Bj (120) and a sampling time of said data by the sampling component of module Bj, wherein said sampling time is temporally directly adjacent to the arrival time; wherein said total adjustment time TT Dj is configured for increasing, for both a sampling, by a sampling component of module A (1 10), of data values of a signal S_Bj sent by the module Bj (120) to the module A and the sampling, by the sampling component of module Bj (120), of data values of the signal S_Aj, a time separation between data arrival at the sampling location of the concerned sampling component and data sampling by said concerned sampling component, wherein the time at which said data sampling takes place is temporally directly adjacent to the time at which the data arrive at said sampling location of the concerned sampling component.

2. System (100) according to claim 1 , configured for automatically determining said total adjustment time TT Dj during a calibration phase, wherein the module Bj is configured for automatically returning to the module A a calibration signal S’_Aj received from the module A.

3. System according to claim 2, wherein said calibration phase comprises a repetition loop configured for automatically determining a value of said total adjustment time TT_Dj by iteratively changing a value of an adjustable time T Dij used for iteratively modifying said time separation, and setting the value of the total adjustment time TT Dj equal to the value of the adjustable time that results in a separation time that prevents a sampling of data at a time at which a data change takes place for both said sampling by the sampling component of module A (110) and said sampling by the sampling component of module Bj (120).

4. System according to claim 3, wherein T_Di = (i-1 )-T_inc whereinT ine is a time increment with T ine < T; i is an integer, wherein 0<i<i max, with i max’ T inc — T; wherein, during said repetition loop, the value of T_Di,j is changed by iteratively taking different values for the integer i.

5. System (100) according to claim 4, wherein N-T_inc > T and (N-1 ) T ine < T, N being an integer, imax = N, and wherein said repetition loop for determining said total adjustment time TT Dj comprises, for i=1 ,...,N, the following steps:- step A: during an initial clock cycle CK0JJ of clock signal CK_A, outputting, by module A, the calibration signal S’_Aj, the latter comprising a change C_i,j from a first data value to a second data value, and applying, to a relative time between an arrival time of signal S'_Aj data at the sampling location of the sampling component of the module Bj (120) and a sampling time of said data by the sampling component of module Bj, a time adjustment T Dij, with T_Di,j = (i-1 )-T_inc, for sampling the signal S’_Aj with said samplingcomponent of module Bj, and starting a counter configured for counting clock signal CK_A cycles;- step B: counting, by means of said counter and from said initial clock cycle CKOJJ, a number Lij of clock signal CK_A cycles until a final clock cycle CKFJJ, wherein said final clock cycle CKF iJ is a clock cycle of clock signal CK_A at which said counter receives a stop signal configured for stopping said counting by said counter, wherein said stop signal is generated upon detection, by the module A, of said change in the signal S’_Aj received back from module Bj, wherein the latter is configured for sending back to module A the received signal S’_Aj during said repetition loop, and wherein, for sending, by the module Bj, the signal S’_Aj back to module A, the system (100) is configured for applying said time adjustmentT Dij to another relative time, wherein said another relative time is a relative time between an arrival time of calibration signal S’_Aj data at a sampling location of the sampling component of the module A (1 10) and a sampling time of said data by the sampling component of module A for sampling the signal S’_Aj with said sampling component of module A;- step C: storing for the time adjustment T_Dij the corresponding number Li.j of counted clock signal CK_A cycles and, if i<N, repeating steps A-C for i=i+1 , otherwise stopping the repetition loop; and after stopping the repetition loop, the system is configured for automatically choosing, among the set of time adjustments {T_Dij,... ,T_DNJ}, a time adjustment T Dsj, with s e{1 ,...,N}, characterized by an even number L _s,j of cycles, and for which, for both the sampling component of module A and the sampling component of module Bj, an arrival of the change C_s,j at the sampling location of the considered sampling component is temporally located the farthest, or among the farthest ones, from adjacent sampling times of said considered sampling component, the system being further configured for setting TT Dj = T Dsj = (s-1 ) T ine.

6. System (100) according to one of the claims 1 -5, wherein said adjusting or controlling is performed by adjusting the sampling time of the sampling component of module Bj (120) and / or the time of data arrival at said sampling location of the sampling component of module Bj (120).

7. System (100) according to one of the claims 1 -5, wherein said phase adjustment circuit comprises at least one adjustable delay component configured for delaying, with respect to the clock signal CK_A (210), a time at which the signal S_Aj (220) is sent by module A (1 10) to module Bj (120) and / or for delaying, after reception of said signal S_Aj (220) by module Bj (120), the time at which said signal S_Aj (220) arrives at said sampling location of the sampling component of module Bj (120) with respect to the time at which the module Bj (120) received the signal S_Aj (220).

8. System (100) according to claim 7, wherein the total adjustment timeTT Dj = TD Aj + TD Bj, wherein TD Aj and TD Bj are delay times implemented by said phase adjustment circuit so that any change between a first data value (222) and a second data value (223) in a signal S_Aj (220) outputted by module A (1 10) and configured for being sent to module Bj (120) has been delayed by the delay time TD Aj with respect to an active transition edge of clock signal CK_A (210) and an arrival of said change at said sampling location has been delayed by the delay time TD Bj with respect to its reception by the module Bj (120), wherein said system (100) comprises, if TD Aj 0, a first adjustable delay component installed within module A (1 10) that is configured for applying said delay time TD _Aj to the sending of signal S_Aj (220) to module Bj (120), and, if TD Bj 0, a second adjustable delay component installed within module Bj (120) and that is configured for implementing the delay time TD Bj.

9. System (100) according to claim 8, configured for implementing a latency adjustment, wherein the system (100) or module A (1 10) is configured:- for determining, for each module Bj, a number Lj of cycles of clock signal CK_A or CK Bj between a time at which a signal S_Aj data isoutputted by module A (1 10) and the time at which said data is sampled by the sampling component of module Bj (120);- for determining, among all numbers Lj, the greatest number called hereafter l_Max, wherein l_Max = Lq> Lr, V q,r G{1 ,...,M}, with q r;- for simultaneously sending to each module Bj (120) a start signal usingS_Aj that is configured for synchronously starting all modules Bj, the module Bj being configured for adjusting said relative time between the arrival time of signal S_Aj data at the sampling location of the sampling component of the module Bj (120) and the sampling time of said data by the sampling component of module Bj by the delay time TD Bj with respect to its reception time by module Bj before its sampling by the sampling component of module Bj takes place and the system (100) is further configured to apply a further delay to the signal S_Aj of l_Max - Lj cycles applied as a first further delay of 0 or more clock signal OK A cycles of delay at module A before transmission of the signal S_Aj and a second further delay of 0 or more clock signal CK Bj cycles of delay at module Bj after sampling the signal S_Aj such that a sum of said first further delay and second further delay totals LMax - Lj cycles.

10. System (100) according to one of the claims 1 -5, wherein the sampling component of module Bj (120) comprises a flip-flop with adjustable clock with respect to the clock signal CK Bj in order to adjust or control the sampling time in function of said total adjustment time TT Dj time, said phase adjustment circuit comprising a retiming element installed within module Bj, said retiming element being configured for retiming the signal sampled by said flip-flop of the sampling component of module Bj to the clock signal CK Bj.11 . System (100) according to one of the claims 1 -10, wherein said phase adjustment circuit is further configured for adjusting or controlling for each couple of modules formed by the module A (1 10) and one of said modules Bj (120) and in function of said total adjustment time TT Dj calculated for the concerned couple, another relative time that is the relative timebetween an arrival time of signal S_Bj data at a sampling location of the sampling component of the module A (110) and a sampling time of said data by the sampling component of module A, wherein said sampling time is temporally directly adjacent to said arrival time.

12. System (100) according to claim 11 , wherein said adjusting or controlling of said another relative time is performed by adjusting the sampling time of the sampling component of module A (110) and / or the time of arrival at said sampling location of the sampling component of module A (1 10).

13. System (100) according to claim 11 , wherein said phase adjustment circuit is configured for applying, for the module Bj (120), a delay time TD’_Bj to the sending of the signal S_Bj to module A (1 10), and, within the module A (1 10), for delaying the arrival of the signal S_Bj at the sampling location of the module A (1 10) by a delay time TD’ Aj with respect to the time at which the signal S_Bj is received by module A, wherein TT Dj = TD’ Aj + TD’ Bj.

14. Method for synchronizing a module A (110) with each module Bj (120) of a set S, wherein j=1 ,...,M, M > 1 , and S={BI ,...,BM}, wherein the module A (1 10) is configured for operating in synchronicity with a clock signal CK_A (210) of period T and the module Bj (120) is configured for operating in synchronicity with a clock signal CK Bj of said period T, the method comprising:- adjusting or controlling, by a phase adjustment circuit, for each couple of modules formed by the module A (110) and one of said modules Bj (120) and in function of a total adjustment time TT Dj calculated for each couple, a relative time between an arrival time of signal S_Aj data at the sampling location of the sampling component of the module Bj (120) and a sampling time of said data by the sampling component of module Bj, wherein said sampling time is temporally directly adjacent to the arrival time; andwherein said total adjustment time TT_Dj is configured for increasing, for both a sampling by a sampling component of module A (1 10) of data values of a signal S_Bj sent by the module Bj (120) to the module A and the sampling by the sampling component of module Bj (120) of data values of the signal S_Aj, a time separation between data arrival at a sampling location of the concerned sampling component and data sampling by said concerned sampling component, wherein the time at which said data sampling takes place is temporally directly adjacent to the time at which the data arrive at said sampling location of the concerned sampling component.

15. Method according to claim 14, comprising automatically determining said total adjustment time TT_Dj during a calibration phase, comprising automatically returning, by the module Bj to the module A, a calibration signal S’_Aj received from the module A.

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