Storage apparatus and electronic device

Abstract

The present invention provides a storage apparatus which consumes little power. Memory cells of the storage apparatus are in a staggered arrangement and are provided in regions where orthogonal word lines and bit lines intersect. Adjacent word lines have different heights. Such a configuration makes it possible to reduce the number of memory cells per word line and makes it possible to reduce power consumption when reading data. Furthermore, it is possible to provide, in the same cell array, a pair of bit lines that connect to a sense amplifier, and therefore it is possible to reduce noise.

Description

Storage devices and electronic equipment

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing the memory device or the semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] One embodiment of the present invention is not limited to the above technical fields. One embodiment of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Another embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0004] While silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, oxide semiconductors have also attracted attention as other materials. Transistors using oxide semiconductors are known to have extremely low current flow in the non-conducting (off) state.

[0005] For example, Patent Document 1 discloses a memory device that can retain stored data for a long period of time by utilizing the characteristic that a transistor including an oxide semiconductor has a small off-state current.

[0006] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. For example, Patent Document 2 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide a plurality of memory cells in a superimposed manner.

[0007] Furthermore, if a transistor can be made vertical, it is possible to increase the density of an integrated circuit. For example, Patent Document 3 discloses a vertical transistor in which a side surface of an oxide semiconductor is covered with a gate electrode via a gate insulator.

[0008] JP 2011-151383 A International Publication No. 2021 / 053473 JP 2013-211537 A

[0009] M. Oota et. al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0010] In a memory device such as a DRAM, multiple memory cells are connected to one word line. In an example of a read operation, all memory cells connected to one word line transfer data to their corresponding bit lines and activate their sense amplifiers.

[0011] However, the number of memory cells from which data can be read externally at one time is limited by the bus width. Therefore, even among memory cells connected to the same word line, there may be memory cells from which data is read and memory cells from which data is not read. In this case, it can be said that unnecessary power consumption occurs due to the operation of the sense amplifier when data is not read from memory cells.

[0012] Furthermore, with the increase in integration density, an open bit line method is widely used, in which a pair of bit lines arranged in different memory arrays is connected to a sense amplifier. However, the open bit line method has the problem that it is susceptible to noise because there are times when the potential of the word lines differs between memory arrays.

[0013] Therefore, an object of one embodiment of the present invention is to provide a memory device with low power consumption. Another object is to provide a memory device with low noise. Another object is to provide a memory device with high integration. Another object is to provide a memory device with high data read reliability. Another object is to provide a memory device with good electrical characteristics. Another object is to provide a memory device with high reliability. Another object is to provide a novel memory device. Another object is to provide a novel semiconductor device or the like.

[0014] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc.

[0015] One embodiment of the present invention has a first word line, a second word line, a first bit line, a second bit line, a first memory cell, and a second memory cell, the first word line and the second word line being arranged in parallel and adjacent positions, the first bit line and the second bit line being arranged in parallel and adjacent positions, the first word line and the second word line being orthogonal to the first bit line and the second bit line, respectively, in a top view, and the distance between the first word line and the second word line being The memory device has a first memory cell having an area overlapping an intersection area of ​​the first word line and the first bit line, a second memory cell having an area overlapping an intersection area of ​​the second word line and the second bit line, the first bit line and the second bit line being provided on the same plane, each of the first word line and the second word line being located higher than each of the first bit line and the second bit line, and the shortest distance between the first bit line and the first word line being greater than the shortest distance between the second bit line and the second word line.

[0016] When the width of each of the first word lines and the second word lines is F and the pitch of each of the first bit lines and the second bit lines is 2F, the area occupied by each of the first memory cells and the second memory cells is 4F. ２ It can be said that:

[0017] The memory cell may further include a plurality of memory cells, and the first memory cell, the second memory cell, and the plurality of memory cells may be arranged in a staggered pattern when viewed from above.

[0018] The first bit line and the second bit line can be connected to different sense amplifiers, or the first bit line and the second bit line can be connected to the same sense amplifier.

[0019] The first memory cell has a first transistor and a first capacitor, and the first transistor has a gate connected to a first word line, one of a source or a drain connected to a first bit line, and the other of the source or the drain connected to one electrode of the first capacitor.The second memory cell has a second transistor and a second capacitor, and the second transistor has a gate connected to a second word line, one of a source or a drain connected to a second bit line, and the other of the source or the drain connected to one electrode of the second capacitor.

[0020] Each of the first transistor and the second transistor preferably has a channel formation region in a semiconductor provided along a side surface of an opening in an insulator.

[0021] The semiconductor is an oxide semiconductor, and the oxide semiconductor preferably contains one or more elements selected from the group consisting of In, Ga, and Zn.

[0022] Each of the first capacitive element and the second capacitive element may be a trench capacitor.

[0023] According to one embodiment of the present invention, a memory device with low power consumption can be provided. Alternatively, a memory device with low noise can be provided. Alternatively, a memory device with high integration can be provided. Alternatively, a memory device with high data read reliability can be provided. Alternatively, a memory device with favorable electrical characteristics can be provided. Alternatively, a memory device with favorable reliability can be provided. Alternatively, a novel memory device can be provided. Alternatively, a novel semiconductor device or the like can be provided.

[0024] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc.

[0025] FIG. 1A is a perspective view illustrating a memory device. FIG. 1B is a circuit diagram illustrating a memory cell. FIGS. 2A and 2B are diagrams illustrating a memory device. FIG. 3 is a diagram illustrating the operation of a memory device. FIG. 4 is a diagram illustrating the operation of a memory device. FIG. 5 is a diagram illustrating the operation of a memory device. FIG. 6 is a diagram illustrating the operation of a memory device. FIG. 7 is a top view, a front view, and a side view illustrating a memory device. FIGS. 8A and 8B are diagrams illustrating a memory device. FIGS. 9A to 9C are cross-sectional views illustrating a memory device. FIGS. 10A and 10B are cross-sectional views illustrating a memory device. FIGS. 11A to 11C are cross-sectional views illustrating a manufacturing method of a memory device. FIG. 12 is a block diagram illustrating a structural example of a semiconductor device. FIGS. 13A to 13H are diagrams illustrating an example of a circuit structure of a memory cell. FIGS. 14A and 14B are perspective views illustrating a structural example of a semiconductor device. FIG. 15 is a block diagram illustrating a CPU. FIG. 16 is a block diagram illustrating a CPU. FIGS. 17A and 17B are perspective views of a semiconductor device. FIGS. 18A and 18B are perspective views of a semiconductor device. Figures 19A and 19B are diagrams explaining the hierarchy of memory devices in a semiconductor device. Figures 20A and 20B are diagrams showing an example of electronic equipment, and Figures 20C to 20E are diagrams showing an example of a mainframe computer. Figure 21 is a diagram showing an example of space equipment. Figure 22 is a diagram showing an example of a storage system applicable to a data center.

[0026] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0027] In the drawings, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations may be omitted. In addition, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0028] In this specification and the like, an oxynitride is a material whose composition contains more oxygen than nitrogen. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride. Examples of nitride oxides are silicon nitride oxide, aluminum nitride oxide, and hafnium nitride oxide.

[0029] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0030] Furthermore, in this specification, "parallel" refers to a state in which two lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" refers to a state in which two lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two lines are arranged at an angle of 60 degrees or more and 120 degrees or less. "Orthogonal" refers to a state in which two lines intersect or connect at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. "Approximately perpendicular" or "approximately perpendicular" refers to a state in which two lines intersect or connect at an angle of 60 degrees or more and 120 degrees or less.

[0031] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. Note that in this specification, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. More specifically, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0032] Furthermore, in this specification, terms indicating position, such as "above" and "below," are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0033] Furthermore, in this specification, "connection" includes "electrical connection." "A and B are electrically connected" means that, among the cases where A and B are connected without an insulator (where A and B are connected via a conductor or semiconductor, or where A and B are in contact), there is a time when exchange of electrical signals or interaction of potentials occurs between A and B during circuit operation. In other words, even if there is a time during circuit operation when exchange of electrical signals or interaction of potentials does not occur between A and B, it can be said that "A and B are electrically connected" as long as there is a time when exchange of electrical signals or interaction of potentials occurs between A and B.

[0034] An "electrical connection" includes a connection (direct connection) that does not involve a circuit element (for example, a transistor, but excluding wiring), and a connection (indirect connection) that involves one or more circuit elements.

[0035] Examples of "A and B being electrically connected" include when A and B are connected without a circuit element, when A and B are connected via the source and drain of one or more transistors, etc. However, this is premised on the fact that there is a timing when an exchange of electrical signals or an interaction of potentials occurs between A and B.

[0036] An example in which it cannot be said that "A and B are electrically connected" because A and B are connected via an insulator is when a dielectric of a capacitive element, a gate insulating film of a transistor, etc. is interposed between A and B.

[0037] Examples of cases where A and B are connected without an insulator between them, but there is no timing at which an electrical signal is exchanged or there is no potential interaction between A and B, and therefore it cannot be said that "A and B are electrically connected" include a case where a potential V is supplied to the path from A to B from a power supply, signal source, etc. (however, this does not include a case where the potential V is supplied via a circuit element), or a case where A and C are connected via the source and drain of a transistor TrP and B and C are connected via the source and drain of a transistor TrQ, but there is no timing at which both the transistor TrP and the transistor TrQ are turned on simultaneously.

[0038] In this embodiment, a memory device according to one embodiment of the present invention will be described. The memory cell included in the memory device according to one embodiment of the present invention is a 1Tr1C type memory cell including a transistor and a capacitor, and adjacent word lines have different heights.

[0039] The transistor is a vertical transistor having a channel formation region along the side of an opening formed in an insulator. A vertical transistor has the advantage of being able to easily increase the on-state current because it has a structure that makes it easy to shorten the channel length and increase the channel width. Furthermore, a vertical transistor can reduce the area it occupies when viewed from above. Therefore, by using a vertical transistor in a memory cell, a memory device capable of high-speed operation and high integration can be formed.

[0040] The capacitance element is a trench capacitor, and by stacking the capacitance element under the transistor, the area occupied by the memory cell is reduced to a minimum of 4F. ２ (F is the minimum processing dimension). The memory cells are arranged in a staggered pattern when viewed from above, with the bit lines and word lines arranged perpendicular to each other. In addition, since the number of word lines increases in this configuration, adjacent word lines are arranged at different heights.

[0041] This configuration reduces the number of memory cells per word line, reducing unnecessary power consumption during data reads. Furthermore, since a pair of bit lines connected to a sense amplifier can be located within the same cell array, a folded bit line scheme can be used, reducing noise.

[0042] FIG. 1A is a perspective view showing a part of a memory device of one embodiment of the present invention, illustrating a memory cell MC (transistor Tr, capacitor C), word lines WL (word lines WL_1 to WL_4), and bit lines BL (bit lines BL_1 to BL_4). Note that a wiring may also have a region of a component of a transistor or a capacitor, such as an electrode. The wiring, electrode, and the like can also be referred to as a conductor. Note that insulators such as an interlayer film are not illustrated in FIGS. 1A and 1B for clarity.

[0043] FIG. 1B is a circuit diagram corresponding to a memory cell MC. The memory cell MC has a 1Tr1C configuration used in DRAMs and the like. One of the source or drain of the transistor Tr is connected to one electrode of a capacitance element C. The other of the source or drain of the transistor Tr is connected to a bit line BL, and the gate is connected to a word line WL. The other electrode of the capacitance element C is connected to a wiring CL. A constant potential can be supplied to the wiring CL, and for example, a low-potential power line or a GND line can be used as the wiring CL.

[0044] A vertical transistor can be used for the transistor Tr, and a trench capacitor can be used for the capacitance element C. By providing both of them overlapping each other, the area occupied by the memory cell MC can be reduced. The structures of the transistor Tr and the capacitance element C will be described in detail later.

[0045] 2A is a diagram corresponding to the top view of the memory device shown in FIG. 1A and shows the positional relationship between the word lines WL (word lines WL_1 to WL_4), the bit lines BL (bit lines BL_1 to BL_4), and the memory cells MC. Adjacent word lines WL are arranged parallel to each other, and adjacent bit lines BL are also arranged parallel to each other. Furthermore, the word lines WL and the bit lines BL are arranged perpendicular to each other. Here, in the top view, adjacent word lines WL are shown as being in contact with each other, but as shown in the perspective view of FIG. 1A, adjacent word lines WL are not in contact with each other because they are positioned at different heights.

[0046] The memory cells MC can reduce their occupied area by providing them with an area overlapping the intersection area of ​​the word lines WL and the bit lines BL. In the memory device shown in FIG. 2A, when the width of the word lines WL is F (F is the minimum processing dimension) and the pitch of the bit lines BL is 2F, the occupied area S of the memory cells MC is 4F. ２ It can be made into.

[0047] 2B is a diagram showing an example of a conventionally proposed cross-point memory device. The pitch of the word lines WL and the pitch of the bit lines BL are both 2F, and the occupied area S of the memory cells MC is reduced to 4F by arranging the memory cells MC in the intersection regions of the word lines WL and the bit lines BL. ２ The memory device of one embodiment of the present invention shown in FIG. 2A has the same occupied area S of the memory cell MC as that shown in FIG. 2B, but differs in the arrangement positions of the memory cells MC and the word lines WL.

[0048] 2B , memory cells MC are provided at all intersections of word lines WL (word lines WL_1 and WL_2) and bit lines BL (bit lines BL_1 to BL_4). On the other hand, in the configuration of one embodiment of the present invention shown in FIG. 2A , memory cells MC are arranged at every other intersection of word lines WL and bit lines BL. Such an arrangement can be called a staggered arrangement or a zigzag arrangement.

[0049] In a memory device according to one embodiment of the present invention, memory cells MC are arranged in a staggered manner, word lines WL and bit lines BL are orthogonal to each other, thereby doubling the number of word lines and reducing the number of memory cells MC per word line.

[0050] The effects of such a configuration and the problems with the conventional configuration (FIG. 2B) will be explained next.

[0051] 3 is a diagram simply explaining the problem with the configuration shown in Fig. 2B. A sense amplifier SA is connected to each bit line BL, and data can be read out to the outside by operating a switch SW (switches SW1 to SW4) connected to the bit line BL or the sense amplifier SA.

[0052] A storage device such as a memory circuit is connected to other circuits such as a CPU via a bus line, and the amount of data that can be read externally in one clock is determined by the bus width. For example, if the bus width is 32 bits, the amount of data that can be read externally in one clock is equivalent to 32 1-bit memory cells. In other words, if there are more than 32 memory cells MC connected to one word line WL, the operation of the memory cells MC from which data is not read externally is wasted.

[0053] The above problem will be explained using Figure 3. Note that, here, an example will be described in which, among memory cells MC1 to MC4 connected to word line WL_1, only data of memory cell MC1 is read out to the outside due to restrictions imposed by the bus width. In addition, in this embodiment, the transistor connected to word line WL is an n-channel type, and the gate potential at which the transistor is turned on is a high potential H, and the gate potential at which the transistor is turned off is a low potential L.

[0054] First, a read potential (high potential H) is supplied to word line WL_1 connected to memory cell MC1, which is the target of reading, and a low potential L is supplied to word line WL_2. At this time, the transistors of each memory cell MC connected to word line WL_1 become conductive, and the charges (data) held in each of memory cells MC1 to MC4 are distributed to precharged bit lines BL_1 to BL_4.

[0055] At this time, the sense amplifier SA connected to each bit line BL is activated, and each bit line BL rises to a potential higher than the precharge potential or falls to a potential lower than the precharge potential depending on the data stored in the memory cells MC1 to MC4.

[0056] Here, the memory cell MC1 is the target for reading, so the switch SW1 connected to the bit line BL_1 is made conductive to read the data (DATA) to the outside. On the other hand, the memory cells MC2 to MC4 are not the target for reading, so the switches SW2 to SW4 connected to the bit lines BL_2 to BL_4, respectively, are made non-conductive and the data is not read to the outside.

[0057] In other words, in the conventional configuration, unnecessary operations related to the charging and discharging of 3-bit bit lines BL occur. Although the charging and discharging of bit lines BL has the effect of rewriting data, this operation can be said to be unnecessary if refresh operations are performed periodically.

[0058] 4 is a diagram illustrating a case where an operation of reading only data from memory cell MC1 is performed in a configuration according to one embodiment of the present invention, similar to the above. In this configuration, the memory cells MC are arranged in a staggered manner, and the word lines WL and bit lines BL intersect at right angles. In FIG. 4, memory cells MC1 and MC3 are connected to word line WL1, and memory cells MC2 and MC4 are connected to word line WL2.

[0059] First, a read potential (high potential H) is supplied to word line WL_1 connected to memory cell MC1, which is the target of reading, and a low potential L is supplied to word lines WL_2 to WL_4. At this time, the transistors of each memory cell connected to word line WL_1 become conductive, and the charges (data) held in memory cells MC1 and MC3 are distributed to precharged bit lines BL_1 and BL_3.

[0060] At this time, the sense amplifier SA connected to the bit lines BL_1 and BL_3 is activated, and the bit lines BL_1 and BL_3 rise to a potential higher than the precharge potential or fall to a potential lower than the precharge potential according to the data held in the memory cells MC1 and MC3. Note that, since the memory cells MC2 and MC4 are connected to the word line WL_2, the sense amplifier SA connected to the memory cells MC2 and MC4 does not operate.

[0061] Here, the read target is memory cell MC1, so switch SW1 connected to bit line BL_1 is made conductive and data (DATA) is read out to the outside. On the other hand, memory cell MC3 is not the read target, so switch SW3 connected to bit line BL_3 is not made conductive and data is not read out to the outside. In other words, unnecessary operations related to charging and discharging the bit line BL are equivalent to one bit of memory cell MC3. In other words, there are fewer unnecessary operations than in the conventional configuration, and power consumption can be reduced.

[0062] The difference from the conventional configuration is that no operations related to reading memory cells MC2 and MC4 are performed, which is an effect obtained by arranging memory cells MC in a staggered manner, orthogonally intersecting word lines WL and bit lines BL, increasing the number of word lines WL, and reducing the number of memory cells MC per word line WL.

[0063] The conventional configuration also has another problem. Figure 5 is a diagram illustrating the connection between a memory array (memory arrays MCA0 and MCA1) having a conventional configuration and a sense amplifier SA. The sense amplifier SA compares the potentials of two bit lines (first bit line and second bit line), raises the potential level of the bit line with the higher potential, and lowers the potential level of the bit line with the lower potential, thereby clarifying the logic of the data held in the memory cells MC.

[0064] In the conventional configuration, memory cells MC are arranged in all of the intersections of word lines WL and bit lines BL, and therefore data is read out to all of the bit lines BL, so that two bit lines connected to a sense amplifier SA cannot be drawn from the same memory array.

[0065] 5, the bit lines BLa (bit lines BLa_1 to BLa_4) arranged in the memory array MCA0 are used as either the first bit lines or the second bit lines. The bit lines BLb (bit lines BLb_1 to BLb_4) arranged in the memory array MCA1 are used as the other of the first bit lines and the second bit lines. This configuration is called an open bit line system.

[0066] In this configuration, a case where memory cells MC1 to MC4 in the memory array MCA0 are to be read will be described.

[0067] First, a low potential L is supplied to all word lines (word lines WLa_1 and WLa_2, word lines WLb_1 and WLb_2), and the bit line BLa (memory array MCA0) functioning as the first bit line and the bit line BLb (memory array MCA1) functioning as the second bit line are precharged so that they both have the same potential.

[0068] A read potential (high potential H) is supplied to the word line WLa_1 connected to the memory cells MC1 to MC4, and a low potential L is supplied to the other word lines (word line WLa_2, word lines WLb_1 and WLb_2).

[0069] At this time, the potential of the bit line BLa functioning as the first bit line changes from the precharge potential due to capacitive coupling of the parasitic capacitance Cp occurring between the word line WLa_1 and the bit line BLa. In the other memory array MCA1, since the potential of the word line WLb does not change, the bit line BLb functioning as the second bit line is not affected by the parasitic capacitance Cp and maintains the precharge potential.

[0070] The change in the potential of the bit line BLa due to the parasitic capacitance Cp becomes noise that disrupts the balance of the potentials of the first bit line and the second bit line, which should have been precharged to the same potential, and this can impair the reliability of data readout.

[0071] 6 is a diagram illustrating a connection between a memory array MCA0 having a configuration according to one embodiment of the present invention and a sense amplifier SA. In this configuration, a pair of adjacent bit lines BL arranged in the same memory array are connected to one sense amplifier SA.

[0072] In the configuration of the present invention, in a region where one word line WL and two adjacent bit lines BL overlap, a memory cell MC is arranged in one region, but no memory cell MC is arranged in the other region. Therefore, even within the same memory array, a change in potential due to a read operation of a memory cell MC appears only on one of the adjacent bit lines BL.

[0073] That is, of two adjacent bit lines BL overlapping one word line WL, the bit line BL on the side where the memory cells MC are arranged can be used as the first bit line, and the bit line BL on the side where the memory cells MC are not arranged can be used as the second bit line to operate the sense amplifier. This configuration is called a folded bit line system.

[0074] In this configuration, a case where memory cells MC1 and MC3 in the memory array MCA0 are to be read will be described.

[0075] First, a low potential L is supplied to all word lines WL (word lines WL_1 to WL_4), and bit line BL1 functioning as the first bit line and bit line BL2 functioning as the second bit line are precharged to the same potential. Also, bit line BL3 functioning as the first bit line and bit line BL4 functioning as the second bit line are precharged to the same potential.

[0076] Then, a read potential (high potential H) is supplied to the word line WL_1 connected to the memory cells MC1 and MC3, and a low potential L is supplied to the other word lines WL (word lines WL2 to WL4).

[0077] At this time, the potentials of all the bit lines BL change from the precharge potential due to the capacitive coupling of the parasitic capacitance Cp occurring between the word line WL_1 and each bit line BL. In this way, the same potential change occurs in both the first bit line and the second bit line, so the noises on both lines cancel each other out. This improves the reliability of data readout.

[0078] In this manner, in the memory device of one embodiment of the present invention, the area occupied by the memory cell MC can be kept small, power consumption can be reduced, and reliability of data reading can be improved.

[0079] Next, the configuration of a storage device according to one embodiment of the present invention will be described in detail. 7A to 7C are a top view, a front view, and a side view of the configuration shown in FIG.

[0080] The memory cells MC (memory cells MC1 to MC8) are arranged in a staggered manner as described above, and each memory cell MC is connected to a word line WL (word lines WL_1 to WL_4) and a bit line BL (bit lines BL_1 to BL_4) that intersects the word line WL at right angles. Each memory cell MC has a capacitance element C at its bottom and a transistor Tr at its top.

[0081] One electrode of the capacitance element C also functions as one of the source electrode or drain electrode of the transistor Tr, and the other electrode of the capacitance element C is connected to a wiring CL. The wiring CL is preferably provided in a form that can be shared by a plurality of memory cells MC or all memory cells MC in the memory array, that is, in a planar form. By providing the wiring CL in a planar form, precise alignment and the like are not required, and some processes can be simplified.

[0082] Each bit line BL is located above the wiring CL and can be provided on the same plane. In other words, each bit line BL can be provided at the same height. A part of the bit line BL also functions as the other of the source electrode and drain electrode of the transistor Tr. A word line WL is provided above the bit line BL.

[0083] The gate of the transistor Tr is provided above the transistor Tr and is connected to the word line WL. As shown in FIG. 8A, if the pitch of the word lines WL and the pitch of the bit lines BL are each 2F (F is the minimum processing dimension) and the memory cells MC are arranged in a staggered pattern, the occupied area S of the memory cells MC is 8F. ２ 8B, it is preferable to make the interval between the word lines WL smaller than the interval between the bit lines BL, and to make the pitch of the word lines WL smaller than 2F.

[0084] In FIG. 7, the occupied area S of the memory cell MC is set to 4F ２ In this configuration, the spacing between adjacent word lines WL is zero by design, and they cannot be provided on the same plane. In other words, adjacent word lines WL cannot be provided at the same height. Also, as shown in FIG. 8B, when the occupied area S is 4F ２ Larger 8F ２ Even if it is smaller, it is difficult to provide the word lines WL on the same plane because the interval between the word lines WL is smaller than the minimum processing dimension F. Therefore, it is preferable to arrange the word lines WL at alternate heights.

[0085] 7 shows an example in which the word lines WL_1 and WL_3 are provided at a relatively high position, and the word lines WL_2 and WL_4 are provided at a relatively low position. In other words, the shortest distance between each of the word lines WL_1 and WL_3 and the bit line BL is greater than the shortest distance between each of the word lines WL_2 and WL_4 and the bit line BL.

[0086] Here, the shortest distance between the word line WL and the bit line BL is the distance between the word line WL and the bit line BL at the position where the word line WL and the bit line BL where the memory cell MC are arranged overlap. More precisely, it can be said to be the distance between the upper surface of the bit line BL and the lower surface of the word line WL at that position. Note that the word line WL is not limited to two heights, and may be provided with three or more heights.

[0087] 9A is a diagram corresponding to the cross section taken along line A1-A2 in the top view of FIG. 7, and is a cross section of a memory cell MC2 and its periphery included in the memory device.

[0088] The memory device has an insulator 140 on a substrate (not shown), a conductor 110 on the insulator 140, a memory cell MC2 on the conductor 110, an insulator 180 on the conductor 110, and an insulator 280. The insulator 140, the insulator 180, and the insulator 280 function as interlayer films. The conductor 110 functions as a wiring CL.

[0089] The memory cell MC2 has a capacitance element C on the conductor 110 and a transistor Tr on the capacitance element C. Note that although the memory cell MC2 will be described here, other memory cells MC can also have a similar configuration.

[0090] The capacitance element C has a conductor 115 provided on and in contact with the conductor 110, an insulator 130 provided in contact with the conductor 115, and a conductor 120 provided in contact with the insulator 130. The conductor 115 functions as one of a pair of electrodes (sometimes referred to as a lower electrode), the conductor 120 functions as the other of the pair of electrodes (sometimes referred to as an upper electrode), and the insulator 130 functions as a dielectric. In other words, the capacitance element C constitutes a MIM (Metal-Insulator-Metal) capacitance.

[0091] 9A , an opening 190 is provided in the insulator 180, reaching the conductor 110. At least a portion of the conductor 115 is disposed in the opening 190. The conductor 115 has a region in the opening 190 that contacts the top surface of the conductor 110, and a region in the opening 190 that is disposed along the side surface of the insulator 180. The insulator 130 is disposed so that at least a portion of it covers the opening 190. The conductor 120 is disposed so that at least a portion of it is located within the opening 190. It is preferable that the conductor 120 is disposed so as to fill the opening 190.

[0092] The capacitance element C has a configuration in which an upper electrode and a lower electrode face each other across a dielectric on the side of the opening 190, which allows for a large capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitance element C can be. Increasing the capacitance per unit area of ​​the capacitance element C in this way can stabilize the read operation of the memory device. Furthermore, it is possible to promote miniaturization or high integration of memory devices.

[0093] The opening 190 has a cylindrical shape with a circular upper surface. By adopting such a configuration, it is possible to achieve miniaturization or high integration of the memory device. Note that it is preferable that the side surface of the opening 190 is perpendicular to the upper surface of the conductor 110.

[0094] Conductor 115 and insulator 130 are stacked along the side surface of opening 190 and the top surface of conductor 110. Furthermore, conductor 120 is provided on insulator 130 so as to fill opening 190. Capacitance element C having such a configuration can also be called a trench capacitor.

[0095] The insulator 280 is disposed on the capacitance element C. That is, the insulator 280 is disposed on the conductor 115, the insulator 130, and the conductor 120. In other words, the conductor 120 is disposed below the insulator 280.

[0096] The transistor Tr includes a conductor 120, a conductor 240 on an insulator 280, a semiconductor 230, an insulator 250 on the semiconductor 230, and a conductor 260 on the insulator 250. The semiconductor 230 functions as a region where a channel is formed, the conductor 260 functions as a gate electrode, the insulator 250 functions as a gate insulator, the conductor 120 functions as one of a source electrode and a drain electrode, and the conductor 240 functions as the other of the source electrode and drain electrode. In the memory cell MC2, the conductor 240 also functions as a bit line BL_2.

[0097] An oxide semiconductor is preferably used as the semiconductor 230. In this specification and the like, a transistor having an oxide semiconductor in a channel formation region is referred to as an OS transistor. Since an OS transistor can be formed using a thin film, stacking is easy. Furthermore, an OS transistor has higher mobility than a transistor using amorphous silicon, does not require a crystallization process required in the manufacturing process of a polycrystalline silicon (LTPS) transistor, and has excellent uniformity of electrical characteristics. Details of oxide semiconductors will be described later.

[0098] The insulator 280 and the conductor 240 have openings 290 that reach the conductor 120. At least a portion of the semiconductor 230 is disposed in the openings 290. The semiconductor 230 has a region that contacts the top surface of the conductor 120 in the openings 290, a region that contacts the side surface of the conductor 240 in the openings 290, and a region that contacts at least a portion of the top surface of the conductor 240 outside the openings 290. The insulator 250 is disposed so that at least a portion of it is located in the openings 290. The conductor 260 is disposed so that at least a portion of it is located in the openings 290. It is preferable that the conductor 260 is disposed so as to fill the openings 290.

[0099] The semiconductor 230 has a region in contact with the side surface of the conductor 240 in the opening 290 and a region in contact with part of the top surface of the conductor 240. In this way, the semiconductor 230 contacts not only the side surface but also the top surface of the conductor 240, so that the contact area between the semiconductor 230 and the conductor 240 can be increased and the contact resistance can be reduced.

[0100] The transistor Tr is provided so as to overlap with the capacitor C. Furthermore, an opening 290 in which part of the structure of the transistor Tr is provided has a region overlapping with an opening 190 in which part of the structure of the capacitor C is provided. In particular, the conductor 120 functions as one of the source electrode and drain electrode of the transistor Tr and as the upper electrode of the capacitor C, and therefore the transistor Tr and the capacitor C share part of their structures.

[0101] By adopting such a configuration, it is possible to provide the transistor Tr and the capacitance element C without significantly increasing the occupied area when viewed from above. This reduces the occupied area of ​​the memory cells MC, allowing the memory cells MC to be arranged at a high density and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0102] In addition, one of the source electrode or drain electrode of the transistor Tr and one of the electrodes of the capacitance element C are shared, i.e., the transistor Tr and the capacitance element C are directly connected without an intervening wiring, etc. Therefore, the electrical resistance between them can be minimized, and current loss during charging or discharging can be reduced.

[0103] An insulator 150 functioning as an interlayer film is provided over the transistor Tr. An opening 210 reaching the conductor 260 is provided in the insulator 150, and a conductor 270 is provided to fill the opening 210. In the memory cell MC2, the conductor 270 functions as the word line WL_2 and is connected to the conductor 260. An insulator 160 is provided over the conductor 270 as an interlayer film.

[0104] 9B is a diagram corresponding to the cross section taken along line A3-A4 in the top view of FIG. 7, and is a cross section of a memory cell MC3 and its periphery included in the memory device.

[0105] In this region, an insulator 160 is provided on the insulator 150. An opening 220 reaching the conductor 260 is provided in the insulator 150 and the insulator 160, and a conductor 270 is provided to fill the opening 220. In the memory cell MC2, the conductor 270 functions as the word line WL_1 and is connected to the conductor 260. The conductor 240 functions as the bit line BL_3.

[0106] 9C is a cross-sectional view corresponding to the cross section taken along line B1-B2 in the top view of FIG. 7 , showing memory cells MC6 and MC2 of the memory device and their peripheries. A conductor 270 functioning as word line WL_4 connected to memory cell MC6 and a conductor 270 functioning as word line WL_2 connected to memory cell MC2 are provided on the same surface on insulator 150. In addition, when viewed from above (see FIG. 7 ), conductor 270 functioning as word line WL_3, which is provided between word line WL_4 and word line WL_2, is provided on insulator 160.

[0107] 9A to 9C, adjacent word lines WL are not provided on the same plane but are arranged at different heights. ２ Even if the width is reduced to as small as 1 / 2, adjacent word lines WL can be arranged without contacting each other.

[0108] Here, a method for improving yield will be described. Fig. 10A is a diagram corresponding to the cross section taken along line B3-B4 in the top view of Fig. 7, and is a cross section of memory cell MC7, memory cell MC3 and their surroundings included in the memory device.

[0109] Here, the conductor 270 functioning as the word line WL_2 is formed over the insulator 150, but it can be seen that the distance between the conductor 270 and the opening 220 provided in the insulator 150 and the insulator 160 is extremely short.

[0110] 10A illustrates a case where alignment is normal, but misalignment can occur due to various factors, and for example, as shown in Fig. 10B, there are cases where opening 220 provided on memory cell MC3 overlaps with conductor 270 functioning as word line WL_2. If conductor 270 functioning as word line WL_3 is formed in such a state, word line WL_2 and word line WL_3 will be short-circuited.

[0111] 11A , it is preferable to provide a protective layer 170 that covers the conductor 270 (here, the word line WL_2) provided on the insulator 150. The protective layer 170 can be formed of a material different from the insulators 150 and 160. It is preferable that the material for forming the protective layer 170 has a smaller etching rate than the insulators 150 and 160 in the step (dry etching or wet etching) for forming the opening 220.

[0112] For example, the protective layer 170 can be formed of aluminum oxide or aluminum nitride, and the insulators 150 and 160 can be formed of silicon oxide or silicon nitride. Alternatively, aluminum or titanium can be used as the conductor 270, and a coating formed by anodization can be used as the protective layer 170.

[0113] By providing the protective layer 170 that covers the conductor 270 (here, the word line WL_2), it is possible to prevent the opening 220 from reaching the conductor 270 even if the above-mentioned misalignment occurs (see FIG. 11B). Therefore, it is possible to prevent a short circuit between the word line WL_2 and the word line WL_3 (see FIG. 11C). In other words, it is possible to improve the manufacturing yield of the memory device.

[0114] In the memory device of one embodiment of the present invention having the above structure, the number of memory cells per word line can be reduced. Furthermore, while increasing the integration density of memory cells, a pair of bit lines connected to a sense amplifier can be provided in the same cell array. Therefore, unnecessary power consumption during data reading can be reduced. Furthermore, a folded bit line scheme with less noise can be used, thereby improving the reliability of data reading.

[0115] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0116] Embodiment Mode 2 In this embodiment mode, semiconductors, insulators, and conductors used as the transistor described in Embodiment Mode 1 and its peripheral components will be described.

[0117] [Semiconductor] A transistor included in a memory device according to one embodiment of the present invention preferably includes an oxide semiconductor as a semiconductor. The crystallinity of a semiconductor material used for the oxide semiconductor is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single-crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics. Note that the oxide semiconductor may have a stacked structure of two or more layers.

[0118] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. Because the off-state current of an OS transistor is low, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0119] The oxide semiconductor preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor, the density of defect states in the oxide semiconductor can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0120] The oxide semiconductor preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor having a CAAC structure can also be said to have a structure having layered crystal parts.

[0121] The crystallinity of an oxide semiconductor can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0122] Note that the crystallinity of the semiconductor material included in the oxide semiconductor is not particularly limited. For example, the oxide semiconductor may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor has crystallinity, deterioration of transistor characteristics may be suppressed.

[0123] Examples of metal oxides contained in the oxide semiconductor of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, e.g., a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may also include metalloid elements.

[0124] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium aluminum oxide. Examples of usable materials include indium zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0125] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-current and high frequency characteristics.

[0126] Instead of indium, the metal oxide may contain one or more metal elements with higher periodic numbers in the periodic table. Alternatively, the metal oxide may contain, in addition to indium, one or more metal elements with higher periodic numbers in the periodic table. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher periodic number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements with higher periodic numbers in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0127] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0128] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0129] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0130] In the present embodiment, an In—Ga—Zn oxide may be used as an example of the metal oxide.

[0131] For example, an oxide semiconductor can have a stacked structure of two or more metal oxides with different crystallinity. In this case, the two or more metal oxides may have different compositions or may have the same or approximately the same composition. For example, when a metal oxide has a two-layer structure, the surface on which the second metal oxide is formed becomes the surface of the first metal oxide, so that the crystallinity of the second metal oxide can be increased in some cases. Furthermore, by performing heat treatment (also called crystallization treatment) after forming the second metal oxide, the crystallinity of the first metal oxide can be increased.

[0132] For example, a first metal oxide layer is formed using an ALD method, and a second metal oxide layer having higher crystallinity than the first layer is formed using a sputtering method. Heat treatment can then be performed to improve the crystallinity of the first and second metal oxide layers. In this case, the crystals contained in the second layer grow continuously vertically toward the first layer, and the boundary between the first and second layers may become indistinguishable from cross-sectional observation.

[0133] Alternatively, a three-layer structure may be formed by depositing a third metal oxide layer on the second metal oxide layer using an ALD method. Heat treatment after deposition of the third metal oxide layer can improve the crystallinity of the first to third metal oxide layers. In this case, the crystals contained in the second layer grow continuously vertically toward the first and third layers and then laterally, which may result in the boundary between the first and second layers and the boundary between the second and third layers becoming indistinguishable from cross-sectional observation.

[0134] In this way, by stacking a metal oxide having low crystallinity and a metal oxide having high crystallinity, continuous crystal growth occurs between them in the film thickness direction, and an oxide semiconductor having high crystallinity can be formed throughout the entire film thickness. Alternatively, by stacking a metal oxide having low crystallinity and a metal oxide having high crystallinity and then performing heat treatment, continuous crystal growth occurs between them in the film thickness direction, and an oxide semiconductor having high crystallinity can be formed throughout the entire film thickness. This makes it possible to realize a highly reliable transistor.

[0135] For example, in a three-layer structure in which a first metal oxide layer is formed by ALD, a second metal oxide layer is formed by sputtering to have a CAAC structure, and a third metal oxide layer is formed by ALD, the second CAAC structure can be used as a nucleus or seed to enhance the crystallinity of the upper and lower metal oxides. A metal oxide with enhanced crystallinity can be called an axial growth CAAC (AG CAAC).

[0136] The heat treatment is carried out at a temperature of 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. The treatment time is preferably, for example, 1 minute to 1 hour, or 10 minutes to 30 minutes, at a temperature of 350° C. to 550° C.

[0137] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA device may be used.

[0138] Examples of RTA devices that can be used include LRTA (Lamp Rapid Thermal Anneal) devices and GRTA (Gas Rapid Thermal Anneal) devices. LRTA devices are devices that heat workpieces by radiating light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. GRTA devices are devices that perform heat treatment using high-temperature gas.

[0139] Increasing the atomic ratio of zinc in the composition of an oxide semiconductor can improve the crystallinity of the oxide semiconductor. In particular, when the oxide semiconductor has a stacked structure of two or more metal oxides as described above, it is preferable that the first metal oxide layer contains zinc. For example, when the first metal oxide layer is formed by an ALD method and the second metal oxide layer is formed by a sputtering method, zinc contained in the first metal oxide layer may diffuse into the second metal oxide layer. This diffusion may occur during sputtering or subsequent heat treatment. The diffusion of zinc from the first metal oxide layer to the second metal oxide layer is expected to improve crystallinity. Alternatively, the diffusion of zinc from the first metal oxide layer to the second metal oxide layer is expected to promote the lateral growth of crystal parts having c-axis orientation, thereby accelerating the formation of CAAC.

[0140] Note that it is preferable to perform a treatment to enhance the crystallinity of the oxide semiconductor during or after the formation of the oxide semiconductor. Examples of the treatment to enhance the crystallinity of the oxide semiconductor include heat treatment, plasma treatment, microwave (typically, 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0141] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0142] It is more preferable to perform the treatment for increasing the crystallinity of the oxide semiconductor multiple times during the formation of the oxide semiconductor. For example, when the oxide semiconductor is formed by an ALD method, it is preferable to perform microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform the treatment for increasing the crystallinity every time an oxide semiconductor having a thickness within a predetermined range is formed, which can increase productivity. Specifically, it is preferable to form a first oxide semiconductor having a thickness of 1 nm to 10 nm and perform the first microwave plasma treatment, and then form a second oxide semiconductor having a thickness of 1 nm to 10 nm and perform the second microwave plasma treatment. Note that the method for forming the first oxide semiconductor and the second oxide semiconductor is not particularly limited, and ALD or sputtering may be used, respectively. In particular, forming the first oxide semiconductor by an ALD method is preferable because it can prevent elements of the layers constituting the formation surface from being mixed (also referred to as mixing) into the first oxide semiconductor and the second oxide semiconductor. This is particularly suitable when the element contained in the layer constituting the formation surface inhibits crystallization of the oxide semiconductor (for example, when silicon, carbon, or the like is contained). The first oxide semiconductor and the second oxide semiconductor may have different compositions. Although a stacked structure of the first oxide semiconductor and the second oxide semiconductor is illustrated here, the present invention is not limited to this. The same treatment can be applied to a single-layer oxide semiconductor or a stacked structure of three or more layers.

[0143] Treatment for increasing the crystallinity of an oxide semiconductor may be performed after the oxide semiconductor is formed. Specifically, the treatment may be performed directly on the formed oxide semiconductor, or may be performed through another film, such as an insulating film, formed on the oxide semiconductor. For example, microwave plasma treatment may be performed after the oxide semiconductor is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, or an aluminum oxide film) may be formed after the oxide semiconductor is formed, and then heat treatment or microwave plasma treatment may be performed on the oxide semiconductor through the insulating film.

[0144] Note that the above-described treatment for increasing the crystallinity of an oxide semiconductor can also serve as treatment for removing impurities contained in the oxide semiconductor. For example, carbon, hydrogen, nitrogen, and the like contained in the oxide semiconductor can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of an oxide semiconductor in an oxygen gas atmosphere, oxygen vacancies in the oxide semiconductor can be reduced.

[0145] When the treatment for increasing the crystallinity of the oxide semiconductor is performed, the substrate temperature is preferably set to room temperature (for example, 25° C.) or higher, 100° C. or higher and 600° C. or lower, or 300° C. or higher and 450° C. The temperature of the heat treatment is preferably set to 100° C. or higher and 700° C. or lower, or 300° C. or higher and 450° C.

[0146] By increasing the crystallinity of an oxide semiconductor, a highly reliable transistor can be realized.

[0147] It is preferable that the amount of hydrogen in the oxide semiconductor be reduced as much as possible. Hydrogen in the oxide semiconductor is generated by oxygen vacancies (V Ｏ ) and V Ｏ Defects with hydrogen in the Ｏ H), which may deteriorate transistor characteristics (for example, the Id-Vg characteristics of the initial transistor or the Id-Vg characteristics in a long-term reliability test).

[0148] Therefore, a material that releases little hydrogen is preferably used as a material surrounding an oxide semiconductor, for example, as a material used for an insulator in contact with the oxide semiconductor, such as silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide.

[0149] This can prevent hydrogen from entering the oxide semiconductor. In particular, using silicon nitride for at least one of the insulators in contact with the oxide semiconductor can improve the reliability of the transistor. Note that a material that releases little hydrogen may have a function of capturing or fixing (also known as gettering) hydrogen inside the insulator.

[0150] The semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material in the channel formation region. Examples of such another semiconductor material include semiconductors made of simple elements or compound semiconductors. Examples of semiconductors made of simple elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductor is also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0151] Silicon that can be used as a semiconductor material for transistors includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low temperature polysilicon (LTPS).

[0152] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0153] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the electrostatic capacitance of the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select materials according to the insulator's function. Note that materials with a low dielectric constant also have high dielectric strength.

[0154] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0155] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. Other inorganic insulating materials with a low dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0156] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0157] Furthermore, an insulator such as a gate insulator that is in contact with a semiconductor or that is provided near the semiconductor is preferably an insulator that has a region containing excess oxygen. For example, by providing an insulator that has a region containing excess oxygen in contact with a semiconductor or near the semiconductor, oxygen vacancies in the semiconductor can be reduced. Examples of insulators that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide with vacancies.

[0158] Examples of insulators having a barrier property against oxygen include oxides containing either or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, silicon nitride, silicon nitride oxide, etc. Examples of oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0159] Examples of insulators having a barrier property against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0160] An insulator having a barrier property against oxygen and an insulator having a barrier property against hydrogen can be said to be an insulator having a barrier property against one or both of oxygen and hydrogen.

[0161] Furthermore, examples of insulators having the function of capturing or fixing hydrogen include oxides containing magnesium, and oxides containing one or both of aluminum and hafnium. These oxides preferably have an amorphous structure. In oxides having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. While these metal oxides preferably have an amorphous structure, they may also have crystalline regions formed in some parts.

[0162] In this specification and the like, a barrier insulating film refers to an insulating film having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). The function of capturing or fixing (also referred to as gettering) a corresponding substance can be rephrased as barrier properties. When hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "barrier property against oxygen" refers to at least one of oxygen atoms, oxygen molecules, etc., which are difficult to diffuse.

[0163] [Conductor] As the conductor, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the aforementioned metal element as a component, or an alloy combining the aforementioned metal elements, etc., may be used. As the alloy containing the aforementioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. may be used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0164] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are difficult to oxidize, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide with added silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification and elsewhere, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0165] Furthermore, conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0166] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0167] When a metal oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure of a combination of a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0168] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the metal element and nitrogen described above may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0169] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0170] Embodiment 3 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0171] Fig. 12 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 12 includes a driver circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. Fig. 12 shows an example in which the memory array 920 includes a plurality of memory cells 950 arranged in a matrix.

[0172] The transistor, the capacitor, or the like described in Embodiment 1 can be applied to the memory cell 950. By using the transistor, the capacitor, or the like, the operation speed of the memory device can be improved. Furthermore, miniaturization and high integration of the memory device can be achieved. Furthermore, the capacitance per area of ​​the memory device can be increased.

[0173] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0174] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0175] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0176] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0177] The voltage generating circuit 928 has a function of generating a voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a voltage.

[0178] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0179] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0180] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0181] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply voltage of the semiconductor device 900 is V ＤＤ and the low power supply voltage is GND (ground potential). ＨＭ is the high power supply voltage used to drive the word line high, and V ＤＤThe signal PON1 controls the on / off of the PSW 931, and the signal PON2 controls the on / off of the PSW 932. In FIG. 12, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch may be provided for each power domain.

[0182] 13A to 13H, examples of other memory cell configurations that can be applied to the memory cell 950 will be described.

[0183] 13A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0184] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected to each other.

[0185] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0186] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0187] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and connecting the wiring BIL and the first terminal of the capacitor CA.

[0188] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 shown in FIG. 13B may be used. The memory cell 952 is an example of a memory cell that does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0189] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0190] Note that the transistor M1 is preferably the OS transistor described in Embodiment 1. For example, the transistor M1 and the capacitor CA of the memory cell 951 can have the same configuration as the transistor Tr and the capacitor C shown in FIG.

[0191] By using the OS transistor described in Embodiment 1, the operation speed of the memory device can be improved. Furthermore, the area occupied by the memory cell can be reduced. Furthermore, the OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0192] 13C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell type memory cell using an OS transistor as the transistor M2 is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0193] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0194] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0195] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and connecting the wiring WBL to the first terminal of the capacitance element CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitance element CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitance element CB and the potential of the gate of the transistor M3.

[0196] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0197] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 13D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0198] 13E is an example in which the capacitance element CB and the wiring CAL are omitted from the memory cell 953. Also, the memory cell 956 shown in Fig. 13F is an example in which the capacitance element CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the integration degree of the memory cells can be increased.

[0199] Note that at least the transistor M2 is preferably the OS transistor described in Embodiment 1. For example, the transistor Tr and the capacitor C shown in FIG. 9A can be used for the transistor M2, the transistor M3, and the capacitor CB of the memory cell 953 and the memory cell 954. By using the OS transistor described in Embodiment 1, the operation speed of the memory device can be improved and the area occupied by the memory cell can be reduced.

[0200] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0201] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, in which an OS transistor is used as the transistor M2, are one embodiment of an NOSRAM.

[0202] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0203] When an OS transistor is used as the transistor M3, the memory cell can be configured as a unipolar circuit.

[0204] 13G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 includes transistors M4 to M6 and a capacitor CC.

[0205] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0206] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0207] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and connecting the wiring BIL to the first terminal of the capacitor CC. Specifically, when the transistor M4 is turned on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0208] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0209] Note that at least the transistor M4 is preferably the OS transistor described in Embodiment 1. By using the OS transistor described in Embodiment 1, the area occupied by the memory cell can be reduced.

[0210] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0211] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured as a unipolar circuit.

[0212] 13H shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 13H is a memory cell of an SRAM capable of backing up data.

[0213] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0214] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0215] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0216] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0217] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0218] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the conductive state and non-conductive state of the transistors M9 and M10.

[0219] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0220] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is in a conductive state, a potential corresponding to information to be recorded is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0221] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is conductive, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Furthermore, because the transistors M9 and M10 are conductive, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Subsequently, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0222] Data is read by precharging the wirings BIL and BILB to a predetermined potential in advance, and then applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL, so that the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. Also, the potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. In the wirings BIL and BILB, the potentials of the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1 change from the precharged potentials, respectively, so that the potential held in the memory cell can be read from the potential of the wiring BIL or the wiring BILB.

[0223] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, thereby reducing the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated. Furthermore, by using the OS transistors described in Embodiment 1 as the transistors M7 to M10, the operating speed of the memory device can be improved. Furthermore, the area occupied by the memory cells can be reduced.

[0224] Note that Si transistors may be used as the transistors MS1 to MS4.

[0225] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 14A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 14B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0226] In the above-described memory array 920, a plurality of memory arrays can be stacked. The memory density of the memory cells 951 can be improved by arranging the plurality of memory arrays in the memory array 920 in the vertical direction of the substrate surface on which the driver circuit 910 is provided. Furthermore, the memory array 920 can be fabricated using the same manufacturing process repeatedly in the vertical direction. The semiconductor device 900 can reduce the manufacturing cost of the memory array 920.

[0227] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0228] 15 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 15 can be applied to, for example, a CPU (Central Processing Unit). The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0229] The arithmetic device 960 shown in FIG. 15 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0230] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0231] As will be described later, a memory array 920 can be provided by stacking it on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 be included as part of the cache interface 989.

[0232] It is also possible to use only the memory array 920 as a cache without providing the cache 999 .

[0233] The arithmetic device 960 shown in FIG. 15 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 15 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle via its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0234] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0235] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates an address for a register 996 and reads or writes data from or to the register 996 depending on the state of the arithmetic unit 960.

[0236] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0237] 15 , the register controller 997 selects the holding operation of the register 996 in accordance with an instruction from the ALU 991. That is, it selects whether the memory cells of the register 996 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 996. If holding data using capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 996 can be stopped.

[0238] FIG. 16 shows an example in which a substrate 990 is provided with not only the arithmetic unit 960 but also a storage device 962, an interface circuit 964, an input / output unit 966, and the like.

[0239] The memory device 962 can be used as a cache lower in level than the cache 999, or as a main memory. The memory device 962 is connected to a cache interface 989 in the arithmetic device 960 via an interface circuit 964. The memory device 962 is also connected to a main memory provided on a separate chip via the interface circuit 964 and an input / output unit 966.

[0240] The semiconductor device 900 having the memory array 920 can be applied to the memory device 962 .

[0241] Various interface circuits and bus lines are provided in the interface circuit 964. The interface circuit 964 may also include a power supply circuit, a clock generation circuit, and the like.

[0242] The interface circuit 964 may include, for example, an I2C (Inter Integrated Circuit), an SPI (Serial Peripheral Interface), or a GPIO (General Purpose Input / Output).

[0243] The input / output portion 966 has an input portion to which a signal, a potential, etc. is input from the outside, and an output portion to which a signal is output to the outside. The input / output portion 966 is provided with a plurality of connection terminals, which are connected to a substrate different from the substrate 990 by connection wiring. The input / output portion 966 may also be provided with a buffer circuit, a protection circuit, etc.

[0244] Methods for connecting the substrate 990 to another substrate include wire bonding using gold or copper wiring, flip-chip bonding using bumps, and direct bonding (hybrid bonding) using a direct bonding technique such as Cu-Cu bonding. Alternatively, a bonding method without using a substrate may be used in which two or more layers are bonded together with insulating films and then through-electrodes are formed to connect electrodes provided on each layer. In particular, using direct bonding or a method using through-electrodes is preferable because it allows the pitch of the connection electrodes to be extremely narrow, making it possible to arrange a large number of connection electrodes at a high density and increasing the amount of data transmitted between layers.

[0245] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in FIGS. 17A and 17B. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in FIG. 17B.

[0246] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0247] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also called monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, the two substrates are bonded together, and the two substrates are electrically connected using a through-via or a conductive film bonding technique (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce the manufacturing cost.

[0248] Here, the arithmetic unit 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also called a level 1 cache), the memory array 920L2 can be used as an L2 cache (also called a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0249] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0250] 17B, ​​a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0251] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0252] When the memory array 920L1 is used as a cache, the driver circuit 910L1 may function as part of the cache interface 989, or may be configured to be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 989, or may be configured to be connected thereto.

[0253] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0254] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0255] Furthermore, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 18A shows a perspective view of a semiconductor device 970B.

[0256] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Fig. 18A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0257] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0258] Also, multiple memory arrays may be stacked. Figure 18B shows a perspective view of a semiconductor device 970C.

[0259] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0260] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0261] Embodiment 4 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0262] First, the hierarchy of a memory device applied to a semiconductor device will be described. Fig. 19A shows the hierarchy of a conventional memory device.

[0263] In Figure 19A, the closer to the processor (CPU / GPU), the higher the access frequency, and the longer the base of the area, the larger the data capacity. The closer the storage device is to the processor, the faster the operating speed is required, and the farther away the storage device, the larger the storage capacity and recording density are required. Figure 19A shows a register as memory integrated into a processor such as a CPU or GPU, and shows an example in which SRAM is used as cache memory, DRAM is used as main memory, and NAND memory and HDD (Hard Disk Drive) are used as storage.

[0264] The memory embedded in processors such as CPUs and GPUs is used for temporary storage of calculation results, and is therefore frequently accessed by the arithmetic processing unit. Therefore, faster operating speed is required rather than storage capacity. Registers also have the function of storing setting information for the arithmetic processing unit.

[0265] A cache has the function of duplicating and storing a portion of the data stored in main memory. By duplicating frequently used data and storing it in the cache, the access speed to the data can be increased. The storage capacity required for a cache is smaller than that of main memory, but it is required to operate at a faster speed than main memory. In addition, data rewritten in the cache is duplicated and supplied to the main memory.

[0266] The main memory has a function of holding programs, data, etc. read from storage.

[0267] Storage has the function of storing data that requires long-term storage, various programs used by processing units, etc. Therefore, storage requires a large memory capacity and a high recording density rather than an operating speed. For example, NAND memory such as 3D NAND, high-capacity non-volatile storage devices such as HDDs can be used.

[0268] In one embodiment of the present invention, among various storage devices shown in FIG. 19A , at least the DRAM used as the main memory is replaced with a storage device using an oxide semiconductor (OS memory). In particular, the DRAM requires a refresh operation and is a destructive readout storage device, and therefore consumes significantly more power than other storage devices. Therefore, power consumption can be significantly reduced by not using the DRAM. Note that in FIG. 19A , the range of various storage devices that is targeted for replacement with the OS memory is indicated by a dashed line. That is, not only the DRAM used as the main memory, but also part of the SRAM used as the cache and the NAND memory used for storage can be replaced with the OS memory.

[0269] 19B illustrates an example of a semiconductor device according to one embodiment of the present invention, and is a schematic diagram illustrating various memory devices used in the semiconductor device, layer by layer.

[0270] In FIG. 19B, a plurality of caches (L1 cache, L2 cache) and a Last Level cache (LLC) are shown as caches.

[0271] Multiple caches are provided in the order of L1 cache and L2 cache from the highest to lowest. The higher the cache, the more frequently it is accessed by the processor, so high-speed operation is required. Since the operating speed can also be increased by reducing the data capacity, it is preferable to reduce the data capacity of the higher-level cache. The higher-level cache is preferably physically closer to the processor and has shorter wiring length, so it is preferable to provide it in a form integrated with the layer where the processor is provided. The lower-level cache may be provided in a layer different from the processor.

[0272] The lowest level cache can be called an LLC. While LLCs are not required to operate faster than higher-level caches, they desirably have a large storage capacity. The OS memory of one embodiment of the present invention, which will be described below, has high operating speed and is capable of retaining data for a long period of time, and is therefore suitable for use as an LLC. Note that the OS memory of one embodiment of the present invention can also be applied to a final level cache (FLC).

[0273] SRAM can be used for various caches. OS memory can be used for LLC and main memory. This storage device has high operating speed and can retain data for a long period of time.

[0274] The configuration exemplified here does not use DRAM, which has been conventionally used as a main memory, etc. Instead, the DRAM is replaced with an OS memory according to one embodiment of the present invention. This configuration allows for a dramatic reduction in power consumption (for example, to one hundredth or one thousandth or less). Therefore, it is expected that the worldwide deployment of information processing devices, including computers, servers, and the like, to which this configuration is applied, will contribute significantly to the prevention of global warming.

[0275] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0276] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiment will be described. The electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0277] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 20A . The electronic device 6500 shown in FIG. 20A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0278] 20B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention in the control device 6509 and the control device 6616 is preferable because power consumption can be reduced.

[0279] [Mainframe] Next, Fig. 20C shows a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 20C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

[0280] The computer 5620 can have, for example, the configuration shown in the perspective view in Fig. 20D. In Fig. 20D, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0281] PC card 5621 shown in Figure 20E is an example of a processing board equipped with a CPU, GPU, storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that Figure 20E illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, please refer to the descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 described below.

[0282] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0283] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. They can also be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB, SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of standards for the respective terminals include HDMI (registered trademark).

[0284] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0285] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.

[0286] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. The semiconductor device 5628 is, for example, a memory device.

[0287] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0288] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as equipment for processing and storing information.

[0289] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space.

[0290] Fig. 21 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 21, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0291] 21 , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0292] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0293] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0294] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0295] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the semiconductor device of one embodiment of the present invention is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0296] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0297] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0298] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0299] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to install storage and servers for storing a huge amount of data, to ensure a stable power supply for maintaining the data, or to ensure cooling equipment required for maintaining the data.

[0300] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0301] Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0302] Fig. 22 shows a storage system applicable to a data center. The storage system 6900 shown in Fig. 22 has a plurality of servers 6901sb as hosts 6901 (illustrated as Host Computers). It also has a plurality of storage devices 6903md as storage 6903 (illustrated as Storage). The host 6901 and storage 6903 are shown connected via a storage area network 6904 (illustrated as SAN: Storage Area Network) and a storage control circuit 6902 (illustrated as Storage Controller).

[0303] The host 6901 corresponds to a computer that accesses data stored in the storage 6903. The hosts 6901 may be connected to each other via a network.

[0304] Although the storage 6903 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 6903, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0305] The above-mentioned cache memory is used in the storage control circuit 6902 and the storage 6903. Data exchanged between the host 6901 and the storage 6903 is stored in the cache memory in the storage control circuit 6902 and the storage 6903, and then output to the host 6901 or the storage 6903.

[0306] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refreshing can be reduced and power consumption can be reduced.Furthermore, by using a stacked memory array, miniaturization is possible.

[0307] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0308] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0309] ADDR: signal, BIL: wiring, BILB: wiring, BL: bit line, BL_1: bit line, BL_2: bit line, BL_3: bit line, BL_4: bit line, BLa: bit line, BLa_1: bit line, BLb: bit line, BLb_1: bit line, BRL: wiring, BW: signal, CA: capacitance element, CAL: wiring, CB: capacitance element, CC: capacitance element, CE: signal, CL: wiring, CLK: signal, Cp: parasitic capacitance, GNDL: wiring, GW: signal, MC: memory cell, RBL: wiring, RDA: signal, RWL: wiring, SA: sense amplifier, SL: wiring, SW: switch Chi, Tr: transistor, TrP: transistor, TrQ: transistor, VDL: wiring, WAKE: signal, WBL: wiring, WDA: signal, WL: word line, WL_1: word line, WL_2: word line, WL_3: word line, WL_4: word line, WLa_1: word line, WLa_2: word line, WLb: word line, WLb_1: word line, WOL: wiring, 110: conductor, 115: conductor, 120: conductor, 130: insulator, 140: insulator, 150: insulator, 160: insulator, 170: protective layer, 180: insulator, 190: opening, 210: opening, 2 20: opening, 230: semiconductor, 240: conductor, 250: insulator, 260: conductor, 270: conductor, 280: insulator, 290: opening, 900: semiconductor device, 910: driver circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952 : memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 958: memory cell, 960: arithmetic unit, 962: memory device, 964: interface circuit, 966: input / output unit, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device, 989: cache interface, 990: substrate, 991: ALU, 992: ALU controller, 993: instruction decoder, 994: interrupt controller, 995: timing controller, 996: register,997: Register controller, 998: Bus interface, 999: Cache, 5600: Mainframe, 5610: Rack, 5620: Computer, 5621: PC card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Semiconductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6500: Electronic device, 6501: Housing, 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Motherboard ik, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 6613: pointing device, 6614: external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: battery, 6807: control device, 6900: storage system, 6901: host, 6901sb: server, 6902: storage control circuit, 6903: storage, 6903md: storage device,

Claims

a first word line, a second word line, a first bit line, a second bit line, a first memory cell, and a second memory cell; the first word line and the second word line are provided in parallel and adjacent positions; the first bit line and the second bit line are provided in parallel and adjacent positions; When viewed from above, each of the first word lines and the second word lines is perpendicular to each of the first bit lines and the second bit lines; When viewed from above, a distance between the first word line and the second word line is narrower than a distance between the first bit line and the second bit line; the first memory cell has a region overlapping an intersection region of the first word line and the first bit line; the second memory cell has an area overlapping an intersection area of ​​the second word line and the second bit line; the first bit line and the second bit line are provided on the same plane; each of the first word lines and the second word lines is located above each of the first bit lines and the second bit lines; A memory device, wherein the shortest distance between the first bit line and the first word line is greater than the shortest distance between the second bit line and the second word line. 　 In claim 1, When the width of each of the first word lines and the second word lines is F and the pitch of each of the first bit lines and the second bit lines is 2F, The area occupied by the first memory cell and the second memory cell is 4F ２ A storage device. 　 In claim 1, Further, the memory cell includes a plurality of memory cells. The first memory cell, the second memory cell, and the plurality of memory cells are arranged in a staggered manner when viewed from above. 　 In claim 1, The first bit line and the second bit line are connected to different sense amplifiers. 　 In claim 1, The first bit line and the second bit line are connected to the same sense amplifier. 　 In claim 1, the first memory cell includes a first transistor and a first capacitance element; the first transistor has a gate connected to the first word line, one of a source and a drain connected to the first bit line, and the other of the source and the drain connected to one electrode of the first capacitance element; the second memory cell includes a second transistor and a second capacitor; A memory device in which the second transistor has a gate connected to the second word line, one of a source or a drain connected to the second bit line, and the other of the source or the drain connected to one electrode of the second capacitance element. 　 In claim 6, The memory device, wherein each of the first transistor and the second transistor has a channel formation region in a semiconductor provided along a side surface of an opening in an insulator. 　 In claim 7, the semiconductor is an oxide semiconductor, The oxide semiconductor includes at least one selected from the group consisting of In, Ga, and Zn. 　 In claim 6, The storage device, wherein each of the first capacitance element and the second capacitance element is a trench capacitor.

10. An electronic device comprising: the storage device according to claim 1; and a display unit.

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