Frame pulse synchronization in a packet optical transport platform (p-OTP)

Abstract

The present disclosure provides a method for achieving synchronization in a Packet- Optical Transport Platform when primary and secondary clock inputs are out of sync. The method comprises periodically sampling (202) the clock inputs using a high-frequency sampling clock. When the primary clock input is unavailable, the method comprises determining (204) the phase difference (β) between the clock inputs based on the previously known phase of the primary clock input, and generating (206) an internal clock with the same frequency and phase as the primary clock input using the high-frequency clock input. Further, the method comprises shifting (208) the internally generated clock with each clock cycle until it aligns with a phase that ensures the phase difference between the internally generated clock and the secondary clock input falls within a predetermined limit, and initiating (210) a switch- over to the secondary clock input, thereby ensuring uninterrupted operation during clock transitions.

Description

FRAME PULSE SYNCHRONIZATION IN A PACKET OPTICAL TRANSPORT PLATFORM (P-OTP)TECHNICAL FIELD

[0001] The present disclosure generally relates to Packet Optical Transport Platform (P-OTP) system. More particularly, the present invention relates to a method for achieving synchronization in a Packet-Optical Transport Platform (P-OTP) when primary and secondary clock inputs are out of synchronization.BACKGROUND

[0002] This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described below. This disclosure is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not just as admissions of prior art.

[0003] In a Packet Optical Transport Platform (P-OTP) system, Optical Transport Network (OTN) data is switched over a packet fabric channel inherently suited for Ethernet, Multiprotocol Label Switching (MPLS) packet based traffic.

[0004] Within the P-OTP architecture, the central component is the OTN processor. The OTN processor primary function involves extracting ODUk signals from incoming OTUk signals, packetizing them, and subsequently transmitting them across the packet fabric channel using a Forwarding and Ingress Controller (FIC) device. However, the packet / cell fabric, through which these packets traverse, introduces variable delays due to congestion, scheduling changes, and other factors.

[0005] This variability in packet delay, often referred to as packet delay variation (PDV), presents a critical challenge. It is imperative that PDV does not compromise the performance of the P-OTP platform when switching OTN traffic through the packet / cell fabric. To address this issue effectively, the system requires adequate buffering to emulate a consistent delay when routing OTN traffic. An interesting approach employed by most commercially deployed OTN framer devices is to add packet “age” information in the form of a time-stamp ahead ofpacket payload data. This time-stamp relies on a phase and frequency synchronized clock shared across all line cards, and any deviation outside the allowed window can result in datapath failure.

[0006] To maintain this synchronization across all line cards, they receive a uniform clock signal from the controller card via the backplane. Within the system, two controller cards exist: primary and secondary, designed for protection switch-over scenarios. While it’s possible to have clock outputs from both cards completely out of sync to simplify hardware and reduce costs, this approach could potentially lead to significant disruptions in the data path during a protection switch-over event.

[0007] To mitigate the risk of such system failures during protection switch-overs, we propose implementing a mechanism on all line cards. This mechanism ensures that clock synchronization is maintained seamlessly, even when switching between the primary and secondary controller cards, thereby enhancing the overall reliability and robustness of the P- OTP platform.SUMMARY

[0008] The present disclosure provides a synchronization method in a Packet-Optical Transport Platform (P-OTP) when primary and secondary clock inputs are out of synchronization. This method ensures reliable clock synchronization and smooth switchover in a Packet-Optical Transport Platform system, offering benefits such as real-time monitoring, immediate response to failures, and uninterrupted operation during clock transitions.

[0009] One aspect of the present disclosure provides a method in a Packet-Optical Transport Platform (P-OTP), where the P-OTP uses primary and secondary clock inputs that are out of synchronization. The method comprises periodically sampling the primary and secondary clock inputs based on a high frequency sampling clock, when the primary clock input is unavailable, the method comprises determining phase difference (P) between the primary and secondary clock inputs based on the previously known phase of the primary clock input, and generating an internal clock with the same frequency and phase as the primary clock input based on the high frequency clock input. Further, the method comprises shifting the internally generated clock in step (a) with each clock cycle until the internally generated clock aligns a phase (P-a), wherein the phase (P-a) ensures that the phase difference between the internally generated clock and the secondary clock input is within a predetermined limit of the data pathdevice. Furthermore, the method comprises initiating a switch-over to the secondary clock input when the phase difference between the internally generated clock and the secondary clock input is within the predetermined limit of the data path device.

[0010] Optionally, the previously known phase of the primary clock is calculated based on the periodically sampled primary clock input.

[0011] Optionally, the step (a) is 1 or any other higher number (p) depending upon the amount of jitter / phase variance the data path device handles.

[0012] Optionally, during working of both primary and secondary clock inputs, maintaining the validity status of the primary and secondary clock inputs based on a predetermined window (±p).

[0013] Optionally, the resolution of the validation status is based on the frequency of the sampling clock.

[0014] According to another aspect of the invention an apparatus comprising an optical transport network (OTN) processor is proposed, where one or more apparatuses are connected to primary and secondary clock inputs generated from the primary and secondary controller cards, respectively, where the primary and secondary clock inputs are out of synchronization. The apparatus periodically samples the primary and secondary clock inputs based on a high frequency sampling clock, when the primary clock input is unavailable, the apparatus determines phase difference (P) between the primary and secondary clock inputs based on the previously known phase of the primary clock input. The apparatus generates an internal clock with the same frequency and phase as the primary clock input based on the high frequency clock input. The apparatus further shifts the internally generated clock in step (a) with each clock cycle until the internally generated clock aligns a phase (P-a), wherein the phase (P-a) ensures that the phase difference between the internally generated clock and the secondary clock input is within a predetermined limit of the data path device. Furthermore, the apparatus initiates a switch-over to the secondary clock input when the phase difference between the internally generated clock and the secondary clock input is within the predetermined limit of the data path device.

[0015] Optionally, the apparatus is further configured to, during working of both primary and secondary clock inputs, maintain the validity status of the primary and secondary clock inputs based on a predetermined window (±p).

[0016] Optionally, the apparatus is a line card in an OTN.

[0017] Optionally, the apparatus comprises a clock processing module which is built in a programmable logic device.

[0018] Optionally, the high frequency clock operates at a frequency that is at least 10 times greater than the frequency of the primary and secondary clock inputs.

[0019] Overall, this method ensures reliable clock synchronization and smooth switchover in a Packet-Optical Transport Platform system, offering benefits such as real-time monitoring, immediate response to failures, and uninterrupted operation during clock transitions.BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To further clarify advantages and features of the present disclosure, a more particular description of the disclosure will be rendered by reference to specific embodiments thereof, which is illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the disclosure and are therefore not to be considered limiting of its scope. The disclosure will be described and explained with additional specificity and detail with the accompanying drawings in which:

[0021] Figure la illustrates a schematic diagram of a Packet Optical Transport Platform (P- OTP) to which an embodiment of this application is applicable;

[0022] Figure lb illustrates a schematic diagram of a line card in a P-OTP;

[0023] Figure 2 illustrates a method in a Packet-Optical Transport Platform (P-OTP) according to an embodiment of this application; and

[0024] Figure 3 is a block diagram of an apparatus to which an embodiment of this application is applicable.DETAILED DESCRIPTION

[0025] For the purpose of promoting an understanding of the principles of the disclosure,reference will now be made to the embodiment illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the disclosure is thereby intended, such alterations and further modifications in the illustrated system, and such further applications of the principles of the disclosure as illustrated therein being contemplated as would normally occur to one skilled in the art to which the disclosure relates.

[0026] It will be understood by those skilled in the art that the foregoing general description and the following detailed description are exemplary and explanatory of the disclosure and are not intended to be restrictive thereof. Throughout the patent specification, a convention employed is that in the appended drawings, like numerals denote like components.

[0027] Reference throughout this specification to “an embodiment”, “another embodiment”, “an implementation”, “another implementation” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrase “in an embodiment”, “in another embodiment”, “in one implementation”, “in another implementation”, and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0028] The terms “comprises”, “comprising”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process or method that comprises a list of steps does not include only those steps but may include other steps not expressly listed or inherent to such process or method. Similarly, one or more devices or sub-systems or elements or structures proceeded by “comprises... a” does not, without more constraints, preclude the existence of other devices or other sub-systems or other elements or other structures or additional devices or additional sub- systems or additional elements or additional structures.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The apparatus, system, and examples provided herein are illustrative only and not intended to be limiting.

[0030] The terms “a” and “an” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced item.

[0031] Embodiments of the disclosure will be described below in detail with reference to the accompanying drawings.

[0032] Figure la illustrates a schematic diagram of a Packet Optical Transport Platform (P- OTP) in which Optical Transport Network (OTN) data is efficiently switched over a packet fabric channel, a platform inherently suited for handling Ethernet and Multiprotocol Label Switching (MPLS) packet-based traffic. Within the P-OTP system, an OTN processor (114) located in the line card (110, 120) performs the task of extracting ODUk signals from incoming OTUk signals, packaging them into an appropriate format, and subsequently transmitting them over the packet fabric channel through the Forwarding and Ingress Controller (FIC) device (116). However, the performance of the Packet / cell fabrics (130) can exhibit variations in terms of delays. These delays may arise from congestion issues, fluctuations in scheduling, and other dynamic factors.

[0033] Analyzing the essential elements within the P-OTP system, both line cards (110, 120) feature an integral clock processing module (119), as illustrated in Figure lb. This module is ingeniously implemented using a programmable logic device such as Complex Programmable Logic Device (CPLD) / Field-Programmable Gate Array (FPGA). To ensure precise clock sampling and monitoring, a high-frequency clock source, operating at a frequency at least ten times greater than the clock to be sampled, is connected to the programmable logic device.

[0034] Each line card (110, 120) establishes connections with clock outputs from both the primary controller card (102) and the secondary controller card (104). These clock outputs from the controller cards (102, 104) can operate entirely out of synchronization, a design choice made to optimize hardware requirements and cost-effectiveness. Alternatively, the clock outputs from the controller cards (102, 104) operates entirely out of synchronization as the clock outputs are sourced from two independent controller cards (102, 104). Furthermore, reference numeral 112 in Figures la-lb indicate Optical Transport Network (OTN) over packet fabric protocol.

[0035] Figure 2 illustrates a method in a Packet-Optical Transport Platform (P-OTP). The primary and secondary clock inputs used in the P-OTP are out of synchronization. This disparity in clock synchronization can occur for various reasons, including simplifying hardware and cost reduction objectives. Alternatively, it might result from the fact that these clock inputs originate from two independent controller cards, denoted as Controller Card 1(102) and Controller Card 2 (104). In another application, this method also serves as a protection switchover mechanism.

[0036] High-Frequency Sampling of Clock Inputs: The method comprises periodic sampling of both the primary and secondary clock inputs based on a high frequency sampling clock, denoted as Step 202. This periodic sampling ensures the ongoing validity of these clock inputs.

[0037] In an embodiment, when both the primary and secondary clock inputs are available, the clocks are periodically sampled with respect to the high frequency sampling clock to maintain the validity status of primary and secondary clock input. The validation logic can be tailored to a predefined allowable window, and can be expressed as ±p, depending on the specific requirements. The precision of this validation process hinges on the frequency of the sampling clock. The predefined allowable window (±p) has a fixed maximum value based on the OTN processor used in the system. In an embodiment, the maximum value of the predefined allowable window (±p) is 626.93 ns / +617.28 ns.

[0038] Handling Primary Clock Unavailability: When the primary clock input is unavailable, the method comprises determining the phase difference (P) between the primary and secondary clock inputs based on the previously known phase of the primary clock input, step 204. Particularly, the phase difference (P) between the primary and secondary clock inputs is determined based on determining the phase difference (P) between the previously known phase of the primary clock input and the current phase of the secondary clock inputs. In another embodiment, the phase difference (P) between the primary and secondary clock inputs is determined using the last known phase of the primary clock input and the current phase of the secondary clock inputs.

[0039] Generation of an Internal Clock: To maintain synchronization, the method proceeds to generate an internal clock with the same frequency and phase as the primary clock input based on the high frequency clock input, step 206. In an embodiment, the internal clock can be generated based on either the frequency and phase of the previously known primary clock input or the last known primary clock input.

[0040] This allows for immediate response to clock failures, ensuring minimal disruption to operations. Further, generation of an Internal Clock maintains synchronization even when the primary clock is unavailable, ensuring seamless operation.

[0041] Aligning the Internally Generated Clock: The method further comprises shifting the internally generated clock in step (a) with each clock cycle until the internally generated clock aligns a phase (P-a), wherein the phase (P-a) ensures that the phase difference between the internally generated clock and the secondary clock input is within a predetermined limit of the data path device, step 208. The aim here is to align the phase of the internally generated clock with the secondary clock input or within an acceptable limit of the secondary clock input so that the operation can be switch-over to the secondary clock input. This alignment is vital to ensure that the phase difference between the internally generated clock and the secondary clock input falls within a predetermined limit defined by the data path device. The choice of the step size (a) is determined by the capacity of the data path device to manage jitter and phase variance effectively.

[0042] In an embodiment, the internally generated clock is shifted in step (a) with each clock cycle until the internally generated clock aligns a phase which ensures that the phase difference between the internally generated clock and the secondary clock input is within a predetermined limit of the data path device.

[0043] In an exemplary embodiment, during normal operation, when both primary and secondary clock inputs are functional, these clocks can be represented by the following equations:^Secondary F(fs> <Ps) (2) where fpis frequency of the primary clock input;(ppis phase of the primary clock input; fsis frequency of the secondary clock input; and(psis phase of the secondary clock input. and where the phase difference i.e., (pp— (psbetween the primary and secondary clocks is calculated to ensures the validity of both clock inputs during normal operation. Particularly, when the phase difference ((pp— (ps) is within an allowed window say ±p which is defined as per the requirement, which can be expressed as below:

[0044] When the primary clock input experiences a failure, the method proceeds to maintain smooth P-OTP operation by generating an internal clock that mirrors the frequency and phase of the last known primary clock input before the failure occurs. The generated internal clock can be represented as below: Internal Clock ~ P 'p. p) (4) where f'pis frequency of the last known primary clock input before the failure; and(f)'pis phase of the last known primary clock input before the failure.

[0045] Further, to initiate the switch-over to the secondary clock input, the phase of the internally generated clock is shifted in step (a) with each clock cycle until the internally generated clock reaches a phase (P-a) or p, which is represented below:where the n is incremented at every clock cycle till the phase of the internal clock reaches P-a or p, which can be represented below equations:<p'p± na -> (p'p± p ; orwhere P represents the phase difference between the previously known phase of the primary clock input and the current phase of the secondary clock inputs.

[0046] Switching to Secondary Clock Input: Once the phase difference between the internally generated clock and the secondary clock input falls within an acceptable limit of the data path device i.e., p - a, Step 210 initiates a switch-over to the secondary clock input. Particularly, the method comprises initiating a switch-over to the secondary clock input when the phase difference between the internally generated clock and the secondary clock input is within the predetermined limit of the data path device. This action ensures a seamless transition to the secondary clock input for continued operation. Specifically, provides a seamless transition tothe secondary clock input, maintaining continuous operation even during primary clock failures.

[0047] Figure 3 represents an apparatus (110) in a Packet-Optical Transport Platform (P- OTP). The apparatus comprises an optical transport network (OTN) processor (114). One or more apparatuses (110) are connected to primary and secondary clock inputs generated from the primary and secondary controller cards (102, 104), respectively, and the primary and secondary clock inputs are out of synchronization. The apparatus periodically samples the primary and secondary clock inputs based on a high frequency sampling clock. When the primary clock input is unavailable, the apparatus further determines phase difference (P) between the primary and secondary clock inputs based on the previously known phase of the primary clock input, and generates an internal clock with the same frequency and phase as the primary clock input based on the high frequency clock input. The apparatus furthermore shifts the internally generated clock in step (a) with each clock cycle until the internally generated clock aligns a phase (P-a), where the phase (P-a) ensures that the phase difference between the internally generated clock and the secondary clock input is within a predetermined limit of the data path device, and initiates a switch-over to the secondary clock input when the phase difference between the internally generated clock and the secondary clock input is within the predetermined limit of the data path device.

[0048] Overall, this method ensures reliable clock synchronization and smooth switchover in a Packet-Optical Transport Platform system, offering benefits such as real-time monitoring, immediate response to failures, and uninterrupted operation during clock transitions.

[0049] The foregoing descriptions of exemplary embodiments of the present disclosure have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiment was chosen and described in order to best explain the principles of the disclosure and its practical application, to thereby enable others skilled in the art to best utilize the disclosure and various embodiments with various modifications as are suited to the particular use contemplated. It is understood that various omissions, substitutions of equivalents are contemplated as circumstance may suggest or render expedient, but is intended to cover the application or implementation without departing from the spirit or scope of the claims of the present disclosure.

[0050] Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any component(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or component of any or all the claims.

[0051] While specific language has been used to describe the disclosure, any limitations arising on account of the same are not intended. As would be apparent to a person in the art, various working modifications may be made to the apparatus in order to implement the inventive concept as taught herein.

Claims

WE CLAIM:

1. A method in a Packet-Optical Transport Platform (P-OTP), wherein the P-OTP uses primary and secondary clock inputs that are out of synchronization, the method comprising: periodically sampling (202) the primary and secondary clock inputs based on a high frequency sampling clock; when the primary clock input is unavailable, determining (204) phase difference (P) between the primary and secondary clock inputs based on the previously known phase of the primary clock input; generating (206) an internal clock with the same frequency and phase as the primary clock input based on the high frequency clock input; shifting (208) the internally generated clock in step (a) with each clock cycle until the internally generated clock aligns a phase (P-a), wherein the phase (P-a) ensures that the phase difference between the internally generated clock and the secondary clock input is within a predetermined limit of the data path device; and initiating (210) a switch-over to the secondary clock input when the phase difference between the internally generated clock and the secondary clock input is within the predetermined limit of the data path device.

2. The method as claimed in Claim 1, wherein the previously known phase of the primary clock is calculated based on the periodically sampled primary clock input.

3. The method as claimed in Claim 1, wherein the step (a) is 1 or any other higher number (p) depending upon the amount of jitter / phase variance the data path device handles.

4. The method as claimed in Claim 1, wherein the method further comprises, during working of both primary and secondary clock inputs, maintaining the validity status of the primary and secondary clock inputs based on a predetermined window (±p).

5. The method as claimed in Claim 4, wherein the resolution of the validation status is based on the frequency of the sampling clock.

6. An apparatus (110) comprising an optical transport network (OTN) processor (114), wherein one or more apparatuses (110) are connected to primary and secondary clock inputs generated from the primary and secondary controller cards, respectively, wherein the primary and secondary clock inputs are out of synchronization, and wherein the apparatus (110) is configured to: periodically sample the primary and secondary clock inputs based on a high frequency sampling clock; when the primary clock input is unavailable, determine phase difference (P) between the primary and secondary clock inputs based on the previously known phase of the primary clock input; generate an internal clock with the same frequency and phase as the primary clock input based on the high frequency clock input; shift the internally generated clock in step (a) with each clock cycle until the internally generated clock aligns a phase (P-a), wherein the phase (P-a) ensures that the phase difference between the internally generated clock and the secondary clock input is within a predetermined limit of the data path device; and initiate a switch-over to the secondary clock input when the phase difference between the internally generated clock and the secondary clock input is within the predetermined limit of the data path device.

7. The apparatus (110) as claimed in Claim 6, wherein the apparatus (110) is further configured to, during working of both primary and secondary clock inputs, maintain the validity status of the primary and secondary clock inputs based on a predetermined window (±p).

8. The apparatus (110) as claimed in Claim 6, wherein the apparatus (110) is a line card in an OTN.

9. The apparatus (110) as claimed in Claim 6, wherein the apparatus (110) comprises a clock processing module which is built in a programmable logic device.

10. The apparatus (110) as claimed in Claim 6, wherein the high frequency clock operates at a frequency that is at least 10 times greater than the frequency of the primary and secondary clock inputs.

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