Monitoring propagation delay

Abstract

A monitor device for monitoring a propagation delay of a signal along a path through an integrated circuit is disclosed. The monitor device comprises a delay device configured to receive the signal and generate a delayed signal being a version of the received signal that is time-delayed relative to the received signal, a detection window device configured to generate a detection window signal based on a clock signal of the integrated circuit, and a determination device configured to determine whether a value of the received signal is different to a value of the delayed signal during a time defined by the detection window signal, and to generate a determination signal based on the determination.

Description

MONITORING PROPAGATION DELAYTECHNICAL FIELD

[0001] The present disclosure relates to monitoring propagation delays through an integrated circuit.BACKGROUND

[0002] Integrated circuits (IC) include chains of interconnected logic cells forming paths for performing logical functions on signals propagating between input and output pins of the IC. Signals propagating along paths through an IC incur some delay, which is effectively the time difference between the input signal being applied to the input pin and the output pin level changing. The expected propagation delay of paths is accounted for by the IC circuit designer, for example, in selecting a sufficiently long clock cycle to accommodate the delay. The propagation delays of constituent logical cells are however susceptible to variation in use, for example, due to different operating conditions, such as process, voltage, and temperature conditions, and also due to silicon degradation due to ageing. Excessive propagation delays can cause data processing errors, for example, due to the propagation delay delaying the signal beyond an IC clock cycle.SUMMARY

[0003] An object of aspects of the present disclosure is to provide a method and an apparatus for monitoring propagation delays of paths through an integrated circuit. In particular, aspects of the present disclosure aim to be able to determine when a propagation delay of a path through an integrated circuit has increased before the propagation delay results in a data error, allowing corrective actions to be taken.

[0004] A first aspect of the present disclosure provides a monitor device for monitoring a propagation delay of a signal along a path through an integrated circuit, comprising: a delay device functional to receive the signal and generate a delayed signal being a version of the received signal that is time-delayed relative to the received signal; a detection window device functional to generate a detection window signal based on a clock signal of the integrated circuit; and a determination device functional to determine whether a value of the received signal is different to a value of the delayed signal during a time defined by the detection window signal, and to generate a determination signal based on the determination.

[0005] The monitor device may thus determine a delay associated with a signal along the path based on the IC clock cycle. As a result, the monitor device may determine the delay of the signal relative to the IC clock cycle. For example, the monitor device may determine whether the signal is delayed relative to an edge of the IC clock cycle. Accordingly, monitoring of propagation delays in the IC may be improved.

[0006] In implementations, the determination device comprises: a XOR logic gate functional to compare the received signal and the delayed signal and generate a comparison signal representative of a difference between the received signal and the delayed signal; and a AND logic gate functional to combine the comparison signal and the detection window signal and generate a combination signal representative of a difference between the received signal and the delayed signal occurring during the time defined by the detection window signal.

[0007] In implementations, the device comprises a flip flop and an input of the flip flop is connected to an output of the determination device to receive the determination signal and store information representative of the determination based on the determination signal.

[0008] In implementations, the flip flop is configured to generate an alarm signal based on the determination signal.

[0009] In implementations, the detection window device is functional to determine a detection window based on a predetermined propagation delay of the path and a positive edge of the clock signal.

[0010] In implementations, the delay device is configured to receive a further signal, wherein for the further received signal, the generating a delayed signal comprises generating a further delayed signal that is time-delayed relative to the further received signal by a different period of time than the delayed signal is time-delayed relative to the received signal.

[0011] In implementations, the generating a further delayed signal comprises generating a further delayed signal that is time-delayed relative to the further received signal by a relatively greater period of time than the delayed signal is time-delayed relative to the received signal.

[0012] In implementations, the delay device is functional to receive a delay set signal representative of time-delay, and the delay device is functional to generate the delayed signal based on the received signal and the delay set signal.

[0013] In implementations, the monitor device is for monitoring respective propagation delays of one or more signals propagating along one or more other paths through theintegrated circuit, the monitor device comprising a plurality of the delay devices, each of the delay devices being functional to receive a signal from a respective path and generate a respective delayed signal being a version of the respective received signal that is time- delayed relative to the respective received signal, wherein the determination device is functional to determine for each delay device whether a value of the respective received signal is different to a value of the respective delayed signal during a time defined by the detection window signal, and to generate one or more determination signals based on the determinations. In other words, the monitor device may be utilized for monitoring propagation delays of multiple paths through the IC. In particular, the monitor device utilizes the same determination device to monitor the signals from the multiple pathways. Thereby for a given number of monitored paths an area overhead incurred by inserting the delay monitors may be minimized.

[0014] In implementations, the determination device comprises an OR logic device configured to combine outputs of the plural delay devices to generate a combined output signal, wherein the determination is performed based on the combined output signal. By combining the signals, communication of the signal to the determination device is simplified compared to communicating multiple discrete signals.

[0015] In implementations, the detection window device is functional to generate an inverted clock signal being an inverted-amplitude version of the clock signal and generate the detection window signal based on the clock signal and the inverted clock signal. In other words, the detection window is generated as a function of the inverted clock signal. Consequently, by applying only a small delay an acceptably delayed clock signal may be generated. Thus, the small delay can be induced by a buffer, which is not susceptible to variation under different PVTA corners. In comparison, a relatively larger delay may be applied to the actual clock signal to produce a suitably delayed signal, and such a larger delay may be undesirably susceptible to PVTA variations.

[0016] In implementations, the detection window device is functional to apply a time delay to the clock signal or to the inverted-amplitude version of the clock signal to generate a delayed inverted clock signal and generate the detection window signal based on the clock signal and the delayed inverted clock signal. By inverting the clock signal and applying a delay to the clock signal, a suitably delayed version of the clock signal may be obtainedwhilst applying a relatively small delay. Thus, the small delay can desirably be induced by a buffer, which is not susceptible to variation under different PVTA corners.

[0017] In implementations, the determination device comprises: an exclusive OR (XOR) logic gate functional to compare the received signal and the delayed signal and generate a comparison signal representative of a difference between the received signal and the delayed signal; a time delay device functional to apply a time-delay to the comparison signal to generate a delayed comparison signal; and an AND logic gate functional to combine the delayed comparison signal and the detection window signal and generate a combination signal representative of a difference between the received signal and the delayed signal occurring during the time defined by the detection window signal, wherein the determining whether a value of the received signal is different to a value of the delayed signal during a time defined by the detection window signal comprises determining the occurrence of the combination signal. Accordingly, whilst the width of the comparison signal may remain fixed, by applying a fixed delay to generate the delayed signal, the amount of delay imparted on the generated comparison signal may still be varied, to thereby vary how early an alarm is raised before a fault actually occurs on the path output. The ability to keep the width of the comparison signal fixed means that the width does not need to be accounted for under different PVTA comers. In implementations of the method, the comparison signal may always be a constant width, and the delay applied to the comparison signal is instead controllable.

[0018] In implementations, the time delay device of the determination device is a variable time delay device functional to apply a variable time-delay to the comparison signal in dependence on a delay set signal supplied to an input of the time delay device. The delay applied to the comparison signal may thereby be varied to thereby enable conveniently vary how early an alarm is raised before a fault actually occurs on the path output.

[0019] In implementations, the determination device is functional to determine whether the received signal transitions during the time defined by the detection window signal and apply a time delay to the comparison signal using the time-delay device in dependence on whether the received signal is determined to transition during the time defined by the detection window signal. In other words, the determination device may determine whether the received signal will already transition with the detection window, and only delay the comparison signal if the received signal does not transition within the detection window.

[0020] In implementations, the detection window device is functional to generate the detection window signal based on the clock signal, a delayed clock signal being a time- delayed version of the clock signal, and an inverted delayed clock signal being an inverted amplitude version of the time-delayed clock signal, by generating an AND combination of the clock signal and the inverted time-delayed clock signal, and generating the detection window signal based on the AND combination of the clock signal and the inverted time- delayed clock signal. The detection window is generated after the clock edge. This enables detection of failed path and hold-time violation signals. It can be inferred that any signal transition occurring within the window immediately after the clock edge indicates a path failure, as it can be inferred that it is either occurring excessively early, or late.

[0021] In implementations, the detection window device is functional to generate an inverted clock signal being an inverted-amplitude version of the clock signal, and generate the detection window signal based on the clock signal and the inverted clock signal, and the determination device is functional to: compare the received signal and the delayed signal and generate a comparison signal representative of a difference between the received signal and the delayed signal; generate a combined signal by applying an AND operation to the comparison signal and the inverted clock signal; apply a time delay to the combined signal to generate a delayed combined signal; and generate the determination signal by application an AND operation to the delayed combined signal and the clock signal. Thereby, a single time delay device may be utilized to induce delay on the combined signal. In comparison, other embodiments of the disclosure utilize separate buffers to induce delays separately on the detection window signal and the delayed comparison signal. Thereby, by this feature, the area overhead of the monitor device may be reduced.

[0022] A second aspect of the present disclosure provides a system comprising: one or more monitor devices as disclosed herein; a controller; and a communication system for communicating the controller with the one or more monitor devices.

[0023] In implementations, the controller is functional to generate the delay set signal and transmit the delay set signal to the one or more monitor devices via the communication system.

[0024] In implementations, each of the one or more monitor devices comprise a flip flop having an input connected to an output of the determination device to receive the determination signal and store information representative of the determination based on thedetermination signal, and the controller is functional to read the information from the flip flop of each of the one or more monitor devices via the communication system.

[0025] A third aspect of the present disclosure provides a method for monitoring propagation delays along one or more paths through an integrated circuit using a monitor device, the method comprising: receiving a signal from a monitored path; generating based on the received signal a delayed signal being a version of the received signal that is time- delayed relative to the received signal; determining a detection window for monitoring the received signal and the delayed signal based on a clock signal of the integrated circuit; and determining whether a value of the received signal is different to a value of the delayed signal during the detection window.

[0026] In implementations, the method comprises generating an alarm signal based on a determination that the value of the received signal is different to the value of the delayed signal during the detection window.

[0027] In implementations, the determining a detection window comprises determining the detection window based on a function of a predetermined propagation delay of the path and a positive edge of the clock signal.

[0028] In implementations, the method comprises repeating the method, wherein for the repetition of the method the generating a delayed signal comprises generating a further delayed signal that is time-delayed relative to the received signal received during the repetition of the method by a different period of time than the delayed signal is time-delayed relative to the received signal received during the initial performance of the method.

[0029] In implementations, the generating a further delayed signal comprises generating a further delayed signal that is time-delayed relative to the received signal received during the repetition of the method by a relatively greater period of time than the delayed signal is time- delayed relative to the received signal during the initial performance of the method.

[0030] In implementations, the method comprises receiving at least one other signal from at least one other monitored path of the integrated circuit, generating for each of the other received signals a respective delayed signal being a version of the respective received signal that is time-delayed relative to the respective received signals, and determining whether a value of each of the other received signals is different to a value of the respective delayed signal during the detection window.

[0031] In implementations, the determining the detection window comprises generating an inverted clock signal being an inverted-amplitude version of the clock signal and generate the detection window signal based on the clock signal and the inverted clock signal.

[0032] In implementations, the determining the detection window comprises applying a time delay to the clock signal or to the inverted-amplitude version of the clock signal to generate a delayed inverted clock signal and generating the detection window signal based on the clock signal and the delayed inverted clock signal.

[0033] In implementations, the determining whether a value of the received signal is different to a value of the delayed signal during a time defined by the detection window signal comprises: comparing the received signal and the delayed signal and generating a comparison signal representative of a difference between the received signal and the delayed signal, applying a time-delay to the comparison signal to generate a delayed comparison signal, and combining the delayed comparison signal and the detection window signal and generate a combination signal representative of a difference between the received signal and the delayed signal occurring during the time defined by the detection window signal, and determining the occurrence of the combination signal.

[0034] In implementations, the applying a time-delay to the comparison signal comprises receiving a delay set signal defining a magnitude of a delay and applying a time-delay to the comparison signal based on the delay set signal.

[0035] In implementations, the applying a time-delay to the comparison signal comprises determining whether the received signal transitions during the time defined by the detection window signal, and applying a time delay to the comparison signal in dependence on whether the received signal is determined to transition during the time defined by the detection window signal.

[0036] A fourth aspect of the present disclosure provides a computer program comprising instructions, which, when executed by a computer, cause the computer to carry out the method of any one of the preceding statements.

[0037] A fifth aspect of the present disclosure provides a data storage apparatus having stored thereon the computer program of the preceding statement.

[0038] These and other aspects of the disclosure are apparent from the embodiments described below.BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order that the present disclosure may be more readily understood, embodiments of the disclosure are now described, by way of example, with reference to the accompanying drawings, in which:

[0040] Figure 1 shows schematically an example of an integrated circuit within which aspects of the present disclosure may be utilized;

[0041] Figure 2 shows schematically an example of a timeline of a signal passing along a path of the integrated circuit;

[0042] Figure 3 shows schematically an example of a delay monitor device for monitoring propagation delays along paths of the integrated circuit;

[0043] Figure 4 shows schematically an example of the delay monitor device deployed in the integrated circuit for monitoring propagation delays along paths of the integrated circuit;

[0044] Figure 5 shows schematically an example of the delay monitor device deployed in the integrated circuit for monitoring propagation delays along paths of the integrated circuit;

[0045] Figure 6 shows an example of a computer system for determining placements of the delay monitor devices in the integrated circuit;

[0046] Figure 7 shows an example of processes involved in a method for determining placement of delay monitor devices for monitoring propagation delays in paths through an integrated circuit;

[0047] Figure 8 shows schematically an example of components of the delay monitor device;

[0048] Figure 9 shows schematically an example of a programmable delay unit of the delay monitor device;

[0049] Figure 10 shows schematically an example of a detection window unit of the delay monitor device;

[0050] Figure 11 shows schematically an example of a system for monitoring propagation delays including a plurality of the delay monitor devices;

[0051] Figure 12 shows schematically an example of a timing diagram;

[0052] Figure 13 shows schematically another embodiment of a delay monitor device embodying the disclosure;

[0053] Figure 14 shows schematically another embodiment of the detection window unit of the delay monitor device;

[0054] Figure 15 shows schematically another embodiment of the programmable delay unit of the delay monitor device;

[0055] Figure 16 shows schematically another embodiment of a delay monitor device embodying the present disclosure;

[0056] Figure 17 shows schematically another embodiment of a delay monitor device embodying the present disclosure;

[0057] Figure 18 shows schematically an example of another timing diagram;

[0058] Figure 19 shows schematically an example of another timing diagram;

[0059] Figure 20 shows schematically an example of another timing diagram;

[0060] Figure 21 shows schematically an example of another timing diagram;

[0061] Figure 22 shows schematically an example of another timing diagram; and

[0062] Figure 23 shows schematically an example of another timing diagram.DETAILED DESCRIPTION

[0063] Example embodiments are described below in sufficient detail to enable those of ordinary skill in the art to embody and implement the systems and processes herein described. It is important to understand that embodiments can be provided in many alternate forms and should not be construed as limited to the examples set forth herein.

[0064] Accordingly, while embodiments can be modified in various ways and take on various alternative forms, specific embodiments thereof are shown in the drawings and described in detail below as examples. There is no intent to limit to the particular forms disclosed. On the contrary, all modifications, equivalents, and alternatives falling within the scope of the appended claims should be included. Elements of the example embodiments are consistently denoted by the same reference numerals throughout the drawings and detailed description where appropriate.

[0065] The terminology used herein to describe embodiments is not intended to limit the scope. The articles “a,” “an,” and “the” are singular in that they have a single referent, however the use of the singular form in the present document should not preclude the presence of more than one referent. In other words, elements referred to in the singular can number one or more, unless the context clearly indicates otherwise. Additionally, the terms “comprises,” “comprising,” “includes,” and / or “including,” when used herein, specify the presence of stated features, items, steps, operations, elements, and / or components, but do notpreclude the presence or addition of one or more other features, items, steps, operations, elements, components, and / or groups thereof.

[0066] Referring to Figure 1, an integrated circuit 101 in which aspects of the present disclosure may be utilized comprises a plurality of flip flops 102 for receiving input signals via input pins D, a plurality of flip flops 103 for outputting output signals via output pins Q, and chains of interconnected logical cells 104 forming a plurality of paths for performing logical functions on signals propagating between the inputs and the outputs. Whilst the example depicts only a single path formed by the chain of logical cells 104, a single input flip flop 102, and a single output flip flop 103, it should be appreciated that in practice such an integrated circuit may comprise many thousands of input and output flip flops, and the logical cells may correspondingly provide many thousands of paths between inputs and outputs, and indeed the logical paths may be interconnected.

[0067] Signals propagating along the paths through the integrated circuit incur some delay, which is effectively the time difference between a signal being applied to the input and a signal at an acceptable level arising at the output. The expected propagation delay of paths is accounted for by the IC circuit designer, for example, in selecting a sufficiently long clock cycle to accommodate the delay.

[0068] Referring to Figure 2 however, the propagation delays of constituent logical cells are susceptible to variation in use, for example, due to different operating conditions, such as process, voltage, and temperature (PVT) corners, and also due to silicon degradation due to ageing. The PVT corners and ageing effect that affect the timing of library cells are referred to herein as PVTA combinations. The PVTA combinations that affect individual cell delays in turn contribute to changing the path delays. This may cause a short path in one PVTA combination to be a long path in another PVTA combination, and vice versa. As depicted in Figure 2, when the delay of a path exceeds the clock period because of these effects, a wrong value may be latched into a flip flop, causing a delay fault. Since the longest paths that are prone to delay faults may vary under different PVTA combinations, the faults may escape detection if the effects of the PVTA combination are not taken into consideration. Such delay faults may also be the root cause of silent data errors (SDEs) in data centers.

[0069] It is therefore appropriate to monitor the changes in the path delays, including under different PVTA combinations, in order that paths exhibiting excessive propagation delays may be identified, allowing corrective actions to be taken. However, since voltage andtemperature are continuous variables, the number of different PVTA combinations for an IC with many thousands of paths is very large, such that monitoring each path, under the different PVTA combinations, may incur an excessively large overhead.

[0070] In examples therefore, aspects of the present disclosure involve identifying and monitoring paths through an integrated circuit with the longest propagation delay times. Methods for identifying longest paths through an integrated circuit under different operating conditions are known in the technical field, for example, from “B. Seshadri, I. Pomeranz, S. Reddy, and S. Kundu, “Path-oriented transition fault test generation considering operating conditions,” in European Test Symposium (ETS’05), 2005, pp. 54-59”, and as disclosed in Applicant’s co-pending international patent application PCT / US2023 / 031744.

[0071] However, again, for an IC with many thousands of paths, and a large number of different PVTA combinations, even monitoring the longest paths identified by the methods disclosed in the above-cited references may require an infeasibly large number of monitors, incurring an excessively large area overhead. Aspects of the present disclosure to be described in detail herein therefore relate to selecting a subset of the longest paths. A method for selecting a subset of paths to monitor is described in further detail with reference to Figures 4 to 7.

[0072] Referring next to Figure 3, aspects of the present disclosure relate to insertion of propagation delay monitors, such as monitor 301, into an integrated circuit to monitor propagation delays along paths, such as path 104 of the integrated circuit 101. As will be known by the skilled person, integrated circuits may be arranged such that multiple paths terminate at a same flip flop. In examples of the present disclosure therefore, the propagation delay monitor is placed in parallel with the terminating flip flop, such as flip flop 103. Consequently, a single monitor may monitor the propagation delay, and propagation delay changes, of all the paths that end at that flip flop. This arrangement has the advantage that the number of monitors required to monitor a given number of paths may be reduced, or conversely, for a given number of monitors in a quota defined by practical constraints, e.g., available area, a greater number of paths may be monitored. The propagation delay monitor 301 is described in further detail with reference to Figures 8 to 10 and 13 to 17.

[0073] Referring next to Figures 4 and 5 collectively, advantages of the present method for selecting a subset of paths for monitoring propagation delays can be appreciated in the context of the integrated circuit 401 which comprises paths / ?, q, and r. Each of the paths / ?, q.and r is formed by a chain of logical cells, for processing a respective signal passing between the input and the output.

[0074] Path p begins at flip flop 402, includes logical cells 403, 404 and 405, and terminates at flip flop 406. Path q begins at flip flop 407, includes logical cells 408, 409 and 405, and terminates at flip flop 406. It can be observed that paths p and q include a relatively high proportion of unique logical cells, inasmuch that they include only a single common logical cell, logical cell 405. Insertion of the monitor 301 in parallel with the flip flop 406 allows monitoring of propagation delays along both path p and path q using a single monitor. Moreover, because the paths p and q include a relatively high number of unique logical cells, and have very little overlap of logical cells, monitor 301 is exposed to propagation delays resulting from a relatively high number of logical cells, and may thus be used to detect propagation delay failures of a relatively high number of logical cells.

[0075] In comparison, referring to Figure 5, path r starts at flip flop 402, the same flip flop at which path p starts, ends at flip flop 501, and includes logical cells 502. It can thus be observed that path r include a relatively high proportion of logical cells in common with path / ?; specifically logical cells 403 and 404 are common with path p. Whereas, path r includes only a single unique logical cell, logical cell 502, that is not also in path p. An additional propagation delay monitor inserted in parallel with flip flop 501 to monitor the propagation delay along path r would thus only be uniquely exposed to propagation delay from one logical cell, logical cell 502, because propagation delays arising from logical cells 403 and 404 may already be monitored by monitor 301 placed in parallel with flip flop 406. The benefit in terms of additional information on propagation delays of logical cells that would result from placement of an additional monitor in parallel with flip flop 501 may thus be considered to be relatively slight, and it may be desirable in such circumstances to avoid the area overhead burden associated with insertion of the additional monitor.

[0076] In view of the above, it can thus be appreciated that it is desirable to be able to identify flip flops at which paths having relatively high numbers of unique logical cells terminate, such that a monitor placed in parallel with the flip flop may be exposed to propagation delays arising from a relatively high number of logical cells. This may desirably allow improved detection of logical cells having excessively long propagation delays that may result in a data error, such as depicted in the scenario of Figure 2.

[0077] Referring next to Figure 6, the present disclosure provides a computer system 601 for determining locations for placement of the propagation delay monitors 301 with the object of allocating monitors of a monitor quota in such a way that monitoring of logical cells of the integrated circuit is maximized. In examples, the computer system 601 comprises a processor 602, memory 603, input / output device 604, and system bus 605.

[0078] Processor 602 is configured for execution of instructions of the computer program for determining locations in an integrated circuit for placement of propagation delay monitors. Memory 603 is configured for non-volatile storage of the computer program, defining machine-readable instructions, for execution by the processor, and for serving as read / write memory for storage of operational data associated with computer programs executed by the processor 602. Input / output interface 604 is configured for connection of the computer system 601 to external systems. For example, input / output interface 604 may communicate with an integrated circuit design system and may receive data describing an integrated circuit design in which the monitors are to be placed. Input / output interface 604 may additionally or alternatively communicate with an external system responsible for identifying longest paths through the integrated circuit design. The components 602 to 604 of the computer system 601 are in communication via system bus 605.

[0079] Referring next to Figure 7, in examples the computer program for determining placements of the propagation delay monitors 301 implemented by the computer system 601 comprises seven operations 701 to 707.

[0080] At operation 701, the computer program causes the processor 602 of the computer system 60 Ito determine paths, / ?, through the integrated circuit for evaluation. Operation could, for example, involve the computer system 601 receiving data describing paths through the integrated circuit for evaluation. The data may describe the paths in terms of starting flip flop, terminating flip flop, logical cells traversed, and propagation delay along the path. In some examples, this may involve the computer system receiving data describing longest paths through the integrated circuit under different PVTA combinations generated by an external system using one of the methods referenced in earlier in this disclosure. In other examples, rather than receiving data describing paths for evaluation, e.g., a describing longest paths, operation 701 could involve the computer system 601 receiving data describing an integrated circuit design and cell library characterizations, and the computer system 601 may itself at stage 701 determine paths through the integrated circuit to be evaluated, for example,by identifying longest paths under different PVTA combinations using the received data and the referenced methods.

[0081] At operation 702, the computer program causes the processor 602 of the computer system 601 to create a data structure forming a list, Path List, of all of the paths determined by operation 701. The Path List may record each path in terms of starting flip flop, terminating flip flop, logical cells traversed, and propagation delay along the path.

[0082] At operation 703, the computer program causes the processor 602 of the computer system 601 to order the paths in the Path List by decreasing order of propagation delay.

[0083] At operation 704, the computer program causes the processor 602 of the computer system 601 to create a number of data structures, referred to herein as ‘lists’. A list Select FF is created to record flip flops of the integrated circuit that are determined for monitoring by the method. A list Covered Paths is created to record paths that terminate in flip flops that are recorded in Select FF. A list Covered Cells is created to record logical cells of the paths that are recorded in Covered Paths. A list Non Covered Paths is created to record paths that are determined by the method as not to be monitored. Initially all of these lists are empty, and the lists are populated during the later operations of the method, as described below.

[0084] At operation 705, the computer program causes the processor 602 of the computer system 601 to determine a quota of monitors available for insertion into the integrated circuit design to monitor the path delays. Operation 705 could, for example, involve the computer system receiving data from an external system describing an available area for placement of monitors, and the computer system may then determine a maximum number of monitors that may permissibly be inserted based on the available area.

[0085] Operations 706 and 707 are performed by the processor 602 of the computer system 601 repeatedly whilst the specified conditions hold true.

[0086] At operation 706, the computer program causes the processor 602 of the computer system 601 to identify a path p at a top of the Path List, that is a path for evaluation that has a longest propagation delay.

[0087] The processor 602 then determines a flip flop ffPat which the path p terminates. The processor 602 then determines a set of other of the paths in the Path List, denoted PxE Path List, that also terminate at the same flip flop ffP.

[0088] The processor 602 then determines for each path pt in the set of paths / A the set SPt of logical cells in each path, and thus the set of logical cells Sxin the set of path Px, given by Sx=UfSp! - pt EPX}.

[0089] The processor 602 then computes a measure of the overlap between the set of cells Sxand the cells contained in the list Covered Cells. The overlap is defined as the ratio of the number of common cells that occur in both the lists to the total number of cells in &, expressed as a percentage, overlap = \SXA Covered ' _Cells\ / \Sx\ * 100.

[0090] The processor 602 then determines whether the overlap is greater than a predetermined threshold, threshold}, that is to say, the processor 602 determines the number of the logical cells Sxin set of paths / A that are in the list Covered Cells, and thus also lie in other paths already determined to be monitored by another monitor. It will be recognized in this regard that during a first iteration of the method, the list Covered Cells will be empty, and thus the percentage of common cells will be zero percent.

[0091] If the overlap is less than the pre-determined threshold threshold}, indicating that a small proportion of the logical cells Sxare already in paths monitored by other monitors, then the flip flop ffPis added to the list Select FF. If the flip flop ffPis added to Select FF, the set of cells Sx= U{Spi: pt E Px} is added to the list Covered Cells, and the paths inxare added to the list Covered Paths. This is the scenario depicted in Figure 4.

[0092] Otherwise, if the processor 602 determined that the overlap between Ak and Covered Cells is larger than the threshold, threshold}, the processor 602 may infer that the added value of monitoring the paths in Pxis small, since a large proportion of the cells are already monitored through other paths. This is the scenario depicted in Figure 5. In this case, the paths in Pxare added to the list Non Covered Paths.

[0093] In both of the above cases, the paths Pxare then deleted from Path List to avoid considering the paths again later in the processes of operation 706.

[0094] The processor 602 then determines, by reference to the list Select FF, whether the number of flip flops that have been determined for monitoring is greater than or equal to the quota of monitors determined at operation 706. In other words, the processor 602 determines whether all of the budgeted monitors have already been allocated to flip flops. If this determination is in the affirmative, the method ends. Else, the method steps of operation 706 are repeated for every path p EPath List. Following consideration of every p EPath List, if the determination at \Select_FF\ >D Mis negative, indicating that there are fewer flip flopsdetermined for monitoring in the list Select FF than there are monitors in the quota D J , or stated more generally that there are spare monitors remaining in the quota D M, the processor 602 proceeds to operation 707.

[0095] Following operation 706, when all of the paths p 6 Path List have been evaluated by reference to the initial threshold threshold}, the processor 602 determines whether the list Non Covered Paths is empty. If the list Non Covered Paths is not empty, at operation 707, the method steps of operation 706 performed on the Path List are repeated for each of the paths in the list Non Covered Paths, but on this iteration using an increased threshold, threshold}.

[0096] Recalling that the list Non Covered Paths was populated during operation 706 by the paths rejected for monitoring by reference to the initial, lower, threshold, operation 707 effectively reconsiders the rejected paths by reference to the higher threshold, in order to fully allocate the available quota of monitors D M. Thus, during operation 707, the overlap between the cells &and the list Covered Cells is permitted to be relatively greater than during operation 706, for the respective flip flop to qualify for monitoring by a monitor 301.

[0097] Accordingly, the method of operations 701 to 707 has the object of allocating a constrained quota of monitors to paths of an integrated circuit in order to monitor the paths of the integrated circuit that are most prone to delay faults, and such that as many as possible of the logical cells are monitored. The method may thereby provide improved detection of propagation delays in paths and logical cells of an integrated circuit.

[0098] Referring next to Figure 8, in examples, each of the propagation delay monitors 301 comprises a programmable delay unit 801, a detection window unit 802, a XOR gate 803, an AND gate 804, and a D flip flop 805. The a XOR gate 803, the AND gate 804, and the D flip flop 805 together constitute a determination device for determining a propagation delay of the monitored path.

[0099] The programmable delay unit 801 introduces a delay in the output signal sg of the path being monitored, to produce the delayed signal d sg. The detection window unit 802 facilitates the monitoring of changes in the path output close to the positive edge of the clock. The XOR gate 803 compares the path output signal sg and the delayed signal d sg. The AND gate 804 combines the XOR gate output 803 and the detection window unit signal w. The flip flop 805 captures the data through the set pin and raises an alarm.

[0100] The programmable delay unit 801 is shown in further detail in Figure 9. The delay unit 801 induces delays of two, three or four gates using a multiplexer depending on the user specification through the select line sei. The delay value determines how early an alarm is raised before a fault actually happens on the signal line sg.

[0101] The detection window unit 802 is shown in further detail in Figure 10. The width of the detection window is denoted by d. The goal is to check whether the delay of the path being monitored is within d gate delays of the positive edge of the clock. The clock is denoted by elk. Its period is denoted by Tclk. In the example, the clock has a 25% duty cycle. To generate the detection window signal w, the clock elk is delayed by the on-time of elk to produce a delayed clock denoted by d elk. The original clock elk and the delayed clock d elk are ORed to generate a new clock denoted by or _clk with 50% duty cycle. The newly generated clock or elk is delayed by Tclk 2 d to produce d or elk. The or elk and d or elk are NORed to generate the detection window signal w.

[0102] The set input S of the flip flop is connected to the output of the AND gate. The reset input R is connected to the reset signal of the delay monitor. When the set input S is high, the flip flop raises the alarm signal. During functional operation, when a path being monitored is close to failure, the path output signal sg, and the delayed signal d ' sg will have different values during the detection window d. In such a case, the output of the XOR gate is set to 1. The AND gate output becomes 1 when the mismatch happens during the detection window d. The flip flop captures this data and raises the alarm. The reset signal reset of the flip flop is low throughout this time. The timing diagram for these signals is shown in Figure 12.

[0103] Referring next to Figure 11, the present disclosure also provides a controller 1101 for controlling the operation of the delay monitors 301 via a communication system 1102.

[0104] The controller 1101 is communicatively coupled to the select line sei and the reset line reset of each of the plurality of delay monitors 301 via the communication system 1102. The controller 1101 is functional to generate a delay set signal, which may be utilized to control the programmable delay unit 801 of each of the delay monitors 301 to set the magnitude of the delay introduced to the delayed signal d sg. The controller 1101 is further functional to interrogate the flip flop 805 of each delay monitor 301, to read the data stored. The controller 1101 may thereby identify propagation delay faults on paths through the IC. The controller 1101 may further be communicatively coupled by the communication system1102 to the alarm line of each delay monitor 301, to receive the alarm signals generated by the respective flip flop 805.

[0105] The controller 1101 may, for example, include the same components as computer system 601, and may thus include a processor, memory, and an input / output interface. In some examples, the controller 1101 may be integrated with the computer system 601, such that the computer system 601 performs the functions of both determining placement of the delay monitors and also controlling the delay monitors.

[0106] Once a specific number of delay monitors 301 are inserted into the design, the select signal sei of the programmable delay unit s and the reset signal reset, in all the delay monitors can be controlled globally by the controller 1101 using a single select line, and a single reset line that are routed to all the monitors. Sets of delay monitors 301 can also be grouped together to maintain more granularity with their own select lines and reset lines.

[0107] The delay monitors 301 can be operated during both the functional mode and the test mode. To offload the alarm data raised by various monitors to the controller 1101, the alarm signals of all the monitors can be ORed together. This generates a single signal that indicates when some of the paths in the design are close to failure. Instead, the flip flops of various delay monitors 301 can be connected to the IJTAG network of the design. The contents of the delay monitors 301 can be off-loaded by scanning out the contents of the IJTAG network in a periodic manner by placing the design in test mode.

[0108] An alternative approach is to combine the data from the delay monitors 301 in a manner such that the contents can be transported via the functional interfaces of a design (such as PCIe, PCB, etc.). This needs that the delay monitors 301 are properly isolated from the rest of the design. The clock driving the D flip flops of the delay monitors 301 when scanning out the data is either the IJTAG-clock in test mode or a slow functional clock in functional mode. Once the alarm data is off loaded, if a significant number of delay monitors 301 have raised an alarm signal, correcting procedures such as dynamic voltage scaling and body biasing can be performed to provide safe functioning of the circuit.

[0109] Referring to the timing diagram of Figure 12, it can be observed that even the delayed signal d_sg would have latched the correct value into the data flip flop if the setup time of the flip flop was satisfied. However, the delay monitor disclosed herein detects that the output signal sg of the monitored path, CP, is close to d gate delays from the positive edgeof the clock and raises the alarm. Thus, degradation of the path, in a way that has resulted in increased propagation delay, may be detected even before a data error occurs.

[0110] Figure 13 depicts another propagation delay monitor 1301 embodying the present disclosure. The propagation delay monitor 1301 is substantially similar to the propagation delay monitor 301, except as described herein, and like components are depicted by like reference numerals.[oni] The propagation delay monitor 1301 differs from the propagation delay monitor 301 in the alternative placement of the programmable delay unit 801, and in the insertion of a variable buffer delay unit 1302 in the original place of the programmable delay unit 801. In this embodiment, the programmable delay unit 801 is located immediately after the XOR gate 803, such that the programmable delay unit 801 receives the output of the XOR gate 803, and in turn outputs a signal to the AND gate 804. In Figure 13, the output of the XOR gate, the comparison signal, is denoted gl, but is analogous to the xor out reference used in Figure 8.

[0112] In embodiment 1301, the variable buffer 1301 is inserted in place of the programmable delay unit 801 of embodiment 301. The variable buffer 1301 may thus be utilized to apply a small, fixed delay to the path signal sg and thereby generate the delayed path signal d sg. As in embodiment 301, the signal sg and the delayed signal d ' sg are XORed by the XOR gate 803, to generate a comparison signal representative of a difference between the signals, which as noted above, is denoted as gl in Figures 13 onwards. Applying a fixed delay to the path signal sg results in a comparison signal, gl, that is correspondingly fixed in width. Accordingly, the signal gl is relatively unsusceptible to variations under different PVT comers.

[0113] As in embodiment 301, in embodiment 1301, the programmable delay unit 801 may be controlled by a delay set signal applied to the sei input to apply a variable delay to the comparison signal gl. Accordingly, whilst the width of the signal gl may remain fixed, by applying the small fixed delay to generate the signal d sg, the amount of delay imparted on the comparison signal gl may still be varied, to thereby vary how early an alarm is raised before a fault actually occurs on the path output sg.

[0114] Similarly to embodiment 301, the AND gate 804 combines the delayed comparison signal d ' gl and the detection window signal w and the output describes whether the signals coincide. The flip flop 805 captures the data through the set pin S and raises an alarm accordingly.

[0115] Figure 14 depicts an alternative embodiment of the detection window device 802. The detection window device 1401 may be usefully used in place of the detection window device 802 of either or both of the propagation delay monitors 301, 1301.

[0116] The detection window device 1401 comprises a variable buffer 1402, inverter gate 1403, and an AND gate 1404.

[0117] Similarly to the detection window unit 802, in the embodiment 1401 of Figure 14, the width of the detection window is denoted by d. The purpose of the detection window is to check whether the delay of the path being monitored is within d gate delays of the positive edge of the clock. Varying the value of d varies the proximity to the clock edge at which the path output sg is monitored. In the example, the clock has a 50% duty cycle. To generate the detection window signal w, the clock elk is delayed by d units, and inverted to generate a delayed inverted clock signal denoted by inv elk. The signals elk and inv elk are ANDed to generate the detection window signal w as shown in Figure 18. From Figure 18, it can be noted that the window w of width d appears after the positive clock edge. The window w may thus be usefully used to detect both paths that are close to failure, and paths that have already failed.

[0118] Figure 15 depicts an alternative embodiment of the programmable delay unit 801. The programmable delay unit 1501 may be usefully used in place of the programmable delay unit 801 of either or both of the propagation delay monitors 301, 1301.

[0119] The delay unit induces delays of zero, one or two buffers onto the comparison signal gl to generate the delayed signal; in the case of embodiment 301 the delayed signal d sg, and in the case of embodiment 1301, the delayed comparison signal d ' gl The delay induced is determined using a multiplexer with select line denoted by sei. The amount of delay induced determines how early an alarm is raised before a fault actually happens on the path output sg.

[0120] Figure 16 depicts another propagation delay monitor 1601 embodying the present disclosure. The propagation delay monitor 1601 is substantially similar to the propagation delay monitor 1301, except as described herein, and like components are depicted by like reference numerals.

[0121] The propagation delay monitor 1301 differs from the propagation delay monitor 1601, inasmuch that it is functional to monitor path signals sg 1 to sg n, propagating along a corresponding plurality of paths of the integrated circuit. Thus, the monitor 1601 receives thepath signals sg 1 to sg n and generates a respective comparison signal gl 1 to gl n for each of the path signals, in the same way previously described with reference to embodiment 1301. The plural comparison signals gl 1 to gl n are then ORed by OR gate 1602 to generate a combined comparison signal. The combined comparison signal is then delayed by the programmable delay device 801 and ANDed with the detection window signal w in the same way previously described with reference to embodiment 1301.

[0122] In this embodiment, a same propagation delay monitor may be utilized for monitoring propagation delays of signals sg 1 to sg n propagating along respective different paths 1 to n of the integrated circuit. Embodiment 1601 may thus involve an advantage compared to embodiments 301 and 1301 in some applications, in that the same detection window unit 802, programmable delay device 801, AND gate 804, and flip flop 805 may be utilized for monitoring propagation delays of multiple paths. Thereby for a given number of monitored paths an area overhead incurred by inserting the delay monitors may be minimized.

[0123] In Figure 16, the propagation delay monitor 1601 is depicted as including the same hardware arrangement as embodiment 1301 for generating the comparison signals gl 1 to glji. However, the propagation delay monitor 1601 could instead use the hardware arrangement of embodiment 301, in which the programmable delay device 801 is used to generate the delayed path signal d sg, and the programmable delay unit 801 may then be omitted between the OR gate 1602 and the AND gate 804.

[0124] Figure 17 depicts a further alternative embodiment of the propagation delay monitor 301, 1301, 1601 embodying aspects of the present disclosure.

[0125] In embodiments 301, 1301 and 1601, the detection window signal w and the delayed glitch signal d ' gl are separate signals that are ANDed together to drive the set pin S of the flip flop that raises the alarm. In the alternative embodiment, 1701, depicted in Figure 17, the comparison signal gl and the inverted clock signal inv elk are ANDed together by AND gate 1702 to produce a combined signal comb. The combined signal comb is delayed using a buffer 1703 to produce a delayed combined signal d comb. The delayed combined signal d comb is then ANDed with the clock signal elk by the AND gate 804 to drive the set pin S of the flip flop 805 that raises the alarm. The embodiment of Figure 17 may thus involve an advantage in some applications, in that only a single buffer is utilized to induce delay on the combined signal comb.

[0126] The timing diagrams of Figures 19 to 23 depict utilizations of the delay monitors for monitoring propagation delays along pathways of the integrated circuit during functional operation.

[0127] Referring firstly to Figures 19 to 21, these diagrams depict scenarios where the path output sg transitions before the clock edge. This causes the comparison signal gl to be produced before the clock edge. In implementations of the present disclosure, the detection window w is generated after the clock edge. Hence in these scenarios to raise the alarm, a delay of two buffers is induced onto gl to generate d ' gl.

[0128] Thus, referring to Figure 19, the path output sg transitions long before the clock edge, representing a path having an acceptable path delay. Thus, there is no overlap between the detection window w and the delayed comparison signal d ' gl. Hence, the flip flop is not set, and no alarm is raised.

[0129] In the scenario of Figure 20, the path output sg transitions close to the clock edge, representing a path that is close to failing. There is thus an overlap between the detection window w and the delayed comparison signal d ' gl. Hence, the output of the AND gate goes high and sets the flip flop which raises the alarm.

[0130] In the scenario of Figure 21, the path output sg transitions very close to the clock edge, representing a path setup time violation. Thus, there is an overlap between the detection window w and the delayed comparison signal d ' gl. Hence, the output of the AND gate goes high and sets the flip flop which raises the alarm.

[0131] Referring next collectively to Figures 22 and 23, these diagrams depict scenarios where the path output sg transitions after the clock edge. This causes the comparison signal gl to be produced after the clock edge. In these scenarios, and where the detection window is generated after the clock edge, no extra delay is induced onto gl to generate d ' gl.

[0132] In the scenario of Figure 22, the path output sg transitions after the clock edge, thus representing a failed path. There is thus an overlap between the detection window w and the delayed comparison signal tZ_ / . Hence, the output of the AND gate goes high and sets the flip flop which raises the alarm.

[0133] Finally, in the scenario of Figure 23, the path output sg transitions immediately after the first clock edge, representing a hold time violation. Such a scenario may occur when the path under consideration is extremely short. There is thus an overlap between thedetection window w and the delayed comparison signal d ' gl. Hence, the output of the AND gate goes high and sets the flip flop which raises the alarm.

[0134] The system and apparatus described above may use dedicated processor systems, micro controllers, programmable logic devices, microprocessors, or any combination thereof, to perform some or all of the operations described herein. Some of the operations described above may be implemented in software and other operations may be implemented in hardware. Any of the operations, processes, and / or methods described herein may be performed by an apparatus, a device, and / or a system substantially similar to those as described herein and with reference to the illustrated figures. References herein to a device, or similar, do not imply a unitary apparatus, and instead include a system of components, which may or may not be co-located.

[0135] The processor may execute instructions or "code" stored in memory. The memory may store data as well. The processing device may include, but may not be limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, or the like. The processing device may be part of an integrated control system or system manager or may be provided as a portable electronic device configured to interface with a networked system either locally or remotely via wireless transmission.

[0136] The memory may be integrated together with the processing device, for example RAM or FLASH memory disposed within an integrated circuit microprocessor or the like. In other examples, the memory may comprise an independent device, such as an external disk drive, a storage array, a portable FLASH key fob, or the like. The memory and processing device may be operatively coupled together, or in communication with each other, for example by an I / O port, a network connection, or the like, and the processing device may read a file stored on the memory. Associated memory may be "read only" by design (ROM) by virtue of permission settings, or not. Other examples of memory may include, but may not be limited to, WORM, EPROM, EEPROM, FLASH, or the like, which may be implemented in solid state semiconductor devices. Other memories may comprise moving parts, such as a known rotating disk drive. All such memories may be "machine-readable" and may be readable by a processing device.

[0137] Operating instructions or commands may be implemented or embodied in tangible forms of stored computer software (also known as "computer program" or "code"). Programs,or code, may be stored in a digital memory and may be read by the processing device. “Computer-readable storage medium" (or alternatively, "machine-readable storage medium") may include all of the foregoing types of memory, as well as new technologies of the future, as long as the memory may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, and as long at the stored information may be "read" by an appropriate processing device. The term "computer-readable" may not be limited to the historical usage of "computer" to imply a complete mainframe, minicomputer, desktop or even laptop computer. Rather, "computer-readable" may comprise storage medium that may be readable by a processor, a processing device, or any computing system. Such media may be any available media that may be locally and / or remotely accessible by a computer or a processor, and may include volatile and non-volatile media, and removable and non-removable media, or any combination thereof.

[0138] A program stored in a computer-readable storage medium may comprise a computer program product. For example, a storage medium may be used as a convenient means to store or transport a computer program. For the sake of convenience, the operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be cases where these functional blocks or diagrams may be equivalently aggregated into a single logic device, program, or operation with unclear boundaries.

[0139] While the application describes specific examples of carrying out embodiments of the disclosure, those skilled in the art will appreciate that there are numerous variations and permutations of the above described systems and techniques that fall within the spirit and scope of the disclosure as set forth in the appended claims. For example, while specific terminology has been employed above to refer to electronic design automation processes, it should be appreciated that various examples of the disclosure may be implemented using any desired combination of electronic design automation processes.

[0140] One of skill in the art will also recognize that the concepts taught herein can be tailored to a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are but one of many alternative implementations that will become apparent upon reading this disclosure.

[0141] Although the specification may refer to “an,” “one,” “another,” or “some” example(s) in several locations, this does not necessarily mean that each such reference is to the same example(s), or that the feature only applies to a single example.

Claims

CLAIMS1. A monitor device for monitoring a propagation delay of a signal along a path through an integrated circuit, the monitor device comprising: a delay device configured to receive the signal and generate a delayed signal being a version of the received signal that is time-delayed relative to the received signal; a detection window device configured to generate a detection window signal based on a clock signal of the integrated circuit; and a determination device configured to determine whether a value of the received signal is different to a value of the delayed signal during a time defined by the detection window signal and generate a determination signal based on the determination.

2. The monitor device of claim 1, wherein the determination device comprises: an XOR logic gate configured to compare the received signal and the delayed signal and generate a comparison signal representative of a difference between the received signal and the delayed signal, and an AND logic gate configured to combine the comparison signal and the detection window signal and generate a combination signal representative of a difference between the received signal and the delayed signal occurring during a time defined by the detection window signal.

3. The monitor device of claim 1, further comprising: a flip flop, wherein an input of the flip flop is connected to an output of the determination device to receive the determination signal and store information representative of the determination based on the determination signal.

4. The monitor device of claim 3, wherein the flip flop is configured to generate an alarm signal based on the determination signal.

5. The monitor device of claim 1, wherein the detection window device is configured to determine a detection window based on a function of a predetermined propagation delay of the path and a positive edge of the clock signal.

6. The monitor device of claim 1, wherein the monitor device is configured to receive a further signal, and wherein, for the further received signal, the generating of the delayed signal comprises generating a further delayed signal that is time-delayed relative to the further received signal by a different period of time than the delayed signal is time-delayed relative to the received signal.

7. The monitor device of claim 6, wherein the further delayed signal is time-delayed relative to the further received signal by a relatively greater period of time than the delayed signal is time-delayed relative to the received signal.

8. The monitor device of claim 1, wherein the delay device is configured to receive a delay set signal representative of time-delay, and wherein the delay device is further configured to generate the delayed signal based on the received signal and the delay set signal.

9. The monitor device of claim 1, for monitoring respective propagation delays of one or more signals propagating along one or more other paths through the integrated circuit, the monitor device further comprises: a plurality of delay devices, each delay device of the plurality of delay devices being configured to receive a signal from a respective path and generate a respective delayed signal being a version of the respective received signal that is time-delayed relative to the respective received signal, wherein the determination device is configured to determine for each delay device of the plurality of delay devices whether a value of the respective received signal is different to a value of the respective delayed signal during a time defined by the detection window signal, and generate one or more determination signals based on the determinations.

10. The monitor device of claim 9, wherein the determination device comprises an OR logic device configured to combine outputs of the plural delay devices to generate a combined output signal, wherein the determination is performed based on the combined output signal.

11. The monitor device of claim 1, wherein the detection window device is configured to: generate an inverted clock signal being an inverted-amplitude version of the clock signal; and generate the detection window signal based on the clock signal and the inverted clock signal.

12. The monitor device of claim 11, wherein the detection window device is configured to: apply a time delay to the clock signal or to the inverted-amplitude version of the clock signal to generate a delayed inverted clock signal; and generate the detection window signal based on the clock signal and the delayed inverted clock signal.

13. The monitor device of claim 1, wherein the determination device comprises: an exclusive OR (XOR) logic gate configured to compare the received signal and the delayed signal and generate a comparison signal representative of a difference between the received signal and the delayed signal; a time delay device configured to apply a time-delay to the comparison signal to generate a delayed comparison signal; and an AND logic gate configured to combine the delayed comparison signal and the detection window signal and generate a combination signal representative of a difference between the received signal and the delayed signal occurring during the time defined by the detection window signal, wherein the determining whether a value of the received signal is different to a value of the delayed signal during a time defined by the detection window signal comprises determining the occurrence of the combination signal.

14. The monitor device of claim 13, wherein the time delay device of the determination device is a variable time delay device configured to apply a variable time-delay to the comparison signal in dependence on a delay set signal supplied to an input of the time delay device.

15. The monitor device of claim 13, wherein the determination device is configured to: determine whether the received signal transitions during a time defined by the detection window signal; and apply a time delay to the comparison signal using the time delay device in dependence on whether the received signal is determined to transition during a time defined by the detection window signal.

16. The monitor device of claim 1, wherein the detection window device is configured to: generate the detection window signal based on the clock signal, a delayed clock signal being a time-delayed version of the clock signal, and an inverted delayed clock signal being an inverted amplitude version of the time-delayed clock signal, by generating an AND combination of the clock signal and the inverted time-delayed clock signal; and generate the detection window signal based on the AND combination of the clock signal and the inverted time-delayed clock signal.

17. The monitor device of claim 1, wherein the detection window device is configured to generate an inverted clock signal being an inverted-amplitude version of the clock signal and generate the detection window signal based on the clock signal and the inverted clock signal, and wherein the determination device is configured to: compare the received signal and the delayed signal and generate a comparison signal representative of a difference between the received signal and the delayed signal; generate a combined signal by applying an AND operation to the comparison signal and the inverted clock signal; apply a time delay to the combined signal to generate a delayed combined signal; andgenerate the determination signal by application an AND operation to the delayed combined signal and the clock signal.

18. A system comprising: one or more monitor devices for monitoring a propagation delay of a signal along a path through an integrated circuit; a controller; and a communication system for communicating the controller with the one or more monitor devices, wherein each monitor device of the one or more monitor devices comprises: a delay device configured to receive the signal and generate a delayed signal being a version of the received signal that is time-delayed relative to the received signal; a detection window device configured to generate a detection window signal based on a clock signal of the integrated circuit; and a determination device configured to determine whether a value of the received signal is different to a value of the delayed signal during a time defined by the detection window signal and generate a determination signal based on the determination.

19. The system of claim 18, wherein the controller is configured to generate a delay set signal and transmit the delay set signal to the one or more monitor devices via the communication system.

20. The system of claim 18, wherein each monitor device of the one or more monitor devices further comprises a flip flop having an input connected to an output of the determination device to receive the determination signal and store information representative of the determination based on the determination signal, and wherein the controller is configured to read the information from the flip flop of each monitor device of the one or more monitor devices via the communication system.

21. A method for monitoring propagation delays along one or more paths through an integrated circuit using a monitor device, the method comprising: receiving a signal from a monitored path; generating based on the received signal a delayed signal being a version of the received signal that is time-delayed relative to the received signal; determining a detection window for monitoring the received signal and the delayed signal based on a clock signal of the integrated circuit; and determining whether a value of the received signal is different to a value of the delayed signal during the detection window.

22. The method of claim 21, further comprising: generating an alarm signal based on a determination that the value of the received signal is different to the value of the delayed signal during the detection window.

23. The method of claim 21, wherein the determining of the detection window is based on a function of a predetermined propagation delay of the path and a positive edge of the clock signal.

24. The method of claim 21, further comprising: repeating the method, wherein, for a repetition of the method, the generating of the delayed signal comprises generating a further delayed signal that is time-delayed relative to the received signal received during the repetition of the method by a different period of time than the delayed signal is time-delayed relative to the received signal received during an initial performance of the method.

25. The method of claim 24, wherein the further delayed signal is time-delayed relative to the received signal received during the repetition of the method by a relatively greater period of time than the delayed signal is time-delayed relative to the received signal during the initial performance of the method.

26. The method of claim 21, further comprising: receiving at least one other signal from at least one other monitored path of the integrated circuit; generating for each of the other received signals a respective delayed signal being a version of the respective received signal that is time-delayed relative to the respective received signals; and determining whether a value of each of the other received signals is different to a value of the respective delayed signal during the detection window.

27. The method of claim 21, wherein the determining of the detection window comprises: generating an inverted clock signal being an inverted-amplitude version of the clock signal; and generating the detection window signal based on the clock signal and the inverted clock signal.

28. The method of claim 27, wherein the determining of the detection window comprises: applying a time delay to the clock signal or to the inverted-amplitude version of the clock signal to generate a delayed inverted clock signal; and generating the detection window signal based on the clock signal and the delayed inverted clock signal.

29. The method of claim 21, wherein the determining whether a value of the received signal is different to a value of the delayed signal during a time defined by the detection window signal comprises: comparing the received signal and the delayed signal and generating a comparison signal representative of a difference between the received signal and the delayed signal; applying a time-delay to the comparison signal to generate a delayed comparison signal; combining the delayed comparison signal and the detection window signal and generate a combination signal representative of a difference between the receivedsignal and the delayed signal occurring during the time defined by the detection window signal; and determining the occurrence of the combination signal.

30. The method of claim 29, wherein the applying of the time-delay to the comparison signal comprises receiving a delay set signal defining a magnitude of a delay and applying the time-delay to the comparison signal based on the delay set signal.

31. The method of claim 29, wherein the applying of the time-delay to the comparison signal comprises: determining whether the received signal transitions during the time defined by the detection window signal; and applying the time delay to the comparison signal in dependence on whether the received signal is determined to transition during the time defined by the detection window signal.

32. A computer program comprising instructions, which, when executed by a computer, cause the computer to carry out the method of any of claims 21 to 31.

33. A data storage apparatus having stored thereon the computer program of claim 32.

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