Display substrate and display apparatus

Abstract

The present disclosure provides a display substrate and a display apparatus. The display substrate comprises: a base substrate; and at least three functional layers, at least two first adaptation layers and a target connecting portion, which are all disposed on the base substrate. At least two functional layers among the at least three functional layers are sequentially stacked along a direction away from the base substrate, and the at least three functional layers comprise a target functional layer, which is a functional layer farthest from the base substrate among the at least three functional layers. The at least two first adaptation layers comprise a top adaptation layer and at least one bottom adaptation layer. The top adaptation layer is located at a side of the target functional layer facing away from the base substrate, and is separately coupled to the target connecting portion and the target functional layer. A bottom adaptation layer is at least partially located between the target functional layer and the base substrate, and is separately coupled to the target functional layer and at least one functional layer among the at least three functional layers other than the target functional layer.

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] In recent years, with the increasing pixel density of display products such as Augmented Reality (AR) and Virtual Reality (VR), the area of ​​a single pixel has become smaller and smaller, placing increasingly higher demands on layout design and manufacturing capabilities. In particular, for some complex processes such as Low Temperature Polycrystalline Oxide (LTPO) fabrication and stacked thin-film transistor (TFT) processes, the smaller area of ​​a single pixel in the layout design presents several challenges. First, the space for metal traces is compressed, leading to short circuits and affecting the product's resolution. Second, multiple vias are needed for electrical connections between metals, between metals and active layers, or between active layers. The increased number of vias increases the width of the metal lines connecting these vias, further impacting the display product's resolution. Therefore, optimizing layout design and manufacturing processes to reduce the density of metal traces or the number of vias to further improve display product resolution has become increasingly important to the display panel industry.

[0003] Summary of the Invention

[0004] The purpose of this disclosure is to provide a display substrate and a display device.

[0005] To achieve the above objectives, this disclosure provides the following technical solution:

[0006] The first aspect of this disclosure provides a display substrate, comprising: a substrate, and at least three functional layers, at least two first transition layers, and a target connection portion, all disposed on the substrate.

[0007] At least two of the at least three functional layers are stacked sequentially in a direction away from the substrate. The at least three functional layers include a target functional layer, which is the functional layer that is furthest from the substrate among the at least three functional layers.

[0008] The at least two first transition layers include: a top transition layer and at least one bottom transition layer;

[0009] The top layer is located on the side of the target functional layer facing away from the substrate, and the top layer is coupled to the target connection portion and the target functional layer respectively.

[0010] At least a portion of the bottom transition layer is located between the target functional layer and the substrate, and the bottom transition layer is coupled to the target functional layer and at least one non-target functional layer among the at least three functional layers.

[0011] Optionally, the at least three functional layers further include a first functional layer and a second functional layer; at least a portion of the first functional layer is located between the substrate and the second functional layer; the at least two first transition layers include a bottom transition layer; the bottom transition layer is coupled to the first functional layer and the second functional layer respectively.

[0012] Optionally, the first functional layer includes a protruding portion, the orthographic projection of the protruding portion on the substrate not overlapping with the orthographic projection of the second functional layer on the substrate;

[0013] The display substrate includes a first sleeve hole, and the bottom transition layer is coupled to the first functional layer and the second functional layer respectively through the first sleeve hole; the target functional layer and the portion of the bottom transition layer outside the first sleeve hole are directly overlapped.

[0014] Optionally, the first via includes a first sub-via and a second sub-via that are interconnected. The first sub-via is located between the second sub-via and the substrate. The diameter of the second sub-via is larger than the diameter of the first sub-via. The bottom transition layer is coupled to the second functional layer through the second sub-via. The bottom transition layer is coupled to the first functional layer through the second sub-via and the first sub-via.

[0015] Optionally, the target functional layer includes a first sub-target functional layer and a second sub-target functional layer stacked together, wherein the first sub-target functional layer is located between the second sub-target functional layer and the substrate, and the carrier mobility of the first sub-target functional layer is greater than that of the second sub-target functional layer.

[0016] The portion of the first sub-target functional layer and the portion of the bottom transition layer located outside the first sleeve hole directly overlaps.

[0017] Optionally, the top-level transition layer is also directly coupled to the bottom-level transition layer.

[0018] Optionally, the display substrate further includes a second set of vias, which includes a third sub-via and a fourth sub-via that are interconnected. The third sub-via is located between the fourth sub-via and the substrate. The aperture of the fourth sub-via is larger than that of the third sub-via. The top layer is coupled to the target functional layer through the fourth sub-via, and the top layer is coupled to the bottom layer through the fourth sub-via and the third sub-via.

[0019] Optionally, the display substrate includes a first source / drain metal layer, and the top transition layer is disposed in the same layer and with the same material as the first source / drain metal layer.

[0020] Optionally, the display substrate includes a plurality of sub-pixels disposed on the substrate. Each sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit includes a driving transistor, a sensing transistor, and a storage capacitor. The first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the second electrode of the driving transistor, the second electrode of the sensing transistor, and the anode of the light-emitting element, respectively.

[0021] The first functional layer includes the active layer in the driving transistor, the second functional layer includes the second plate of the storage capacitor, the target functional layer includes the sensing active layer in the sensing transistor, and the target connection includes the anode of the light-emitting element.

[0022] Optionally, when the target functional layer includes a first sub-target functional layer and a second sub-target functional layer stacked together, both the first sub-target functional layer and the second sub-target functional layer are made of transparent metal oxide material.

[0023] Optionally, the display substrate further includes a data line; the sub-pixel driving circuit further includes a data writing transistor, the first terminal of the data writing transistor being coupled to the corresponding data line, and the second terminal of the data writing transistor being coupled to the gate of the driving transistor;

[0024] The data writing transistor includes a data writing active layer, and the data line is located on the side of the data writing active layer facing the substrate.

[0025] Optionally, the display substrate further includes a light-shielding layer located on the side of the data line facing the substrate.

[0026] Optionally, the display substrate further includes a sensing signal line, a second adapter layer, and a compensation signal line; the first electrode of the sensing transistor is coupled to the corresponding sensing signal line; the sensing signal line is coupled to the corresponding compensation signal line through the corresponding second adapter layer.

[0027] The compensation signal line is disposed in the same layer and material as the light-shielding layer, and at least a portion of the second transition layer is located between the sensing signal line and the compensation signal line.

[0028] Optionally, the display substrate further includes a light-shielding layer, with the data line located on the side of the light-shielding layer facing the substrate.

[0029] Optionally, the display substrate further includes a light-shielding layer, and the data line is disposed in the same layer and made of the same material as the light-shielding layer.

[0030] Optionally, the display substrate further includes a second gate metal layer; the sub-pixel driving circuit further includes a third transition layer, the third transition layer being coupled to the portion of the data writing active layer that serves as the first electrode of the data writing transistor, and the data line, respectively; the third transition layer and the second gate metal layer are disposed in the same layer and with the same material.

[0031] Optionally, the display substrate further includes a fourth transition layer, which is coupled to the portion of the data writing active layer that serves as the second electrode of the data writing transistor and the gate of the driving transistor, respectively; the fourth transition layer and the bottom transition layer are disposed in the same layer and made of the same material.

[0032] Optionally, the display substrate further includes a third gate insulating layer;

[0033] The sensing active layer includes a sensing channel portion and a sensing conductor portion, the sensing conductor portion serving as the first and second electrodes of the sensing transistor, and at least a portion of the third gate insulating layer located between the gate of the sensing transistor and the sensing channel portion; the orthographic projection of the third gate insulating layer on the substrate does not overlap with the orthographic projection of the sensing conductor portion on the substrate.

[0034] Optionally, the display substrate further includes a third gate insulating layer;

[0035] The sensing active layer includes a sensing channel portion and a sensing conductor portion, the sensing conductor portion serving as the first and second electrodes of the sensing transistor, and at least a portion of the third gate insulating layer located between the gate of the sensing transistor and the sensing channel portion; the orthographic projection of the third gate insulating layer on the substrate covers the orthographic projection of the sensing conductor portion on the substrate.

[0036] Based on the above-described display substrate technical solution, a second aspect of this disclosure provides a display device including the above-described display substrate. Attached Figure Description

[0037] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0038] Figure 1 is a schematic diagram of the circuit structure of the sub-pixel driving circuit provided in an embodiment of this disclosure;

[0039] Figure 2 is a timing diagram of the sub-pixel driving circuit provided in an embodiment of this disclosure;

[0040] Figure 3 is a first cross-sectional schematic diagram of the display substrate provided in an embodiment of this disclosure;

[0041] Figure 4 is a second cross-sectional schematic diagram of the display substrate provided in an embodiment of this disclosure;

[0042] Figure 5 is a schematic diagram of the connection between the oxide active layer and the first source / drain metal layer provided in an embodiment of this disclosure;

[0043] Figure 6 is an enlarged schematic diagram of the top and bottom transition layers in Figure 4;

[0044] Figure 7 is a schematic diagram of the third cross-section of the display substrate provided in an embodiment of this disclosure;

[0045] Figure 8 is a fourth cross-sectional schematic diagram of the display substrate provided in an embodiment of this disclosure;

[0046] Figure 9 is an enlarged schematic diagram of the top and bottom transition layers in Figure 8;

[0047] Figure 10 is a fifth cross-sectional schematic diagram of the display substrate provided in an embodiment of this disclosure;

[0048] Figures 11 to 15 are schematic diagrams illustrating the manufacturing process of the display substrate provided in the embodiments of this disclosure;

[0049] Figure 16 is a sixth cross-sectional schematic diagram of the display substrate provided in an embodiment of this disclosure. Detailed Implementation

[0050] To further illustrate the display substrate and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0051] Based on the analysis of the background technology, it is clear that optimizing layout design and processes to reduce the density of metal traces or the number of vias, thereby reducing layout difficulty while further improving the resolution of display products, is receiving increasing attention from the display panel industry. Based on this, the embodiments of this disclosure provide the following technical solutions.

[0052] Please refer to Figure 4. This embodiment of the present disclosure provides a display substrate, including: a substrate 10, and at least three functional layers, at least two first transition layers, and a target connection portion 20, all disposed on the substrate 10.

[0053] At least two of the at least three functional layers are stacked sequentially in a direction away from the substrate 10. The at least three functional layers include a target functional layer 33, which is the functional layer furthest from the substrate 10 among the at least three functional layers.

[0054] The at least two first transition layers include: a top transition layer 42 and at least one bottom transition layer 41;

[0055] The top layer transition layer 42 is located on the side of the target functional layer 33 facing away from the substrate 10, and the top layer transition layer 42 is coupled to the target connection portion 20 and the target functional layer 33 respectively.

[0056] At least a portion of the bottom transition layer 41 is located between the target functional layer 33 and the substrate 10. The bottom transition layer 41 is coupled to the target functional layer 33 and at least one non-target functional layer (e.g., the first functional layer 31 and the second functional layer 32) of the at least three functional layers.

[0057] For example, the display substrate includes a display area and a peripheral area surrounding the display area. The display area includes a plurality of sub-pixels arranged in an array and a plurality of signal lines of different types. The peripheral area may include a gate driving circuit and a plurality of signal lines of different types, and may also include other circuit structures. The peripheral area may also exclude the gate driving circuit.

[0058] For example, the display area includes the at least three functional layers, the at least two first transition layers, and the target connection portion 20; and / or, the surrounding area includes the at least three functional layers, the at least two first transition layers, and the target connection portion 20.

[0059] For example, the at least three functional layers are stacked sequentially in a direction away from the substrate 10, and an insulating layer may be disposed between adjacent functional layers. For example, the orthographic projections of any two functional layers on the substrate 10 may or may not overlap.

[0060] For example, the target connection portion 20 is located on the side of the top layer transition layer 42 facing away from the substrate 10, but is not limited to this.

[0061] For example, the non-target functional layer includes the remaining film layers in the at least three functional layers other than the target functional layer 33.

[0062] For example, the bottom transition layer 41 is coupled to the target functional layer 33 and all non-target functional layers among the at least three functional layers.

[0063] As can be seen from the specific structure of the display substrate described above, in the display substrate provided in this embodiment, the target functional layer 33 and non-target functional layers are first connected together through the bottom transition layer 41, and then the target functional layer 33 and the target connection portion 20 are connected together through the top transition layer 42. In this way, all functional layers can be coupled to the target connection portion 20 through the top transition layer 42. Since the top transition layer 42 only needs to be coupled to the target functional layer 33 in the functional layers, the top transition layer 42 only needs to cover the vias between the top transition layer 42 and the target functional layer 33, thereby reducing the number of vias between the top transition layer 42 and the functional layers, reducing the area of ​​the top transition layer 42, and further improving the resolution of the display product while reducing the layout difficulty of the display substrate.

[0064] More specifically, as shown in Figure 3, another connection method is provided for comparison. Figure 3 shows only one top-level transition layer 42, which is used to couple with each functional layer. This method requires the top-level transition layer 42 to have a large area, capable of simultaneously covering the vias between the top-level transition layer 42 and each functional layer. Compared to this method, the area of ​​the top-level transition layer 42 in the display substrate provided in this embodiment is significantly reduced, which not only reduces the layout difficulty of the film layer containing the top-level transition layer 42 but also helps to improve the resolution of the display substrate.

[0065] As shown in Figure 4, in some embodiments, the at least three functional layers further include a first functional layer 31 and a second functional layer 32; at least a portion of the first functional layer 31 is located between the substrate 10 and the second functional layer 32; the at least two first transition layers include a bottom transition layer 41; the bottom transition layer 41 is coupled to the first functional layer 31 and the second functional layer 32 respectively.

[0066] For example, the orthographic projection of the first functional layer 31 on the substrate 10 at least partially overlaps with the orthographic projection of the second functional layer 32 on the substrate 10.

[0067] In the display substrate provided in the above embodiment, the target functional layer 33, the first functional layer 31, and the second functional layer 32 are first connected together through the bottom transition layer 41, and then the target functional layer 33 and the target connection portion 20 are connected together through the top transition layer 42. In this way, all functional layers can be coupled to the target connection portion 20 through the top transition layer 42. Since the top transition layer 42 only needs to be coupled to the target functional layer 33 in the functional layers, the top transition layer 42 only needs to cover the vias between the top transition layer 42 and the target functional layer 33, thereby reducing the number of vias between the top transition layer 42 and the functional layers, reducing the area of ​​the top transition layer 42, and further improving the resolution of the display product while reducing the layout difficulty of the display substrate.

[0068] As shown in FIG4, in some embodiments, the first functional layer 31 includes a protruding portion, and the orthographic projection of the protruding portion on the substrate 10 does not overlap with the orthographic projection of the second functional layer 32 on the substrate 10.

[0069] The display substrate includes a first sleeve hole, and the bottom transition layer 41 is coupled to the first functional layer 31 and the second functional layer 32 respectively through the first sleeve hole; the target functional layer 33 directly overlaps with the portion of the bottom transition layer 41 located outside the first sleeve hole.

[0070] For example, in a direction parallel to the substrate 10, the protruding portion protrudes beyond the second functional layer 32 and is not covered by the second functional layer 32.

[0071] For example, the first via includes a first sub-via and a second sub-via that are interconnected. The first sub-via is located between the second sub-via and the substrate 10. The diameter of the second sub-via is larger than the diameter of the first sub-via. The bottom transition layer 41 is coupled to the second functional layer 32 through the second sub-via. The bottom transition layer 41 is coupled to the first functional layer 31 through the second sub-via and the first sub-via.

[0072] For example, the first sub-via penetrates the insulating layer located between the first functional layer 31 and the second functional layer 32, as well as the insulating layer adjacent to and covering the second functional layer 32. The second sub-via penetrates the insulating layer between the target functional layer 33 and the second functional layer 32.

[0073] In the display substrate provided in the above embodiments, the bottom transition layer 41 is coupled to the first functional layer 31 and the second functional layer 32 respectively through the first via; the target functional layer 33 directly overlaps with the portion of the bottom transition layer 41 outside the first via; the specific connection method between the bottom transition layer 41 and the first functional layer 31, the second functional layer 32 and the target functional layer 33 is optimized, reducing connection complexity and facilitating the development of display products towards higher resolution. Simultaneously, since the top transition layer 42 only needs to be coupled to the target functional layer 33 in the functional layers, the top transition layer 42 only needs to cover the vias between the top transition layer 42 and the target functional layer 33, thereby reducing the number of vias between the top transition layer 42 and the functional layers, reducing the area of ​​the top transition layer 42, and further improving the resolution of the display product while reducing the layout difficulty of the display substrate.

[0074] As shown in FIG7, in some embodiments, the target functional layer 33 includes a first sub-target functional layer 331 and a second sub-target functional layer 332 stacked together. The first sub-target functional layer 331 is located between the second sub-target functional layer 332 and the substrate 10. The carrier mobility of the first sub-target functional layer 331 is greater than that of the second sub-target functional layer 332. The first sub-target functional layer 331 and the portion of the bottom transition layer 41 located outside the first via are directly overlapped.

[0075] For example, both the first sub-target functional layer 331 and the second sub-target functional layer 332 are made of transparent metal oxide. For instance, the first sub-target functional layer 331 is made of indium gallium zinc oxide (IGZO); the second sub-target functional layer 332 is made of indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZYO), etc., but is not limited to these.

[0076] Taking the target functional layer 33, which includes a metal oxide active layer ACT (e.g., indium gallium zinc oxide IGZO material), as an example, when the metal oxide active layer ACT is coupled to the metal layer, the metal oxide active layer ACT is located between the substrate 10 and the metal layer, that is, the metal oxide active layer ACT is located below the metal layer, and the surface of the metal oxide active layer ACT facing away from the substrate 10 contacts the metal layer. The portion of the metal oxide active layer ACT that contacts the metal layer needs to be conductive to achieve good electrical connection. The conductiveing ​​of the metal oxide active layer ACT can be achieved by doping ions, by dry etching plasma, or by H ion diffusion.

[0077] As shown in Figure 5, the metal oxide active layer ACT is located below the metal layer. As long as the upper surface of the metal oxide active layer ACT (point A in the figure) is made conductive, even if the dopant ions used for conductiveing ​​do not enter the middle layer of the metal oxide active layer ACT (point C in the figure), the metal oxide active layer ACT and the metal layer can form a good electrical contact.

[0078] As shown in Figure 6, the connection between the top transition layer 42 and the bottom transition layer 41 requires an electrical connection between the lower surface of the metal oxide active layer ACT and the bottom transition layer 41, and then an electrical connection between the upper surface of the metal oxide active layer ACT and the top transition layer 42. Because the conductor-conducting degree of the lower surface of the metal oxide active layer ACT is less than that of the upper surface, the contact resistance is higher when the lower surface of the metal oxide active layer ACT is connected to the bottom transition layer 41. This ultimately affects the connection performance between the top transition layer 42 and the bottom transition layer 41, and consequently affects the electrical connection between the top transition layer 42 and the first functional layer 31 and the second functional layer 32.

[0079] In the display substrate provided in the above embodiments, by setting the carrier mobility of the first sub-target functional layer 331 to be greater than that of the second sub-target functional layer 332, and by directly overlapping the portion of the first sub-target functional layer 331 and the bottom transition layer 41 located outside the first via, not only is the contact resistance between the target functional layer 33 and the bottom transition layer 41 reduced, effectively improving the problem of high contact resistance when overlapping between the target functional layer 33 and the bottom transition layer 41, but also, the use of the second sub-target functional layer 332 as the top layer can ensure the stability of the transistor structure formed therefrom.

[0080] As shown in Figure 8, in some embodiments, the top layer 42 is also directly coupled to the bottom layer 41.

[0081] For example, the display substrate further includes a second set of vias, which also includes a third sub-via and a fourth sub-via that are interconnected. The third sub-via is located between the fourth sub-via and the substrate 10. The aperture of the fourth sub-via is larger than that of the third sub-via. The top layer transition layer 42 is coupled to the target functional layer 33 through the fourth sub-via. The top layer transition layer 42 is coupled to the bottom layer transition layer 41 through the fourth sub-via and the third sub-via.

[0082] For example, the third sub-via penetrates and covers the insulating layer that is immediately adjacent to the target functional layer 33. The fourth sub-via penetrates the insulating layer between the top transition layer 42 and the target functional layer 33.

[0083] For example, the portion of the top layer 42 and the bottom layer 41 located outside the first sleeve hole directly overlaps.

[0084] In the display substrate provided in the above embodiment, by setting the top layer transition layer 42 to be directly coupled to the bottom layer transition layer 41, a good electrical connection is further formed between the top layer transition layer 42 and the bottom layer transition layer 41. More specifically, the electrical connection between the top layer transition layer 42 and the target functional layer 33 is formed through the top layer transition layer 42 and the upper surface of the target functional layer 33, while the top layer transition layer 42 and the bottom layer transition layer 41 are directly in contact to form an electrical connection. Therefore, a good electrical connection can be formed between the top layer transition layer 42 and the first functional layer 31 and the second functional layer 32. This arrangement avoids the problem of high contact resistance when the lower surface of the target functional layer 33 is connected to the bottom layer transition layer 41.

[0085] As shown in Figure 8, in some embodiments, the display substrate includes a first source / drain metal layer SD1, and the top layer transition layer 42 is disposed in the same layer and with the same material as the first source / drain metal layer SD1.

[0086] When the top layer transition layer 42 and the first source / drain metal layer SD1 are set in the same layer and with the same material, the area of ​​the top layer transition layer 42 is greatly reduced, thereby effectively reducing the layout difficulty of the first source / drain metal layer SD1.

[0087] As shown in Figures 1 to 10, in some embodiments, the display substrate includes a plurality of sub-pixels disposed on the substrate 10. Each sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit includes a driving transistor DTFT, a sensing transistor M2, and a storage capacitor C1. The first plate C11 of the storage capacitor C1 is coupled to the gate g3 of the driving transistor DTFT, and the second plate C12 of the storage capacitor C1 is coupled to the second electrode of the driving transistor DTFT, the second electrode of the sensing transistor M2, and the anode of the light-emitting element, respectively.

[0088] The first functional layer 31 includes the active layer in the driving transistor DTFT, the second functional layer 32 includes the second plate C12 of the storage capacitor C1, the target functional layer 33 includes the sensing active layer in the sensing transistor M2, and the target connection portion 20 includes the anode of the light-emitting element.

[0089] For example, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixel pixels are arranged in an array. The plurality of sub-pixel driving circuits are divided into multiple rows of sub-pixel driving circuits and multiple columns of sub-pixel driving circuits. The multiple rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The multiple columns of sub-pixel driving circuits are arranged along the first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. For example, the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0090] For example, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to the anode of the light-emitting element and is used to provide a driving signal to the light-emitting element to drive it to emit light.

[0091] For example, the display substrate further includes multiple power lines VDD, multiple data lines DA, multiple sensing signal lines Sens, and multiple scan lines Scan. The sub-pixel driving circuit includes a driving transistor DTFT, a data writing transistor M1, a sensing transistor M2, and a storage capacitor C1.

[0092] The gate g3 of the driving transistor DTFT is coupled to the first plate C11 of the storage capacitor C1, the first electrode of the driving transistor DTFT is coupled to the corresponding power line VDD, and the second electrode of the driving transistor DTFT is coupled to the anode of the light-emitting element.

[0093] The gate g1 of the data writing transistor M1 is coupled to the corresponding scan line Scan, the first terminal of the data writing transistor M1 is coupled to the corresponding data line DA, and the second terminal of the data writing transistor M1 is coupled to the gate g3 of the driving transistor DTFT.

[0094] The gate of the sensing transistor M2 is coupled to the corresponding scan line Scan, the first electrode of the sensing transistor M2 is coupled to the corresponding sensing signal line Sens, and the second electrode of the sensing transistor M2 is coupled to the anode of the light-emitting element. The cathode of the light-emitting element receives the power supply signal VSS. For example, the sensing transistor M2 includes a top gate g22 and a bottom gate g21.

[0095] As shown in Figure 1, the sensing signal line Sens is coupled to a first signal terminal via a first switch K1, and to a second signal terminal via a second switch K2. The first signal terminal receives a 0V voltage signal, and the second signal terminal includes a sensing signal terminal VSens. Both the first signal terminal and the sensing signal terminal are coupled to a driver chip included in the display substrate. The on / off state of the first switch K1 is controlled by a first control signal. The on / off state of the second switch K2 is controlled by a second control signal.

[0096] For example, the sensing transistor M2 includes an oxide transistor. The data writing transistor M1 and the driving transistor DTFT include low-temperature polycrystalline silicon transistors. The driving transistor DTFT, the data writing transistor M1, and the sensing transistor M2 are all N-type transistors, but are not limited thereto.

[0097] Figure 2 shows the driving timing diagram of the sub-pixel driving circuit. The first control signal, the second control signal, and the scan signal transmitted by the scan line Scan are all active high. That is, when the signal is high, it can control the corresponding switch to close or control the transistor to turn on. The potential V-N2 of node N2 is initially 0V, and then gradually rises to the threshold voltage Vth of the driving transistor DTFT. The potential of the data signal transmitted by the data line DA is 5V. In Figure 2, a high level represents an active level, controlling the corresponding transistor to turn on.

[0098] As shown in Figure 2, it includes three stages: reset stage t1, compensation stage t2, and sensing stage t3.

[0099] During the reset phase t1: the first switch K1 is closed, the data writing transistor M1 and the sensing transistor M2 are turned on, and nodes N1 and N2 are reset; the potential of node N1, V_N1 = Vdata, where Vdata is the voltage value of the data signal transmitted by the data line DA, and the potential of node N2, V_N2 = 0V.

[0100] During the compensation phase t2: the gate-source voltage Vgs of the driving transistor DTFT is Vdata-Vref>Vth, so the driving transistor DTFT is turned on. The power supply line VDD continuously charges the N2 node through the driving transistor DTFT. As the potential of the N2 node rises, the voltage difference Vgs decreases, and the degree of turn-on of the driving transistor DTFT gradually decreases until the source voltage Vs of the driving transistor is charged to a difference of Vth from the gate voltage Vg. At this point, the driving transistor DTFT is completely turned off, and V_N1 = Vdata, V_N2 = Vdata-Vth.

[0101] During the sensing phase t3: the second switch K2 is closed, and the sensing signal line Sens reads the voltage Vdata-Vth at this time. The driver chip IC extracts Vdata-Vth and outputs it to the FPGA (Field Programmable Gate Array). Through an algorithm, the FPGA outputs the algorithm-compensated value back to the driver chip IC, which then compensates for it in the data signal.

[0102] To achieve a high resolution, if all three transistors are low-temperature polysilicon (LTPS) transistors, the required layout space is large. If two transistors are oxide transistors and one is an LPS transistor, the display substrate may be thicker in the thickness direction, making cross-line connections difficult and reducing the yield of the display product. Therefore, in the display substrate provided in the above embodiment, the sub-pixel driving circuit includes one oxide transistor and two LPS transistors, which can overcome the above problems while effectively improving the resolution of the display product.

[0103] More specifically, as shown in Figure 3, as the resolution of display products gradually increases, the size of individual sub-pixels gradually decreases, making the layout of the first source-drain metal layer SD1 in the display substrate more complex. The first source-drain metal layer SD1 is used to form complex and independent multiple signal traces, as well as some transition layers with transition functions. For example, the signal traces include power lines VDD, sensing signal lines Sens, and data lines DA, etc.; the transition layers include the top transition layer 42 and other transition layers with transition functions. As the resolution increases, the problem of insufficient trace space gradually emerges. If the line width or spacing of the signal traces is compressed, problems such as short circuits or open circuits will occur, thus affecting the further improvement of the display product's resolution.

[0104] In the display substrate provided in the above embodiments, the first functional layer 31 includes the active layer of the driving transistor DTFT, the second functional layer 32 includes the second electrode C12 of the storage capacitor C1, the target functional layer 33 includes the sensing active layer of the sensing transistor M2, and the target connection portion 20 includes the anode of the light-emitting element. For example, the active layer of the driving transistor DTFT includes a polysilicon active layer (Poly), and the sensing active layer of the sensing transistor M2 includes a metal oxide active layer (ACT).

[0105] In the display substrate provided in the above embodiments, the first source / drain metal layer SD1 includes the top layer transition layer 42. Since the active layer in the driving transistor DTFT, the second electrode C12 of the storage capacitor C1, and the sensing active layer in the sensing transistor M2 can be coupled together through the bottom layer transition layer 41, the top layer transition layer 42 only needs to be coupled to the sensing active layer and / or the bottom layer transition layer 41. This reduces the number of vias required when the top layer transition layer 42 is connected to the bottom film layer, thereby reducing the number of vias that the top layer transition layer 42 needs to cover. This reduces the area or size of the top layer transition layer 42, and consequently reduces the area or size of the required first source / drain metal layer SD1, alleviating the problem of insufficient layout space for the first source / drain metal layer SD1, and is beneficial for further improving the resolution of high-resolution display products.

[0106] Furthermore, by directly coupling the top-level transition layer 42 to both the sensing active layer and the bottom-level transition layer 41, the problem of high contact resistance when the sensing active layer overlaps the bottom-level transition layer 41 is solved, improving the display effect of the display product. Simultaneously, the conductivity between the top-level transition layer 42 and the bottom-level transition layer 41 is enhanced, reducing loading and improving the uniformity of the display image.

[0107] As shown in FIG7, in some embodiments, when the target functional layer 33 includes a first sub-target functional layer 331 and a second sub-target functional layer 332 stacked together, both the first sub-target functional layer 331 and the second sub-target functional layer 332 are made of transparent metal oxide material.

[0108] For example, the sensing active layer includes a first sub-target functional layer 331 and a second sub-target functional layer 332 stacked together.

[0109] Because the carrier mobility of the first sub-target functional layer 331 is greater than that of the second sub-target functional layer 332, the portion of the first sub-target functional layer 331 and the bottom transition layer 41 located outside the first via directly overlaps. This not only reduces the contact resistance between the target functional layer 33 and the bottom transition layer 41, effectively improving the problem of high contact resistance when overlapping between the target functional layer 33 and the bottom transition layer 41, but also ensures the stability of the characteristics of the sensing transistor M2 by using the second sub-target functional layer 332 as the top layer.

[0110] As shown in Figures 4, 7, 8 and 10, in some embodiments, the display substrate further includes a data line DA; the sub-pixel driving circuit further includes a data writing transistor M1, the first terminal of which is coupled to the corresponding data line DA, and the second terminal of which is coupled to the gate g3 of the driving transistor DTFT; the data writing transistor M1 includes a data writing active layer, and the data line DA is located on the side of the data writing active layer facing the substrate 10.

[0111] It should be noted that in Figures 4, 7, 8 and 10, g3 is marked on the right side of the figure. This g3 can be a structure coupled to the gate g3 of the driving transistor DTFT, that is, it has the same potential as the gate g3 of the driving transistor DTFT, and may not be used as the gate g3 of the driving transistor DTFT.

[0112] For example, the data writing active layer includes a polysilicon active layer (Poly).

[0113] More specifically, as shown in Figure 3, when the first source-drain metal layer SD1 is used to form complex and independent multiple signal traces, as well as some transition layers, the signal traces and transition patterns need to transmit different signals and cannot be short-circuited with each other; that is, a certain distance needs to be maintained between them. However, due to the high resolution, the layout space of the first source-drain metal layer SD1 is squeezed, making layout difficult and thus affecting the improvement of pixel resolution.

[0114] In the display substrate provided in the above embodiments, the data line DA is located on the side of the data writing active layer facing the substrate 10. The data line DA, which was originally made using the first source-drain metal layer SD1, is transferred to the bottom layer of the display substrate, thereby reducing the complexity of the first source-drain metal layer SD1. This is equivalent to improving the layout space of the first source-drain metal layer SD1 and reducing the layout difficulty of the first source-drain metal layer SD1, which is conducive to further improving the resolution of high-resolution display products.

[0115] In the display substrate provided in the above embodiments, the data line DA and the first source / drain metal layer SD1 can be disposed in different layers, that is, the data line DA is disposed above or below the first source / drain metal layer SD1, which reduces the layout difficulty of the first source / drain metal layer SD1 and is conducive to further improving the resolution of high-resolution display products.

[0116] In some embodiments, the display substrate further includes a light-shielding layer LS, as shown in Figures 4, 7, 8 and 10, wherein the light-shielding layer LS is located on the side of the data line DA facing the substrate 10; or, as shown in Figure 16, the data line DA is located on the side of the light-shielding layer LS facing the substrate 10; or, the data line DA and the light-shielding layer LS are disposed in the same layer and of the same material.

[0117] The above-described method of placing the light-shielding layer LS and the data line DA on different film layers provides both the light-shielding layer LS and the data line DA with ample layout space, which helps reduce the layout difficulty of the display substrate. Furthermore, the above-described method of placing the data line DA and the light-shielding layer LS on the same layer and with the same material allows the data line DA to be formed simultaneously with the light-shielding layer LS in the same patterning process, thereby significantly simplifying the display substrate manufacturing process and reducing its manufacturing cost.

[0118] The data line DA is positioned on the side of the light-shielding layer LS facing the substrate 10, as described above. This helps to further reduce parasitic capacitances generated between the data line DA and surrounding structures, such as the parasitic capacitance between the data line and the gate of the data writing transistor. It should be noted that the isolation layer Bar is also illustrated in Figure 16.

[0119] As shown in Figures 4, 7, 8 and 10, in some embodiments, the display substrate further includes a sensing signal line Sens, a second transition layer 46 and a compensation signal line Sens-B; the first terminal of the sensing transistor M2 is coupled to the corresponding sensing signal line Sens; the sensing signal line Sens is coupled to the corresponding compensation signal line Sens-B through the corresponding second transition layer 46.

[0120] The compensation signal line Sens-B is disposed in the same layer and with the same material as the light-shielding layer LS, and at least a portion of the second transition layer 46 is located between the sensing signal line Sens and the compensation signal line Sens-B.

[0121] For example, the display substrate includes a second gate metal layer, and the second transition layer 46 is disposed in the same layer and with the same material as the second gate metal layer.

[0122] The above-mentioned arrangement of the compensation signal line Sens-B and the light-shielding layer LS in the same layer and with the same material allows the compensation signal line Sens-B and the light-shielding layer LS to be formed simultaneously in the same patterning process, thereby greatly simplifying the manufacturing process of the display substrate and reducing the manufacturing cost of the display substrate.

[0123] The second transition layer 46 is located at least a portion between the sensing signal line Sens and the compensation signal line Sens-B, so that the second transition layer 46 can act as a transition between the corresponding sensing signal line Sens and compensation signal line Sens-B. This not only ensures the connection performance between the sensing signal line Sens and the compensation signal line Sens-B, but also avoids the need to make deep holes for directly connecting the compensation signal line Sens-B and the sensing signal line Sens, thereby improving the manufacturing yield of the display substrate.

[0124] As shown in Figures 4, 7, 8 and 10, in some embodiments, the display substrate further includes a second gate metal layer; the sub-pixel driving circuit further includes a third transition layer 43, which is coupled to the portion of the data writing active layer that serves as the first electrode of the data writing transistor M1, and to the data line DA; the third transition layer 43 and the second gate metal layer are disposed in the same layer and with the same material.

[0125] The above configuration not only ensures the connection performance between the data writing transistor M1 and the corresponding data line DA, but also reduces the connection difficulty between the data writing transistor M1 and the data line DA. Furthermore, by placing the third transition layer 43 and the second gate metal layer on the same layer and made of the same material, the third transition layer 43 and the second gate metal layer can be formed simultaneously in the same patterning process, thereby greatly simplifying the manufacturing process of the display substrate and reducing its manufacturing cost.

[0126] As shown in Figures 4, 7, 8 and 10, in some embodiments, the display substrate further includes a fourth transition layer 44, which is coupled to the portion of the data writing active layer that serves as the second electrode of the data writing transistor M1, and to the gate g3 of the driving transistor DTFT, respectively; the fourth transition layer 44 is disposed in the same layer and with the same material as the bottom transition layer 41.

[0127] The above configuration not only ensures the connection performance between the data writing transistor M1 and the driving transistor DTFT, but also reduces the connection difficulty between them. Furthermore, by placing the fourth transition layer 44 and the bottom transition layer 41 on the same layer and made of the same material, they can be formed simultaneously in the same patterning process, thus greatly simplifying the display substrate manufacturing process and reducing its manufacturing cost.

[0128] As shown in FIG10, in some embodiments, the display substrate further includes a third gate insulating layer GI3; the sensing active layer includes a sensing channel portion and a sensing conductor portion, the sensing conductor portion being used as the first and second electrodes of the sensing transistor M2, and at least a portion of the third gate insulating layer GI3 being located between the gate of the sensing transistor M2 and the sensing channel portion; the orthographic projection of the third gate insulating layer GI3 on ​​the substrate 10 does not overlap with the orthographic projection of the sensing conductor portion on the substrate 10.

[0129] For example, the orthographic projection of the sensing channel portion on the substrate 10 overlaps with the orthographic projection of the gate of the sensing transistor M2 on the substrate 10. The orthographic projection of the sensing conductor portion on the substrate 10 does not overlap with the orthographic projection of the gate of the sensing transistor M2 on the substrate 10.

[0130] For example, the gate of the sensing transistor M2 is located on the side of the third gate insulating layer GI3 facing away from the substrate 10.

[0131] In the display substrate provided in the above embodiments, by setting the orthographic projection of the third gate insulating layer GI3 on ​​the substrate 10 to not overlap with the orthographic projection of the sensing conductor portion on the substrate 10, the conductor effect of the sensing conductor portion can be improved, thereby enhancing the connection performance between the target functional layer 33 and the top layer transition portion and the bottom layer transition portion.

[0132] As shown in Figures 4, 7, and 8, in some embodiments, the display substrate further includes a third gate insulating layer GI3; the sensing active layer includes a sensing channel portion and a sensing conductor portion, the sensing conductor portion serving as the first and second electrodes of the sensing transistor M2, and at least a portion of the third gate insulating layer GI3 is located between the gate of the sensing transistor M2 and the sensing channel portion; the orthographic projection of the third gate insulating layer GI3 on ​​the substrate 10 covers the orthographic projection of the sensing conductor portion on the substrate 10.

[0133] For example, the third gate insulating layer GI3 is a whole-layer structure covering the substrate 10.

[0134] As shown in Figures 4, 7, 8 and 10, in some embodiments, the display substrate further includes a fifth transition layer 45, which is located on the side of the sensing signal line Sens facing away from the substrate 10, and is coupled to the sensing signal line Sens.

[0135] For example, the fifth transition layer 45 is made of Mo (molybdenum) metal, or a metal stack structure such as Ti / Al / Ti (titanium / aluminum / titanium).

[0136] The fifth adapter layer 45 is configured to bring out the sensing signal line Sens, enabling its coupling with other structures.

[0137] It should be noted that the fifth transition layer 45 is disposed on a different layer from the first source / drain metal layer SD1. The fifth transition layer 45 is also disposed on a different layer from the anode of the light-emitting element. In the above display substrate, by providing an independent fifth transition layer 45, not only can the sensing signal line Sens be led out, but the layout bottleneck problem of the first source / drain metal layer SD1 and the anode film layer can also be overcome.

[0138] This disclosure also provides a method for manufacturing a display substrate, the specific manufacturing process of which is as follows:

[0139] As shown in Figure 11, a light-shielding layer LS, a barrier layer, a first conductive layer (for forming the data line DA), a first buffer layer BUF1, a polysilicon active layer Poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a via connecting the second gate metal layer to the lower layer, a second gate metal layer, a first interlayer insulating layer ILD1, and a second buffer layer BUF2 are sequentially formed on the substrate 10. In this way, the data line DA is placed on the side of the polysilicon active layer Poly facing the substrate 10, which improves the problem of insufficient layout space for the first source / drain metal layer SD1 at high resolution, thereby further improving the resolution of high-resolution display products.

[0140] As shown in Figure 12, the first set of holes, the bottom transition layer 41, and the fourth transition layer 44 are formed. This method further improves the problem of insufficient space for the first source / drain metal layer SD1 at high resolutions, thereby further improving the resolution of high-resolution display products.

[0141] As shown in Figure 13, the metal oxide active layer ACT, the third gate insulating layer GI3, the third gate metal layer and the second interlayer insulating layer ILD2, and the first interconnection hole CNT-L are formed.

[0142] As shown in Figure 14, the second connecting hole CNT-O (including the second set of holes) is then formed.

[0143] As shown in Figure 15, the first source / drain metal layer SD1 was then formed.

[0144] As shown in Figure 8, the first planarization layer PLN1, the fifth transition layer 45, the second planarization layer PLN2, the anode layer, and the pixel delimiting layer PDL are then formed. Further layers such as a light-emitting functional layer, a cathode layer, and an encapsulation layer can be formed subsequently; these layers are not shown in the attached figures.

[0145] This disclosure also provides a display device, including the display substrate provided in the above embodiments.

[0146] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0147] In the display substrate provided in the above embodiment, the target functional layer 33 and non-target functional layers are first connected together through the bottom transition layer 41, and then the target functional layer 33 and the target connection portion 20 are connected together through the top transition layer 42. In this way, all functional layers can be coupled to the target connection portion 20 through the top transition layer 42. Since the top transition layer 42 only needs to be coupled to the target functional layer 33 in the functional layers, the top transition layer 42 only needs to cover the vias between the top transition layer 42 and the target functional layer 33, thereby reducing the number of vias between the top transition layer 42 and the functional layers, reducing the area of ​​the top transition layer 42, and further improving the resolution of the display product while reducing the layout difficulty of the display substrate.

[0148] The display device provided in this disclosure, when including the display substrate provided in the above embodiments, also has the above-mentioned beneficial effects, which will not be repeated here.

[0149] It should be noted that in the display substrate provided in the above embodiments, the function of the second set of holes is to connect the target functional layer 33 and the bottom transition layer 41 together through the top transition layer 42. The size or position of the second set of holes can be appropriately optimized to adjust the contact area between the top transition layer 42, the upper surface of the target functional layer 33, and the bottom transition layer 41, so as to ensure the connection performance of the three. The connection relationship between the top transition layer 42, the upper surface of the target functional layer 33, and the bottom transition layer 41 includes, but is not limited to, the several embodiments mentioned above. Some changes and improvements can be made without departing from the spirit and scope of this disclosure.

[0150] In the display substrate provided in the above embodiments, the number of the first set of vias and the second set of vias is one in each sub-pixel layout area. However, depending on the needs of the display product, multiple similar vias can be added in each sub-pixel layout area to improve the resolution of the display product. Some modifications and improvements can be made without departing from the spirit and scope of this disclosure.

[0151] In the display substrate provided in the above embodiments, the target functional layer 33 can be other transparent metal oxide semiconductor active layers, such as IGTO, IGZYO, etc., or it can be formed by stacking two or more transparent metal oxide semiconductor active layers. The polysilicon active layer Poly in the above embodiments can be replaced with active layers such as IGZO, that is, the IGZO and polysilicon active layer Poly in the embodiments can also be replaced with other active layers. Some changes and improvements can be made without departing from the spirit and scope of this disclosure.

[0152] In the display substrate provided in the above embodiments, the structure (such as data line DA) originally formed by the first source / drain metal layer SD1 can be placed at the bottom or at the top. The purpose is to place the bottom or top structure on a different layer from the first source / drain metal layer SD1, so as to further increase the wiring space of the first source / drain metal layer SD1, thereby further improving the resolution of the high-resolution display product. Some changes and improvements can be made without departing from the spirit and scope of this disclosure.

[0153] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0154] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0155] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0156] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0157] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0158] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0159] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising: A substrate, and at least three functional layers, at least two first transition layers, and a target connection portion, all disposed on the substrate; At least two of the at least three functional layers are stacked sequentially in a direction away from the substrate. The at least three functional layers include a target functional layer, which is the functional layer that is furthest from the substrate among the at least three functional layers. The at least two first transition layers include: a top transition layer and at least one bottom transition layer; The top layer is located on the side of the target functional layer facing away from the substrate, and the top layer is coupled to the target connection portion and the target functional layer respectively. At least a portion of the bottom transition layer is located between the target functional layer and the substrate, and the bottom transition layer is coupled to the target functional layer and at least one non-target functional layer among the at least three functional layers.

2. The display substrate according to claim 1, wherein, The at least three functional layers further include a first functional layer and a second functional layer; at least a portion of the first functional layer is located between the substrate and the second functional layer; the at least two first transition layers include a bottom transition layer; the bottom transition layer is coupled to the first functional layer and the second functional layer respectively.

3. The display substrate according to claim 2, wherein, The first functional layer includes a protruding portion, the orthographic projection of which on the substrate does not overlap with the orthographic projection of the second functional layer on the substrate; The display substrate includes a first sleeve hole, and the bottom transition layer is coupled to the first functional layer and the second functional layer respectively through the first sleeve hole; the target functional layer and the portion of the bottom transition layer outside the first sleeve hole are directly overlapped.

4. The display substrate according to claim 3, wherein, The first set of vias includes a first sub-via and a second sub-via that are interconnected. The first sub-via is located between the second sub-via and the substrate. The diameter of the second sub-via is larger than the diameter of the first sub-via. The bottom transition layer is coupled to the second functional layer through the second sub-via. The bottom transition layer is coupled to the first functional layer through the second sub-via and the first sub-via.

5. The display substrate according to claim 3, wherein, The target functional layer includes a first sub-target functional layer and a second sub-target functional layer stacked together. The first sub-target functional layer is located between the second sub-target functional layer and the substrate. The carrier mobility of the first sub-target functional layer is greater than that of the second sub-target functional layer. The portion of the first sub-target functional layer and the portion of the bottom transition layer located outside the first sleeve hole directly overlaps.

6. The display substrate according to claim 3, wherein, The top-level transition layer is also directly coupled to the bottom-level transition layer.

7. The display substrate according to claim 6, wherein, The display substrate further includes a second set of vias, which in turn includes a third sub-via and a fourth sub-via that are interconnected. The third sub-via is located between the fourth sub-via and the substrate. The aperture of the fourth sub-via is larger than that of the third sub-via. The top layer is coupled to the target functional layer through the fourth sub-via, and the top layer is coupled to the bottom layer through the fourth sub-via and the third sub-via.

8. The display substrate according to claim 3, wherein, The display substrate includes a first source / drain metal layer, and the top transition layer is disposed in the same layer and with the same material as the first source / drain metal layer.

9. The display substrate according to any one of claims 3 to 8, wherein, The display substrate includes a plurality of sub-pixels disposed on the substrate. Each sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit includes a driving transistor, a sensing transistor, and a storage capacitor. The first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the second electrode of the driving transistor, the second electrode of the sensing transistor, and the anode of the light-emitting element, respectively. The first functional layer includes the active layer in the driving transistor, the second functional layer includes the second plate of the storage capacitor, the target functional layer includes the sensing active layer in the sensing transistor, and the target connection includes the anode of the light-emitting element.

10. The display substrate according to claim 9, wherein, In the case where the target functional layer includes a first sub-target functional layer and a second sub-target functional layer stacked together, both the first sub-target functional layer and the second sub-target functional layer are made of transparent metal oxide material.

11. The display substrate according to claim 9, wherein, The display substrate further includes a data line; the sub-pixel driving circuit further includes a data writing transistor, the first terminal of the data writing transistor is coupled to the corresponding data line, and the second terminal of the data writing transistor is coupled to the gate of the driving transistor. The data writing transistor includes a data writing active layer, and the data line is located on the side of the data writing active layer facing the substrate.

12. The display substrate according to claim 11, wherein, The display substrate further includes a light-shielding layer located on the side of the data line facing the substrate.

13. The display substrate according to claim 12, wherein, The display substrate further includes a sensing signal line, a second adapter layer, and a compensation signal line; the first electrode of the sensing transistor is coupled to the corresponding sensing signal line; the sensing signal line is coupled to the corresponding compensation signal line through the corresponding second adapter layer; The compensation signal line is disposed in the same layer and material as the light-shielding layer, and at least a portion of the second transition layer is located between the sensing signal line and the compensation signal line.

14. The display substrate according to claim 11, wherein, The display substrate further includes a light-shielding layer, and the data line is located on the side of the light-shielding layer facing the substrate.

15. The display substrate according to claim 11, wherein, The display substrate also includes a light-shielding layer, and the data line is disposed in the same layer and made of the same material as the light-shielding layer.

16. The display substrate according to claim 11, wherein, The display substrate further includes a second gate metal layer; the sub-pixel driving circuit further includes a third transition layer, the third transition layer being coupled to the portion of the data writing active layer that serves as the first electrode of the data writing transistor, and the data line, respectively; the third transition layer and the second gate metal layer are disposed in the same layer and made of the same material.

17. The display substrate according to claim 11, wherein, The display substrate further includes a fourth transition layer, which is coupled to the portion of the data writing active layer that serves as the second electrode of the data writing transistor and the gate of the driving transistor, respectively; the fourth transition layer and the bottom transition layer are disposed in the same layer and made of the same material.

18. The display substrate according to claim 9, wherein, The display substrate also includes a third gate insulating layer; The sensing active layer includes a sensing channel portion and a sensing conductor portion, the sensing conductor portion being used as a first electrode and a second electrode of the sensing transistor, and at least a portion of the third gate insulating layer being located between the gate of the sensing transistor and the sensing channel portion; The orthographic projection of the third gate insulating layer on the substrate does not overlap with the orthographic projection of the sensing conductor portion on the substrate.

19. The display substrate according to claim 9, wherein, The display substrate also includes a third gate insulating layer; The sensing active layer includes a sensing channel portion and a sensing conductor portion, the sensing conductor portion being used as a first electrode and a second electrode of the sensing transistor, and at least a portion of the third gate insulating layer being located between the gate of the sensing transistor and the sensing channel portion; The orthographic projection of the third gate insulating layer on the substrate covers the orthographic projection of the sensing conductor portion on the substrate.

20. A display device comprising a display substrate as claimed in any one of claims 1 to 19.

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