Level conversion circuit, LIN bus control chip, and micro-processing chip

Abstract

Provided in the present application are a level conversion circuit, an LIN bus control chip, and a micro-processing chip. The level conversion circuit comprises a signal input module, a signal output module, an amplitude limitation module, an inversion module and a delay module, wherein the signal input module is used for receiving an input signal of a communication bus; the signal output module is used for converting the input signal into a digital signal; the amplitude limitation module is connected to the signal input module, and is used for performing pull-down amplitude limitation on the input signal, so as to reduce the amplitude of the input signal; the inversion module is connected to the signal input module, and is used for controlling potential jump points of the input signal; and the delay module is connected to the signal input module, and is used for controlling widths between the potential jump points of the input signal, so as to realize a hysteresis effect. Therefore, attenuation and noise reduction are performed on the input signal by means of the amplitude limitation module, the inversion module and the delay module, so as to provide a stable voltage for an internal circuit of a chip.

Description

Level conversion circuit, LIN bus control chip and microprocessor chip

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on October 26, 2023, with application number 202311408778.1 and application name “Level conversion circuit, LIN bus control chip and microprocessor chip”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of electronic circuits, and in particular to a level conversion circuit, a LIN bus control chip, and a microprocessor chip. Background Art

[0003] The complex nature of automotive operating procedures, often accompanied by the instantaneous release of large currents, leads to significant voltage ripple and noise on automotive communication buses. For example, the LIN communication bus transmits data to the chip via signals on the bus. Ideally, the signal within the chip is a square wave, but in reality, due to coupling and interference, many ripples appear, resulting in an unclean signal.

[0004] How to reduce noise and transmit a clean signal into the chip is a more important issue.

[0005] Summary of the Invention

[0006] The present application provides a level conversion circuit, a LIN bus control chip and a microprocessor chip for processing signals on a communication bus to provide a stable voltage to the internal circuits of the chip.

[0007] In a first aspect, the present application provides a level conversion circuit, the circuit comprising: a signal input module and a signal output module, the signal input module being configured to receive an input signal from a communication bus, the signal output module being configured to convert the input signal into a digital signal, and further comprising: a limiting module, an inversion module, and a delay module;

[0008] The limiting module is connected to the signal input module and is used to pull down and limit the input signal;

[0009] The inversion module is connected to the signal input module and is used to control the potential jump point of the input signal;

[0010] The delay module is connected to the signal input module and the signal output module, and is used to control the voltage width between potential jump points of the input signal.

[0011] Optionally, the limiting module includes a first switch circuit and a plurality of PMOS tubes;

[0012] A first end of the first switch circuit is connected to the output end of the signal input module, a second end of the first switch circuit is connected to the source of each of the PMOS transistors, a gate of each PMOS transistor receives a first bias voltage, and a drain of each PMOS transistor is grounded;

[0013] The first switch circuit is used to control the number of connected PMOS tubes.

[0014] Optionally, the inversion module includes a third switch circuit and a plurality of second NMOS transistors;

[0015] A first end of the third switch circuit is connected to the output end of the signal input module, a second end of the third switch circuit is connected to the drain of each second NMOS transistor, a gate of each second NMOS transistor receives a third bias voltage, and a source of each second NMOS transistor is grounded;

[0016] The third switch circuit is used to control the number of connected second NMOS transistors.

[0017] Optionally, the delay module includes a fourth switch circuit, a second switch circuit and a plurality of first NMOS transistors;

[0018] A first end of the fourth switch circuit is connected to the output end of the signal input module, a second end of the fourth switch circuit is connected to the first end of the second switch circuit, and a third end of the fourth switch circuit is connected to the first output end of the signal output module;

[0019] The second end of the second switch circuit is connected to the drain of each first NMOS transistor, the gate of each first NMOS transistor receives the second bias voltage signal, and the source of each first NMOS transistor is grounded;

[0020] The fourth switch circuit and the second switch circuit are used to control the number of first NMOS transistors connected to the circuit.

[0021] Optionally, the first switch circuit includes a plurality of first control transistors;

[0022] A first end of each first control transistor is connected to the output end of the input signal module, and a second end of each first control transistor is connected to the source of a PMOS transistor;

[0023] The third switch circuit includes a plurality of third control transistors;

[0024] A first end of each of the third control transistors is connected to the output end of the input signal module, and a second end of each of the third control transistors is connected to the drain of a second NMOS transistor.

[0025] Optionally, the second switch circuit includes a plurality of second control transistors;

[0026] A first end of each second control transistor is connected to the fourth switch circuit, and a second end of each second control transistor is connected to the drain of a first NMOS transistor.

[0027] Optionally, the signal input module includes: a resistance module;

[0028] The first end of the resistance module serves as the input end of the signal input module to receive the input signal of the communication bus, and the second end of the resistance module serves as the output end of the signal input module. The resistance module is used to reduce the amplitude of the input signal.

[0029] Optionally, the signal input module includes: a diode;

[0030] The anode of the diode serves as the input end of the signal input module to receive the input signal of the communication bus, and the cathode of the diode serves as the output end of the signal input module. The diode is used to suppress current backflow.

[0031] Optionally, the signal output module includes: an inverter;

[0032] The input end of the inverter serves as the input end of the signal output module and is connected to the output end of the signal input module. The output end of the inverter serves as the first output end of the signal output module.

[0033] Optionally, the signal output module includes: a level shift circuit;

[0034] The input end of the level shift circuit is connected to the output end of the inverter, the output end of the level shift circuit serves as the second output end of the signal output module, and the level shift circuit is used to convert the inverse signal of the input signal into a digital signal.

[0035] In a second aspect, the present application provides a LIN bus control chip, comprising the above-mentioned level conversion circuit.

[0036] In a third aspect, the present application provides a microprocessor chip comprising the above-mentioned level conversion circuit.

[0037] The level conversion circuit, LIN bus control chip and microprocessor chip provided by the present application include a signal input module, a signal output module, a limiting module, an inversion module and a delay module. The signal input module is used to receive the input signal of the communication bus, and the signal output module is used to convert the input signal into a digital signal. The limiting module is connected to the signal input module and is used to pull down the input signal to reduce the amplitude of the input signal. The inversion module is connected to the signal input module and is used to control the potential jump point of the input signal. The delay module is connected to the signal input module and is used to control the width between the potential jump points of the input signal to achieve a hysteresis effect, thereby attenuating and reducing the noise of the input signal through the limiting module, the inversion module and the delay module to provide a stable voltage to the internal circuit of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0039] FIG1 is a schematic structural diagram of a level conversion circuit provided by an embodiment of the present application;

[0040] FIG2 is a circuit diagram of a level conversion circuit provided in an embodiment of the present application;

[0041] FIG3 is a schematic diagram of a transition of an input signal provided in an embodiment of the present application;

[0042] FIG4 is a signal block diagram provided in an embodiment of the present application;

[0043] FIG5 is an equivalent schematic diagram of a level conversion circuit provided in an embodiment of the present application;

[0044] FIG6 is an equivalent schematic diagram of a level conversion circuit provided in another embodiment of the present application;

[0045] FIG7 is a simulation diagram provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0047] As described in the background art, due to the complexity of automobile working links, which are often accompanied by the instantaneous release of large currents, the voltage ripple and noise on the automobile communication bus are extremely large.

[0048] In some embodiments, the voltage on the communication bus may be filtered to reduce voltage ripple and noise on the communication bus.

[0049] However, it can only isolate noise outside of a specific frequency range and cannot suppress noise across the entire frequency band. Furthermore, extremely high or low bus voltages are sent directly to the core components within the integrated circuit, requiring these components to withstand high voltages and increasing the complexity of circuit design. Furthermore, while simple passive filters filter the voltage waveform, they introduce a certain amount of time delay, making it difficult to meet the timing requirements of chip design.

[0050] In response to the above problems, the present application proposes a level conversion circuit, which pulls down and limits the input signal through a limiting module, adjusts the potential jump point of the input signal through an inversion module, and controls the width between the potential jump points of the input signal through a delay module to achieve a hysteresis effect, thereby attenuating and reducing the noise of the input signal on the communication bus through the limiting module, inversion module and delay module.

[0051] The following specific embodiments are used to describe the technical solution of the present application in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0052] FIG1 and FIG2 are schematic diagrams showing the structure of a level conversion circuit provided by an embodiment of the present application. In conjunction with FIG1 and FIG2 , the level conversion circuit provided by this embodiment includes:

[0053] A signal input module 104 and a signal output module 105 , wherein the signal input module 104 is used to receive an input signal Vin from the communication bus, and the signal output module 105 is used to convert the input signal Vin into a digital signal;

[0054] A limiting module 101, an inversion module 103 and a delay module 102;

[0055] The limiter module 101 is connected to the signal input module 104 and is used to pull down and limit the input signal Vin;

[0056] The inversion module 103 is connected to the signal input module 104 and is used to control the potential jump point of the input signal Vin;

[0057] The delay module 102 is connected to the signal input module 104 and the signal output module 105 and is used to control the voltage width between potential transition points of the input signal Vin.

[0058] In the embodiment of the present application, the signal input module 104 includes an input end and an output end. The input end of the signal input module 104 receives an input signal Vin on the communication bus and outputs it through the output end of the signal output module 105 .

[0059] The signal output module 105 includes an input end, a first output end, and a second output end. The input end of the signal output module 105 is connected to the output end of the signal input module 104. The signal output module 105 can convert the signal output by the signal input module 104 into a digital signal to realize analog-to-digital conversion processing of the input signal, and then output the digital signal through the second output end of the signal output module 105.

[0060] The limiting module 101 is connected to the output end of the signal input module 104. The limiting module 101 can pull down the signal output by the signal output module 105, that is, implement pull-down limiting of the input signal. For example, the limiting module 101 may include a first end and a second end, the first end of the limiting module 101 being connected to the output end of the signal input module 104, and the second end of the limiting module 101 being grounded.

[0061] The inversion module 103 is connected to the output end of the signal input module 104. The inversion module 103 can control the potential jump point of the signal output by the signal output module 105, that is, to realize the control of the potential jump point of the input signal. Because when the voltage of the input signal received by the signal input module 104 is very high, the current pulling capability of the inversion module 103 is not enough to keep the signal output by the signal input module 104 at a low voltage, the signal output by the signal input module 104 will jump upward. Therefore, the inversion module 103 can control the point at which the potential of the signal output by the signal output module 105 jumps upward.

[0062] It can be understood that the potential jump point of the input signal Vin refers to the point where the voltage Vt at the output end of the signal input module 104 increases, as shown in Figure 3, which is the point corresponding to VIN_TH+. Since the waveform of the input signal Vin is undulating, that is, the input signal Vin has a high potential and a low potential, the inversion module 103 and the limiting module 101 can both pull down and limit the input signal Vin, that is, pull the current downward. When the voltage of the input signal Vin increases, the inversion module 103 and the limiting module 101 can control the amplitude (maximum value) and the position of the waveform rise of the input signal Vin, where the limiting module 101 controls the amplitude of the input signal Vin, and the inversion module 103 controls the point where the voltage rises (jumps upward).

[0063] For example, the inverting module 103 may include a first end and a second end. The first end of the inverting module 103 is connected to the output end of the signal input module 104 , and the second end of the inverting module 103 is grounded.

[0064] The delay module 102 is connected to the output of the signal input module 104 and the first output terminal Output1 of the signal output module 105. The delay module 102 can control the width between the potential jump points of the signal output by the signal input module 104, that is, control the width (hysteresis voltage) between the point where the potential of the signal jumps upward and the point where the potential jumps downward, so as to achieve control of the voltage width between the potential jump points of the input signal. For example, the delay module 102 includes a first end, a second end, and a third end. The first end of the delay module 102 is connected to the output of the signal input module 104, the second end of the delay module 102 is grounded, and the third end of the delay module 102 is connected to the first output terminal Output1 of the signal output module 105.

[0065] In some embodiments, as shown in FIG2 , the signal input module 104 includes a resistor module 106. The first end of the resistor module 106 serves as the input end of the signal input module 104 and receives the input signal Vin from the communication bus. The second end of the resistor module 106 serves as the output end of the signal input module 104. Since the amplitude of the input signal Vin is very high, but the amplitude required within the chip is lower, for example, the amplitude of the input signal Vin is 0V-42V, and the amplitude required within the chip is 0V-5V, the resistor module 106 can share a portion of the voltage. When the waveform amplitude passes through one or more resistors, it is divided by the resistors, resulting in a smaller waveform amplitude. Thus, the resistor module 106 can be used to reduce the amplitude of the input signal Vin. Because the resistor module 106 can share most of the voltage, the components in the limiter module 101, the inversion module 103, and the delay module 102 can use low-voltage components, reducing the power consumption and area of ​​the level conversion circuit, thereby reducing the complexity of the circuit design. For example, the resistor module 106 may include one or more resistors connected in series, which can be determined based on actual conditions.

[0066] In some embodiments, as shown in FIG2 , the signal input module 104 includes a diode 107, which is used to suppress current backflow. It should be noted that backflow is the flow of current into the chip (IC). Current always flows to a place with low potential, such as a voltage source, which generally outputs current. However, if another power supply exists at the same time and has a higher potential than this power supply, current will flow into this power supply, which is called backflow. Specifically, if the input signal Vin is lower than 0V and the ground terminal is 0V, the voltage of the ground terminal is higher than the voltage on the communication bus. If there is no diode, current backflow will occur. If there is a diode, because it is reverse cutoff, current backflow can be prevented, thereby preventing damage to the device caused by current backflow.

[0067] In some embodiments, as shown in Figure 2, the signal output module 105 includes an inverter 108, the input end of the inverter 108 serves as the input end of the signal output module 105, is connected to the output end of the signal input module 104, and receives the signal output by the signal input module 104. The output end of the inverter 108 serves as the first output end Output1 of the signal output module 105. The inverter 108 is used to reversely process the signal output by the signal input module 104, and output the reverse signal of the signal output by the signal input module 104 through the output end of the inverter 108.

[0068] In some examples, as shown in Figure 2, the signal output module 105 includes a level shift circuit 109, the input end of the level shift circuit 109 is connected to the output end of the inverter 108, and the output end of the level shift circuit 109 serves as the second output end Output2 of the signal output module 105. The level shift circuit 109 is used to perform analog-to-digital conversion on the signal output by the inverter 108, and output a digital signal through the output end of the level shift circuit 109 to convert the inverse signal of the input signal into a digital signal, thereby providing voltage for the internal circuit of the chip.

[0069] In practical applications, the enable terminal of the inverter 108 receives a first enable signal VDD1, and is used to invert the signal output by the signal input module 104 under the control of the first enable signal VDD1. The enable terminal of the level shift circuit 109 receives a second enable signal VDD2, and is used to perform analog-to-digital conversion on the signal output by the inverter 108 under the control of the second enable signal VDD2. In some examples, the voltage of the first enable signal VDD1 is generated by an on-chip module and is substantially equal to (the same as) the voltage Vt at the output terminal of the signal input module 104, so that the inverter 108 can flip normally. In other examples, the voltage of the first enable signal VDD1 can also be generated synchronously by the first bias voltage Voltage_Bias1, the second bias voltage Voltage_Bias2, or the third bias voltage Voltage_Bias3.

[0070] In some embodiments, as shown in FIG2 , the limiting module 101 includes a first switching circuit 1011 and multiple PMOS transistors P. The first end of the first switching circuit 1011 serves as the first end of the limiting module 101 and is connected to the output end of the signal input module 104. The second end of the first switching circuit 1011 is connected to the source of each PMOS transistor P. The gate of each PMOS transistor P receives a first bias voltage, Voltage_Bias1, and the drain of each PMOS transistor P is grounded. The first switching circuit 1011 is used to control the number of connected PMOS transistors P. Once connected, the PMOS transistors P can pull down the current to attenuate the amplitude of the input signal Vin. In this embodiment, there is no need to use a passive filter, which reduces delay and meets the timing requirements of the chip design.

[0071] The amplitude attenuation of the input signal Vin varies depending on the number of PMOS transistors P connected to the limiter module 101. When the input signal Vin increases, the voltage Vt at the output of the signal input module 104 also increases. If the first bias voltage Voltage_Bias1 connected to the gate of the PMOS transistor P remains unchanged, and the voltage Vt at the output of the signal input module 104 is too high, the source-gate voltage Vsg (source voltage Vs minus gate voltage Vg) of the PMOS transistor P will increase. Consequently, the current-sourcing capability of a single PMOS transistor P increases, and the greater the number of PMOS transistors P, the greater the current-sourcing capability.

[0072] Specifically, as shown in FIG4 , when the Vin voltage is low, the effect is not significant. When the Vin voltage is higher, the feedback will be stronger, resulting in the voltage Vt at the output end of the signal input module 104 not being very high, and most of the voltage drop will be reflected on the resistor, thereby avoiding the impact of high voltage on other modules and devices on the chip and simplifying the circuit design.

[0073] The formula in Figure 4 is:

[0074] Among them, f(V t ) represents the on-state current of the transistor; μ p C ox represents electron mobility; W / L represents the ratio of the width to the length of the transistor; V t Represents the source voltage; V g Represents the gate voltage; V THP Indicates the threshold voltage.

[0075] In practical applications, the number of connected PMOS transistors P can be determined according to actual conditions, so that the waveform of the input signal Vin can be adjusted as needed. The first bias voltage Voltage_Bias1 can be provided by a current mirror, or by a diode or resistor.

[0076] For example, the first switch circuit 1011 may use a trimming circuit to flexibly control the number of connected PMOS transistors, thereby flexibly controlling the voltage reduction amplitude.

[0077] As an implementation, the first switch circuit 1011 may include multiple first control transistors, wherein a first end of each first control transistor is connected to the second end of the resistor module 104, and a second end of each first control transistor is connected to the source of a PMOS transistor P. By controlling the first control transistors to be turned on or off, the number of connected PMOS transistors P is controlled.

[0078] In some embodiments, the inversion module 103 includes a third switch circuit 1031 and multiple second NMOS transistors N2. The first end of the third switch circuit 1031 serves as the first end of the inversion module 103 and is connected to the output end of the signal input module 104. The second end of the third switch circuit 1031 is connected to the drain of each second NMOS transistor N2. The gate of each second NMOS transistor N2 receives a third bias voltage Voltage_Bias3, and the source of each second NMOS transistor N2 is grounded. The third switch circuit 1031 is used to control the number of second NMOS transistors N2 connected to the circuit. After the second NMOS transistor N2 is connected to the circuit, it can pull down the current, thereby controlling the potential jump point of the input signal Vin. In actual applications, the number of second NMOS transistors N2 connected can be determined as needed. Different numbers of connected NMOS transistors will result in different signal jump times.

[0079] As an implementation, the third switch circuit 1031 may include multiple third control transistors, with a first end of each third control transistor connected to the output end of the signal input module 104, and a second end of each third control transistor connected to the drain of a second NMOS transistor N2. By controlling the third control transistors to be turned on or off, the number of connected second NMOS transistors is controlled.

[0080] In some embodiments, the delay module 102 includes a fourth switch circuit 1022, a second switch circuit 1021 and multiple first NMOS transistors N1. The first end of the fourth switch circuit 1022 serves as the first end of the delay module 102 and is connected to the output end of the input signal module. The third end of the fourth switch circuit 1022 serves as the third end of the delay module 102 and is connected to the first output end of the signal output module 105. The second end of the fourth switch circuit 1022 is connected to the first end of the second switch circuit 1021. The second end of the second switch circuit 1021 is connected to the drain of each first NMOS transistor N1. The gate of each first NMOS transistor N1 receives the second bias voltage Voltage_Bias2. The source of each first NMOS transistor N1 is grounded. The second switch circuit 1021 controls the number of first NMOS transistors N1 connected to the circuit. The fourth switch circuit 1022 and the second switch circuit 1021 can control whether the delay circuit is in a connected state. Specifically, the second switch circuit 1021 can only work after the fourth switch circuit 1022 is turned on. Therefore, after the fourth switch circuit 1022 and the second switch circuit 1021 are turned on, the delay module 102 is in a connected state.

[0081] In addition, since the waveform of the input signal Vin is undulating, the signal output by the first output terminal of the signal output module 105 has a high level and a low level, so the fourth switch circuit 1022 is sometimes turned on and sometimes turned off, that is, the delay module 102 is sometimes turned on and sometimes turned off, while the limiting module 101 and the inversion module 103 are controlled by a separate control circuit and can be always turned on. Then, the pull-down capability of the delay module 102 is weaker than the pull-down capability of the inversion module 103, thereby achieving a hysteresis effect and determining the hysteresis voltage, such as VIN_TH- in Figure 2.

[0082] For example, when the level at the output end of the signal input module 104 is 1, the level output by the first output end of the signal output module 105 is 0, and the level of the input to the delay module 102 connected to the fourth switch circuit 1022 is also 0, so the delay module 102 will not be turned on, and at this time only the limiting module 101 and the inversion module 103 will work; if the level at the output end of the signal input module 104 is 0, the level output by the first output end of the signal output module 105 is 1, and the signal input to the delay module 102 is also 1, and the delay module 102 will be turned on, thereby realizing the hysteresis effect.

[0083] In practical applications, the number of connected first NMOS transistors N1 can be determined as needed. Different numbers of connected first NMOS transistors N1 result in different widths between the high potential jump point and the low potential jump point of the signal.

[0084] As an implementation, the second switch circuit 1021 may include multiple second control transistors, with a first end of each second control transistor connected to the fourth switch circuit 1022, and a second end of each second control transistor connected to the drain of a first NMOS transistor N1. By controlling the second control transistors to be turned on or off, the number of connected first NMOS transistors is controlled.

[0085] In practical applications, if the resistance module 104 can share most of the voltage, the PMOS transistor P in the limiting module 101, the first NMOS transistor N1 in the delay module 102, and the second NMOS transistor N2 in the inversion module 103 can use low-voltage devices to reduce the power consumption and area of ​​the level conversion circuit 107.

[0086] To facilitate understanding of the beneficial effects of this embodiment, a small signal analysis is performed on the adjustment circuit provided in this embodiment. Part of the PMOS transistor in the first circuit can be equivalent to other circuits to facilitate analysis of the effects. The analysis is as follows:

[0087] When the amplitude of the input signal Vin is high, the current mirror tube and the PMOS tube are all saturated. The equivalent diagram of the level conversion circuit is shown in Figure 5. The calculation formula is as follows:

[0088] Among them, ro1 is the impedance of the NMOS tube and the PMOS tube P in parallel, g m is the transconductance of the PMOS transistor P, and C is the parasitic capacitance at the output end of the signal input module. The NMOS transistor includes a first NMOS transistor and a second NMOS transistor.

[0089] Therefore, the size of the resistor determines the gain of the attenuation.

[0090] When the amplitude of the input signal Vin is low, the current mirror tube and PMOS are not saturated. The equivalent diagram of the level conversion circuit is shown in Figure 6. The calculation formula is as follows:

[0091] Where r is the on-resistance in the linear region.

[0092] The level of the input signal Vin is usually from 0-40V, which determines that the MOS tube is sometimes saturated and sometimes linear. Therefore, if the linear recognition model is used directly, the state needs to be judged in segments.

[0093] If the voltage is too low, the PMOS may enter the linear region, which is equivalent to a small resistor, so the low level also has an attenuation effect.

[0094] If the voltage is high, then in the saturation region, a linear identification model g is required. m v t(KΩ level) and ro1 (MΩ level), only considering the capacitance, the saturation region model also has an attenuation effect.

[0095] To further understand the beneficial effects of this solution, a circuit simulation test was conducted. The simulation results are shown in Figure 7. In Figure 7, the lower curve is the digital signal, and the upper curve is the adjusted signal. The adjusted signal is relatively clean, and the digital module within the chip processes it without errors, such as misinterpretation or bit errors. Furthermore, as shown in Figure 7, the input signal Vin is accompanied by significant noise, but the output signal has minimal noise and is free of misinterpretation. This effectively attenuates ripple disturbances on the bus.

[0096] The level conversion circuit provided in the present application is described in detail above. An embodiment of the present application further provides a LIN bus control chip, including the above-mentioned level conversion circuit.

[0097] An embodiment of the present application further provides a microprocessor chip, comprising the above-mentioned level conversion circuit.

[0098] Optionally, the microprocessor chip can be a micro central control chip or system-on-chip chip such as MCU, DSP, MPU, micro CPU, etc. that can process digital signals, analog signals, or perform signal control functions, instruction processing and calculation functions.

[0099] Finally, it should be noted that the above embodiments are intended only to illustrate the technical solutions of this application and are not intended to limit them. Although this application has been described in detail with reference to the aforementioned embodiments, those skilled in the art will appreciate that they may modify the technical solutions described in the aforementioned embodiments or replace some or all of the technical features therein with equivalents. However, such modifications or replacements do not deviate from the essence of the corresponding technical solutions within the scope of the various embodiments of this application.

Claims

1. A level conversion circuit, the circuit comprising: A signal input module and a signal output module, wherein the signal input module is used to receive an input signal of a communication bus, and the signal output module is used to convert the input signal into a digital signal, wherein the module further includes: a limiting module, an inversion module and a delay module; The limiting module is connected to the signal input module and is used to perform pull-down limiting on the input signal; The inversion module is connected to the signal input module and is used to control the potential jump point of the input signal; The delay module is connected to the signal input module and the signal output module, and is used to control the voltage width between the potential jump points of the input signal.

2. The circuit according to claim 1, wherein The limiting module includes a first switch circuit and a plurality of PMOS tubes; A first end of the first switch circuit is connected to the output end of the signal input module, a second end of the first switch circuit is connected to the source of each of the PMOS tubes, a gate of each PMOS tube receives a first bias voltage, and a drain of each PMOS tube is grounded; The first switch circuit is used to control the number of connected PMOS tubes.

3. The circuit according to claim 2, wherein: The inversion module includes a third switch circuit and a plurality of second NMOS tubes; The first end of the third switch circuit is connected to the output end of the signal input module, the second end of the third switch circuit is connected to the drain of each second NMOS tube, the gate of each second NMOS tube receives the third bias voltage, and the source of each second NMOS tube is grounded; The third switch circuit is used to control the number of connected second NMOS transistors.

4. The circuit according to any one of claims 1 to 3, wherein: The delay module includes a fourth switch circuit, a second switch circuit and a plurality of first NMOS tubes; A first end of the fourth switch circuit is connected to the output end of the signal input module, a second end of the fourth switch circuit is connected to the first end of the second switch circuit, and a third end of the fourth switch circuit is connected to the first output end of the signal output module; The second end of the second switch circuit is connected to the drain of each first NMOS tube, the gate of each first NMOS tube receives the second bias voltage signal, and the source of each first NMOS tube is grounded; The fourth switch circuit and the second switch circuit are used to control the number of first NMOS tubes connected to the circuit.

5. The circuit according to claim 3, wherein: The first switch circuit includes a plurality of first control transistors; A first end of each of the first control transistors is connected to the output end of the input signal module, and a second end of each of the first control transistors is connected to the source of a PMOS tube; The third switch circuit includes a plurality of third control transistors; A first end of each of the third control transistors is connected to the output end of the input signal module, and a second end of each of the third control transistors is connected to the drain of a second NMOS tube.

6. The circuit according to claim 4, wherein: The second switch circuit includes a plurality of second control transistors; A first end of each second control transistor is connected to the fourth switch circuit, and a second end of each second control transistor is connected to a drain of a first NMOS tube.

7. The circuit according to any one of claims 1 to 6, wherein: The signal input module includes: a resistance module; The first end of the resistor module serves as the input end of the signal input module to receive the input signal of the communication bus, and the second end of the resistor module serves as the output end of the signal input module. The resistor module is used to reduce the amplitude of the input signal.

8. The circuit according to any one of claims 1 to 6, wherein: The signal input module includes: a diode; The anode of the diode serves as the input end of the signal input module to receive the input signal of the communication bus, and the cathode of the diode serves as the output end of the signal input module. The diode is used to suppress current backflow.

9. The circuit according to any one of claims 1 to 6, wherein: The signal output module comprises: an inverter; The input end of the inverter serves as the input end of the signal output module and is connected to the output end of the signal input module. The output end of the inverter serves as the first output end of the signal output module.

10. The circuit according to claim 9, wherein: The signal output module comprises: a level shift circuit; The input end of the level shift circuit is connected to the output end of the inverter. The output end of the circuit serves as the second output end of the signal output module, and the level shift circuit is used to convert the inverse signal of the input signal into a digital signal.

11. A LIN bus control chip, wherein: A level conversion circuit comprising any one of claims 1 to 10.

12. A microprocessor chip, wherein: A level conversion circuit comprising any one of claims 1 to 10.

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