Processor fetch redirection timing optimization circuit

Abstract

Disclosed is a processor fetch redirection timing optimization circuit, comprising a redirection distributor, a first selector, a second selector, an expected register, a bus packaging unit, a bus register, an address increment unit, a sequence register, and a comparison module. Redirected fetch is optimized by means of using an optimization policy of independently using or using, in combination, part of a redirection request and part of address data. The redirection distributor outputs a first recombination signal to the first selector and outputs a second recombination signal to the second selector. The first selector is connected to the expected register, the second selector is connected to the bus packaging unit, and the comparison module is used to separately compare expected data and bus data, to determine, on the basis of a comparison result, whether the sequence register needs to be restored, so as to ensure the accuracy of data in a timing optimization process. The circuit of the present invention is simple, has strong extensibility and good versatility, and also has good capabilities and timing performance.

Description

A processor instruction fetch redirection timing optimization circuit Technical Field

[0001] The present invention belongs to the technical field of processors, and in particular relates to a processor instruction fetch redirection timing optimization circuit. Background Art

[0002] The instruction fetch module (IFM) sits at the front end of the modern processor pipeline, primarily responsible for prefetching program instructions from memory into the instruction register. Instruction fetches don't always access sequential addresses; they also need to quickly respond to various redirection requests from downstream pipeline stages, such as program branches, interrupt requests, exception requests, and debug requests. Furthermore, the IFM decodes addresses and generates control signals, such as chip select and cacheability signals. Some application processors also need to translate virtual addresses into physical addresses. These control / address signals are connected to the system bus interconnect and, after arbitration, to the corresponding memory interfaces with other system modules. As can be seen above, the IFM must accept redirection requests from downstream pipeline stages, requiring rapid instruction fetches. Furthermore, it must connect to the system bus interconnect, requiring good bus signal timing, which is crucial for system power, performance, and area convergence. IFM designers often face a trade-off between timing and performance: better timing comes at the expense of performance, while better performance comes at the expense of worse timing and increased area. Therefore, the performance and timing of the instruction fetch module play a vital role in the entire processor architecture and system memory architecture.

[0003] Summary of the Invention

[0004] Purpose of the invention: In order to solve the problem in the prior art that it is difficult to achieve both performance and timing in a processor instruction fetch module, the present invention provides a processor instruction fetch redirection timing optimization circuit.

[0005] Technical solution: A processor instruction fetch redirection timing optimization circuit, including a redirection distributor, a first selector, a second selector, a desired register, a bus encapsulation unit, a bus register, an address increment unit, a sequence register, and a comparison module;

[0006] The redirection distributor inputs a CPU redirection request signal, and an output end of the redirection distributor outputs a first recombined signal to the first selector and outputs a second recombined signal to the second selector;

[0007] The input end of the sequence register is connected to the two-to-one selector, and the output end is connected to the first selector, the second selector and the bus encapsulation unit;

[0008] The input end of the expectation register is connected to at least the output end of the first selector, the expectation register is used to receive the complete expected address bit, and the output end of the expectation register is connected to the comparison module and the one-of-two selector;

[0009] The input end of the bus encapsulation unit is connected to the output end of the second selector and the output end of the sequence register, the output end of the bus encapsulation unit is connected to the bus register and the address increment unit, the output end of the bus register is connected to the comparison module, the output end of the address increment unit is connected to the two-to-one selector, and the bus encapsulation unit sends the signal to the system bus matrix;

[0010] The output end of the comparison module is connected to the signal selection end of the two-choice selector;

[0011] The CPU redirection request signal, the first reassembly signal, and the second reassembly signal are all array structures. The array sizes of the CPU redirection request signal, the first reassembly signal, and the second reassembly signal are n0, n1, and n2, respectively. n0, n1, and n2 represent the number of types of redirection requests, and n0=n1. Each set of data in the CPU redirection request signal includes a redirection enable bit, a redirection address high bit, and a redirection address low bit. Each set of data in the first reassembly signal includes at least a redirection enable bit and a redirection address high bit. Each set of data in the second reassembly signal includes at least a redirection enable bit and a redirection address low bit. At least one of the following conditions is met:

[0012] (1) Each group of data in the second reorganized signal does not contain the high bit of the redirection address;

[0013] (2)n2<n0.

[0014] Furthermore, when the satisfied condition includes (1), the signal transmitted by the sequence register to the second selector only includes the lower bits of the sequence address; the output end of the sequence register is also connected to the bus encapsulation unit for providing the higher bits of the sequence address to the bus encapsulation unit.

[0015] Furthermore, each group of data in the first reorganized signal also includes a redirected address low bit; the signal transmitted by the sequential register to the first selector includes a sequential address high bit and a sequential address low bit, and the first selector is used to provide a complete expected address bit for the expected register, including an expected address high bit and an expected address low bit.

[0016] Furthermore, when only condition (2) is satisfied, each set of data in the second reorganized signal includes a redirection enable bit, a redirection address high bit, and a redirection address low bit, and the signal transmitted from the sequence register to the second selector includes a sequence address high bit and a sequence address low bit.

[0017] Furthermore, each group of data in the first reorganized signal does not include the low bit of the redirected address; the signal transmitted by the sequential register to the first selector only includes the high bit of the sequential address, and the first selector is used to provide the high bit of the expected address for the expected register; the output end of the second selector is also connected to the expected register, and is used to provide the low bit of the expected address for the expected register.

[0018] Furthermore, the output end of the sequence register is also connected to the bus encapsulation unit, for providing the high bits of the sequence address to the bus encapsulation unit.

[0019] Furthermore, the comparison module includes a control comparison unit and an address comparison unit.

[0020] Furthermore, the expectation register includes an expectation control generator and an expectation address register, the output end of the first selector is connected to the expectation address register, the output end of the expectation address register is connected to the input end of the address comparison unit and the input end of the expectation control generator, the CPU configuration information is input from the expectation control generator, the expectation control generator is used to generate required expected control bit data according to the expected address data and the CPU configuration information, and the output end of the expectation control generator is connected to the input end of the control comparison unit;

[0021] The bus register includes a bus control register and a bus address register, the input end of the bus control register and the input end of the bus address register are connected to the bus encapsulation unit, and the output end of the bus control register and the output end of the bus address register are respectively connected to the input end of the control comparison unit and the input end of the address comparison unit.

[0022] Furthermore, the sequential register includes a sequential control register and a sequential address register, and the input ends of the sequential control register and the sequential address register are each connected to a two-to-one selector; the first input end of the two-to-one selector connected to the sequential control register is connected to the output end of the sequential control register, and the second input end is connected to the output end of the expected control generator; the output end of the sequential control register is connected to the bus encapsulation unit; the first input end of the two-to-one selector connected to the sequential address register is connected to the output end of the address increment unit, and the second input end is connected to the output end of the expected address register; the output end of the sequential address register is connected to the first selector and the second selector.

[0023] Furthermore, the bus encapsulation unit is used to receive signals output by the sequence register and the second selector, assemble them into bus control bits and bus address bits, transmit the bus control bits to the bus control register, and transmit the bus address bits to the bus address register.

[0024] Compared with the prior art, the processor instruction fetch redirection timing optimization circuit provided by the present invention has the following beneficial effects:

[0025] The timing optimization circuit has a simple structure, strong scalability and good versatility; it uses optimized branches to select partial redirection requests and / or partial address bit data instead of selecting complete data, which can speed up the redirection response speed to a certain extent. When encountering a redirection request, the processor can respond quickly and have good performance; a comparison mechanism is designed to compare bus data with expected data to prevent errors when selecting partial data. In the case of inconsistent data, it will be restored to the expected data to ensure that the system can run correctly; the timing performance is good, which has a positive impact on system power consumption and area convergence; it can take into account both good performance and timing. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG1 is a schematic diagram of the structure of a processor value redirection timing optimization circuit according to an embodiment of the present invention;

[0027] FIG2 is a schematic diagram of the structure of a processor value redirection timing optimization circuit according to a second embodiment;

[0028] FIG3 is a schematic diagram of the structure of a processor value redirection timing optimization circuit according to a third embodiment;

[0029] FIG4 is a timing diagram of an example of redirection without recovery in Example 3;

[0030] FIG5 is a timing diagram of a redirection recovery example according to the third embodiment. DETAILED DESCRIPTION

[0031] The present invention will be further explained below with reference to the accompanying drawings and specific embodiments.

[0032] Embodiment 1: The optimization branch adopts the optimization strategy of complete redirection request + partial address data.

[0033] As shown in FIG1 , a processor instruction fetch redirection timing optimization circuit includes a redirection distributor, a first selector, a second selector, a desired register, a bus encapsulation unit, a bus register, an address increment unit, a sequence register, and a comparison module;

[0034] The input end of the redirection distributor inputs the CPU redirection request signal, and the output end of the redirection distributor outputs the first recombined signal to the first selector and outputs the second recombined signal to the second selector.

[0035] The input end of the sequence register is connected to a two-choice selector, and the output end is connected to a first selector, a second selector, and a bus encapsulation unit. The sequence register includes a sequence control register and a sequence address register, and the input ends of the sequence control register and the sequence address register are each connected to a two-choice selector. The first input end of the two-choice selector connected to the sequence control register is connected to the output end of the sequence control register, and the second input end is connected to the output end of the expected control generator; the output end of the sequence control register is connected to the bus encapsulation unit; the first input end of the two-choice selector connected to the sequence address register is connected to the output end of the address increment unit, and the second input end is connected to the output end of the expected address register; the output end of the sequence address register is connected to the first selector and the second selector. The signal selection ends of the two two-choice selectors are both connected to the output end of the comparison module. The comparison module obtains a signal whether it is consistent by comparing the address and control bit data. If the comparison result is consistent, the sequence signal is output, and the two-choice selector selects the data at the first input end to be stored in the sequence register; if the comparison result is inconsistent, the recovery signal is output, and the two-choice selector selects the data at the second input end to be stored in the sequence register, that is, the data from the expected register. The sequential address register transmits the low-order address data to the second selector. At this point, the signal transmitted by the sequential register to the second selector contains only the low-order bits of the sequential address. The output of the sequential register is also connected to the bus encapsulation unit to provide the high-order bits of the sequential address to the bus encapsulation unit. For example, if the sequential address has a total of 32 bits, the high-order bits of the sequential address are the upper 12 bits of data, and the low-order bits of the sequential address are the lower 20 bits of data.

[0036] The expected register includes an expected control generator and an expected address register. The output of the first selector is connected to the expected address register. The output of the expected address register is connected to the input of the address comparison unit and the input of the expected control generator. The CPU configuration information is input from the expected control generator. The expected control generator is used to generate the required expected control bit data based on the expected address data and the CPU configuration information after decoding and comparison and other combinational logic. The output of the expected control generator is connected to the input of the control comparison unit. The input of the expected register is at least connected to the output of the first selector. The signal received by the expected register needs to be a complete expected address, including the high bit of the expected address and the low bit of the expected address. Therefore, if the sequential register transmits only the high bit address to the first selector, because the first selector can only provide the high bit address for the expected register, the expected register also needs to be connected to the second selector, and the second selector provides the low bit address. The output of the expected register is connected to the comparison module and the second input of the two selectors.

[0037] The input of the bus encapsulation unit is connected to the output of the second selector and the output of the sequence register. The output of the bus encapsulation unit is connected to the bus register and the address increment unit. The output of the bus register is connected to the comparison module. The output of the address increment unit is connected to the first input of the two-selector selector connected to the sequence address register. The bus encapsulation unit is used to receive the sequence control bit transmitted by the sequence control register, the sequence address high bit directly provided by the sequence register, and the sequence address low bit output by the second selector. It assembles the sequence control bit, the sequence address high bit, and the desired address low bit together to form the bus control bit and the bus address bit, and outputs the bus control bit to the bus control register and the bus address bit to the bus address register and the address increment unit. The bus encapsulation unit sends the signal to the system bus matrix (not shown).

[0038] The bus register includes a bus control register and a bus address register, the input end of the bus control register and the input end of the bus address register are connected to the bus encapsulation unit, and the output end of the bus control register and the output end of the bus address register are respectively connected to the input end of the control comparison unit and the input end of the address comparison unit.

[0039] The output of the comparison module is connected to the signal selection terminal of the two-choose-one selector. The comparison module compares the data in the desired register with the data in the bus register. Based on whether the comparison is consistent, it determines whether to restore the selected data, ensuring the correct data after the optimized branch selection. The comparison module includes a control comparison unit and an address comparison unit. The control comparison unit compares the data in the desired control generator with the data in the bus control register, while the address comparison unit compares the data in the desired address register with the data in the bus address register.

[0040] Among them, the CPU redirection request signal, the first reorganization signal, and the second reorganization signal are all array structures. Let the array sizes of the CPU redirection request signal, the first reorganization signal, and the second reorganization signal be n0, n1, and n2 respectively, where n0, n1, and n2 represent the number of types of redirection requests, and n0=n1. Each set of data in the CPU redirection request signal includes a redirection enable bit, a high bit of the redirection address, and a low bit of the redirection address. Each set of data in the first reorganization signal includes at least a redirection enable bit and a high bit of the redirection address; each set of data in the second reorganization signal includes a redirection enable bit and a low bit of the redirection address, and does not include a high bit of the redirection address. For example, the redirection address has a total of 32 bits, the high bit of the redirection address is the upper 12 bits of data, and the low bit of the redirection address is the lower 20 bits of data. In Figures 1 to 3, mark 12 represents the upper 12 bits of the address, and mark 20 represents the lower 20 bits of the address.

[0041] The first reorganized signal may or may not include the redirection address low bit. When the redirection address low bit is included, the signal transmitted by the sequence register to the first selector includes the sequence address high bit and the sequence address low bit. In this case, the output end of the first selector is connected to the desired register, providing the desired address high bit and the desired address low bit to the desired register, but this method is redundant. When the first reorganized signal does not include the redirection address low bit, the signal transmitted by the sequence register to the first selector only includes the sequence address high bit. The first selector only provides the desired address high bit to the desired register. In this case, the second selector also needs to be connected to the desired register, and the second selector provides the desired address low bit to the desired register. Compared with the former, the latter is more preferable.

[0042] Because the critical path of the redirected address often comes from the addition circuit, the high-order address is affected by the carry chain and has a greater delay than the low-order address. However, in most cases, the redirected high-order address will not change. In this circuit structure, only the low-order address data is used in the selection, and the high-order address data is avoided. This can reduce the output delay to a certain extent, so that the redirected request can be responded to more quickly. However, when the comparison results obtained by the comparison module are inconsistent, it means that the high-order address data and / or control bits have changed, so the optimized branch selection cannot continue. It is necessary to restore the correct address data and / or control bit data from the desired register to the second selector and re-initiate access to the bus to ensure data correctness.

[0043] The main functions of each module are:

[0044] (1) Sequential address register

[0045] This register contains the high-order address data and low-order address data of the sequential fetch. During sequential prefetch, it is updated with the output value of the address increment module; when information is restored, it is updated with the output value of the expected address register (S1 expected address bit);

[0046] (2) Sequence Control Register

[0047] This register includes but is not limited to chip select, cacheable, protection and other control information. It remains unchanged during sequential prefetching; when the information is restored, it is updated to the output value of the expected control generator (S1 expected control bit);

[0048] (3) Expected Address Register

[0049] The D end (input end) of this register is connected to the output address of the first selector (S0 expected address bit, including address high bit and address low bit), and sometimes it is also connected to the output end of the second selector (the first selector provides address high bit, and the second selector provides address low bit). It is controlled by the pipeline handshake signal, registered on the rising edge of the clock (CLOCK), and output to the Q end (S1 expected address bit).

[0050] (4) Expected Control Generator

[0051] This module generates the required control information (S1 expected control bit) based on the expected address register and CPU configuration information after decoding, comparison and other combinational logic.

[0052] (5) Bus address register

[0053] The D end (input end) of this register is connected to the address signal of the bus encapsulation unit (S0 bus address bit, including high and low bits), controlled by the pipeline handshake signal, registered on the rising edge of the clock (CLOCK), and output to the Q end (S1 bus address bit).

[0054] (6) Bus Control Register

[0055] The D end (input end) of this register is connected to the control signal of the bus encapsulation unit (S0 bus control bit), which ultimately comes from the output signal of the sequence control register, is controlled by the pipeline handshake signal, is registered on the rising edge of the clock (CLOCK), and output to the Q end (S1 bus control bit).

[0056] (7) Redirect Distributor

[0057] The input of this module is the enable and address signals of all redirection requests in the CPU. A reorganization signal is generated according to the allocation strategy. The reorganization signal contains the corresponding selection, enable and address signals, and the reorganization signal is distributed to the first selector and the second selector. The array size of the first reorganization signal distributed to the first selector is consistent with the array size of the CPU redirection request, and it must include all redirection requests. Each set of data includes at least the redirection enable bit and the redirection address high bit, and may also include the redirection address low bit, which is used to subsequently generate the correct expected address signal to the expected register. In the array of the second reorganization signal distributed to the second selector, each set of data only contains the redirection enable bit and the redirection address low bit, and does not contain the redirection address high bit, and the array size of the second reorganization signal is the same as that of the first reorganization signal.

[0058] (8) First selector

[0059] This module is a multiplexer that receives all redirection request enable and complete redirection address information from the redirection distributor, as well as at least the high-order address information provided by the sequential address register. After priority selection, it can provide at least the high-order address information for the expected register and send it to the D terminal (input terminal) of the expected address register (EXP_ADDR). If there is no redirection request at this time, the output value of this module is the address data provided by the sequential address register. If the sequential address register only provides the high-order address for the first selector, the output value of this module is only the high-order address data.

[0060] (9) Second selector

[0061] This module is a multiplexer that receives all redirection request enable and redirection address low bits (no redirection address high bits) from the redirection distributor, as well as the sequence address low bits from the sequence address register. After priority selection, it outputs the low-order address data to the bus encapsulation unit. If there is no redirection request, the module outputs the sequence address low bits provided by the sequence address register.

[0062] (10) Bus encapsulation unit

[0063] The high-order address data of the sequential address register, the low-order address data of the second selector, and the sequential control bit data of the sequential control register are received and, after simple encapsulation, form a bus signal (BUS) which is sent to the address increment module, the bus address register, and the bus control register, and at the same time to the system's bus interconnection matrix (not shown in the figure).

[0064] (11) Address increment module

[0065] This module receives the complete bus address information assembled by the bus encapsulation unit (the concatenation of the high-order address information of the sequential address register and the low-order address data of the second selector) and generates the address signal for the next instruction based on constraints such as the instruction width and alignment. This module is generally an addition circuit for the bus address signal and a constant.

[0066] (12) Comparison module

[0067] This module is used to compare the expected data with the bus data for consistency, including comparing the expected address register with the bus address register, and comparing the output values ​​of the expected control generator with the bus control register. If the address and control bit data are consistent, the optimized bus instruction fetch is considered valid, and the bus return data and the relevant address and control information of this stage can be sent to the subsequent pipeline stage. Otherwise, the optimized bus instruction fetch is considered invalid, an S1 recovery request is generated, and the data of the expected address register is restored to the sequential address register, the data of the expected control generator is restored to the sequential control register, and the bus access is re-initiated.

[0068] Embodiment 2: The optimization branch adopts the optimization strategy of partial redirection request + complete address data.

[0069] Compared to the first embodiment, the second embodiment differs in that each set of data in the second reorganization signal includes a redirection enable bit, a redirection address low bit, and a redirection address high bit. However, the array size n2 of the second reorganization signal is smaller than the array size n1 of the first reorganization signal (or the CPU redirection request signal n0).

[0070] In terms of the connection relationship, as shown in Figure 2, the sequential address register transmits the complete sequential address (including the high order address and the low order address) data to the first selector and the second selector. The address data received by the bus encapsulation unit are all provided by the second selector. At this time, the sequential address register does not need to be connected to the bus encapsulation unit. The address data received by the bus encapsulation unit can also be directly provided by the sequential address register with the high order address, and the low order address is provided by the second selector. At this time, the sequential address register needs to be connected to the bus encapsulation unit. The first reorganization signal contains the complete redirection enable bit, the low order redirection address, and the high order redirection address. The expected address sources of subsequent expected registers all come from the first selector.

[0071] This embodiment uses partial redirection to participate in the selection process, reducing the fan-in of the multiplexer and, to a certain extent, minimizing output latency. For example, consider the five common redirection requests in a system: reset request, debug request, interrupt request, branch prediction request, and misprediction request. Reset and debug requests do not require fast instruction fetches, meaning they are infrequent and insensitive to latency. In contrast, interrupt requests, branch prediction requests, and misprediction requests require fast instruction fetches, meaning they are frequent and sensitive to latency. Therefore, redirection requests requiring fast instruction fetches can be selected in the second selector, while the first selector still selects all redirection requests. If the actual redirection request requires fast instruction fetches, the second selector can be used to select it directly. Because the number of redirection requests selectable in the second selector is smaller than that in the first selector, selecting through the second selector results in a faster response. This is manifested in the array sizes of the CPU redirection request signal, the first reassembly signal, and the second reassembly signal, n0, n1, and n2, respectively. n0, n1, and n2 represent the number of redirection request types, such that n0 = n1 > n2. If the actual redirection request doesn't require fast instruction fetch, then the redirection request selected by the second selector is necessarily incorrect, and the comparison module's comparison result is inconsistent. The expected register is then used to restore the data in the sequential register, ensuring that the data in the second selector comes from the expected register, which is the actual correct data. The bus is then accessed again to ensure data correctness. Overall, this method achieves fast instruction fetch while ensuring correctness.

[0072] The main functions of each module are:

[0073] (1) The sequence address register, sequence control register, expected control generator, bus address register, bus control register, and comparison module are the same as those in the first embodiment.

[0074] (2) Expected Address Register

[0075] The D end (input end) of this register is connected to the output address of the first multiplexer (S0 expected address bit, including high and low bits), is controlled by the pipeline handshake signal, is registered on the rising edge of the clock (CLOCK), and is output to the Q end (S1 expected address bit).

[0076] (3) Redirect Distributor

[0077] The input of this module is the enable and address signals of all redirection requests in the CPU. A reorganization signal is generated according to the allocation strategy. The reorganization signal contains the corresponding selection, enable and address signals, and the reorganization signal is distributed to the first selector and the second selector. The array size of the first reorganization signal distributed to the first selector is consistent with the array size of the CPU redirection request, that is, n0=n1. It must include all redirection requests and include the complete redirection address (high bit, low bit) for the subsequent generation of the correct expected address signal to the expected register. Each set of data in the second reorganization signal contains the redirection enable bit, the redirection address low bit, and the redirection address high bit. However, the array size of the second reorganization signal distributed to the second selector is smaller than the array size of the first reorganization signal, that is, n2<n1 (or the array size n0 of the CPU redirection request).

[0078] (4) First selector

[0079] This module is a multiplexer that receives the first reassembled data from the redirection distributor and the complete sequential address provided by the sequential address register. After priority selection, it outputs the complete address signal to the D terminal (input terminal) of the expected address register (EXP_ADDR). If there is no redirection request at this time, the output value of this module is the address data provided by the sequential address register.

[0080] (5) Second selector

[0081] This module is a multiplexer that receives the second reorganized data from the redirection distributor and the complete address data from the sequential address register. After priority selection, it outputs at least the low-order address data to the bus encapsulation unit. It can also directly output the complete address data to the bus encapsulation unit (without the need for the sequential address register to connect to the bus encapsulation unit). When directly outputting only the low-order address, the output of the sequential address register is also connected to the bus encapsulation unit, which directly provides the high-order address. If there is no redirection request at this time, the output value of this module is the complete sequential address data provided by the sequential address register.

[0082] (6) Bus encapsulation unit

[0083] Receive the complete address data of at least the second selector (or including the sequential address register), and after simple packaging, form a bus signal (BUS), which is sent to the address increment module, bus address register and bus control register, and at the same time sent to the system's bus interconnection matrix (not shown in the figure).

[0084] (7) Address increment module

[0085] Receives the complete address information from the bus encapsulation unit (the concatenation of the high-order address information of the sequential address register and the low-order address data of the second selector, or the complete address data of the second selector) and generates the address signal for the next instruction based on constraints such as the instruction fetch width and alignment. This module is generally an addition circuit for the bus address signal and a constant.

[0086] Embodiment 3: The optimization branch adopts the optimization strategy of partial redirection request + partial address data.

[0087] The third embodiment is equivalent to the combination of the first and second embodiments, and its effect is the best. The following two conditions must be met at the same time:

[0088] (1) Each group of data in the second reorganized signal does not contain the high bit of the redirection address;

[0089] (2)n2<n0.

[0090] In terms of connection relationship, the third embodiment is the same as the first embodiment.

[0091] The main functions of each module are:

[0092] (1) The sequential address register, sequential control register, expected address register, expected control generator, bus address register, bus control register, first selector, bus encapsulation unit, address increment module, and comparison module are the same as those in the first embodiment.

[0093] (2) Redirect Distributor

[0094] The input of this module is the enable and address signals of all redirection requests in the CPU. A reorganization signal is generated according to the allocation strategy. The reorganization signal contains the corresponding selection, enable and address signals, and the reorganization signal is distributed to the first selector and the second selector. The array size of the first reorganization signal distributed to the first selector is consistent with the array size of the CPU redirection request, which must include all redirection requests and at least include the high bit of the redirection address. It can also include the low bit of the redirection address, which is used to subsequently generate the correct expected address signal to the expected register. Each group of data in the array of the second reorganization signal distributed to the second selector only contains the redirection enable bit and the low bit of the redirection address, but does not contain the high bit of the redirection address, and the array size n2 of the second reorganization signal is smaller than the array size n1 of the first reorganization signal (or the array size n0 of the CPU redirection request).

[0095] (3) Second selector

[0096] This module is a multiplexer that receives the partial redirection request enable and redirection address low bits (no redirection address high bits) from the redirection distributor, as well as the sequence address low bits provided by the sequence address register. After priority selection, it outputs the low-order address data to the bus encapsulation unit. If there is no redirection request, the module outputs the sequence address low bits provided by the sequence address register.

[0097] This embodiment fully utilizes the spatial and temporal locality of programs, combined with the fact that not all redirections require a fast response. Using selective partial redirection and low-order address data can minimize latency while maintaining the performance of critical code, making it a preferred solution. The following example illustrates the operation of the optimization circuit in this embodiment.

[0098] 1. A timing example of a redirection without restoration example in this embodiment is shown in FIG4 .

[0099] S0 represents the data input to the expected register and bus register, and S1 represents the data output from the expected register and bus register. The whole process is as follows:

[0100] (1) T0 period:

[0101] Assuming there is no redirection request, the value of the sequence address register (SEQ_ADDR) is 0x0000_0000; the value of the sequence control register (SEQ_CTRL) is FLASH, not cached, XR (executable, readable);

[0102] Assume that S1 is currently invalid;

[0103] Therefore:

[0104] S0 expects address bits 0x0000_0000, which is equivalent to the sequential address register (SEQ_ADDR);

[0105] The S0 bus address bit is 0x0000_0000, which is equivalent to the sequential address register (SEQ_ADDR);

[0106] S0 bus control bit FLASH, not cached, XR (executable, readable), equivalent to the sequence control register (SEQ_CTRL);

[0107] When the cycle ends (rising edge of the next cycle), the following steps are performed:

[0108] a. Store the expected address bit of S0 into the expected address register (EXP_ADDR);

[0109] b. Store the S0 bus address bit in the bus address register (BUS_ADDR);

[0110] c. Store the S0 bus control bit in the bus control register (BUS_CTRL);

[0111] d. Update the sequential address register (SEQ_ADDR) to the output value of the address increment module (0x0000_0004);

[0112] e. The sequence control register (SEQ_CTRL) remains unchanged;

[0113] (2) T1 cycle:

[0114] The expected address bit of S1 is 0x0000_0000, which is equivalent to the expected address bit of S0 in the previous cycle;

[0115] The S1 bus address bit is 0x0000_0000, which is equivalent to the S0 bus address bit in the previous cycle;

[0116] S1 expected control bit FLASH, not cached, XR (executable, readable), obtained by decoding and comparing the S1 expected address bit and the CPU configuration register;

[0117] S1 bus control bit FLASH, not cached, XR (executable, readable), equivalent to the S0 bus control bit in the previous cycle;

[0118] After the comparison module (CMP) compares the expected data and the bus data, it finds that the bus data is consistent. This time the bus returns valid and outputs a valid instruction at address 0x0000_0000. It is assumed that the instruction is predicted to branch in the current cycle, and its target address is 0x0000_1000. In addition, it is assumed that the control bit of the target address is FLASH, not cached, XR (executable, readable). Therefore, the redirect dispatcher receives a predicted branch request with a target address of 0x0000_1000, FLASH, not cached, and XR (executable, readable).

[0119] Therefore:

[0120] S0 expects address 0x0000_1000, which comes from the redirect dispatcher;

[0121] The S0 bus address is 0x0000_1000, the high-order address comes from the sequential address register (SEQ_ADDR), and the low-order address comes from the redirector.

[0122] S0 bus control bit FLASH, not cached, XR (executable, readable), equivalent to the sequence control register (SEQ_CTRL);

[0123] When the cycle ends (rising edge of the next cycle), the following steps are performed:

[0124] a. Store the expected address bit of S0 into the expected address register (EXP_ADDR);

[0125] b. Store the S0 bus address bit in the bus address register (BUS_ADDR);

[0126] c. Store the S0 bus control bit in the bus control register (BUS_CTRL);

[0127] d. Update the sequential address register (SEQ_ADDR) to the output value of the address increment module (0x0000_1004);

[0128] e. The sequence control register (SEQ_CTRL) remains unchanged;

[0129] (3) T2 cycle:

[0130] The expected address bit of S1 is 0x0000_1000, which is equivalent to the expected address bit of S0 in the previous cycle;

[0131] The S1 bus address bit is 0x0000_1000, which is equivalent to the S0 bus address bit in the previous cycle;

[0132] S1 expects the control bit to be FLASH, not cached, XR (executable, readable), and the S1 expects the address bit to be decoded and compared with the CPU configuration register;

[0133] S1 bus control bit FLASH, not cached, XR (executable, readable), equivalent to the S0 bus control bit in the previous cycle;

[0134] After comparison by the comparison module (CMP), the expected data and the bus data are consistent. This time the bus returns valid, and the valid instruction at address 0x0000_1000 is output. It is assumed that this instruction is a normal instruction and no prediction branch occurs. The redirection dispatcher has no request, so the instruction fetch unit completes the redirection and continues the sequential prefetch process.

[0135] Therefore:

[0136] S0 expects address bits 0x0000_1004, which is equivalent to the sequential address register (SEQ_ADDR);

[0137] The S0 bus address bit is 0x0000_1004, which is equivalent to the sequential address register (SEQ_ADDR);

[0138] S0 bus control bit FLASH, not cached, XR (executable, readable), equivalent to the sequence control register (SEQ_CTRL);

[0139] When the cycle ends (rising edge of the next cycle), the following steps are performed:

[0140] a. Store the expected address bit of S0 into the expected address register (EXP_ADDR);

[0141] b. Store the S0 bus address bit in the bus address register (BUS_ADDR);

[0142] c. Store the S0 bus control bit in the bus control register (BUS_CTRL);

[0143] d. Update the sequential address register (SEQ_ADDR) to the output value of the address increment module (0x0000_1008);

[0144] e. The sequence control register (SEQ_CTRL) remains unchanged.

[0145] 2. The time sequence of the redirection recovery example of this embodiment is shown in FIG5 .

[0146] (1) T0 period:

[0147] Assuming there is no redirection request, the value of the sequence address register (SEQ_ADDR) is 0x0000_0000; the value of the sequence control register (SEQ_CTRL) is FLASH, not cached, XR (executable, readable);

[0148] Assume that S1 is currently invalid;

[0149] Therefore:

[0150] S0 expects address bits 0x0000_0000, which is equivalent to the sequential address register (SEQ_ADDR);

[0151] The S0 bus address bit is 0x0000_0000, which is equivalent to the sequential address register (SEQ_ADDR);

[0152] S0 bus control bit FLASH, not cached, XR (executable, readable), equivalent to the sequence control register (SEQ_CTRL);

[0153] When the cycle ends (rising edge of the next cycle), the following steps are performed:

[0154] a. Store the expected address bit of S0 into the expected address register (EXP_ADDR);

[0155] b. Store the S0 bus address bit in the bus address register (BUS_ADDR);

[0156] c. Store the S0 bus control bit in the bus control register (BUS_CTRL);

[0157] d. Update the sequential address register (SEQ_ADDR) to the output value of the address increment module (0x0000_0004);

[0158] e. The sequence control register (SEQ_CTRL) remains unchanged;

[0159] (2) T1 cycle:

[0160] The expected address bit of S1 is 0x0000_0000, which is equivalent to the expected address bit of S0 in the previous cycle;

[0161] The S1 bus address bit is 0x0000_0000, which is equivalent to the S0 bus address bit in the previous cycle;

[0162] S1 expects the control bit to be FLASH, not cached, XR (executable, readable), and the S1 expects the address bit to be decoded and compared with the CPU configuration register;

[0163] S1 bus control bit FLASH, not cached, XR (executable, readable), equivalent to the S0 bus control bit in the previous cycle;

[0164] After the comparison module (CMP) compares the expected data and the bus data, it finds that the bus data is consistent. This time, the bus returns valid and outputs the valid instruction at address 0x0000_0000. It is assumed that the instruction is predicted to branch in the current cycle, and its target address is 0x2000_1000. In addition, it is assumed that the control bits of the target address are SRAM0, not cached, XR (executable, readable). Therefore, the redirect dispatcher receives the predicted branch request, the target address is 0x2000_1000, SRAM0, not cached, XR (executable, readable);

[0165] Therefore:

[0166] S0 expects address 0x2000_1000, which comes from the redirector.

[0167] The S0 bus address is 0x0000_1000, the high-order address comes from the sequential address register (SEQ_ADDR), and the low-order address comes from the redirector.

[0168] S0 bus control bit FLASH, not cached, XR (executable, readable), equivalent to the sequence control register (SEQ_CTRL);

[0169] When the cycle ends (rising edge of the next cycle), the following steps are performed:

[0170] a. Store the expected address bit of S0 into the expected address register (EXP_ADDR);

[0171] b. Store the S0 bus address bit in the bus address register (BUS_ADDR);

[0172] c. Store the S0 bus control bit in the bus control register (BUS_CTRL);

[0173] d. Update the sequential address register (SEQ_ADDR) to the output value of the address increment module (0x0000_1004);

[0174] e. The sequence control register (SEQ_CTRL) remains unchanged;

[0175] (3) T2 cycle:

[0176] The expected address bit of S1 is 0x2000_1000, which is equivalent to the expected address bit of S0 in the previous cycle;

[0177] The S1 bus address bit is 0x0000_1000, which is equivalent to the S0 bus address bit in the previous cycle;

[0178] S1 expects control bit SRAM0, not cached, XR (executable, readable), S1 expects address bit and CPU configuration register decoded and compared;

[0179] S1 bus control bit FLASH, not cached, XR (executable, readable), equivalent to the S0 bus control bit in the previous cycle;

[0180] After comparison by the comparison module (CMP), if the expected data and the bus data are inconsistent, the bus return is invalid, a recovery signal is generated, and the current bus access of S0 is revoked.

[0181] Therefore, S0 is invalid.

[0182] When the cycle ends (rising edge of the next cycle), the following steps are performed:

[0183] a. Restore the Sequence Address Register (SEQ_ADDR) to the output value of the Expected Address Register (EXP_ADDR) (0x2000_1000);

[0184] b. Restore the sequence control register (SEQ_CTRL) to the output value of the expected control generator (EXP_CTRL) (SRAM0, not cached, XR (executable, readable));

[0185] (4) T3 cycle:

[0186] The previous cycle S0 is invalid, so the current cycle S1 is invalid.

[0187] The recovery signal is generated in the previous cycle, so:

[0188] S0 expects address bits 0x2000_1000, which is equivalent to the sequential address register (SEQ_ADDR);

[0189] The S0 bus address bit is 0x2000_1000, which is equivalent to the sequential address register (SEQ_ADDR);

[0190] S0 bus control bit SRAM0, not cached, XR (executable, readable), equivalent to the sequence control register (SEQ_CTRL);

[0191] When the cycle ends (rising edge of the next cycle), the following steps are performed:

[0192] a. Store the expected address bit of S0 into the expected address register (EXP_ADDR);

[0193] b. Store the S0 bus address bit in the bus address register (BUS_ADDR);

[0194] c. Store the S0 bus control bit in the bus control register (BUS_CTRL);

[0195] d. Update the sequential address register (SEQ_ADDR) to the output value of the address increment module (0x2000_1004);

[0196] e. The sequence control register (SEQ_CTRL) remains unchanged;

[0197] (5) T4 cycle:

[0198] The expected address bit of S1 is 0x2000_1000, which is equivalent to the expected address bit of S0 in the previous cycle;

[0199] The S1 bus address bit is 0x2000_1000, which is equivalent to the S0 bus address bit in the previous cycle;

[0200] S1 expects control bit SRAM0, not cached, XR (executable, readable), S1 expects address bit and CPU configuration register decoded and compared;

[0201] S1 bus control bit SRAM0, not cached, XR (executable, readable), equivalent to the S0 bus control bit in the previous cycle;

[0202] After the comparison module (CMP) performs the comparison, the expected data and the bus data are consistent. This time the bus returns to valid and outputs the valid instruction at the address 0x2000_1000. At this point, the instruction fetch unit completes recovery and continues the sequential prefetch process.

[0203] Therefore:

[0204] S0 expects address bits 0x2000_1004, which is equivalent to the sequential address register (SEQ_ADDR);

[0205] The S0 bus address bit is 0x2000_1004, which is equivalent to the sequential address register (SEQ_ADDR);

[0206] S0 bus control bit FLASH, not cached, XR (executable, readable), equivalent to the sequence control register (SEQ_CTRL);

[0207] When the cycle ends (rising edge of the next cycle), the following steps are performed:

[0208] f. Store the expected address bit of S0 into the expected address register (EXP_ADDR);

[0209] g. Store the S0 bus address bit in the bus address register (BUS_ADDR);

[0210] h. Store the S0 bus control bit in the bus control register (BUS_CTRL);

[0211] i. Update the sequential address register (SEQ_ADDR) to the output value of the address increment module (0x2000_1008);

[0212] j. The sequence control register (SEQ_CTRL) remains unchanged.

Claims

1. A processor instruction fetch redirection timing optimization circuit, characterized in that: It includes a redirection distributor, a first selector, a second selector, an expectation register, a bus encapsulation unit, a bus register, an address increment unit, a sequence register and a comparison module; The redirection distributor inputs a CPU redirection request signal, and an output end of the redirection distributor outputs a first reorganization signal to the first selector and outputs a second reorganization signal to the second selector; The input end of the sequence register is connected to the one-to-two selector, and the output end is connected to the first selector, the second selector and the bus encapsulation unit; The input end of the expectation register is connected to at least the output end of the first selector, the expectation register is used to receive the complete expected address bit, and the output end of the expectation register is connected to the comparison module and the one-out-of-two selector; The input end of the bus encapsulation unit is connected to the output end of the second selector and the output end of the sequence register, the output end of the bus encapsulation unit is connected to the bus register and the address increment unit, the output end of the bus register is connected to the comparison module, the output end of the address increment unit is connected to the two-to-one selector, and the bus encapsulation unit sends the signal to the system bus matrix; The output end of the comparison module is connected to the signal selection end of the two-to-one selector; Wherein, the CPU redirection request signal, the first reorganization signal, and the second reorganization signal are all array structures. Assume that the array sizes of the CPU redirection request signal, the first reorganization signal, and the second reorganization signal are n0, n1, and n2 respectively, where n0, n1, and n2 represent the number of types of redirection requests, and n0=n1. Each group of data in the CPU redirection request signal includes a redirection enable bit, a redirection address high bit, and a redirection address low bit. Each group of data in the first reorganization signal includes at least a redirection enable bit and a redirection address high bit. Each group of data in the second reorganization signal includes at least a redirection enable bit and a redirection address low bit, and at least one of the following conditions is satisfied: (1) Each group of data in the second reorganized signal does not contain the high bit of the redirection address; (2)n2<n0.

2. The processor instruction fetch redirection timing optimization circuit according to claim 1, characterized in that: When the satisfied condition includes (1), the signal transmitted by the sequence register to the second selector only includes the sequence address low bits; the output end of the sequence register is also connected to the bus encapsulation unit to provide the sequence address high bits to the bus encapsulation unit.

3. The processor instruction fetch redirection timing optimization circuit according to claim 2, characterized in that: Each group of data in the first reorganized signal also includes a redirected address low bit; the signal transmitted by the sequential register to the first selector includes a sequential address high bit and a sequential address low bit, and the first selector is used to provide a complete expected address bit for the expected register, including an expected address high bit and an expected address low bit.

4. The processor instruction fetch redirection timing optimization circuit according to claim 1, characterized in that: When only condition (2) is met, each group of data in the second reorganized signal includes a redirection enable bit, a redirection address high bit, and a redirection address low bit, and the signal transmitted from the sequence register to the second selector includes a sequence address high bit and a sequence address low bit.

5. The processor instruction fetch redirection timing optimization circuit according to any one of claims 1 to 4, characterized in that: Each group of data in the first reorganized signal does not include the redirection address low bit; the signal transmitted by the sequential register to the first selector only includes the sequential address high bit, and the first selector is used to provide the expected address high bit for the expected register; the output end of the second selector is also connected to the expected register, and is used to provide the expected address low bit for the expected register.

6. The processor instruction fetch redirection timing optimization circuit according to any one of claims 1 to 4, characterized in that: The output end of the sequence register is also connected to the bus encapsulation unit, and is used to provide the high bits of the sequence address to the bus encapsulation unit.

7. The processor instruction fetch redirection timing optimization circuit according to any one of claims 1 to 4, characterized in that: The comparison module includes a control comparison unit and an address comparison unit.

8. The processor instruction fetch redirection timing optimization circuit according to any one of claims 1 to 4, characterized in that: The expected register includes an expected control generator and an expected address register, the output end of the first selector is connected to the expected address register, the output end of the expected address register is connected to the input end of the address comparison unit and the input end of the expected control generator, the CPU configuration information is input from the expected control generator, the expected control generator is used to generate the required expected control bit data according to the expected address data and the CPU configuration information, and the output end of the expected control generator is connected to the input end of the control comparison unit; The bus register includes a bus control register and a bus address register, the input end of the bus control register and the input end of the bus address register are connected to the bus encapsulation unit, and the output end of the bus control register and the output end of the bus address register are respectively connected to the input end of the control comparison unit and the input end of the address comparison unit.

9. The processor instruction fetch redirection timing optimization circuit according to claim 8, characterized in that: The sequential register comprises a sequential control register and a sequential address register, wherein the input ends of the sequential control register and the sequential address register are respectively connected to a two-to-one selector; the first input end of the two-to-one selector connected to the sequential control register is connected to the output end of the sequential control register, and the second input end is connected to the output end of the expected control generator; the output end of the sequential control register is connected to the bus encapsulation unit; the first input end of the two-to-one selector connected to the sequential address register is connected to the output end of the address increment unit, and the second input end is connected to the output end of the expected address register; the output end of the sequential address register is connected to the first selector and the second selector.

10. The processor instruction fetch redirection timing optimization circuit according to claim 8, characterized in that: The bus encapsulation unit is used to receive signals output by the sequence register and the second selector, assemble them into bus control bits and bus address bits, transmit the bus control bits to the bus control register, and transmit the bus address bits to the bus address register.

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