Method for managing shared cache, and electronic device

Abstract

The present application relates to the technical field of electronic device control. Provided are a method for managing a shared cache, and an electronic device. By means of the method, a running frequency point of a processing unit and a running frequency point of a shared cache can be matched, such that the processing unit can acquire data from the shared cache in a timely manner, thereby ensuring the running speed of an application. The method comprises: in response to a first event, setting a running frequency point of a shared cache to be a first frequency point on the basis of a focused application, user operation information, performance information of each processing core, and thread running information, wherein the focused application is an application that is last operated by a user, the user operation information comprises the types and number of operations of the user performed on the focused application within a preset time, the performance information of each processing core is used for reflecting a shared-cache miss rate of the processing core, and the thread running information is used for reflecting respective running time proportions of a plurality of thread groups on N processing cores, each thread group comprising one or more threads running on an electronic device.

Description

Shared cache management method and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on October 25, 2023, with application number 202311399261.0 and invention name “A shared cache management method and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of electronic device control, and in particular to a shared cache management method and electronic device. Background Art

[0003] Shared cache refers to the sharing of cache resources between multiple entities in a cache architecture (e.g., multiple applications, multiple processing cores in an electronic device, etc.) to accommodate varying cache requirements. For example, in an electronic device with multiple central processing units (CPUs), the multiple cores share the CPU's Level 3 cache.

[0004] In related technologies, when multiple applications share a cache, to avoid cache contention, the cache can be partitioned, so that different partitions are used to cache data for different applications. This method can, to a certain extent, balance the use of the third-level cache by different applications.

[0005] However, when the actual occupancy of the application's L3 cache is sufficient, if the frequency of the L3 cache does not match the CPU frequency, the CPU cannot obtain data from the L3 cache in a timely manner, affecting the response speed of the foreground application and thus affecting the user experience.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a shared cache management method and an electronic device, which enable a CPU to obtain data from the shared cache in a timely manner.

[0008] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0009] In a first aspect, a shared cache management method is provided, which is applied to an electronic device, the electronic device including a processor, the processor including a shared cache and N processing cores, where N is an integer greater than or equal to 1, the method including: receiving a first event for triggering a change in a focus application; in response to the first event, setting the operating frequency of the shared cache to a first frequency based on the focus application, user operation information, performance information of each processing core, and thread running information; wherein the focus application is the application last operated by the user, the user operation information includes the type and number of operations performed by the user on the focus application within a preset time, the performance information of each processing core is used to reflect the shared cache miss rate of the processing core, and the thread running information is used to reflect the running time proportion of multiple thread groups on the N processing cores, each thread group including one or more threads running on the electronic device.

[0010] It can be understood that the focus application and user operation information can be used to reflect the focus application's demand for resources in the current user scenario, because the shared cache's operating frequency is obtained by combining the focus application, user operation information, thread operation information, and the performance information of each processing core. In this way, the obtained shared cache's operating frequency can match the operating frequency of one or more processing cores and adapt to the current user scenario and thread grouping, so that one or more processing cores can obtain data or instructions from the shared cache in a timely manner, reducing the impact of the mismatch between the shared cache frequency and the processing core's operating frequency on the processing core's operating speed, improving the processing core's operating speed, and thereby improving the application's responsiveness and user experience.

[0011] In an implementation provided in the first aspect, before setting the operating frequency of the shared cache to the first frequency based on the focus application, user operation information, performance information of each processing core, and thread running information, the method also includes: determining the user scenario based on the focus application and user operation information; determining resource configuration information based on the user scenario, the resource configuration information including the space ratio of multiple thread groups in the shared cache; setting the operating frequency of the shared cache to the first frequency based on the focus application, user operation information, performance information of each processing core, and thread running information, including: setting the operating frequency of the shared cache to the first frequency based on the user scenario, resource configuration information, performance information of each processing core, and thread running information.

[0012] In an implementation method provided in the first aspect, the operating frequency of the shared cache is set to the first frequency based on the user scenario, resource configuration information, performance information of each processing core, and thread running information, including: for the i-th processing core among N processing cores, the operating frequency of the i-th processing core is obtained based on the user scenario, resource configuration information, performance information of the i-th processing core, and the proportion of the running time of multiple thread groups on the i-th processing core, i=1~N; based on the running frequencies of the N processing cores, the shared cache demand frequency corresponding to the N processing cores is respectively queried in the first configuration information; wherein, the shared cache demand frequency corresponding to the i-th processing core is positively correlated with the operating frequency of the i-th processing core; the maximum value of the shared cache demand frequency corresponding to the N processing cores is used as the first frequency; and the operating frequency of the shared cache is set to the first frequency.

[0013] In an implementation method provided in the first aspect, the performance information of the i-th processing core also includes the clock cycle of the i-th processing core, the multiple thread groupings include a first control group and a second control group, the threads included in the first control group are more correlated with the user interaction experience than the threads included in the second control group, and there is no intersection between the threads included in the first control group and the threads included in the second control group; wherein, the operating frequency of the i-th processing core is positively correlated with the clock cycle of the i-th processing core, the space share of the first control group in the shared cache, and the running time share of the first control group on the i-th processing core, and the operating frequency of the i-th processing core is negatively correlated with the space share of the second control group in the shared cache and the running time share of the second control group on the i-th processing core.

[0014] In an implementation provided by the first aspect, the operating frequency of the i-th processing core is also positively correlated with the shared cache miss rate of the i-th processing core.

[0015] In an implementation manner provided by the first aspect, when the user scenario is the first user scenario, the operating frequency of the i-th processing core, the clock cycle of the i-th processing core, the space proportion of the first control group in the shared cache, the space proportion of the second control group in the shared cache, the running time proportion of the first control group on the i-th processing core, and the running time proportion of the second control group on the i-th processing core satisfy:

[0016] Fcpu[i]=(cycle_count[i] / sample_ms)*Function1(P1,P2,Pt,x[i],y[i])

[0017] Function1(P1,P2,Pt,x[i],y[i])=C1*(1+P1 / Pt)*(1+x[i])*(1-P2 / Pt)*(1-y[i])

[0018] Among them, Fcpu[i] is the operating frequency of the i-th processing core, cycle_count[i] is the clock cycle of the i-th processing core, sample_ms is the time interval for the electronic device to obtain performance information of N processing cores, P1 is the space ratio of the first control group in the shared cache, P2 is the space ratio of the second control group in the shared cache, Pt is the sum of P1 and P2, x[i] is the running time ratio of the first control group on the i-th processing core, y[i] is the running time ratio of the second control group on the i-th processing core, and C1 is a preset first constant.

[0019] In an implementation manner provided by the first aspect, when the user scenario is the second user scenario, the operating frequency of the i-th processing core, the clock cycle of the i-th processing core, the space proportion of the first control group in the shared cache, the space proportion of the second control group in the shared cache, the running time proportion of the first control group on the i-th processing core, and the running time proportion of the second control group on the i-th processing core satisfy:

[0020] Fcpu[i]=(cycle_count[i] / sample_ms)*Function2(P1,P2,Pt,x[i],y[i])

[0021] Function2(P1,P2,Pt,x[i],y[i])=C2*(1+P1 / Pt)*(1+x[i])*(1+(ipm_meas[i]-ipm_ceil) / ipm_meas[i])*(1-P2 / Pt)*(1-y[i])

[0022] Among them, Fcpu[i] is the operating frequency of the i-th processing core, cycle_count[i] is the clock cycle of the i-th processing core, sample_ms is the time interval for the electronic device to obtain performance information of N processing cores, P1 is the space ratio of the first control group in the shared cache, P2 is the space ratio of the second control group in the shared cache, Pt is the sum of P1 and P2, x[i] is the running time ratio of the first control group on the i-th processing core, y[i] is the running time ratio of the second control group on the i-th processing core, ipm_meas[i] is the shared cache miss rate of the i-th processing core, ipm_ceil is the preset miss rate waterline value, and C2 is the preset second constant.

[0023] In an implementation method provided in the first aspect, the user scenario includes a first user scenario and a second user scenario; when the user scenario is the first user scenario, the space proportion of the first control group in the shared cache is the first space proportion, and the space proportion of the second control group in the shared cache is the second space proportion; when the user scenario is the second user scenario, the space proportion of the shared cache of the first control group is the third space proportion, and the space proportion of the shared cache of the second control group is the fourth space proportion; wherein, the first space proportion is less than the third space proportion, and the second space proportion is greater than the fourth space proportion.

[0024] In an implementation provided by the first aspect, the method further includes: in response to the first event, configuring cache partitions of the multiple thread groups in the shared cache according to the space proportions of the multiple thread groups in the shared cache.

[0025] In other words, compared to the prior art method of allocating shared cache partitions to thread groups based on fixed values, this application can divide threads into multiple thread groups based on the degree of relevance between each thread and the user interaction experience, determine the space share of the shared cache corresponding to each thread group based on the user scenario, and then configure cache partitions for multiple thread groups in the shared cache based on the space share of the multiple thread groups in the shared cache, so that different partitions are used to cache the data to be cached for different thread groups. In this way, the shared cache occupancy rate of threads with a strong relevance to the user interaction experience can be guaranteed, thereby ensuring the response speed of the focus application.

[0026] In an implementation provided by the first aspect, the resource configuration information further includes a priority of each thread group in the multiple thread groups for using the shared cache, and the method further includes: configuring the multiple thread groups according to the priority of each thread group for using the shared cache.

[0027] In this way, when multiple threads initiate access requests to the third-level cache at the same time, not only can the cgroup partition to which the threads that are more relevant to the user interaction experience belong have sufficient third-level cache space, so that the operating frequency of the third-level cache matches the operating frequency of one or more processing cores, but it can also enable the threads with higher priority in using the third-level cache in the cgroup to which they belong (that is, the threads with higher relevance to the user interaction experience) to access the third-level cache first to obtain data, thereby ensuring the response speed of the application to which the threads that are more relevant to the user interaction experience belong, which is beneficial to improving the user experience.

[0028] In an implementation provided in the first aspect, the thread running information also includes a shared cache miss rate of the first thread, the first thread is a thread ranked in the top M in load, and M is a positive integer. The method also includes: adjusting the priority of the second thread in the first thread so that the priority of the second thread is higher than the priority of other threads other than the second thread in the thread group to which the second thread belongs; wherein the second thread is a thread in the first thread whose shared cache miss rate is higher than the first threshold.

[0029] That is to say, the present application can also adjust the priority of using the shared cache at the thread granularity, so that threads with a high shared cache miss rate and a high load can have priority access to the shared cache, thereby reducing the shared cache miss rate of the thread.

[0030] In an implementation method provided in the first aspect, for the i-th processing core among N processing cores, the operating frequency of the i-th processing core is obtained based on the user scenario, resource configuration information, performance information of the i-th processing core, and the proportion of the running time of multiple thread groups on the i-th processing core, including: for the i-th processing core among the N processing cores, if the shared cache miss rate of the i-th processing core is less than or equal to the miss rate waterline value, the operating frequency of the i-th processing core is obtained based on the user scenario, resource configuration information, performance information of the i-th processing core, and the proportion of the running time of multiple thread groups on the i-th processing core; if the shared cache miss rate of the i-th processing core is greater than the miss rate waterline value, the operating frequency of the i-th processing core is determined according to the rated operating frequency of the i-th processing core.

[0031] In an implementation provided in the first aspect, the resource configuration information also includes a load waterline, and the method also includes: obtaining the system load; in response to a first event, setting the operating frequency of the shared cache to a first frequency based on the focus application, user operation information, performance information of each processing core, and thread running information, including: in response to the first event and the system load is less than or equal to the load waterline, configuring cache partitions of multiple thread groups in the shared cache, and setting the operating frequency of the shared cache to the first frequency based on the focus application, user operation information, performance information of each processing core, and thread running information.

[0032] In an implementation provided in the first aspect, the load waterline includes a first load waterline and a second load waterline. The first load waterline is the load waterline when the user scenario is the first user scenario, and the second load waterline is the load waterline when the user scenario is the second user scenario. The first load waterline is smaller than the second load waterline.

[0033] In a second aspect, the present application also provides an electronic device, which includes: a memory and a processor, the processor including a shared cache and N processing cores, where N is an integer greater than or equal to 1; the processor is coupled to the storage; wherein the memory is used to store computer program code, and the computer program code includes computer instructions; when the computer instructions are executed by the processor, the electronic device executes the method of the first aspect and any one of its implementation methods.

[0034] In a third aspect, the present application further provides a computer-readable storage medium comprising computer instructions; when the computer instructions are executed on an electronic device, the electronic device executes the method of the first aspect and any one of its implementations.

[0035] It can be understood that the beneficial effects that can be achieved by the electronic device of the second aspect and the computer-readable storage medium of the third aspect provided above can be referred to the beneficial effects in the first aspect and any possible implementation thereof, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG1 is a schematic diagram of the structure of a shared cache provided in an embodiment of the present application;

[0037] FIG2 is a hardware structure diagram of an electronic device provided in an embodiment of the present application;

[0038] FIG3 is a software structure block diagram of an electronic device provided in an embodiment of the present application;

[0039] FIG4 is a flow chart of a method for managing a shared cache according to an embodiment of the present application;

[0040] FIG5 is a schematic diagram of a hierarchical level provided in an embodiment of the present application;

[0041] FIG6 is a schematic diagram of allocation of cache partitions provided in an embodiment of the present application;

[0042] FIG7 is a second flow chart of a shared cache management method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. Among them, in the description of the embodiments of the present application, the terms used in the following embodiments are only for the purpose of describing specific embodiments, and are not intended to be used as limitations on the present application. As used in the specification and claims of the present application, the singular expressions "a", "said", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" refer to one or more (including two). The term "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist; for example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0044] References to "one embodiment" or "some embodiments" etc. described in this specification mean that the specific features, structures or characteristics described in conjunction with the embodiment are included in one or more embodiments of the present application. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. appearing in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in another way. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in another way. The term "connected" includes direct and indirect connections, unless otherwise stated. "First" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0045] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0046] In order to better understand the embodiments of the present application, some of the terms or technologies involved in the embodiments of the present application are explained below:

[0047] 1. Cache

[0048] A cache is a memory that allows for high-speed data exchange. When the CPU issues a data access request, it first checks to see if the requested data exists in the cache. If the requested data exists in the cache (called a hit), the data is returned directly to the CPU without accessing the main memory. If the requested data does not exist in the cache (called a miss), it is read from the slower main memory and sent to the CPU for processing. At the same time, the data block containing the data is loaded into the cache, allowing the CPU to read the data directly from the cache next time. In other words, the cache can exchange data with the CPU before the main memory, reducing the time it takes for the CPU to read data.

[0049] The memory, also known as main memory, is a storage space that can be directly addressed by the CPU. As an example, the memory can be a dynamic random access memory (DRAM), etc., but is not limited thereto.

[0050] The data stored in the cache is usually the data that the CPU has accessed most recently, or the data that the CPU accesses frequently. This can improve the hit rate of the CPU reading data and enhance the CPU performance.

[0051] With the development of multi-core CPUs, CPU cache is generally divided into three levels: Level 1 Cache, Level 2 Cache, and Level 3 Cache. The smaller the level, the closer it is to the CPU, the faster the computing speed, but also the smaller its capacity.

[0052] For example, referring to Figure 1, a schematic diagram of a shared cache scenario is shown. A CPU 10 of an electronic device includes three processing cores, namely, processing core 1, processing core 2, and processing core 3. Each of the three processing cores of CPU 10 is configured with an independent L1 cache and L2 cache, and all three processing cores of CPU 10 can access the L3 cache of CPU 10. That is, the L3 cache of CPU 10 is a shared cache for these three processing cores.

[0053] In the process of reading data, processing core 1, processing core 2 or processing core 3 will first search for data in its corresponding first-level cache. If the data required by the processing core is not in the first-level cache (i.e., a miss), it will go to the next level, that is, search for data in its corresponding second-level cache. If the data required by the processing core is not in the second-level cache (i.e., a miss), it will go to the next level, that is, query data in the shared third-level cache. Until the data required by the processing core is not in the third-level cache (i.e., a miss), it will search for data in the memory.

[0054] 2. Cache performance

[0055] Cache performance can be evaluated by hit rate or miss rate.

[0056] In the data read scenario, the hit rate is the ratio of the number of cache hits for I / O read requests within a time period to the total number of I / O read requests within that time period. The miss rate is the ratio of the number of cache misses for I / O read requests within a time period to the total number of I / O read requests within that time period. The shared cache miss rate is the ratio of the number of cache misses for I / O read requests within the shared cache to the total number of I / O read requests within that time period.

[0057] 3. Control groups (cgroup)

[0058] Cgroups manage and control the use of system resources by threads (processes or applications) in groups. In other words, electronic devices can use cgroups to group all threads and then allocate and control resources for the entire group. System resources can include the shared cache mentioned above.

[0059] In related technologies, when multiple applications share a cache, in order to avoid cache contention, the cache shared by multiple applications can be partitioned so that different partitions are used to cache data to be cached by different applications. This method can, to a certain extent, balance the amount of third-level cache occupied by different applications. However, considering that the third-level cache of the foreground application has sufficient occupancy, if the frequency of the third-level cache does not match the CPU frequency, the CPU will not be able to obtain data from the third-level cache in a timely manner, affecting the response speed of the application and, in turn, the user experience.

[0060] To this end, the shared cache management method provided in this application can determine the operating frequency (i.e., the first frequency) of the shared cache (e.g., the third-level cache) based on the focus application, user operation information, performance information of each processing core, and thread operation information. The focus application is the application last operated by the user, the user operation information includes the type and number of operations performed by the user on the focus application within a preset time, the performance information of each processing core is used to reflect the shared cache miss rate of the processing core, and the thread operation information can be used to reflect the operation status of multiple thread groups (also called control groups) on one or more processing cores.

[0061] It can be understood that the focus application and user operation information can be used to reflect the focus application's demand for resources in the current user scenario, because the shared cache's operating frequency is obtained by combining the focus application, user operation information, thread operation information, and the performance information of each processing core. In this way, the obtained shared cache's operating frequency can match the operating frequency of one or more processing cores and adapt to the current user scenario and thread grouping, so that one or more processing cores can obtain data or instructions from the shared cache in a timely manner, reducing the impact of the mismatch between the shared cache frequency and the processing core's operating frequency on the processing core's operating speed, improving the processing core's operating speed, and thereby improving the application's responsiveness and user experience.

[0062] Considering that when dividing cache partitions in the current shared cache, the partition size is usually specified manually, this cannot guarantee the actual occupancy of the shared cache of the foreground application, affecting the response speed of the foreground application.

[0063] The shared cache management method provided in the embodiment of the present application can also divide threads into multiple thread groups (or control groups) according to the degree of relevance between each thread and the user interaction experience, determine the space share of the shared cache (i.e., the third-level cache) corresponding to each thread group according to the user scenario, and then configure the cache partitions of the multiple thread groups in the shared cache according to the space share of the multiple thread groups in the shared cache, so that different partitions are used to cache the data to be cached of different thread groups. In this way, the thread with a strong degree of relevance to the user interaction experience (such as the thread of the focus application) can be guaranteed to occupy the shared cache, thereby ensuring the response speed of the focus application.

[0064] It should be noted that the following will take the shared cache as the third-level cache and the control group to refer to the thread group as an example to specifically illustrate the relevant methods and electronic devices provided by this application.

[0065] It should also be noted that the electronic devices provided in the embodiments of the present application can be mobile phones, tablet computers, desktop computers, laptop computers, handheld computers, notebook computers, ultra-mobile personal computers (UMPCs), netbooks, as well as cellular phones, personal digital assistants (PDAs), augmented reality (AR) devices, virtual reality (VR) devices, artificial intelligence (AI) devices, wearable devices, in-vehicle devices, smart home devices and / or smart city devices. The embodiments of the present application do not impose any special restrictions on the specific types of the electronic devices.

[0066] Figure 2 is a hardware structure diagram of an electronic device 100 provided in an embodiment of the present application. As shown in Figure 2, the electronic device 100 may include: a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, a wireless communication module 150, a display screen 160, etc.

[0067] The processor 110 may include one or more processing units, for example: the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Among them, different processing units can be independent devices or integrated into one or more processors. The processor 110 can be the nerve center and command center of the electronic device 100. The processor 110 can generate operation control signals based on instruction opcodes and timing signals to complete the control of instruction fetching and execution.

[0068] In one embodiment, the processor 110 may be the CPU 10 shown in FIG1 , which includes one or more processing cores. The processing cores can be categorized into large cores, medium cores, and small cores based on their performance. Large cores typically have higher frequencies and higher performance, and are used to handle high-load tasks, such as running large applications and games with high graphics requirements. Small cores, on the other hand, have low power consumption and high efficiency, and are used to handle low-load tasks, such as browsing the web and answering calls. Medium cores are intermediate between large and small cores.

[0069] Processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in processor 110 is a cache memory. This memory can store instructions or data that have just been used or are being recycled by processor 110. If processor 110 needs to use the same instruction or data again, it can directly access the memory. This avoids duplicate accesses, reduces processor 110 latency, and thus improves system efficiency.

[0070] In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface.

[0071] It is understood that the interface connection relationship between the modules illustrated in this embodiment is merely an illustrative illustration and does not constitute a structural limitation on the electronic device 100. In other embodiments, the electronic device 100 may also adopt different interface connection methods from the above embodiments, or a combination of multiple interface connection methods.

[0072] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 via the external memory interface 120 to implement data storage functions. For example, files such as music and videos can be stored on the external memory card.

[0073] The internal memory 121 can be used to store computer executable program code, which includes instructions. The processor 110 executes various functional applications and data processing of the electronic device 100 by running the instructions stored in the internal memory 121. For example, in an embodiment of the present application, the processor 110 can execute instructions stored in the internal memory 121, and the internal memory 121 can include a program storage area and a data storage area.

[0074] Among them, the program storage area can store the operating system, at least one application required for a function (such as a recent task management function), etc. The data storage area can store data created during the use of the electronic device 100. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. For example, in an embodiment of the present application, the internal memory 121 includes an L3 register.

[0075] It should be understood that the structure illustrated in this embodiment does not constitute a specific limitation on the electronic device 100. In other embodiments, the electronic device 100 may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0076] The software system of the electronic device 100 can adopt a layered architecture, an event-driven architecture, a micro-kernel architecture, a micro-service architecture, or a cloud architecture. TM Taking the system as an example, the software structure of the electronic device 100 is exemplarily described. FIG3 is a block diagram of the software structure of the electronic device 100 according to an embodiment of the present application.

[0077] The layered architecture divides the software into several layers, each with a clear role and division of labor. The layers communicate with each other through software interfaces. In some embodiments, the electronic device 100 may include an application layer, an application framework layer, a hardware abstraction layer (HAL), and a kernel layer. In addition, in different operating systems (such as Android TM System, IOS TM system, etc.), as long as the functions implemented by each functional module are similar to those of the embodiments of the present application, the solution of the present application can also be implemented.

[0078] The application layer may include a series of applications. As shown in FIG3 , the application layer may include applications such as video, navigation, music, news, and shopping.

[0079] The application framework layer provides an application programming interface (API) and programming framework for applications in the application layer. The application framework layer includes some predefined functions. For example, as shown in Figure 3, the application framework layer may include a scene recognition module and a group management module.

[0080] The scene recognition module is used to obtain the focus application and user operation information to determine the user scene of the electronic device 100. The specific process of the scene recognition module determining the user scene of the electronic device 100 can be found in the description of S401 and S701 below and will not be described here.

[0081] The group management module is used to divide threads into different control groups (thread groups) based on the degree of relevance between the threads and the user interaction experience.

[0082] The HAL layer encapsulates the Linux kernel driver, providing an interface to the upper layer and shielding the implementation details of the underlying hardware. In the embodiment of the present application, the HAL layer includes a policy management module. The policy management module is used to obtain resource configuration information based on user scenarios and thread grouping information. This resource configuration information includes information such as the load watermark, the space usage of each cgroup in the L3 cache, and the priority of each cgroup in using the shared L3 cache.

[0083] The kernel layer is the layer between hardware and software. It includes at least a scheduling module, a packet control module, a memory system resource partitioning and monitoring (MPAM) driver module, and a frequency modulation driver module.

[0084] The scheduling module is used to obtain the actual load of the electronic device 100, the load of the thread, and the running status of the related threads on different processing cores.

[0085] The group control module is used to perform partition processing on the third-level cache based on the multiple control groups and resource configuration information obtained by the group management module.

[0086] The mpam driver module can use the mpam function to partition and monitor the third-level cache. mpam can partition cache resources from a hardware perspective to address the problem of critical service performance degradation or overall system performance degradation caused by shared resource competition during CPU memory access.

[0087] The frequency modulation driver module is used to determine the operating frequency of the third-level cache that matches the operating frequency of one or more processing cores.

[0088] It should also be noted that the software architecture shown in FIG3 only shows part of the layers, and the operating system may also include more layers than those shown in FIG3 , and no specific limitation is made here.

[0089] The shared cache management method provided in the embodiment of the present application can be applied to scenarios such as application startup, scenarios where foreground applications interact with users, etc. In scenarios where applications are started or where foreground applications interact with users, the applications have a large number of cache resource requirements. In this case, the shared cache management method provided in the present application can effectively ensure that the foreground application has sufficient third-level cache occupancy, ensuring that the foreground application can quickly start or quickly respond to user operations, thereby improving the user experience. The shared cache management method provided in the embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0090] Please refer to Figure 4, which is a flowchart of a shared cache management method provided in an embodiment of the present application. The method can be applied to the electronic device shown in Figure 2. As shown in Figure 4, the shared cache management method includes S401 to S411.

[0091] S401: The electronic device determines a user scenario based on a focus application and user operation information.

[0092] In the embodiments of the present application, user scenarios can be used to reflect the resource demands of applications. The resource demands of applications include the demands for cache resources, CPU resources, and GPU resources, etc., which are not specifically limited here. In the embodiments of the present application, user scenarios can include video playback scenarios, sliding scenarios, etc., depending on the focus application and user operation information. Applications have different resource demands in different user scenarios.

[0093] For example, in a video playback scenario, there is less interaction between the user and the electronic device, and the CPU of the electronic device does not need to read data from the cache frequently. In this case, the cache space required by the application is less.

[0094] For example, in a sliding scenario, there is a lot of interaction between the user and the electronic device. The electronic device can update the content on the page in response to the user's sliding operation. During this period, the CPU of the electronic device may need to frequently read data from the cache to update the page content. In this case, the application requires more cache space.

[0095] The focus application is the application that the user last operated on. For example, if the most recent input received by the phone is for a chat application, the focus application is the chat application; if the most recent input received by the user is for a navigation application, the focus application is the navigation application.

[0096] It can be understood that the focus application can be used to preliminarily predict the user's next behavior and the focus application's demand for resources. For example, if the focus application is a video application, it can be inferred that the user has a need to watch videos, and therefore it can be determined that the application may require certain cache resources to cache the video, and need to use GPU resources for decoding. For another example, if the focus application is a short video application, it can be inferred that the user is likely to watch short videos, and based on the characteristics of short video applications that users need to frequently slide pages to refresh short videos, it can be preliminarily determined that the application may require a large amount of cache resources to cache short videos, and need to use GPU resources for decoding.

[0097] But in fact, the same application may have different usage scenarios, and the resource requirements in different usage scenarios are also different. For example, when the focus application is a video application, the user can watch a certain video resource, or just browse the page of the video application and select the video resource to be played. Among them, when the user watches a certain video resource, there is less interaction between the user and the electronic device, and the processor of the electronic device does not need to read data from the cache frequently. In this case, the cache resources required by the application are relatively small; when the user only browses the page of the video application, the electronic device can update the content on the page in response to the user's sliding operation. During this period, the processor of the electronic device may need to frequently read data from the cache to update the page content. In this case, the cache resources required by the application are relatively large.

[0098] Therefore, this application combines the focus application and user operation information to determine the user scenario. The user operation information may include the number and type of operations performed by the user on the current focus application within a preset time. The operation performed on the focus application may be a click operation, a slide operation, etc.

[0099] For example, if the focus application is a video application and the user operation information indicates that the user frequently performs sliding operations on the video application, it indicates that the user is likely to need to browse and select video resources to be played in the video application, and the video application has not yet played the video. Therefore, the user scenario can be determined to be a sliding scenario. In an optional embodiment, when the number of sliding operations performed by the user on the video application exceeds a threshold of 1, the user operation information indicates that the user frequently performs sliding operations on the video application.

[0100] For another example, if the focused application is a video application and the user operation information indicates that the user has performed only a few operations on the video application, this indicates that the user is likely watching a video and has had little interaction with the video application. Therefore, the user scenario can be determined to be a video playback scenario. In an optional embodiment, if the number of operations performed on the video application is less than a threshold of 2, the user operation information indicates that the user has performed only a few operations on the video application.

[0101] It can be seen that combining the focus application and user operation information to comprehensively determine the user scenario can more accurately predict the application's demand for resources, which is conducive to subsequent accurate resource scheduling, quickly meeting user needs, and improving user experience.

[0102] In some embodiments, the electronic device can perceive changes in the focus application through the process manager, and determine the user scenario based on the current focus application and user operation information when the focus application is perceived to have changed. This makes it easier for the electronic device to readjust the resource allocation strategy when the focus application changes.

[0103] S402: The electronic device groups threads to obtain thread grouping information.

[0104] The thread grouping information includes multiple cgroups (also called thread groups) and the threads contained in each cgroup.

[0105] Specifically, each cgroup may include one or more threads, or may not include any threads. As shown in Figure 5, it is a schematic diagram of a hierarchy. The hierarchy can be understood as a cgroup tree with a hierarchical relationship. Each node of the tree is a cgroup. Referring to Figure 5, for example, the thread tree includes a top-app (top-level application) group, a foreground (foreground) group, a system (system) group, and a background (background) group. It should be noted that the number and name of each cgroup shown in this application are only illustrative examples, and this application does not limit this.

[0106] In an embodiment of the present application, the electronic device may divide threads into different cgroups based on the degree of relevance between the threads and the user interaction experience, thereby executing the scheduling policy corresponding to the cgroup to which the threads belong. In an optional embodiment, the electronic device may determine the degree of relevance between the thread and the user interaction experience based on whether the application to which the thread belongs is running in the foreground or background. Among them, the thread of the application running in the foreground has a higher degree of relevance to the user interaction experience; the thread of the application running in the background has a lower degree of relevance to the user interaction experience.

[0107] For example, the top-app group includes threads that are strongly related to the user interaction experience, such as the thread of the focus application, the thread of the foreground application, the rendering line (such as the Render thread), the thread that updates the user interface (such as the UI thread), etc.; the foreground group includes service threads related to the user interaction experience, such as the audio thread, the framework core thread, the thread of the navigation bar, the status bar and other applications, etc.; the background group includes threads that are not strongly related to the user interaction experience, such as the thread of the application switched to the background, the thread that executes the download task in the background, etc.; the system group includes system threads and kernel threads, such as the thread of the application such as the battery power statistics, etc. Among them, the foreground application may refer to the application that runs in the foreground but is not the last operation of the user. For example, the electronic device can display the interface of the video application and the interface of the chat application at the same time, but the application last operated by the user is the chat application, then the focus application is the chat application, and the video application is the foreground application. The above division method is only an illustrative example, and this application is not limited to this.

[0108] S403: The electronic device obtains resource configuration information based on the user scenario.

[0109] Resource configuration information includes load watermarks and cache configuration information, including the space usage of each cgroup in the L3 cache. The load watermark can be used as a parameter for electronic devices to determine whether to improve performance or reduce power consumption. The space usage of each cgroup in the L3 cache refers to the maximum L3 cache usage that cgroup can use. The actual L3 cache usage of each cgroup must not exceed the L3 cache usage of that cgroup.

[0110] In an optional embodiment, the electronic device pre-stores configuration information, which includes correspondences between different user scenarios and resource configuration information. In this way, the electronic device can query the configuration information based on the user scenario to obtain the corresponding resource configuration information.

[0111] For example, the correspondence between different user scenarios and resource configuration information may be as shown in Table 1.

[0112] Table 1

[0113] For example, based on Table 1, when the user scenario is a video playback scenario, the electronic device can determine that the load waterline is 70%, the top-app group and the foreground group can occupy 60% of the space in the third-level cache, the background group can occupy 30% of the space in the third-level cache, and the system group can occupy 10% of the space in the third-level cache.

[0114] It should be noted that Table 1 is only used to illustrate the correspondence between user scenarios and resource configuration information, but does not mean that user scenarios and corresponding resource configuration information must be stored in the form of a table. For example, resource configuration information can also be stored in a designated field corresponding to the user scenario in the resource configuration file.

[0115] S404: The electronic device obtains a system load.

[0116] The system load is the sum of the loads of all threads running on the electronic device.

[0117] S405: The electronic device determines whether the system load is less than or equal to the load waterline.

[0118] The electronic device can determine whether to improve performance or reduce power consumption by comparing the system load and the load waterline, and further determine whether to use the aforementioned resource configuration information to manage the shared cache.

[0119] It can be understood that when the system load is greater than the load waterline, it indicates that the current system load is high. In this case, the electronic device needs to give priority to performance. Therefore, the electronic device does not use the aforementioned resource configuration information to manage the shared cache, but instead takes measures to quickly increase the CPU operating frequency to meet the high load requirements.

[0120] In an optional embodiment, when the system load is greater than the load waterline, the electronic device sets the user scenario to the default scenario and obtains the corresponding resource configuration information under the default scenario. The resource configuration information corresponding to the default scenario may also include the space proportion of each control group in the three-level cache, but in the default scenario, the space proportion of the top-app group and the foreground group in the three-level cache (for example, 50%) is less than the space proportion of the top-app group and the foreground group in the three-level cache in the video playback scenario (for example, 60%), and the space proportion of the background group in the three-level cache in the default scenario (for example, 40%) is greater than the space proportion of the background group in the three-level cache in the video playback scenario (for example, 30%).

[0121] When the system load is less than or equal to the load waterline, it indicates that the current system load is moderate. In this case, the electronic device can balance performance and power consumption without quickly increasing the CPU operating frequency. Therefore, the electronic device can use the aforementioned resource configuration information to manage the shared cache, that is, execute S406.

[0122] In an optional implementation, the resource configuration information may not include the load waterline, and the electronic device may not execute S404 and S405 but directly execute S406.

[0123] S406: The electronic device partitions the third-level cache based on the cache configuration information to obtain mpam configuration information.

[0124] The MPAM configuration information includes partition identifiers for multiple cache partitions and the corresponding cgroup for each cache partition. In embodiments of the present application, electronic devices can utilize the MPAM function to partition and monitor the third-level cache. For example, the electronic device can divide the third-level cache into multiple cache partitions, assign a different partition identifier to each cache partition, and assign a cache partition to each cgroup.

[0125] When allocating cache partitions to each cgroup, the electronic device may refer to the space ratio of each cgroup in the third-level cache, and take the space ratio of each cgroup in the third-level cache as the basis.

[0126] For example, the electronic device can divide the L3 cache into 10 cache partitions, and the partition identifiers of the 10 cache partitions are way[j], j=0~9. It should be noted that the 10 cache partitions do not need to be continuous in physical address. According to Table 1, when the user scenario is a sliding scenario, the top-app group and the foreground group account for 80% of the space in the third-level cache, the background group accounts for 10% of the space in the third-level cache, and the system group accounts for 10%~20% of the space in the third-level cache. In this way, the electronic device can allocate cache partitions way0~way9 in the manner shown in Figure 6.

[0127] As shown in Figure 6, the electronic device allocates eight cache partitions, way0 to way7, to the top-app group and the foreground group, which together occupy 80% of the L3 cache space. It allocates the cache partition way8 to the background group, which makes the background group occupy 10% of the L3 cache space. It allocates two cache partitions, way8 to way9, to the system group, which makes the system group occupy 20% of the L3 cache space.

[0128] In this way, different cgroups can access their corresponding cache partitions, which not only achieves physical isolation of data but also ensures each cgroup's share of the third-level cache and reduces fluctuations in the running time of threads within each cgroup.

[0129] S407: The electronic device obtains performance information of each processing core at a first time interval.

[0130] The performance information of each processing core may be monitored by a performance monitoring unit (PMU) of the electronic device.

[0131] In the embodiment of the present application, the electronic device obtains the performance information of each processing core once every first time interval sample_ms. For example, if the first time interval sample_ms is 50ms, the PMU obtains the performance information of each processing core once every 50ms.

[0132] The performance information of a processing core includes a number of L3 cache misses (cache_miss_count) of the processing core in a first time interval, a number of instructions (instruction_count) executed in the first time interval, a clock cycle (cycle_count), and a L3 cache miss rate of the processing core. The clock cycle of the processing core may be the time required for the processing core to execute an instruction.

[0133] Taking an electronic device including N processing cores as an example, the electronic device can obtain cache_miss_count[i], instruction_count[i] and cycle_count[i], where i=1~N, cache_miss_count[i] represents the number of misses of the i-th processing core on the third-level cache within the first time interval, instruction_count[i] represents the number of instructions run by the i-th processing core within the first time interval, and cycle_count[i] represents the clock cycle of the i-th processing core.

[0134] For example, the first time interval is 100ms, and the electronic device includes 4 processing cores. Then, the electronic device obtains the number of misses of each of the 4 processing cores on the third-level cache within 100ms, the number of instructions run by each of the 4 processing cores within 100ms, and the clock cycle of each of the 4 processing cores every 100ms.

[0135] In this way, the electronic device can determine the L3 cache miss rate ipm_meas[i] of the i-th processing core based on cache_miss_count[i] and instruction_count[i]. Where cache_miss_count[i], instruction_count[i], and ipm_meas[i] satisfy the formula: ipm_meas[i] = instruction_count[i] / cache_miss_count[i], where i = 1 to N.

[0136] S408: The electronic device obtains thread running information.

[0137] The thread running information includes the running time ratio of the critical thread group and the non-critical thread group on each processing core.

[0138] In an embodiment of the present application, the critical thread group may include the top-app group and the foreground group, and the non-critical thread group may include the background group. In an optional embodiment, the critical thread group may also be referred to as the first control group, and the non-critical thread group may also be referred to as the second control group, and the threads included in the first control group and the threads included in the second control group do not overlap.

[0139] Still taking the example of an electronic device including N processing cores, the electronic device can obtain a first running time proportion x[i] and a second running time proportion y[i], wherein the first running time proportion x[i] is used to represent the running time proportion of the critical thread group on the i processing cores, and the second running time proportion y[i] is used to represent the running time proportion of the non-critical thread group on the i processing cores, i=1~N.

[0140] It can be understood that by obtaining the runtime percentage of the critical and non-critical thread groups on each processing core, the processing cores on which the threads within the critical and non-critical thread groups execute can be determined. For example, if the runtime percentage of the critical thread group on a large core is higher than the runtime percentage of the critical thread group on other cores, this indicates that the majority of threads within the critical thread group execute on the large core.

[0141] S409 , the electronic device obtains a third-level cache demand frequency corresponding to each processing core based on the user scenario, cache configuration information, performance information of each processing core, and thread running information.

[0142] The L3 cache demand frequency corresponding to each processing core is the operating frequency of the L3 cache matched to that processing core. The method for deriving the L3 cache demand frequency corresponding to each processing core varies in different user scenarios. The following uses video playback and scrolling as examples to illustrate the process of deriving the L3 cache demand frequency corresponding to each processing core in different user scenarios.

[0143] 1. Video playback scenario

[0144] When the user scenario is a video playback scenario, for the i-th processing core, the electronic device may first compare the third-level cache miss rate ipm_meas[i] of the i-th processing core with the miss rate waterline value ipm_ceil, where the miss rate waterline value ipm_ceil is a preset value.

[0145] If the L3 cache miss rate of the i-th processing core is greater than the miss rate waterline value, that is, ipm_meas[i]>ipm_ceil, it means that the L3 cache miss rate of the i-th processing core is low, that is, the current operating frequency of the L3 cache can already meet the operating requirements of the i-th processing core, so it can be frequency-reduced to reduce power consumption. In this case, the electronic device can obtain the rated operating frequency F of the i-th processing core. 额 [i]. The i-th processing core includes multiple rated operating frequencies F 额 [i] In the case of electronic equipment, multiple rated operating frequencies F 额 The minimum value in [i] is used as the operating frequency point Fcpu[i] of the i-th processing core, that is:

[0146] Fcpu[i]=min{F 额 [i]}, i=1~N.

[0147] For example, the rated operating frequencies of the i-th processing core include 2.5 GHz, 2.8 GHz, and 3.0 GHz, and the electronic device may use the minimum value 2.5 GHz as the operating frequency of the i-th processing core.

[0148] If the third-level cache miss rate of the i-th processing core is less than or equal to the miss rate waterline value, that is,

[0149] If ipm_meas[i]≤ipm_ceil, it means that the L3 cache miss rate of the i-th processing core is high, and the current operating frequency of the L3 cache cannot meet the operating requirements of the i-th processing core. Therefore, the operating frequency of the L3 cache can be increased. In this case, the electronic device can determine the operating frequency Fcpu[i] of the i-th processing core based on the following formula, where Fcpu[i] satisfies the formula:

[0150] Fcpu[i]=(cycle_count[i] / sample_ms)*Function1(P1,P2,Pt,x[i],y[i])

[0151] Function1(P1, P2, Pt, x[i], y[i]) = C1*(1+P1 / Pt)*(1+x[i])*(1-P2 / Pt)*(1-y[i])

[0152] Wherein, cycle_count[i] is the clock cycle cycle_count[i] of the i-th processing core, sample_ms is the first time interval, Function1 is a variable parameter, P1 is the space ratio of the critical thread group (such as the top-app group and the foreground group) in the third-level cache, P2 is the space ratio of the non-critical thread group (such as the background group) in the third-level cache, Pt is the sum of P1 and P2, x[i] is the running time ratio of the critical thread group on the i-th processing core, y[i] is the running time ratio of the non-critical thread group on the i-th processing core, and C1 is a preset constant.

[0153] It can be seen that in the video playback scenario, for any processing core, the longer the clock cycle of the processing core, the higher the space ratio of the critical thread group in the three-level cache (i.e., P1), and the higher the running time ratio of the critical thread group on the processing core (i.e., x[i]); or, the lower the space ratio of the non-critical thread group in the three-level cache (i.e., P2), and the lower the running time ratio of the non-critical thread group on the processing core (i.e., y[i]), the higher the running frequency of the processing core.

[0154] After determining the operating frequency of the i-th processing core, the electronic device may query the first configuration information based on the operating frequency of the i-th processing core to obtain the corresponding operating frequency of the third-level cache as the required third-level cache frequency Fcache[i] corresponding to the i-th processing core, where i = 1 to N. The first configuration information stores a correspondence between the operating frequencies of the processing cores and the operating frequencies of the third-level cache, and the higher the operating frequency of the processing core, the higher the operating frequency of the third-level cache.

[0155] 2. Sliding scene

[0156] It should be noted that the process of obtaining the third-level cache demand frequency corresponding to each processing core in the sliding scenario is partially the same as the process of obtaining the third-level cache demand frequency corresponding to each processing core in the video playback scenario. The same parts can be found in the previous description and will not be repeated here.

[0157] When the user scenario is a sliding scenario, for the i-th processing core, the electronic device may also first compare the third-level cache miss rate ipm_meas[i] and the miss rate waterline value ipm_ceil of the i-th processing core.

[0158] If the L3 cache miss rate of the i-th processing core is greater than the miss rate waterline value, i.e., ipm_meas[i]>ipm_ceil, then Fcpu[i]=min{F 额 [i]}.

[0159] If the L3 cache miss rate of the i-th processing core is less than or equal to the miss rate waterline value, that is, ipm_meas[i]≤ipm_ceil, the electronic device can determine the operating frequency Fcpu[i] of the i-th processing core based on the following formula, where Fcpu[i] satisfies the formula:

[0160] Fcpu[i]=(cycle_count[i] / sample_ms)*Function2(P1,P2,Pt,x[i],y[i])

[0161] Function2(P1,P2,Pt,x[i],y[i])=C2*(1+P1 / Pt)*(1+x[i])*(1+(ipm_meas[i]-ipm_ceil) / ipm_meas[i])*(1-P2 / Pt)*(1-y[i])

[0162] Among them, ipm_meas[i] is the third-level cache miss rate of the i-th processing core, and ipm_ceil is the miss rate waterline value.

[0163] It can be seen that in the sliding scenario, for any processing core, the longer the clock cycle of the processing core, the higher the space ratio of the critical thread group in the three-level cache, and the higher the running time ratio of the critical thread group on the processing core; or, the lower the running time ratio of the non-critical thread group on the processing core, the lower the space ratio of the non-critical thread group in the three-level cache, and the lower the three-level cache miss rate of the processing core, then the operating frequency of the processing core will be higher.

[0164] Similarly, after the electronic device determines the operating frequency of each processing core, it can search the first configuration information for the operating frequency of the third-level cache corresponding to the operating frequency of the processing core as the third-level cache demand frequency corresponding to the processing core, that is, obtain Fcache[i], i=1~N.

[0165] It should be noted that, as previously described, when the system load exceeds the load threshold, the electronic device sets the user scenario to the default scenario and obtains the resource configuration information corresponding to the default scenario. In the default scenario, the electronic device can also obtain the L3 cache demand frequency corresponding to each processing core. However, in the default scenario, the L3 cache demand frequency corresponding to each processing core is not highly correlated with the cache configuration information, the performance information of each processing core, and the thread running information.

[0166] In a default scenario, for the i-th processing core, the electronic device may first compare the third-level cache miss rate ipm_meas[i] of the i-th processing core with the miss rate waterline value ipm_ceil, where the miss rate waterline value ipm_ceil is a preset value.

[0167] If the L3 cache miss rate of the i-th processing core is greater than the miss rate waterline value, i.e., ipm_meas[i]>ipm_ceil, then the electronic device can take multiple rated operating frequencies F 额 The minimum value in [i] is used as the operating frequency point Fcpu[i] of the i-th processing core, that is, Fcpu[i]=min{F 额 [i]}, i=1~N.

[0168] If the third-level cache miss rate of the i-th processing core is less than or equal to the miss rate waterline value, that is, ipm_meas[i]≤ipm_ceil, the electronic device can determine the operating frequency Fcpu[i] of the i-th processing core based on the clock cycle cycle_count[i] and the first time interval sample_ms of the i-th processing core, where cycle_count[i], sample_ms and Fcpu[i] satisfy the formula: Fcpu[i]=cycle_count[i] / sample_ms.

[0169] It can be seen that for any processing core, the larger the clock cycle of the processing core, the higher the corresponding operating frequency of the processing core.

[0170] Similarly, after the electronic device determines the operating frequency of each processing core, it can search the first configuration information for the operating frequency of the third-level cache corresponding to the operating frequency of the processing core as the third-level cache demand frequency corresponding to the processing core, that is, obtain Fcache[i], i=1~N.

[0171] S410, the electronic device uses the maximum value of the three-level cache requirement frequency points corresponding to each processing core as the first frequency point. That is, the first frequency point and the three-level cache requirement frequency points corresponding to each processing core satisfy the formula:

[0172] Fcache=max{Fcache[i]}

[0173] Fcache is the first frequency point, which can be used as the operating frequency point of the third-level cache.

[0174] It can be understood that using the maximum value of the third-level cache demand frequency corresponding to all processing cores as the operating frequency of the third-level cache can meet the frequency requirements of all processing cores for the third-level cache, so that all processing cores can obtain data from the third-level cache in a timely manner.

[0175] S411: The electronic device manages the third-level cache based on the mapm configuration information and the first frequency point.

[0176] In one embodiment, the electronic device can write the mapm information and the first frequency point into the register so that the electronic device can configure the cache partitions of multiple control groups in the third-level cache according to the space ratio of the multiple control groups in the third-level cache, and set the first frequency point as the operating frequency point of the third-level cache.

[0177] Based on the above content, it can be seen that the present application can divide threads into multiple cgroups according to the degree of relevance between each thread and the user interaction experience, and allocate a three-level cache space adapted to the current user scenario to each control group. The cgroup to which the thread with a higher degree of relevance to the user interaction experience belongs is allocated more three-level cache space, thereby ensuring the response speed of the application to which the thread with a higher degree of relevance to the user interaction experience belongs, which is conducive to improving the user experience.

[0178] In addition, the electronic device can also determine the operating frequency of the third-level cache based on the user scenario, resource configuration information, performance information of each processing core, and thread operation information. In this way, the operating frequency of the third-level cache can match the operating frequency of one or more processing cores and adapt to the current user scenario and thread grouping. This allows one or more processing cores to retrieve data or instructions from the third-level cache in a timely manner, reducing the impact of the mismatch between the operating frequency of the third-level cache and the operating frequency of the processing core on the operating speed of the processing core, improving the operating speed of the processing core, and thus improving the responsiveness of the application and the user experience.

[0179] Considering that more L3 cache space is allocated to the cgroup to which threads more relevant to the user interaction experience belong, it cannot be guaranteed that threads more relevant to the user interaction experience can have priority access to the L3 cache when there is resource competition.

[0180] Therefore, in an optional embodiment, the resource configuration information may further include the priority of each cgroup in using the third-level cache, and the upper and lower limits of the frequency of the third-level cache. In this case, the correspondence between different user scenarios and resource configuration information may be as shown in Table 2.

[0181] Table 2

[0182] A space usage percentage of -1 for the system's L3 cache indicates that the system group can occupy the L3 cache of cgroups whose L3 cache usage priority is lower than that of the system group. Furthermore, priorities are classified into three levels: high, medium, and low. A high-priority cgroup has a higher L3 cache usage priority than a medium- or low-priority cgroup, and a medium-priority cgroup has a higher L3 cache usage priority than a low-priority cgroup. When threads belonging to different cgroups simultaneously initiate access requests to the L3 cache, the thread in the cgroup with the higher priority has priority access to the L3 cache, allowing threads in the higher-priority cgroup to obtain data more efficiently. Furthermore, f1 < f3, and f2 < f4.

[0183] It should be noted that the correspondence between different user scenarios and resource configuration information shown in this application is only an illustrative example and this application does not limit this.

[0184] For example, based on Table 2, when the user scenario is a video playback scenario, the electronic device can determine the load waterline to be 70%; the lower limit value of the frequency point of the three-level cache is f1, and the upper limit value of the frequency point of the three-level cache is f2; the top-app group and the foreground group can occupy 60% of the space of the three-level cache, and the background group can occupy 30% of the space of the three-level cache, and the priority of the top-app group and the foreground group to use the three-level cache is higher than the priority of the system group to use the three-level cache, and the priority of the system group to use the three-level cache is higher than the priority of the background group to use the three-level cache, and since the space ratio of the system group's three-level cache is -1, it means that when the space ratio of the three-level cache required by the system group is higher than 10%, the background group's three-level cache can be occupied, that is, the system group occupies up to 40% of the space of the three-level cache.

[0185] In addition, based on Table 2, we can see that the cgroup to which the thread with a higher degree of relevance to the user interaction experience belongs has a higher priority in using the third-level cache.

[0186] It should also be noted that after the electronic device determines the maximum value of the third-level cache demand frequency corresponding to each processing core, it can compare the upper limit value of the third-level cache frequency in the current user scenario and the maximum value of the third-level cache demand frequency corresponding to each processing core, and take the smaller value as the first frequency.

[0187] That is, the first frequency point satisfies the formula: Fcache=min{Fcache[i]max,fmax}

[0188] Among them, Fcache is the first frequency point, Fcache[i]max is the maximum value of the three-level cache demand frequency points corresponding to each processing core, and fmax is the upper limit of the three-level cache frequency point in the current user scenario.

[0189] In this case, the electronic device can write the mapm configuration information, the first frequency point, and the priority of each cgroup using the third-level cache into the register to manage the third-level cache.

[0190] In this way, when multiple threads initiate access requests to the third-level cache at the same time, not only can the cgroup partition to which the threads that are more relevant to the user interaction experience belong have sufficient third-level cache space, so that the operating frequency of the third-level cache matches the operating frequency of one or more processing cores, but it can also enable the threads with higher priority in using the third-level cache in the cgroup to which they belong (that is, the threads with higher relevance to the user interaction experience) to access the third-level cache first to obtain data, thereby ensuring the response speed of the application to which the threads that are more relevant to the user interaction experience belong, which is beneficial to improving the user experience.

[0191] The above methods all use cgroup as the granularity to adjust the priority and space usage of the third-level cache used by the cgroup, but do not adjust it for threads.

[0192] Therefore, in an optional embodiment, the thread execution information also includes the load of each thread. In this way, the electronic device can filter out the first thread from all threads. The first thread can be a thread with a high load ranking, for example, the top M threads in the load ranking. Where M is a positive integer, for example, 3, 5, 10, etc.

[0193] Furthermore, the thread running information also includes the number of cache_miss_count2 misses of the first thread in the third-level cache within the second time and the number of instructions instruction_count2 executed by the first thread within the second time. The second time can be any time, such as the aforementioned first time interval, or other time, and no specific limitation is made here.

[0194] Taking the existence of M first threads in an electronic device as an example, the electronic device can obtain cache_miss_count2[k] and instruction_count2[k], where k=1~M; cache_miss_count2[k] represents the number of misses of the kth first thread on the third-level cache within the second time, and instruction_count2[k] represents the number of instructions run by the kth first thread within the second time.

[0195] In this way, the electronic device can determine the L3 cache miss rate ipm_meas2[k] of the Mth first thread based on cache_miss_count2[k] and instruction_count2[k]. Wherein, ipm_meas2[k], cache_miss_count2[k], and instruction_count2[k] satisfy the formula:

[0196] ipm_meas2[k]=instruction_count2[k] / cache_miss_count2[k], k=1~M

[0197] On this basis, the electronic device may determine the first thread whose L3 cache miss rate is greater than a threshold value 3 as the second thread, and increase the priority of the second thread in using the L3 cache.

[0198] In the embodiment of the present application, raising the priority of the second thread in using the L3 cache can be understood as making the priority of the second thread in using the L3 cache higher than the priority of all other threads in the cgroup to which the second thread belongs. In other words, the present application can also adjust the priority of using the L3 cache at the thread level, so that threads with a high L3 cache miss rate and a high load can have priority access to the L3 cache, thereby reducing the L3 cache miss rate of these threads.

[0199] For example, in a video playback scenario, the top-app group includes thread 1, thread 2, and thread 3, and the system group includes thread 4 and thread 5. The electronic device determines that thread 1 and thread 5 are the first threads based on the thread load conditions, and the third-level cache miss rate of thread 1 is greater than the threshold 3, and the third-level cache miss rate of thread 5 is greater than the threshold 3. Therefore, the electronic device adjusts the priority of thread 1 and thread 5 in using the third-level cache, so that the priority of thread 1 in using the third-level cache is higher than the priority of thread 2 and thread 3 in using the third-level cache, and the priority of thread 5 in using the third-level cache is higher than the priority of thread 4 in using the third-level cache, but the priority of thread 4 and thread 5 in using the third-level cache is still lower than the priority of thread 1, thread 2, and thread 3 in using the third-level cache. In this way, when thread 1, thread 2, and thread 3 simultaneously initiate access requests to the third-level cache, thread 1 can access the third-level cache first before thread 2 and thread 3. When thread 4 and thread 5 simultaneously initiate access requests to the third-level cache, thread 5 can access the third-level cache first before thread 4. When thread 2 / thread 3 and thread 5 simultaneously initiate access requests to the third-level cache, thread 2 / thread 3 can access the third-level cache first before thread 5.

[0200] In this case, the electronic device can write the mapm configuration information, the operating frequency of the third-level cache, the priority of each cgroup using the third-level cache, and the adjusted priority of the second thread into the register to manage the third-level cache, so that threads with higher loads and lower third-level cache hit rates can access the third-level cache first to reduce load pressure.

[0201] The following will further illustrate the shared cache management method provided by this application in conjunction with the software structure shown in Figure 3. Please refer to Figure 7, which is a second flow chart of a shared cache management method provided in an embodiment of this application. This method can be applied to an electronic device having the software structure shown in Figure 3. As shown in Figure 7, the shared cache management method includes S701 to S724.

[0202] S701 : In response to a change in a focus application, a scene recognition module determines a user scene based on the focus application and user operation information.

[0203] Among them, the explanation of user scenarios, focus applications and user operation information can be found in the relevant description in S401, which will not be repeated here.

[0204] In a possible design, the scene recognition module may register a monitor with the process manager, and the process manager may send a notification to the scene recognition module when the focus application changes, and the notification carries the current focus application.

[0205] Optionally, the scene recognition module can also register a listener with the input module to obtain the type and object of the user operation. The scene recognition module can also count the number and type of operations performed by the user on the current focus application over a period of time to obtain user operation information.

[0206] S702: The scenario recognition module sends the user scenario to the policy management module.

[0207] S703: The policy management module obtains resource configuration information based on the user scenario.

[0208] In this embodiment of the present application, resource configuration information includes a load watermark and cache configuration information. The load watermark can be used as a parameter for electronic devices to determine whether the cache configuration information is valid. The cache configuration information includes the space allocated to each cgroup in the L3 cache, the priority of each cgroup in using the L3 cache, and the upper and lower limits of the L3 cache frequency.

[0209] The process of determining resource configuration information can be found in Table 2 and related descriptions, which will not be repeated here.

[0210] S704: The policy management module sends resource configuration information to the frequency modulation driving module.

[0211] For the description of resource configuration information, please refer to S703 and will not be repeated here.

[0212] S705: The group management module groups the threads to obtain thread group information.

[0213] The group management module can divide threads into top-app (top-level application) groups, foreground (foreground) groups, system (system) groups, and background (background) groups based on whether the application to which each thread belongs is a foreground application or a background application, thereby obtaining thread grouping information. The specific process is described in S402 and will not be repeated here.

[0214] S706: The group management module sends thread grouping information to the group control module.

[0215] S707: The grouping control module adds a group identifier to the thread based on the thread grouping information.

[0216] That is to say, the group control module can add a group identifier to the threads involved in the thread grouping information to determine the cgroup to which the thread belongs. It should be noted that different cgroups have different group identifiers. For example, the group identifiers of the top-app group, foreground group, system group, and background group are 1, 2, 3, and 4, respectively. The electronic device can set the group identifier of all threads in the top-app group to 1, the group identifier of all threads in the foreground group to 2, the group identifier of all threads in the system group to 3, and the group identifier of all threads in the background group to 4.

[0217] S708: The grouping control module sends thread grouping information to the frequency modulation driving module.

[0218] It should be noted that there is no strict execution order between S701 to S704 and S705 to S708. S701 to S704 may be executed first and then S705 to S708, or S705 to S708 may be executed first and then S701 to S704, or they may be executed in parallel, which is not specifically limited here.

[0219] S709: The frequency modulation driving module sends a query request 1 to the scheduling module.

[0220] In an optional implementation, the frequency modulation driving module may send a query request 1 to the scheduling module by way of a function call.

[0221] S710: The scheduling module sends the system load to the frequency modulation driving module.

[0222] In the embodiment of the present application, the scheduling module obtains the system load in response to receiving the query request 1 and sends the obtained system load to the frequency modulation driving module. Optionally, the scheduling module can send the system load to the frequency modulation driving module by way of function callback.

[0223] S711: The frequency modulation drive module determines whether the system load is less than or equal to the load waterline.

[0224] When the system load is less than or equal to the load waterline, the frequency modulation driving module executes S712 ; when the system load is greater than the load waterline, the third-level cache is managed according to the resource configuration information under the default scenario.

[0225] S712: The FM driver module sends cache configuration information to the mpam driver module.

[0226] For the description of the cache configuration information, please refer to S707 and will not be repeated here.

[0227] S713, the mpam driver module partitions the third-level cache based on the cache configuration information to obtain the mpam configuration information.

[0228] S714: The mpam driver module writes the mpam configuration information and the priority of each cgroup using the third-level cache into the L3 register.

[0229] The L3 register is used to set parameters related to the L3 cache. The processor can read the MPAM configuration information and the priority of each cgroup using the L3 cache from the L3 register, and process each thread's I / O requests to the L3 cache according to the MPAM configuration information and the priority of each cgroup using the L3 cache. For example, when multiple threads simultaneously initiate access requests to the L3 cache, the processor prioritizes access to the L3 cache for threads with a higher priority in the cgroup to which they belong, and can only access the cache partition corresponding to the cgroup to which the thread belongs.

[0230] S715: The frequency modulation driving module obtains performance information of each processing core according to the first time interval.

[0231] The process of the frequency modulation driving module acquiring the performance information of each processing core and the detailed description of the performance information of each processing core are described in S407 , which will not be repeated here.

[0232] S716: The frequency modulation driving module sends a query request 2 to the scheduling module.

[0233] The query request 2 carries thread grouping information.

[0234] In an optional implementation, the frequency modulation driving module may send a query request 2 to the scheduling module by way of a function call.

[0235] S717: The scheduling module sends thread running information to the frequency modulation driving module.

[0236] In the embodiment of the present application, in response to receiving the query request 2, the scheduling module can obtain the thread running information and send the thread running information to the frequency modulation driving module. Optionally, the scheduling module can send the thread running information to the frequency modulation driving module by way of function callback.

[0237] In an embodiment of the present application, the thread execution information includes the execution time percentage of the critical thread group and the non-critical thread group on each processing core, the number of level 3 cache misses of the first thread within the second time period, and the number of instructions executed by the first thread within the second time period. The first thread may be one of the top M threads in terms of load, for example, one of the top 10 threads in terms of load.

[0238] The frequency modulation driving module may calculate the L3 cache miss rate of the first thread to the L3 cache based on the number of L3 cache misses of the first thread and the number of instructions executed by the first thread in the second time.

[0239] S718: The frequency modulation driving module obtains the L3 cache demand frequency corresponding to each processing core based on the user scenario, cache configuration information, performance information of each processing core, and thread running information.

[0240] The process of the frequency modulation driving module obtaining the required frequency point of the third-level cache corresponding to each processing core can be referred to S410 and will not be described in detail here.

[0241] S719: The frequency modulation driving module uses the maximum value of the three-level cache requirement frequency points corresponding to each processing core as the first frequency point.

[0242] S720: The frequency modulation driving module writes the first frequency point into the L3 register.

[0243] It can be understood that the frequency modulation driver module writes the operating frequency of the third-level cache into the L3 register, so that the third-level cache can exchange data with the CPU at this operating frequency. Since the operating frequency of the third-level cache is determined based on the current user scenario, the performance information of each processing core, and the thread running information, the operating frequency of the third-level cache can match the operating frequency of one or more processing cores, and adapt to the current user scenario and thread grouping, so that one or more processing cores can obtain data or instructions from the third-level cache in a timely manner, reduce the impact of the mismatch between the frequency of the third-level cache and the operating frequency of the processing core on the processing core running speed, improve the processing core running speed, and thereby improve the application response speed and user experience.

[0244] S721: The frequency modulation driving module determines whether a second thread exists.

[0245] The second thread is the first thread whose level 3 cache miss rate is greater than a threshold value 3.

[0246] If the second thread exists, execute S722; if the second thread does not exist, end the process.

[0247] S722: The frequency modulation driver module sends a notification of adjusting the thread priority to the mpam driver module.

[0248] The notification of adjusting the thread priority carries the name or identifier of the second thread.

[0249] S723: The mpam driver module increases the priority of the second thread in using the third-level cache.

[0250] Raising the priority of the second thread's use of the L3 cache can be understood as making the second thread's use of the L3 cache priority higher than the use of the L3 cache priority of all other threads in the cgroup to which the second thread belongs. In other words, the present application can also adjust the use of the L3 cache priority at the thread level granularity, so that threads with a high L3 cache miss rate and a high load can have priority access to the L3 cache, thereby reducing the L3 cache miss rate of these threads.

[0251] S724: The mpam driver module writes the adjusted priority of the second thread into the L3 register.

[0252] It can be understood that after the mpam driver module writes the updated priority information into the L3 register, the processor can read the mpam configuration information, the priority of each cgroup using the third-level cache, and the adjusted priority of the second thread from the L3 register, and process the I / O requests of each thread to the third-level cache according to the mpam configuration information, the priority of each cgroup using the third-level cache, and the adjusted priority of the second thread. In this way, it can ensure that the cgroup to which threads that are more relevant to the user interaction experience (such as threads of the focus application) belong has sufficient cache space, and at the same time, threads with higher loads and lower third-level cache hit rates can have priority access to the third-level cache, so that the application to which threads that are more relevant to the user interaction experience belong has a faster response speed, thereby improving the user experience.

[0253] An embodiment of the present application further provides a chip system, which includes at least one processor and at least one interface circuit. The processor and the interface circuit can be interconnected via lines. For example, the interface circuit can be used to receive signals from other devices (such as a memory of an electronic device). For another example, the interface circuit can be used to send signals to other devices (such as a processor). Exemplarily, the interface circuit can read instructions stored in the memory and send the instructions to the processor. When the instructions are executed by the processor, the electronic device can perform the various steps in the above embodiments. Of course, the chip system can also include other discrete devices, which is not specifically limited in the embodiment of the present application.

[0254] This embodiment further provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on an electronic device, the electronic device executes each function or step in the above method embodiment.

[0255] This embodiment further provides a computer program product. When the computer program product is run on an electronic device, the electronic device is enabled to perform each function or step in the above method embodiment.

[0256] In addition, an embodiment of the present application also provides a device, which can specifically be a chip, component or module, and the device may include a connected processor and memory; wherein the memory is used to store computer-executable instructions, and when the device is running, the processor can execute the computer-executable instructions stored in the memory to enable the chip to perform the various functions or steps performed by the electronic device in the above method embodiment.

[0257] Among them, the electronic device, computer-readable storage medium, computer program product or chip provided in this embodiment are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0258] Through the description of the above implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0259] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0260] The units described as separate components may or may not be physically separate, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0261] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0262] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0263] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit the present application. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present application.

Claims

1. A method for managing a shared cache, characterized in that: Applied to an electronic device, the electronic device includes a processor, the processor includes a shared cache and N processing cores, N is an integer greater than or equal to 1, the method includes: Receive a first event for triggering a change in the focus application; In response to the first event, setting the operating frequency of the shared cache to a first frequency based on a focus application, user operation information, performance information of each processing core, and thread running information; Among them, the focus application is the application last operated by the user, the user operation information includes the type and number of operations performed by the user on the focus application within a preset time, the performance information of each processing core is used to reflect the shared cache miss rate of the processing core, and the thread running information is used to reflect the running time proportion of multiple thread groups on the N processing cores, each thread group includes one or more threads running on the electronic device.

2. The method according to claim 1, characterized in that Before setting the operating frequency of the shared cache to the first frequency based on the focus application, user operation information, performance information of each processing core, and thread running information, the method further includes: Determining a user scenario according to the focus application and the user operation information; Determine resource configuration information according to the user scenario, the resource configuration information including the space proportion of the multiple thread groups in the shared cache; The step of setting the operating frequency of the shared cache to a first frequency based on the focus application, user operation information, performance information of each processing core, and thread operation information includes: The operating frequency of the shared cache is set to the first frequency based on the user scenario, the resource configuration information, the performance information of each processing core, and the thread running information.

3. The method according to claim 2, characterized in that The step of setting the operating frequency of the shared cache to the first frequency based on the user scenario, the resource configuration information, the performance information of each processing core, and the thread running information includes: For an i-th processing core among the N processing cores, obtaining an operating frequency of the i-th processing core based on the user scenario, the resource configuration information, the performance information of the i-th processing core, and the proportion of the running time of the multiple thread groups on the i-th processing core, where i=1-N; Based on the operating frequencies of the N processing cores, the shared cache requirement frequencies corresponding to the N processing cores are respectively queried in the first configuration information; wherein the shared cache requirement frequency corresponding to the i-th processing core is positively correlated with the operating frequency of the i-th processing core; The maximum value of the shared cache demand frequency points corresponding to the N processing cores is used as the first frequency point; The operating frequency of the shared cache is set to the first frequency.

4. The method according to claim 3, characterized in that The performance information of the i-th processing core also includes a clock cycle of the i-th processing core, the multiple thread groups include a first control group and a second control group, the threads included in the first control group have a higher degree of relevance to the user interaction experience than the threads included in the second control group, and there is no intersection between the threads included in the first control group and the threads included in the second control group; Among them, the operating frequency of the i-th processing core and the clock cycle of the i-th processing core, the first control The space occupation of the first control group in the shared cache and the running time occupation of the first control group on the i-th processing core are positively correlated, and the running frequency of the i-th processing core is negatively correlated with the space occupation of the second control group in the shared cache and the running time occupation of the second control group on the i-th processing core.

5. The method according to claim 4, characterized in that The operating frequency of the i-th processing core is also positively correlated with the shared cache miss rate of the i-th processing core.

6. The method according to claim 4 or 5, characterized in that: When the user scenario is the first user scenario, the operating frequency of the i-th processing core, the clock cycle of the i-th processing core, the space proportion of the first control group in the shared cache, the space proportion of the second control group in the shared cache, the operating time proportion of the first control group on the i-th processing core, and the operating time proportion of the second control group on the i-th processing core satisfy: Fcpu[i]=(cycle_count[i] / sample_ms)*Function1(P1,P2,Pt,x[i],y[i]) Function1(P1,P2,Pt,x[i],y[i])=C1*(1+P1 / Pt)*(1+x[i])*(1-P2 / Pt)*(1-y[i]) Among them, Fcpu[i] is the operating frequency of the i-th processing core, cycle_count[i] is the clock cycle of the i-th processing core, sample_ms is the time interval for the electronic device to obtain the performance information of the N processing cores, P1 is the space proportion of the first control group in the shared cache, P2 is the space proportion of the second control group in the shared cache, Pt is the sum of P1 and P2, x[i] is the operating time proportion of the first control group on the i-th processing core, y[i] is the operating time proportion of the second control group on the i-th processing core, and C1 is a preset first constant.

7. The method according to claim 4 or 5, characterized in that: When the user scenario is the second user scenario, the operating frequency of the i-th processing core, the clock cycle of the i-th processing core, the space proportion of the first control group in the shared cache, the space proportion of the second control group in the shared cache, the operating time proportion of the first control group on the i-th processing core, and the operating time proportion of the second control group on the i-th processing core satisfy: Fcpu[i]=(cycle_count[i] / sample_ms)*Function2(P1,P2,Pt,x[i],y[i]) Function2(P1,P2,Pt,x[i],y[i])=C2*(1+P1 / Pt)*(1+x[i])*(1+(ipm_meas[i]-ipm_ceil) / ipm _meas[i])*(1-P2 / Pt)*(1-y[i]) Among them, Fcpu[i] is the operating frequency of the i-th processing core, cycle_count[i] is the clock cycle of the i-th processing core, sample_ms is the time interval for the electronic device to obtain the performance information of the N processing cores, P1 is the space proportion of the first control group in the shared cache, P2 is the space proportion of the second control group in the shared cache, Pt is the sum of P1 and P2, x[i] is the operating time proportion of the first control group on the i-th processing core, y[i] is the operating time proportion of the second control group on the i-th processing core, ipm_meas[i] is the shared cache miss rate of the i-th processing core, ipm_ceil is the preset miss rate waterline value, and C2 is the preset second constant.

8. The method according to any one of claims 4 to 7, characterized in that: The user scenario includes a first user scenario and a second user scenario; When the user scenario is the first user scenario, the space proportion of the first control group in the shared cache is the first space proportion, and the space proportion of the second control group in the shared cache is the second space proportion; When the user scenario is the second user scenario, the space proportion of the shared cache of the first control group is the third space proportion, and the space proportion of the shared cache of the second control group is the fourth space proportion; Among them, the first space proportion is smaller than the third space proportion, and the second space proportion is larger than the fourth space proportion.

9. The method according to any one of claims 2 to 8, characterized in that: The method further comprises: In response to the first event, cache partitions of the multiple thread groups in the shared cache are respectively configured according to space occupations of the multiple thread groups in the shared cache.

10. The method according to any one of claims 2 to 9, characterized in that: The resource configuration information also includes a priority of each thread group in the plurality of thread groups for using the shared cache, and the method further includes: The plurality of thread groups are configured according to a priority of each thread group in using the shared cache.

11. The method according to claim 10, characterized in that The thread running information further includes a shared cache miss rate of a first thread, where the first thread is a thread ranked in the top M by load, where M is a positive integer, and the method further includes: Adjust the priority of a second thread in the first thread so that the priority of the second thread is higher than the priorities of other threads in the thread group to which the second thread belongs except the second thread; wherein the second thread is a thread in the first thread whose shared cache miss rate is higher than a first threshold.

12. The method according to any one of claims 3 to 11, characterized in that: For an i-th processing core among the N processing cores, obtaining an operating frequency of the i-th processing core based on the user scenario, the resource configuration information, the performance information of the i-th processing core, and the running time proportions of the multiple thread groups on the i-th processing core, including: For an i-th processing core among the N processing cores, if a shared cache miss rate of the i-th processing core is less than or equal to a miss rate waterline value, an operating frequency of the i-th processing core is obtained based on the user scenario, the resource configuration information, the performance information of the i-th processing core, and the proportion of the running time of the multiple thread groups on the i-th processing core; If the shared cache miss rate of the i-th processing core is greater than the miss rate waterline value, the operating frequency of the i-th processing core is determined according to the rated operating frequency of the i-th processing core.

13. The method according to any one of claims 2 to 11, characterized in that: The resource configuration information also includes a load waterline, and the method further includes: Get system load; The step of setting the operating frequency of the shared cache to a first frequency based on the focus application, user operation information, performance information of each processing core, and thread running information in response to the first event includes: In response to the first event and the system load is less than or equal to the load waterline, multiple thread groups are configured as cache partitions in the shared cache, and the operating frequency of the shared cache is set to the first frequency based on the focus application, user operation information, performance information of each processing core, and thread running information.

14. The method according to claim 13, characterized in that The load waterline includes a first load waterline and a second load waterline. The first load waterline is the load waterline when the user scenario is a first user scenario, and the second load waterline is the load waterline when the user scenario is a second user scenario. The first load waterline is smaller than the second load waterline.

15. An electronic device, characterized in that: The electronic device includes: a memory and a processor, the processor includes a shared cache and N processing cores, where N is an integer greater than or equal to 1; The processor is coupled to the storage; wherein the storage is used to store computer program code, Computer program code includes computer instructions; When the computer instructions are executed by the processor, the electronic device executes the method according to any one of claims 1 to 14.

16. A computer-readable storage medium, characterized in that: The method comprises computer instructions; when the computer instructions are executed on an electronic device, the electronic device is caused to execute the method as claimed in any one of claims 1 to 14.

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