Heterojunction solar cell preparation method

Abstract

A heterojunction solar cell preparation method, belonging to the technical field of solar cells. The method comprises: providing a semiconductor substrate layer; forming on at least one side of the semiconductor substrate layer a doped semiconductor layer; forming a transparent conductive film on the surface of the side of the doped semiconductor layer facing away from the semiconductor substrate layer, the transparent conductive film comprising electrode regions and non-electrode regions, which are alternately arranged in sequence; sequentially forming a metal seed layer and an anti-oxidation layer on the surface of the side of the transparent conductive film facing away from the semiconductor substrate layer; removing the anti-oxidation layer of the electrode regions; forming an electrode on the surface of the side of the metal seed layer of each electrode region facing away from the semiconductor substrate layer; and removing the metal seed layer and the anti-oxidation layer of the non-electrode regions. The formed heterojunction solar cell has small electrode contact resistance and excellent electrode adhesion. Using an etching process enables selective removal of the metal seed layer and the anti-oxidation layer of the non-electrode regions, so that required patterns can be processed without the need for mold making, thus reducing the mold making cost while improving the processing precision and the flatness of substrate layers.

Description

A method for preparing a heterojunction battery

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on October 30, 2023, with application number 202311436318.X and invention name “A method for preparing a heterojunction battery”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the technical field of solar cells, and in particular to a method for preparing a heterojunction cell. Background Art

[0004] In heterojunction cells, metallized electrodes are typically prepared using screen printing technology to collect carriers generated by the photoelectric effect. Due to the specific nature of the heterojunction process, the curing temperature of the metallization paste cannot exceed 250°C, typically ranging from 150-200°C, hence the name "low-temperature paste." Due to the presence of resin, the line resistivity of low-temperature paste is approximately 5μΩ·cm-9μΩ·cm. This compares to the approximately 2μΩ·cm-5μΩ·cm resistivity of the high-temperature sintering paste used in other crystalline silicon cells. Therefore, the power loss in heterojunction cells due to the low-temperature metallization electrodes is significantly greater than that of conventional high-temperature metallization cells.

[0005] Furthermore, due to the inherent properties of silver paste and its sintering characteristics, pores remain after the paste is formed into electrodes. Furthermore, the contact surface between the particles within the electrodes is insufficient. Therefore, even though silver is more conductive than copper, its high-temperature metallization paste resistivity is still higher than that of pure copper. Consequently, copper metal exhibits lower wire and contact resistance, and due to its reduced light-shielding area when patterned, it can improve the conversion efficiency of heterojunction cells. Cost-effective, copper is approximately 1 / 100 of silver, offering a very high cost-performance ratio, thus garnering significant attention from photovoltaic professionals. Copper electroplating's low-temperature characteristics align with the process requirements of heterojunction cells, and the metallization cost of heterojunction cells accounts for approximately 50% of the non-silicon cost. Therefore, copper electroplating and heterojunction cells are a perfect match, both in terms of process and cost.

[0006] In the copper electroplating process of heterojunction batteries, magnetron sputtering (PVD) is generally used to prepare a pure copper seed layer. However, pure copper is very easy to oxidize. The oxidized copper seed layer has a very large impact on the efficiency and adhesion of copper electroplating. Even if acid is used to remove the oxide layer before forming the electrode, since the seed layer itself has been oxidized, the electroplating efficiency and adhesion of the electrode will be deteriorated after pickling.

[0007] Therefore, it is necessary to provide a new method for preparing a heterojunction battery.

[0008] Summary of the Invention

[0009] Therefore, the technical problem to be solved by the present application is to overcome the defects of the prior art heterojunction battery, namely, large contact resistance and poor electrode adhesion, thereby providing a method for preparing a heterojunction battery.

[0010] The present application provides a method for preparing a heterojunction battery, comprising providing a semiconductor substrate layer; forming a doped semiconductor layer on at least one side of the semiconductor substrate layer; forming a transparent conductive film on a surface of the doped semiconductor layer facing away from the semiconductor substrate layer, wherein the transparent conductive film includes an electrode region and a non-electrode region alternately arranged in sequence; forming a stacked metal seed layer and an anti-oxidation layer in sequence on a surface of the transparent conductive film facing away from the semiconductor substrate layer; removing the anti-oxidation layer in the electrode region; forming an electrode on a surface of the metal seed layer in the electrode region facing away from the semiconductor substrate layer; and removing the metal seed layer and the anti-oxidation layer in the non-electrode region by an etching process.

[0011] Optionally, the material of the anti-oxidation layer includes one or more combinations of copper, nickel, and chromium, and the material of the metal seed layer includes one or more combinations of copper, nickel, and chromium. The material of the anti-oxidation layer and the material of the metal seed layer are not selected as the same material at the same time.

[0012] Optionally, the thickness of the anti-oxidation layer is 0.2 to 0.5 times the thickness of the metal seed layer.

[0013] Optionally, the thickness of the metal seed layer is 50 nm-200 nm, and the thickness of the anti-oxidation layer is 10 nm-100 nm.

[0014] Optionally, the process of forming the electrode includes an electroplating process.

[0015] Optionally, the step of removing the anti-oxidation layer of the electrode area includes: using an etching solution to remove the anti-oxidation layer of the electrode area; the step of removing the metal seed layer and the anti-oxidation layer of the non-electrode area includes: using an etching solution to remove the metal seed layer and the anti-oxidation layer of the non-electrode area; the reaction time of the etching solution with the anti-oxidation layer of the electrode area is less than the reaction time of the etching solution with the metal seed layer and the anti-oxidation layer of the non-electrode area.

[0016] Optionally, the etching solution includes sulfuric acid with a mass fraction of 0.2%-5%; the reaction time of the etching solution with the anti-oxidation layer in the electrode area is 2 seconds-10 seconds, and the reaction time of the etching solution with the metal seed layer and the anti-oxidation layer in the non-electrode area is 20 seconds-60 seconds.

[0017] Optionally, the process of forming the metal seed layer includes a physical vapor deposition process; and the process of forming the anti-oxidation layer includes a physical vapor deposition process.

[0018] Optionally, the metal seed layer and the anti-oxidation layer are formed in the same cavity.

[0019] Optionally, the step of forming the doped semiconductor layer includes: forming a first doped semiconductor layer on one side of the semiconductor substrate layer, and / or forming a second doped semiconductor layer on the other side of the semiconductor substrate layer; the step of forming a transparent conductive film on the surface of the doped semiconductor layer facing away from the semiconductor substrate layer includes: forming a first transparent conductive film on the surface of the first doped semiconductor layer facing away from the semiconductor substrate layer, and / or forming a second transparent conductive film on the surface of the second doped semiconductor layer facing away from the semiconductor substrate layer, the first transparent conductive film includes a first electrode area and a first non-electrode area alternately arranged in sequence, and the second transparent conductive film includes a second electrode area and a second non-electrode area alternately arranged in sequence; the step of sequentially forming a stacked metal seed layer and an anti-oxidation layer on the surface of the transparent conductive film facing away from the semiconductor substrate layer includes: sequentially forming layers on the surface of the first transparent conductive film facing away from the semiconductor substrate layer A stacked first metal seed layer and a first anti-oxidation layer are formed, and / or a stacked second metal seed layer and a second anti-oxidation layer are formed in sequence on the surface of the second transparent conductive film on the side away from the semiconductor substrate layer; the step of removing the anti-oxidation layer in the electrode area includes: removing the first anti-oxidation layer in the first electrode area, and / or removing the second anti-oxidation layer in the second electrode area; the step of forming an electrode on the surface of the metal seed layer in the electrode area away from the semiconductor substrate layer includes: forming a first electrode on the surface of the first metal seed layer in the first electrode area away from the semiconductor substrate layer, and / or forming a second electrode on the surface of the second metal seed layer in the second electrode area away from the semiconductor substrate layer; the step of removing the metal seed layer and the anti-oxidation layer in the non-electrode area includes: removing the first metal seed layer and the first anti-oxidation layer in the first non-electrode area, and / or removing the second metal seed layer and the second anti-oxidation layer in the second non-electrode area.

[0020] The technical solution of this application has the following advantages:

[0021] The present application provides a method for preparing a heterojunction battery, comprising: providing a semiconductor substrate layer; forming a doped semiconductor layer on at least one side of the semiconductor substrate layer; forming a transparent conductive film on a surface of the doped semiconductor layer facing away from the semiconductor substrate layer, the transparent conductive film comprising an electrode region and a non-electrode region arranged alternately in sequence; forming a stacked metal seed layer and an anti-oxidation layer on a surface of the transparent conductive film facing away from the semiconductor substrate layer; removing the anti-oxidation layer in the electrode region; forming an electrode on a surface of the metal seed layer in the electrode region facing away from the semiconductor substrate layer; and removing the metal seed layer and the anti-oxidation layer in the non-electrode region using an etching process. Because the anti-oxidation layer can prevent the metal seed layer from oxidizing, before forming the electrode, the anti-oxidation layer in the electrode region is first removed, and then the electrode is formed on a surface of the metal seed layer in the electrode region facing away from the semiconductor substrate layer. Because the electrode is formed directly on the surface of the unoxidized metal seed layer, good contact can be formed between the metal seed layer and the electrode, reducing the contact resistance of the heterojunction battery and improving the conductivity of the heterojunction battery. In summary, the heterojunction battery formed by the above-mentioned method for preparing a heterojunction battery has low contact resistance and good electrode adhesion. The etching process can selectively remove the metal seed layer and anti-oxidation layer in the non-electrode area, so the required pattern can be processed without mold opening, saving mold opening costs. The etching process can also improve processing accuracy and the flatness of the semiconductor substrate layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] FIG1 is a flow chart of a method for preparing a heterojunction battery according to an embodiment of the present application;

[0024] 2-5 are flow charts of a method for preparing a heterojunction battery provided in one embodiment of the present application.

[0025] Description of the drawings; 1-semiconductor substrate layer; 21-first doped semiconductor layer; 22-second doped semiconductor layer; 31-first passivation layer; 32-second passivation layer; 41-first transparent conductive film; 42-second transparent conductive film; 51-first metal seed layer; 52-second metal seed layer; 61-first anti-oxidation layer; 62-second anti-oxidation layer; 71-first electrode; 72-second electrode; M1-first mask; M2-second mask. DETAILED DESCRIPTION

[0026] The following will clearly and completely describe the technical solution of this application in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0027] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0028] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0029] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0030] Example 1

[0031] This embodiment provides a method for preparing a heterojunction battery, which includes the following steps, referring to FIG1 :

[0032] Step S1: providing a semiconductor substrate layer;

[0033] Step S2: forming a doped semiconductor layer on at least one side of the semiconductor substrate layer;

[0034] Step S3: forming a transparent conductive film on a surface of the doped semiconductor layer facing away from the semiconductor substrate layer, wherein the transparent conductive film includes electrode regions and non-electrode regions alternately arranged in sequence;

[0035] Step S4: forming a stacked metal seed layer and an anti-oxidation layer in sequence on the surface of the transparent conductive film on the side facing away from the semiconductor substrate layer;

[0036] Step S5: removing the anti-oxidation layer in the electrode area;

[0037] Step S6: forming an electrode on a surface of the metal seed layer in the electrode region facing away from the semiconductor substrate layer;

[0038] Step S7: using an etching process to remove the metal seed layer and the anti-oxidation layer in the non-electrode area.

[0039] The preparation method of the heterojunction battery provided in this embodiment, since the anti-oxidation layer can prevent the metal seed layer from oxidizing, before forming the electrode, the anti-oxidation layer in the electrode area is first removed, and then the electrode is formed on the surface of the metal seed layer in the electrode area away from the semiconductor substrate layer. Because the electrode is directly formed on the surface of the metal seed layer that has not been oxidized, good contact can be formed between the metal seed layer and the electrode, reducing the contact resistance of the heterojunction battery and improving the conductivity of the heterojunction battery. In summary, the heterojunction battery formed by the preparation method of the heterojunction battery has a low contact resistance and good electrode adhesion. The use of an etching process can selectively remove the metal seed layer and the anti-oxidation layer in the non-electrode area, so the required pattern can be processed without mold opening, saving mold opening costs, and the etching process can improve processing accuracy and improve the flatness of the semiconductor substrate layer.

[0040] In step S1, referring to FIG2 , a semiconductor substrate layer 1 is provided. Specifically, the semiconductor substrate layer 1 is subjected to a texturing treatment. In one embodiment, the light-receiving surface of the semiconductor substrate layer is subjected to the texturing treatment. In other embodiments, both the light-receiving surface and the backlight surface of the semiconductor substrate layer are subjected to the texturing treatment. The texturing treatment utilizes a high-temperature, low-concentration alkaline solution to treat the semiconductor substrate layer with different crystal orientation etching rates, thereby forming a pyramid-textured light-trapping structure on the surface of the semiconductor substrate layer, which is beneficial for increasing the reflectivity of the heterojunction battery by 9%-11%.

[0041] In step S2, the step of forming the doped semiconductor layer includes: forming a first doped semiconductor layer on one side of the semiconductor substrate layer, and / or forming a second doped semiconductor layer on the other side of the semiconductor substrate layer. Specifically, the step of forming the doped semiconductor layer includes: forming the first doped semiconductor layer on one side of the semiconductor substrate layer, or forming the second doped semiconductor layer on the other side of the semiconductor substrate layer, or forming the first doped semiconductor layer on one side of the semiconductor substrate layer and forming the second doped semiconductor layer on the other side of the semiconductor substrate layer.

[0042] In one embodiment, with continued reference to FIG. 2 , the step of forming the doped semiconductor layer includes: forming a first doped semiconductor layer 21 on one side of the semiconductor substrate layer 1 and forming a second doped semiconductor layer 22 on the other side of the semiconductor substrate layer 1 .

[0043] In one embodiment, the process of forming the first doped semiconductor layer 21 includes a plasma enhanced chemical vapor deposition process, and the process of forming the second doped semiconductor layer 22 includes a plasma enhanced chemical vapor deposition process.

[0044] In one embodiment, the material of the first doped semiconductor layer 21 includes amorphous silicon, nanocrystalline silicon, oxygen-doped amorphous silicon, oxygen-doped nanocrystalline silicon, carbon-doped amorphous silicon, or carbon-doped nanocrystalline silicon doped with first conductive ions.

[0045] In one embodiment, the thickness of the first doped semiconductor layer 21 is 5 nm-40 nm, for example, 10 nm, 25 nm, 30 nm or 35 nm.

[0046] In one embodiment, the material of the second doped semiconductor layer 22 includes amorphous silicon, nanocrystalline silicon, oxygen-doped amorphous silicon, oxygen-doped nanocrystalline silicon, carbon-doped amorphous silicon, or carbon-doped nanocrystalline silicon doped with second conductive ions.

[0047] In one embodiment, the thickness of the second doped semiconductor layer 22 is 5 nm-50 nm, for example, 10 nm, 25 nm, 30 nm, or 35 nm.

[0048] In one embodiment, before forming the doped semiconductor layer on at least one side of the semiconductor substrate layer, the method further includes: forming a passivation layer on at least one side of the semiconductor substrate layer; the step of forming the passivation layer includes: forming a first passivation layer on one side of the semiconductor substrate layer, and / or forming a second passivation layer on the other side of the semiconductor substrate layer. Specifically, forming the passivation layer on at least one side of the semiconductor substrate layer includes: forming the first passivation layer on one side of the semiconductor substrate layer, or forming the second passivation layer on the other side of the semiconductor substrate layer, or forming the first passivation layer on one side of the semiconductor substrate layer and forming the second passivation layer on the other side of the semiconductor substrate layer. After forming the first doped semiconductor layer, the first passivation layer is located between the semiconductor substrate layer and the first doped semiconductor layer, and after forming the second doped semiconductor layer, the second passivation layer is located between the semiconductor substrate layer and the second doped semiconductor layer.

[0049] In one embodiment, referring to FIG. 2 , forming a passivation layer on at least one surface of the semiconductor substrate layer includes forming a first passivation layer 31 on one surface of the semiconductor substrate layer 1 and forming a second passivation layer 32 on the other surface of the semiconductor substrate layer 1 .

[0050] In one embodiment, the process of forming the first passivation layer 31 includes a plasma enhanced chemical vapor deposition process, and the process of forming the second passivation layer 32 includes a plasma enhanced chemical vapor deposition process.

[0051] In one embodiment, the material of the first passivation layer 31 includes amorphous silicon or nanocrystalline silicon, and the material of the second passivation layer 32 includes amorphous silicon or nanocrystalline silicon.

[0052] In one embodiment, the thickness of the first passivation layer 31 is 1 nm to 10 nm, such as 3 nm, 6 nm, 8 nm or 9 nm. The thickness of the second passivation layer 32 is 1 nm to 10 nm, such as 3 nm, 6 nm, 8 nm or 9 nm.

[0053] In step S3, the step of forming a transparent conductive film on the surface of the doped semiconductor layer facing away from the semiconductor substrate layer includes: forming a first transparent conductive film on the surface of the first doped semiconductor layer facing away from the semiconductor substrate layer, and / or forming a second transparent conductive film on the surface of the second doped semiconductor layer facing away from the semiconductor substrate layer, the first transparent conductive film including a first electrode region and a first non-electrode region alternately arranged in sequence, and the second transparent conductive film including a second electrode region and a second non-electrode region alternately arranged in sequence. Specifically, the step of forming a transparent conductive film on the surface of the doped semiconductor layer facing away from the semiconductor substrate layer includes: forming the first transparent conductive film on the surface of the first doped semiconductor layer facing away from the semiconductor substrate layer, or forming the second transparent conductive film on the surface of the second doped semiconductor layer facing away from the semiconductor substrate layer, or forming the first transparent conductive film on the surface of the first doped semiconductor layer facing away from the semiconductor substrate layer and forming the second transparent conductive film on the surface of the second doped semiconductor layer facing away from the semiconductor substrate layer.

[0054] In one embodiment, referring to Figure 2 , the step of forming a transparent conductive film on the surface of the doped semiconductor layer facing away from the semiconductor substrate layer includes: forming a first transparent conductive film 41 on the surface of the first doped semiconductor layer 21 facing away from the semiconductor substrate layer 1 and forming a second transparent conductive film 42 on the surface of the second doped semiconductor layer 22 facing away from the semiconductor substrate layer 1.

[0055] In one embodiment, the process of forming the first transparent conductive film 41 includes a physical vapor deposition process, and the process of forming the second transparent conductive film 42 includes a physical vapor deposition process.

[0056] In one embodiment, the thickness of the first transparent conductive film 41 is 80 nm-90 nm, for example, 85 nm; the thickness of the second transparent conductive film 42 is 90 nm-120 nm, for example, 95 nm.

[0057] In step S4, the step of sequentially forming a stacked metal seed layer and an anti-oxidation layer on the surface of the side of the transparent conductive film facing away from the semiconductor substrate layer includes: sequentially forming a stacked first metal seed layer and a first anti-oxidation layer on the surface of the first transparent conductive film facing away from the semiconductor substrate layer, and / or sequentially forming a stacked second metal seed layer and a second anti-oxidation layer on the surface of the second transparent conductive film facing away from the semiconductor substrate layer. Specifically, the step of sequentially forming a stacked metal seed layer and an anti-oxidation layer on the surface of the side of the transparent conductive film facing away from the semiconductor substrate layer includes: sequentially forming a stacked first metal seed layer and a first anti-oxidation layer on the surface of the first transparent conductive film facing away from the semiconductor substrate layer, or sequentially forming a stacked second metal seed layer and a second anti-oxidation layer on the surface of the second transparent conductive film facing away from the semiconductor substrate layer, or sequentially forming a stacked first metal seed layer and a first anti-oxidation layer on the surface of the first transparent conductive film facing away from the semiconductor substrate layer, and sequentially forming a stacked second metal seed layer and a second anti-oxidation layer on the surface of the second transparent conductive film facing away from the semiconductor substrate layer.

[0058] In one embodiment, referring to FIG3 , the step of sequentially forming a stacked metal seed layer and an anti-oxidation layer on the surface of the transparent conductive film facing away from the semiconductor substrate layer includes: sequentially forming a stacked first metal seed layer 51 and a first anti-oxidation layer 61 on the surface of the first transparent conductive film 41 facing away from the semiconductor substrate layer 1, and sequentially forming a stacked second metal seed layer 52 and a second anti-oxidation layer 62 on the surface of the second transparent conductive film 42 facing away from the semiconductor substrate layer.

[0059] In one embodiment, the process of forming the metal seed layer includes a physical vapor deposition process, and the process of forming the anti-oxidation layer includes a physical vapor deposition process.

[0060] In one embodiment, the thickness of the anti-oxidation layer is 0.2 to 0.5 times, for example, 0.3 times, the thickness of the metal seed layer.

[0061] In one embodiment, the material of the anti-oxidation layer includes one or more of copper, nickel, and chromium. In other embodiments, the material of the metal seed layer may also include other metal elements or mixed metals.

[0062] In one embodiment, the material of the metal seed layer includes one or more of copper, nickel, or chromium. The material of the anti-oxidation layer and the material of the metal seed layer are different. In other embodiments, the material of the metal seed layer may also include other metal elements or mixed metals.

[0063] In one embodiment, the thickness of the metal seed layer is 50nm-200nm, for example, 55nm, 60nm, 70nm, 85nm, 120nm, 180nm; if the thickness of the metal seed layer is less than 50nm, the effect of improving the electrode adhesion and conductivity is not obvious; if the thickness of the metal seed layer is greater than 200nm, it not only wastes resources but also increases the time to form the metal seed layer.

[0064] In one embodiment, the thickness of the anti-oxidation layer is 10nm-100nm, for example, 20nm, 25nm, 50nm, 65nm, 75nm, 80nm; if the thickness of the anti-oxidation layer is less than 10nm, the effect of preventing the metal seed layer from oxidizing is not obvious; if the thickness of the anti-oxidation layer is greater than 100nm, resources are wasted.

[0065] In one embodiment, the metal seed layer and the anti-oxidation layer are formed in the same chamber. Specifically, a target is added to the chamber of the physical vapor deposition process equipment. This simplifies the process and improves the efficiency of heterojunction cell fabrication. It also helps isolate oxygen during the formation of the anti-oxidation layer, preventing oxidation of the metal seed layer caused by changing the chamber or target material.

[0066] In step S5, the step of removing the anti-oxidation layer in the electrode region includes: removing the first anti-oxidation layer in the first electrode region, and / or removing the second anti-oxidation layer in the second electrode region. Specifically, the step of removing the anti-oxidation layer in the electrode region includes: removing the first anti-oxidation layer in the first electrode region, or removing the second anti-oxidation layer in the second electrode region, or removing the first anti-oxidation layer in the first electrode region and removing the second anti-oxidation layer in the second electrode region.

[0067] In step S5, removing the anti-oxidation layer from the electrode region includes removing the anti-oxidation layer from the electrode region using an etching solution. The etching solution includes sulfuric acid having a mass fraction of 0.2% to 5%, such as 1%, 2%, or 4%. The reaction time between the etching solution and the anti-oxidation layer from the electrode region is 2 seconds to 10 seconds, such as 5 seconds, 7 seconds, or 8 seconds.

[0068] In one embodiment, referring to Figure 4, the anti-oxidation layer of the electrode area is removed, and the steps include: using an etching solution to remove the first anti-oxidation layer of the first electrode area and the second anti-oxidation layer of the second electrode area, the etching solution includes sulfuric acid, the mass fraction of sulfuric acid is 4%, the reaction time of the etching solution with the first anti-oxidation layer of the first electrode area is 8 seconds, and the reaction time of the etching solution with the second anti-oxidation layer of the second electrode area is 8 seconds.

[0069] In step S6, the step of forming an electrode on a surface of the metal seed layer in the electrode region facing away from the semiconductor substrate layer includes: forming a first electrode on a surface of the first metal seed layer in the first electrode region facing away from the semiconductor substrate layer, and / or forming a second electrode on a surface of the second metal seed layer in the second electrode region facing away from the semiconductor substrate layer. Specifically, the step of forming an electrode on a surface of the metal seed layer in the electrode region facing away from the semiconductor substrate layer includes: forming the first electrode on a surface of the first metal seed layer in the first electrode region facing away from the semiconductor substrate layer, or forming the second electrode on a surface of the second metal seed layer in the second electrode region facing away from the semiconductor substrate layer, or forming the first electrode on a surface of the first metal seed layer in the first electrode region facing away from the semiconductor substrate layer and forming the second electrode on a surface of the second metal seed layer in the second electrode region facing away from the semiconductor substrate layer.

[0070] In one embodiment, the process for forming the electrode includes an electroplating process. The material of the electrode includes copper, which facilitates good contact between the electrode and the metal seed layer.

[0071] In one embodiment, the width of the electrode is 5 μm-30 μm, for example, 10 μm, 20 μm or 25 μm.

[0072] In one embodiment, the height of the electrodes is 5 μm-25 μm, for example 10 μm, 15 μm or 20 μm.

[0073] In one embodiment, referring to Figure 4, an electrode is formed on the surface of the metal seed layer in the electrode area facing away from the semiconductor substrate layer, and the steps include: forming a first electrode 71 on the surface of the first metal seed layer 51 in the first electrode area facing away from the semiconductor substrate layer 1, and forming a second electrode 72 on the surface of the second metal seed layer 52 in the second electrode area facing away from the semiconductor substrate layer 1.

[0074] In step S7, the step of removing the metal seed layer and the anti-oxidation layer of the non-electrode region includes: removing the first metal seed layer and the first anti-oxidation layer of the first non-electrode region, and / or removing the second metal seed layer and the second anti-oxidation layer of the second non-electrode region. Specifically, the step of removing the metal seed layer and the anti-oxidation layer of the non-electrode region includes: removing the first metal seed layer and the first anti-oxidation layer of the first non-electrode region, or removing the second metal seed layer and the second anti-oxidation layer of the second non-electrode region, or removing the first metal seed layer and the first anti-oxidation layer of the first non-electrode region and removing the second metal seed layer and the second anti-oxidation layer of the second non-electrode region.

[0075] In one embodiment, an etching solution is used to remove the metal seed layer and the anti-oxidation layer in the non-electrode area, and the reaction time of the etching solution with the anti-oxidation layer in the electrode area is less than the reaction time of the etching solution with the metal seed layer and the anti-oxidation layer in the non-electrode area. The etching solution includes sulfuric acid, and the mass fraction of sulfuric acid is 0.2%-5%, for example, 1.2%, 2%, 3% or 4%. The reaction time of the etching solution with the metal seed layer and the anti-oxidation layer in the non-electrode area is 20 seconds-60 seconds, for example, 30 seconds, 40 seconds or 50 seconds.

[0076] In one embodiment, a photoresist having a specific shape is stacked on the metal seed layer and the anti-oxidation layer in the non-electrode region, and the metal seed layer and the anti-oxidation layer covered by the photoresist are removed by plasma etching, sputter etching or reactive ion etching.

[0077] In one embodiment, referring to FIG. 5 , the first metal seed layer 51 and the first oxidation protection layer 61 of the first non-electrode region are removed, and the second metal seed layer 52 and the second oxidation protection layer 62 of the second non-electrode region are removed.

[0078] In one embodiment, the etching solution reacts with the first metal seed layer and the first anti-oxidation layer in the first non-electrode region for 30 seconds; the etching solution reacts with the second metal seed layer and the second anti-oxidation layer in the second non-electrode region for 30 seconds. The etching solution comprises sulfuric acid at a mass fraction of 4%. In other embodiments, the etching solution may also be other types of acidic solutions.

[0079] In one embodiment, before removing the anti-oxidation layer in the electrode region, the process further includes forming a mask on a surface of the anti-oxidation layer in the non-electrode region facing away from the semiconductor substrate layer, whereby the mask exposes the anti-oxidation layer in the electrode region. Specifically, referring to FIG4 , a first mask M1 is formed on a surface of the first anti-oxidation layer 61 in the first non-electrode region facing away from the semiconductor substrate layer 1, and a second mask M2 is formed on a surface of the second anti-oxidation layer 62 in the second non-electrode region facing away from the semiconductor substrate layer 1.

[0080] In one embodiment, the mask is a dry film.

[0081] In another embodiment, the mask is a wet film, and the wet film needs to be dried before forming the electrode.

[0082] In another embodiment, the mask is formed by printing.

[0083] In one embodiment, the width of the pattern of the mask is 5 μm-30 μm, such as 10 μm, 20 μm or 25 μm, and the height of the pattern of the mask is 5 μm-25 μm, such as 10 μm, 15 μm or 20 μm.

[0084] The preparation method of the heterojunction battery further includes: after forming an electrode on the surface of the metal seed layer in the electrode area facing away from the semiconductor substrate layer, and before removing the metal seed layer and the anti-oxidation layer in the non-electrode area, it also includes: removing the mask.

[0085] In one embodiment, the mask is removed by soaking in an alkaline solution, the alkaline solution includes a sodium hydroxide solution or a potassium hydroxide solution, the mass fraction concentration of the alkaline solution is 1%-5%, and the soaking time is 1 min-5 min, for example, 3 min.

[0086] Comparative Example 1

[0087] The preparation method of the heterojunction battery provided in this comparative example is different from the preparation method of the heterojunction battery provided in Example 1 in that the preparation method of the heterojunction battery provided in this comparative example does not include: forming an anti-oxidation layer, and the preparation method of the heterojunction battery provided in this comparative example includes: before forming an electrode in the electrode area, performing hydrogen plasma treatment on the metal seed layer to remove the oxide layer and dirt on the surface of the metal seed layer, and then forming the electrode.

[0088] Comparative Example 2

[0089] The preparation method of the heterojunction battery provided in this comparative example is different from the preparation method of the heterojunction battery provided in Example 1 in that the heterojunction battery provided in this comparative example does not include: forming an anti-oxidation layer. The preparation method of the heterojunction battery provided in this comparative example includes: before forming an electrode in the electrode area, forming a protective layer on the surface of the metal seed layer away from the semiconductor substrate layer, the material of the protective layer includes a mixture of copper and copper oxide, and then removing the copper oxide in the protective layer to form a hollow copper film, and then forming an electrode, and filling the hollow area during the process of forming the electrode.

[0090] Test Example 1

[0091] Although the preparation method of the heterojunction battery provided in Comparative Example 1 can remove the oxide layer and surface dirt on the surface of the metal seed layer, it will also damage the surface of the metal seed layer and contaminate the cavity of the plasma processing equipment. After removing the oxide layer on the surface of the metal seed layer, the metal seed layer will also be oxidized. Therefore, it cannot solve the oxidation problem in the long term. For mass production, the plasma processing equipment, process and cost will increase.

[0092] In the preparation method of the heterojunction battery provided in Comparative Example 1, the presence of copper oxide in the protective layer on the surface of the metal seed layer is not conducive to the formation of the electrode, and copper oxidation cannot protect the metal seed layer. When the copper oxide is removed, the metal seed layer will be destroyed, causing the adhesion and contact resistance of the electrode to deteriorate.

[0093] The method for preparing a heterojunction battery provided in Example 1 can completely prevent the metal seed layer from being oxidized and is very easy to mass-produce.

[0094] This test example tested the heterojunction cells formed in Example 1, Comparative Example 1, and Comparative Example 2. Compared with the heterojunction cell formed in Comparative Example 1, the heterojunction cell formed in Example 1 had a 10% relative improvement in electrode plating efficiency, and a 50% relative reduction in contact resistance. Compared with the heterojunction cell formed in Comparative Example 2, the heterojunction cell formed in Example 1 had a 50% relative reduction in contact resistance.

[0095] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A method for preparing a heterojunction battery, characterized in that: include: providing a semiconductor substrate layer; forming a doped semiconductor layer on at least one side of the semiconductor substrate layer; Forming a transparent conductive film on a surface of the doped semiconductor layer facing away from the semiconductor substrate layer, wherein the transparent conductive film comprises electrode regions and non-electrode regions alternately arranged in sequence; Forming a stacked metal seed layer and an anti-oxidation layer in sequence on a surface of the transparent conductive film on a side away from the semiconductor substrate layer; removing the anti-oxidation layer of the electrode area; forming an electrode on a surface of the metal seed layer in the electrode region facing away from the semiconductor substrate layer; The metal seed layer and the anti-oxidation layer in the non-electrode area are removed by an etching process.

2. The method for preparing a heterojunction battery according to claim 1, characterized in that: The material of the anti-oxidation layer includes one or more combinations of copper, nickel, and chromium, and the material of the metal seed layer includes one or more combinations of copper, nickel, and chromium. The material of the anti-oxidation layer and the material of the metal seed layer are not selected to be the same material at the same time.

3. The method for preparing a heterojunction battery according to claim 1, characterized in that: The thickness of the anti-oxidation layer is 0.2 to 0.5 times the thickness of the metal seed layer.

4. The method for preparing a heterojunction battery according to claim 1, characterized in that: The thickness of the metal seed layer is 50nm-200nm, and the thickness of the anti-oxidation layer is 10nm-100nm.

5. The method for preparing a heterojunction battery according to claim 1, characterized in that: The process of forming the electrodes includes an electroplating process.

6. The method for preparing a heterojunction battery according to claim 1, characterized in that: The step of removing the anti-oxidation layer of the electrode region comprises: removing the anti-oxidation layer of the electrode region by using an etching solution; The step of removing the metal seed layer and the anti-oxidation layer in the non-electrode area comprises: removing the metal seed layer and the anti-oxidation layer in the non-electrode area by using an etching solution; The reaction time between the etching solution and the anti-oxidation layer in the electrode area is shorter than the reaction time between the etching solution and the metal seed layer and the anti-oxidation layer in the non-electrode area.

7. The method for preparing a heterojunction battery according to claim 6, characterized in that: The etching solution includes sulfuric acid, and the mass fraction of the sulfuric acid is 0.2%-5%; The reaction time between the etching solution and the anti-oxidation layer in the electrode area is 2 seconds to 10 seconds, and the reaction time between the etching solution and the metal seed layer and the anti-oxidation layer in the non-electrode area is 20 seconds to 60 seconds.

8. The method for preparing a heterojunction battery according to claim 1, characterized in that: The process of forming the metal seed layer includes a physical vapor deposition process; the process of forming the anti-oxidation layer includes a physical vapor deposition process.

9. The method for preparing a heterojunction battery according to claim 1, characterized in that: The metal seed layer and the anti-oxidation layer are formed in the same cavity.

10. The method for preparing a heterojunction battery according to claim 1, characterized in that: The step of forming the doped semiconductor layer comprises: forming a first doped semiconductor layer on one side of the semiconductor substrate layer, and / or forming a second doped semiconductor layer on the other side of the semiconductor substrate layer; The step of forming a transparent conductive film on a surface of the doped semiconductor layer facing away from the semiconductor substrate layer comprises: forming a first transparent conductive film on a surface of the first doped semiconductor layer facing away from the semiconductor substrate layer, and / or forming a second transparent conductive film on a surface of the second doped semiconductor layer facing away from the semiconductor substrate layer, wherein the first transparent conductive film comprises a first electrode region and a first non-electrode region which are alternately arranged in sequence, and the second transparent conductive film comprises a second electrode region and a second non-electrode region which are alternately arranged in sequence; The step of sequentially forming a stacked metal seed layer and an anti-oxidation layer on a surface of the transparent conductive film facing away from the semiconductor substrate layer comprises: sequentially forming a stacked first metal seed layer and a first anti-oxidation layer on a surface of the first transparent conductive film facing away from the semiconductor substrate layer, and / or sequentially forming a stacked second metal seed layer and a second anti-oxidation layer on a surface of the second transparent conductive film facing away from the semiconductor substrate layer; The step of removing the anti-oxidation layer of the electrode region comprises: removing the first anti-oxidation layer of the first electrode region, and / or removing the second anti-oxidation layer of the second electrode region; The step of forming an electrode on a surface of the metal seed layer in the electrode region facing away from the semiconductor substrate layer comprises: forming a first electrode on a surface of the first metal seed layer in the first electrode region facing away from the semiconductor substrate layer, and / or forming a second electrode on a surface of the second metal seed layer in the second electrode region facing away from the semiconductor substrate layer; The step of removing the metal seed layer and the anti-oxidation layer in the non-electrode area includes: removing the first metal seed layer and the first anti-oxidation layer in the first non-electrode area, and / or removing the second metal seed layer and the second anti-oxidation layer in the second non-electrode area.

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