High-speed comparator circuit with rail-to-rail input and push-pull output

Abstract

Disclosed in the present invention is a high-speed comparator circuit with rail-to-rail input and push-pull output. The high-speed comparator circuit comprises a rail-to-rail input stage circuit, a low-power-supply inverter circuit, and a level shifter output circuit. The output end of the rail-to-rail input stage circuit is electrically connected to the input end of the low-power-supply inverter circuit, and the output end of the low-power-supply inverter circuit is electrically connected to the input end of the level shifter output circuit. The rail-to-rail input stage circuit comprises a folded cascode input circuit and an amplitude-limiting circuit; the output end of the folded cascode input circuit is electrically connected to the input end of the amplitude-limiting circuit; the folded cascode input circuit performs amplification and full-differential processing on two input signals of the positive and negative input ends of the comparator, so that the input common-mode range reaches rail-to-rail; and the amplitude-limiting circuit limits the amplitude of differential-mode signal output. By constructing a 'high voltage-low voltage-high voltage' working mode, maximum speed increase is achieved; furthermore, the present invention has low power consumption and significantly shortens the delay of the comparator.

Description

A high-speed comparator circuit with rail-to-rail input and push-pull output Technical Field

[0001] The present invention relates to the field of comparators, and in particular to a high-speed comparator circuit with rail-to-rail input and push-pull output. Background Art

[0002] In integrated circuit systems, comparators are fundamental analog circuit modules, with high-speed comparators widely used in fields like lidar and sensors. A comparator's primary function is to compare two input signals. If the positive input voltage is greater than the negative input voltage, the output is high; otherwise, the output is low. A comparator typically uses a preamplifier stage and a latch structure with a push-pull output. This architecture requires greater power consumption under the same conditions to achieve higher speeds, while also requiring a larger device size, resulting in a larger circuit layout and higher costs. Technical issues

[0003] In order to overcome the shortcomings of the existing technology, the present invention provides a high-speed comparator circuit with rail-to-rail input and push-pull output. To address the problems that traditional high-speed comparators require high power consumption and high cost, a newly constructed "high-low-high" circuit module is used to form a high-speed static comparator, which greatly shortens the delay, improves the speed of the comparator, and greatly reduces power consumption. Technical Solutions

[0004] To achieve the above objectives, the present invention provides a high-speed comparator with rail-to-rail input and push-pull output, comprising a rail-to-rail input stage circuit, a low-power inverter circuit, and a level converter output circuit; the output end of the rail-to-rail input stage circuit is electrically connected to the input end of the low-power inverter circuit, and the output end of the low-power inverter circuit is electrically connected to the input end of the level converter output circuit; the rail-to-rail input stage circuit comprises a folded cascode input circuit and a limiter circuit; the output end of the folded cascode input circuit is electrically connected to the input end of the limiter circuit; the folded cascode input circuit amplifies and fully differentially processes the two input signals at the positive and negative input ends of the comparator, so that the input common-mode range reaches rail-to-rail, and the limiter circuit limits the amplitude of the differential-mode signal output.

[0005] Furthermore, the folded common-source common-gate input circuit includes an INP input terminal, an INN input terminal, a differential circuit and a common-source common-gate circuit; the output terminal of the differential circuit is electrically connected to the input terminal of the common-source common-gate circuit, and the differential circuit includes an MP1 transistor, an MP2 transistor, an MN1 transistor and an MN2 transistor; the gates of the MN1 transistor and the MP1 transistor are electrically connected to the INP input terminal, and the gates of the MN2 transistor and the MP2 transistor are electrically connected to the INN input terminal; the source of the MP1 transistor and the source of the MP2 transistor are electrically connected to the VDD power supply, and the drains of the MP1 transistor, MN1 transistor, MP2 transistor and MN2 transistor all serve as the output terminal of the differential circuit.

[0006] Further, the cascode circuit includes an MP3 transistor, an MP4 transistor, an MP5 transistor, an MP6 transistor, an MN3 transistor, an MN4 transistor, an MN5 transistor, and an MN6 transistor; the drain of the MP3 transistor is electrically connected to the source of the MP5 transistor, and the drain of the MP4 transistor is electrically connected to the source of the MP6 transistor; the gate of the MP3 transistor is electrically connected to the gate of the MP4 transistor, the gate of the MP5 transistor is electrically connected to the gate of the MP6 transistor, and the sources of the MP3 transistor and the MP4 transistor are electrically connected to the VDD power supply; the source of the MP5 transistor is electrically connected to the drain of the MN2 transistor, and the source of the MP6 transistor is electrically connected to the drain of the MN1 transistor;

[0007] The source of the MN3 transistor is electrically connected to the drain of the MN5 transistor, and the source of the MN4 transistor is electrically connected to the drain of the MN6 transistor; the gate of the MN3 transistor is electrically connected to the gate of the MN4 transistor, and the gate of the MN5 transistor is electrically connected to the gate of the MN6 transistor, and the sources of the MN5 transistor and the MN6 transistor are both electrically connected to VSS; the source of the MN3 transistor is electrically connected to the drain of the MP2 transistor, and the source of the MN4 transistor is electrically connected to the drain of the MP1 transistor; the drains of the MP5 transistor, the MP6 transistor, the MN3 transistor, and the MN4 transistor all serve as output ends of the folded common-source input circuit.

[0008] Furthermore, the limiting circuit includes a D1 diode and a D2 diode; the anode of the D1 diode is electrically connected to the cathode of the D2 diode, and the cathode of the D1 diode and the anode of the D2 diode are both electrically connected to the gate of the MN5 transistor; the anode of the D1 diode is electrically connected to the drain of the MP6 transistor, and the cathode of the D1 diode is electrically connected to the drain of the MP5 transistor; the anode of the D2 diode is electrically connected to the drain of the MN3 transistor, and the cathode of the D2 diode is electrically connected to the drain of the MN4 transistor; the anode of the D1 diode and the cathode of the D2 diode serve as the VR output terminal and the VL output terminal, respectively.

[0009] Furthermore, the low power inverter circuit includes an MP7 transistor, an MP8 transistor, an MP9 transistor, an MP10 transistor, an MN7 transistor, an MN8 transistor, an MN9 transistor and an MN10 transistor; the drain of the MP7 transistor is electrically connected to the drain of the MN7 transistor through a resistor, the drain of the MP7 transistor is electrically connected to the gate of the MP8 transistor, and the drain of the MN7 transistor is electrically connected to the gate of the MN8 transistor; the drain of the MP8 transistor is electrically connected to the drain of the MN8 transistor; the drain of the MP9 transistor is electrically connected to the drain of the MN9 transistor through a resistor, the drain of the MP9 transistor is electrically connected to the gate of the MP10 transistor, and the drain of the MN9 transistor is electrically connected to the gate of the MN10 transistor; the drain of the MP10 transistor is electrically connected to the drain of the MN10 transistor.

[0010] Furthermore, the sources of the MP7 transistor, the MP8 transistor, the MP9 transistor, and the MP10 transistor are electrically connected to the low power supply generated by the LDO low-voltage difference linear regulator; the gates of the MP7 transistor and the MN7 transistor are electrically connected to the VR output terminal, and the gates of the MP9 transistor and the MN9 transistor are electrically connected to the VR output terminal; the drain of the MP8 transistor serves as the OUTB output terminal, and the drain of the MP10 transistor serves as the OUTD output terminal.

[0011] Furthermore, the level converter output circuit includes an MP11 transistor, an MP12 transistor, an MP13 transistor, an MP14 transistor, an MP15 transistor, an MP16 transistor, an MN11 transistor, an MN12 transistor, an MN13 transistor, and an MN14 transistor; the gate of the MP16 transistor, the gate of the MN14 transistor, the drain of the MP11 transistor, the drain of the MP12 transistor, and the gate of the MP13 transistor are all electrically connected to the drain of the MN11 transistor; the gate of the MP15 transistor, the gate of the MN13 transistor, the drain of the MP14 transistor, the drain of the MP13 transistor, and the gate of the MP12 transistor are all electrically connected to the drain of the MN12 transistor; the drain of the MP16 transistor is electrically connected to the drain of the MN14 transistor, and the drain of the MP15 transistor is electrically connected to the drain of the MN13 transistor.

[0012] Furthermore, the sources of the MP16 transistor, the MP11 transistor, the MP12 transistor, the MP13 transistor, the MP14 transistor, and the MP15 transistor are electrically connected to the VDD power supply; the gate of the MN11 transistor is electrically connected to the OUTB output terminal, and the gate of the MN12 transistor is electrically connected to the OUTD output terminal; the drain of the MP16 transistor serves as the OUTB-CMP output terminal, which is electrically connected to the gate of the MP14 transistor; the drain of the MP15 transistor serves as the OUT-CMP output terminal, which is electrically connected to the gate of the MP11 transistor; and the OUT-CMP output terminal serves as the final output terminal of the high-speed comparator. Beneficial effects

[0013] The high-speed comparator circuit with rail-to-rail input and push-pull output of the present invention has more symmetrical input stage circuits on both sides compared with traditional high-speed comparators, which greatly reduces the mismatch caused by system asymmetry; at the same time, it saves clock signals and can basically achieve the transmission delay of the dynamic comparator by using a static comparator architecture; the invention achieves maximum speed improvement by constructing a "high voltage-low voltage-high voltage" working mode. At the same time, the power consumption of the present invention is low, only at the microampere level, and the delay is greatly shortened, which is better than traditional analog comparators. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a high-speed comparator circuit with track input and push-pull output;

[0015] Figure 2 is a rail-to-rail input stage circuit;

[0016] Figure 3 is a connection circuit diagram of the limiter circuit and the folded cascode input circuit;

[0017] Figure 4 is a low power inverter circuit;

[0018] Figure 5 is a level converter output circuit;

[0019] FIG6 is a dynamic timing diagram of the limiter circuit to save delay. Modes for Carrying Out the Invention

[0020] The present invention will be further described below with reference to the accompanying drawings.

[0021] As shown in FIG1 , a high-speed comparator with rail-to-rail input and push-pull output includes a rail-to-rail input stage circuit 1, a low-power inverter circuit 2, and a level converter output circuit 3; the output end of the rail-to-rail input stage circuit 1 is electrically connected to the input end of the low-power inverter circuit 2, and the output end of the low-power inverter circuit 2 is electrically connected to the input end of the level converter output circuit 3; the rail-to-rail input stage circuit 1 includes a folded cascode input circuit 4 and a limiter circuit 5; the output end of the folded cascode input circuit 4 is electrically connected to the input end of the limiter circuit 5, the folded cascode input circuit 4 amplifies and fully differentially processes the two input signals at the positive and negative input ends of the comparator, so that the input common-mode range reaches rail-to-rail, and the limiter circuit 5 limits the amplitude of the differential-mode signal output.

[0022] The folded cascode input circuit 4 serves as the high-voltage module input stage of the "high-low-high" structure of the high-speed comparator. Two differential pairs are set to ensure rail-to-rail input. The folded cascode input circuit 4 is powered by the actual power supply voltage VDD; the output stage of the folded cascode input circuit 4 is connected to the limiter circuit 5 to limit the amplitude of the differential mode signal output; the output end of the limiter circuit 5 serves as the output end of the rail-to-rail input stage circuit, and the low-power inverter circuit 2 uses the low power generated by the LDO low-voltage difference linear regulator circuit to power a group of inverters, while increasing the driving capability to continue driving the next stage circuit. The output of the limiter circuit 5 is directly input to the low-power inverter circuit 2, thereby saving the signal transmission delay to the greatest extent; finally, the output of the low-power inverter circuit 2 is boosted to the VDD power supply voltage through the level converter output circuit 3, thereby achieving a large drive output.

[0023] As shown in FIG2 , the folded cascode input circuit 4 includes an INP input terminal 7, an INN input terminal 8, a differential circuit and a cascode circuit; the output terminal of the differential circuit is electrically connected to the input terminal of the cascode circuit, and the differential circuit includes an MP1 transistor 11, an MP2 transistor 12, an MN1 transistor 13 and an MN2 transistor 14; the gates of the MN1 transistor 13 and the MP1 transistor 11 are electrically connected to the INP input terminal 7, and the gates of the MN2 transistor 14 and the MP2 transistor 12 are electrically connected to the INP input terminal 7. electrically connected to the INN input terminal 8; the source of the MP1 transistor 11 and the source of the MP2 transistor 12 are both electrically connected to the VDD power supply, and a galvanometer is provided between the source of the MP1 transistor 11 and the source of the MP2 transistor 12 and the VDD power supply, and the source of the MN1 transistor 13 and the MN2 transistor 14 are connected to VSS, that is, grounded, through the galvanometer; the drains of the MP1 transistor 11, the MN1 transistor 13, the MP2 transistor 12 and the MN2 transistor 14 all serve as output terminals of the differential circuit.

[0024] The INP input terminal 7 serves as the positive input terminal of the high-speed comparator, and the INN input terminal 8 serves as the negative input terminal of the high-speed comparator. A pair of NMOS transistors and a pair of PMOS transistors are provided to achieve a fully differential input common mode, with a rail-to-rail input common mode range. The pair of NMOS transistors are MN1 transistor 13 and MN2 transistor 14, and the pair of PMOS transistors are MP1 transistor 11 and MP2 transistor 12. The input signal is converted from voltage to current after passing through the input pair of transistors, and the current difference is then reflected as a voltage through the load transistor. To achieve high-speed comparison, while maintaining the overall power consumption of the circuit, the tail current of a portion of the input pair of transistors is appropriately reduced, and more current is instead distributed to the two branches of the load transistor. This is because the speed at which the current in the load circuit is converted to voltage has a greater impact on the overall circuit delay, and an increase in the current in the load circuit reduces the overall circuit delay.

[0025] As shown in FIG2 , the cascode circuit includes an MP3 transistor 15, an MP4 transistor 16, an MP5 transistor 17, an MP6 transistor 18, an MN3 transistor 19, an MN4 transistor 20, an MN5 transistor 21, and an MN6 transistor 22; the drain of the MP3 transistor 15 is electrically connected to the source of the MP5 transistor 17, and the drain of the MP4 transistor 16 is electrically connected to the source of the MP6 transistor 18; the gate of the MP3 transistor 15 is electrically connected to the gate of the MP4 transistor 16, and the gate of the MP5 transistor 17 is electrically connected to the gate of the MP6 transistor 18; the sources of the MP3 transistor 15 and the MP4 transistor 16 are both electrically connected to the VDD power supply; the source of the MP5 transistor 17 is electrically connected to the drain of the MN2 transistor 14, and the source of the MP6 transistor 18 is electrically connected to the drain of the MN1 transistor 13;

[0026] The source of the MN3 transistor 19 is electrically connected to the drain of the MN5 transistor 21, and the source of the MN4 transistor 20 is electrically connected to the drain of the MN6 transistor 22; the gate of the MN3 transistor 19 is electrically connected to the gate of the MN4 transistor 20, and the gate of the MN5 transistor 21 is electrically connected to the gate of the MN6 transistor 22. The sources of the MN5 transistor 21 and the MN6 transistor 22 are both electrically connected to VSS, and the electrical connection to VSS can be understood as grounding or a low voltage; the source of the MN3 transistor 19 is electrically connected to the drain of the MP2 transistor 12, and the source of the MN4 transistor 20 is electrically connected to the drain of the MP1 transistor 11; the drains of the MP5 transistor 17, the MP6 transistor 18, the MN3 transistor 19, and the MN4 transistor 20 all serve as output terminals of the folded common-source input circuit 4.

[0027] The MP5 transistor 17 and the MP6 transistor 18 are two MOS transistors in a cascode structure (common source and common gate). The substrates and sources of the MP5 and MP6 transistors 17 and 18 should be short-circuited. When Vbs = 0, this eliminates the PMOS transistor's body effect, lowers its threshold voltage, and reduces transmission delay. The bias voltage VBN2 for the MN5 and MN6 transistors 21 and 22 comes from the current mirror and also serves as the DC bias for the limiter circuit 5. Similarly, VBN1 is the bias voltage for the MN3 and MN4 transistors 19 and 20, VBP1 is the bias voltage for the MP3 and MP4 transistors 15 and 16, and VBP2 is the bias voltage for the MP5 and MP6 transistors 17 and 18.

[0028] As shown in Figures 2-3, the limiter circuit 5 includes a D1 diode 51 and a D2 diode 52; the anode of the D1 diode 51 is electrically connected to the cathode of the D2 diode 52, and the cathode of the D1 diode 51 and the anode of the D2 diode 52 are both electrically connected to the gate of the MN5 transistor 21; the anode of the D1 diode 51 is electrically connected to the drain of the MP6 transistor 18, and the cathode of the D1 diode 51 is electrically connected to the drain of the MP5 transistor 17; the anode of the D2 diode 52 is electrically connected to the drain of the MN3 transistor 19, and the cathode of the D2 diode 52 is electrically connected to the drain of the MN4 transistor 20; the anode of the D1 diode 51 and the cathode of the D2 diode 52 serve as the VR output terminal and the VL output terminal, respectively.

[0029] The swing range of the voltage VR outputted by the VR output terminal and the voltage VL outputted by the VL output terminal is determined to be within the range [Vgsn-ΔV2, Vgsn+ΔV1]. This reduces the voltage amplitude and the delay of the voltage passing through the MOS transistor in the circuit, greatly improving the comparison speed of this stage of the circuit. Vgsn is the gate voltage of the MN5 transistor 21, or can also be the voltage from the gate to the source of the MN5 transistor 21. ΔV2 is the threshold voltage of the D2 diode 52, and ΔV1 is the threshold voltage of the D1 diode 51. As shown in FIG6 , after the addition of the limiter circuit 5, the output signal is reduced from the high and low voltage range of the previous stage from [0, VDD] to the range [Vgsn-ΔV2, Vgsn+ΔV1]. As can be seen from the figure, when the signal undergoes level conversion, the delay of the output voltage after limiter is reduced by ΔT compared to the delay of the voltage without limiter. Therefore, the use of the limiter circuit 5 at the output stage of the folded cascode input circuit 4 reduces the delay of the entire high-speed comparator and speeds up the comparison time.

[0030] As shown in FIG4 , the low power inverter circuit 2 includes an MP7 transistor 27, an MP8 transistor 29, an MP9 transistor 25, an MP10 transistor 23, an MN7 transistor 28, an MN8 transistor 30, an MN9 transistor 26, and an MN10 transistor 24; the drain of the MP7 transistor 27 is electrically connected to the drain of the MN7 transistor 28 via a resistor, the drain of the MP7 transistor 27 is electrically connected to the gate of the MP8 transistor 29, and the drain of the MN7 transistor 28 is electrically connected to the gate of the MN8 transistor 30; the drain of the MP8 transistor 29 is electrically connected to the drain of the MN8 transistor 30; the drain of the MP9 transistor 25 is electrically connected to the drain of the MN9 transistor 26 via a resistor, the drain of the MP9 transistor 25 is electrically connected to the gate of the MP10 transistor 23, and the drain of the MN9 transistor 26 is electrically connected to the gate of the MN10 transistor 24; and the drain of the MP10 transistor 23 is electrically connected to the drain of the MN10 transistor 24.

[0031] As shown in FIG4 , the sources of the MP7 transistor 27, the MP8 transistor 29, the MP9 transistor 25, and the MP10 transistor 23 are electrically connected to a low power supply generated by an LDO low-dropout linear regulator. Using the low power supply to power a pair of inverter circuits can achieve the purpose of reducing the power consumption of the circuit; the sources of the MN7 transistor 28, the MN8 transistor 30, the MN9 transistor 26, and the MN10 transistor 24 are electrically connected to VSS, that is, grounded; the gates of the MP7 transistor 27 and the MN7 transistor 28 are electrically connected to the VR output terminal, and the gates of the MP9 transistor 25 and the MN9 transistor 26 are electrically connected to the VR output terminal; the drain of the MP8 transistor 29 serves as the OUTB output terminal, and the drain of the MP10 transistor 23 serves as the OUTD output terminal.

[0032] The low-voltage module, or low-power inverter circuit, within the "high-low-high" high-speed comparator structure serves a clear purpose. It fully utilizes the swing of the previous stage's limiting output. The low-power supply output, approximately 2V, ensures that the PMOS and NMOS transistors in this stage's inverter are not simultaneously conductive after the conversion is complete. Resistors are connected in series between MP7 transistor 27 and MN7 transistor 228, and similarly between MP9 transistor 25 and MN9 transistor 26. The values ​​of these two resistors can be adjusted based on a trade-off between dynamic power consumption and transmission delay. The output signals of low-power inverter circuit 2, after passing through the buffer circuit, are OUTB and OUTD, which are input to level shifter output circuit 3. This low-power supply significantly reduces circuit power consumption. The gate flip voltage of the first inverter in this stage of low-power inverter circuit 2 is set to the same voltage as VBN2, minimizing the system mismatch average and reducing circuit mismatch.

[0033] The level converter output circuit 3 is the last high voltage level in the "high-low-high" high-speed comparator structure, that is, a module powered by the VDD power supply voltage, which converts the low voltage signal of the low power inverter circuit 2 into a high level before outputting it. The level converter output circuit 3 includes an MP11 transistor 33, an MP12 transistor 34, an MP13 transistor 36, an MP14 transistor 38, an MP15 transistor 39, an MP16 transistor 31, an MN11 transistor 35, an MN12 transistor 37, an MN13 transistor 40 and an MN14 transistor 32; the gate of the MP16 transistor 31, the gate of the MN14 transistor 32, the drain of the MP11 transistor 33, the drain of the MP12 transistor 34 and the gate of the MP13 transistor 36 are all electrically connected to the drain of the MN11 transistor 35. The gate of the MP15 transistor 39, the gate of the MN13 transistor 40, the drain of the MP14 transistor 38, the drain of the MP13 transistor 36, and the gate of the MP12 transistor 34 are all electrically connected to the drain of the MN12 transistor 37; the drain of the MP16 transistor 31 is electrically connected to the drain of the MN14 transistor 32, and the drain of the MP15 transistor 39 is electrically connected to the drain of the MN13 transistor 40; the push-pull output is achieved by the connection of the PMOS transistor and the NMOS transistor in the low power inverter circuit 2 and the level converter output circuit 3.

[0034] The level converter output circuit 3 in this embodiment differs from conventional level converter circuits in that it includes external feedback transistors MP11 33 and MP14 32. This employs a cross-coupling structure to prevent dead zones in the circuit while also preventing them from occurring. The OUT-CMP signal output by the inverters of MP15 39 and MN13 40 pulls the gate of MP11 33 on the symmetrical side. Conversely, the OUTB-CMP signal output by the inverters of MP16 31 and MN14 32 pulls the gate of MP14 32 on the symmetrical side. This achieves a left-side-pulling-right and right-side-pulling-left effect, effectively utilizing the positive feedback acceleration effect and further avoiding the occurrence of a dead zone where one side pulls its own side.

[0035] The sources of the MP16 transistor 31, the MP11 transistor 33, the MP12 transistor 34, the MP13 transistor 36, the MP14 transistor 38, and the MP15 transistor 39 are electrically connected to the VDD power supply; the sources of the MN11 transistor 35, the MN12 transistor 37, the MN13 transistor 40, and the MN14 transistor 32 are electrically connected to VSS, i.e., ground; the gate of the MN11 transistor 35 is electrically connected to the OUTB output terminal, and the gate of the MN12 transistor 37 is electrically connected to the OUTD output terminal; the drain of the MP16 transistor 31 serves as the OUTB-CMP output terminal, which is electrically connected to the gate of the MP14 transistor 38; the drain of the MP15 transistor 39 serves as the OUT-CMP output terminal, which is electrically connected to the gate of the MP11 transistor 33; and the OUT-CMP output terminal serves as the final output terminal of the high-speed comparator. Example

[0036] The two signals to be compared are input to the INP input terminal 7 and the INN input terminal 8 respectively; the two signals are input to the folded cascode input circuit 2 from the INP input terminal 7 and the INN input terminal 8, and differential amplification is performed to make the input reach the common mode range and reach rail-to-rail; the two signals are input to the source of the MP5 transistor 17 and the MP6 transistor 18 and the source of the MN3 transistor 19 and the MN4 transistor 20 respectively, and the voltage range of the signal is increased to the [0, VDD] voltage range; then the signal is limited by the limiter circuit 5, and the VL signal and the VR signal are output from the VL output terminal and the VR output terminal respectively; the VL signal and the VR signal are input to the two inverters of the low power inverter circuit 2, and after inversion, the OUTD signal and the OUTB signal are output respectively; the OUTD signal and the OUTB signal are input to the level converter output circuit 3, and finally the comparison result of the high-speed comparator is output from the OUT_CMP output terminal.

[0037] Assuming that the INP input terminal and the INN input terminal are initially connected to the same common-mode level VCM, the signal at the INP input terminal increases and the signal at the INN input terminal decreases. After processing by the folded common-source common-gate input circuit 4 and the limiter circuit 5, the VL signal increases and the VR signal decreases. The low-power inverter circuit 2 senses the changes in the VL signal and the VR signal and reshapes them into digital signals. The gate voltages of the MN8 transistor and the MP8 transistor are LVDD, and the gate voltages of the MP10 transistor and the MN10 transistor are 0. The signal output by the OUTB output terminal becomes 0, and the signal output by the OUTD output terminal becomes LVDD; the OUTD signal and the OUTB signal are input to the level converter output circuit 3, the output of the OUT_CMP output terminal becomes VDD, and the output of the OUTB_CMP output terminal becomes 0. The OUT_CMP output terminal is the final output of the high-speed comparator, and the output signal is a VDD high level. Then, the signal at the positive input terminal is greater than the signal at the negative input terminal.

[0038] The above is only a description of the preferred embodiment of the present invention. Ordinary technicians in this technical field can make several modifications and optimizations based on the above disclosure without departing from the above basic principles. These improvements and optimizations should be regarded as the scope of protection understood by the present invention.

Claims

1. A high-speed comparator circuit with rail-to-rail input and push-pull output, characterized in that: The invention comprises a rail-to-rail input stage circuit (1), a low power inverter circuit (2) and a level converter output circuit (3); the output end of the rail-to-rail input stage circuit (1) is electrically connected to the input end of the low power inverter circuit (2), and the output end of the low power inverter circuit (2) is electrically connected to the input end of the level converter output circuit (3); the rail-to-rail input stage circuit (1) comprises a folded cascode input circuit (4) and a limiter circuit (5); the output end of the folded cascode input circuit (4) is electrically connected to the input end of the limiter circuit (5), the folded cascode input circuit (4) amplifies and fully differentially processes two input signals at the positive and negative input ends of the comparator, so that the input common mode range reaches rail-to-rail, and the limiter circuit (5) limits the amplitude of the differential mode signal output.

2. The high-speed comparator circuit with rail-to-rail input and push-pull output according to claim 1, characterized in that: The folded cascode input circuit (4) comprises an INP input terminal (7), an INN input terminal (8), a differential circuit and a cascode circuit; the output terminal of the differential circuit is electrically connected to the input terminal of the cascode circuit, and the differential circuit comprises an MP1 transistor (11), an MP2 transistor (12), an MN1 transistor (13) and an MN2 transistor (14); the gates of the MN1 transistor (13) and the MP1 transistor (11) are electrically connected to the INP input terminal (7), and the gates of the MN2 transistor (14) and the MP2 transistor (12) are electrically connected to the INN input terminal (8); the source of the MP1 transistor (11) and the source of the MP2 transistor (12) are electrically connected to a VDD power supply, and the drains of the MP1 transistor (11), the MN1 transistor (13), the MP2 transistor (12) and the MN2 transistor (14) serve as the output terminal of the differential circuit.

3. The high-speed comparator circuit with rail-to-rail input and push-pull output according to claim 2, characterized in that: The common-source and common-gate circuit comprises an MP3 transistor (15), an MP4 transistor (16), an MP5 transistor (17), an MP6 transistor (18), an MN3 transistor (19), an MN4 transistor (20), an MN5 transistor (21) and an MN6 transistor (22); the drain of the MP3 transistor (15) is electrically connected to the source of the MP5 transistor (17), and the drain of the MP4 transistor (16) is electrically connected to the source of the MP6 transistor (18); the gate of the MP3 transistor (15) is electrically connected to the gate of the MP4 transistor (16), the gate of the MP5 transistor (17) is electrically connected to the gate of the MP6 transistor (18), and the sources of the MP3 transistor (15) and the MP4 transistor (16) are both electrically connected to a VDD power supply; the source of the MP5 transistor (17) is electrically connected to the drain of the MN2 transistor (14), and the source of the MP6 transistor (18) is electrically connected to the drain of the MN1 transistor (13); The source of the MN3 transistor (19) is electrically connected to the drain of the MN5 transistor (21), and the source of the MN4 transistor (20) is electrically connected to the drain of the MN6 transistor (22); the gate of the MN3 transistor (19) is electrically connected to the gate of the MN4 transistor (20), and the gate of the MN5 transistor (21) is electrically connected to the gate of the MN6 transistor (22); the sources of the MN5 transistor (21) and the MN6 transistor (22) are both electrically connected to VSS; the source of the MN3 transistor (19) is electrically connected to the drain of the MP2 transistor (12), and the source of the MN4 transistor (20) is electrically connected to the drain of the MP1 transistor (11); the drains of the MP5 transistor (17), the MP6 transistor (18), the MN3 transistor (19) and the MN4 transistor (20) all serve as output terminals of the folded common-source and common-gate input circuit (4).

4. The high-speed comparator circuit with rail-to-rail input and push-pull output according to claim 3, characterized in that: The amplitude limiting circuit (5) comprises a D1 diode (51) and a D2 diode (52); the anode of the D1 diode (51) is electrically connected to the cathode of the D2 diode (52), and the cathode of the D1 diode (51) and the anode of the D2 diode (52) are both electrically connected to the gate of the MN5 transistor (21); the anode of the D1 diode (51) is electrically connected to the drain of the MP6 transistor (18), and the cathode of the D1 diode (51) is electrically connected to the drain of the MP5 transistor (17); the anode of the D2 diode (52) is electrically connected to the drain of the MN3 transistor (19), and the cathode of the D2 diode (52) is electrically connected to the drain of the MN4 transistor (20); the anode of the D1 diode (51) and the cathode of the D2 diode (52) serve as a VR output terminal and a VL output terminal, respectively.

5. The high-speed comparator circuit with rail-to-rail input and push-pull output according to claim 1, characterized in that: The low power inverter circuit (2) comprises an MP7 transistor (27), an MP8 transistor (29), an MP9 transistor (25), an MP10 transistor (23), an MN7 transistor (28), an MN8 transistor (30), an MN9 transistor (26) and an MN10 transistor (24); the drain of the MP7 transistor (27) is electrically connected to the drain of the MN7 transistor (28) via a resistor, the drain of the MP7 transistor (27) is electrically connected to the gate of the MP8 transistor (29), and the drain of the MN7 transistor (28) is electrically connected to the gate of the MP8 transistor (29). The drain of the MP8 transistor (29) is electrically connected to the drain of the MN8 transistor (30); the drain of the MP9 transistor (25) is electrically connected to the drain of the MN9 transistor (26) via a resistor, the drain of the MP9 transistor (25) is electrically connected to the gate of the MP10 transistor (23), and the drain of the MN9 transistor (26) is electrically connected to the gate of the MN10 transistor (24); the drain of the MP10 transistor (23) is electrically connected to the drain of the MN10 transistor (24).

6. The high-speed comparator circuit with rail-to-rail input and push-pull output according to claim 5, characterized in that: The sources of the MP7 transistor (27), the MP8 transistor (29), the MP9 transistor (25) and the MP10 transistor (23) are electrically connected to a low power source generated by an LDO low voltage drop linear regulator; the gates of the MP7 transistor (27) and the MN7 transistor (28) are electrically connected to a VR output terminal, and the gates of the MP9 transistor (25) and the MN9 transistor (26) are electrically connected to a VR output terminal; the drain of the MP8 transistor (29) serves as an OUTB output terminal, and the drain of the MP10 transistor (23) serves as an OUTD output terminal.

7. The high-speed comparator circuit with rail-to-rail input and push-pull output according to claim 1, characterized in that: The level converter output circuit (3) comprises an MP11 transistor (33), an MP12 transistor (34), an MP13 transistor (36), an MP14 transistor (38), an MP15 transistor (39), an MP16 transistor (31), an MN11 transistor (35), an MN12 transistor (37), an MN13 transistor (40) and an MN14 transistor (32); a gate of the MP16 transistor (31), a gate of the MN14 transistor (32), a drain of the MP11 transistor (33), a drain of the MP12 transistor (34) and an MP16 transistor (31). The gates of the MP13 transistors (36) are all electrically connected to the drain of the MN11 transistor (35); the gates of the MP15 transistor (39), the gates of the MN13 transistor (40), the drain of the MP14 transistor (38), the drain of the MP13 transistor (36) and the gate of the MP12 transistor (34) are all electrically connected to the drain of the MN12 transistor (37); the drain of the MP16 transistor (31) is electrically connected to the drain of the MN14 transistor (32), and the drain of the MP15 transistor (39) is electrically connected to the drain of the MN13 transistor (40).

8. The high-speed comparator circuit with rail-to-rail input and push-pull output according to claim 1, characterized in that: The sources of the MP16 transistor (31), the MP11 transistor (33), the MP12 transistor (34), the MP13 transistor (36), the MP14 transistor (38) and the MP15 transistor (39) are electrically connected to the VDD power supply; the gate of the MN11 transistor (35) is electrically connected to the OUTB output terminal, and the gate of the MN12 transistor (37) is electrically connected to the OUTD output terminal; the drain of the MP16 transistor (31) serves as the OUTB-CMP output terminal, and the OUTB-CMP output terminal is electrically connected to the gate of the MP14 transistor (38); the drain of the MP15 transistor (39) serves as the OUT-CMP output terminal, and the OUT-CMP output terminal is electrically connected to the gate of the MP11 transistor (33); and the OUT-CMP output terminal serves as the final output terminal of the high-speed comparator.

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