Multilayer wiring board, and method for manufacturing multilayer wiring board

Abstract

The purpose of the present invention is to provide a multilayer wiring board that can suppress warpage and exhibits high reliability, and to provide a method for manufacturing said multilayer wiring board.　One multilayer wiring board according to the present invention is characterized by comprising: an inorganic substrate having a first surface, a second surface opposing the first surface, and a side surface connecting a peripheral edge portion of the first surface and a peripheral edge portion of the second surface, the inorganic substrate also having formed therein at least one through hole penetrating from the first surface to the second surface; a protective resin part disposed in the through hole of the inorganic substrate and disposed so as to cover the side surface of the inorganic substrate; and a through electrode including a conductor part extending inside the through hole, the through electrode electrically connecting the first surface and the second surface.

Description

Multilayer wiring board and method of manufacturing the same

[0001] The present invention relates to a multilayer wiring board and a method for manufacturing the multilayer wiring board.

[0002] In recent years, three-dimensional packaging technology for semiconductor elements using a packaging substrate in which circuit boards are stacked has been used. In such packaging substrates, through electrodes are formed in the circuit boards. The through electrodes are formed by forming through holes in a substrate made of an insulator and placing a conductor in the through holes. As circuit boards become more highly integrated, the through holes also need to be made smaller.

[0003] Generally, ceramic or resin is chosen as the material for packaging substrate. However, ceramic substrates have high resistance or dielectric constant, making it difficult to mount high-frequency semiconductor elements. On the other hand, resin substrates are relatively suitable for high-frequency semiconductor elements, but there is a limit to how narrow the wiring pitch can be.

[0004] In recent years, research into the application of silicon and glass to high-end packaging substrates has been ongoing. By forming through-holes in silicon or glass substrates and filling these through-holes with a conductive material, the wiring length between the device and the motherboard can be shortened, resulting in excellent electrical characteristics. Examples of research into packaging substrates include the following Patent Documents 1 to 3.

[0005] Patent Document 1 addresses the issue of strengthening the power supply of a wiring board, and discloses the following content regarding a wiring board and a manufacturing method for the wiring board: "The wiring board 1 of the embodiment includes a core substrate 10, a first buildup layer 11 formed by alternately stacking first interlayer insulating layers 32 and first conductor layers 31, and a second buildup layer 12 formed by alternately stacking second interlayer insulating layers 42 and second conductor layers 41, and among the first conductor layers 31 and the second conductor layers 41 that are positioned at the same rank from the core substrate 10, the area and thickness of the conductor layer in the second buildup layer 12 are greater than the area and thickness of the conductor layer in the first buildup layer 11." Furthermore, Patent Document 2 addresses the issue of providing a printed wiring board that can improve the mountability of multiple electronic components when mounting these electronic components on the printed wiring board via solder, and discloses the following content regarding a printed wiring board and a semiconductor device including the same. "On the surface of the printed wiring board 1A, there are formed a plurality of first conductor pads 51, 52 connected to a first electronic component 7 at upper surfaces 51a, 52a via solder 70, and a plurality of second conductor pads 61, 62 connected to a second electronic component 8 at upper surfaces 61a, 62a via solder 80. The upper surfaces 51a, 52a of each of the first conductor pads 51, 52 and the upper surfaces 61a, 62a of each of the second conductor pads 61, 62 have the same shape and size, and the upper surfaces 51a, 52a of the first conductor pads 51, 52 and the upper surfaces 61a, 62a of the second conductor pads 61, 62 are formed on the same plane F3." Furthermore, Patent Document 3 discloses the following regarding a semiconductor packaging glass substrate, a semiconductor packaging substrate, and a semiconductor device."A packaging glass substrate for semiconductors comprising: a glass substrate having a first surface and a second surface facing each other; and a number of core vias penetrating the glass substrate in a thickness direction; wherein plain lines are straight lines connecting locations on the first surface of the glass substrate where no core vias are formed, and via lines are straight lines connecting locations on the first surface of the glass substrate where the core vias are formed, and the stress difference value (P) is a value obtained by the following formula (1), and the stress difference value (P) is 1.5 MPa or less; Formula (1): P = Vp - Np In formula (1), P is the stress difference value measured on the same glass substrate, Vp is the difference between the maximum and minimum stress values ​​measured in the via lines, and Np is the difference between the maximum and minimum stress values ​​measured in the plain lines."

[0006] Japanese Patent No. 7288339 Japanese Patent Application Laid-Open No. 2016-66745 Japanese Patent No. 7087205

[0007] The package substrates described in Patent Documents 1 and 2 are intended to use a glass epoxy substrate as a core material. However, Patent Documents 1 and 2 do not consider high-end package substrates, i.e., large-area package substrates on which multiple semiconductor elements are mounted via a silicon interposer. In recent high-end package substrates, multiple semiconductor elements are mounted via a silicon interposer, and when bonding to the package substrate, there is a problem of warping of the package substrate due to the different linear expansion coefficients of the silicon interposer and the package substrate, and the upper limit of the elastic modulus of the glass epoxy substrate is 40 GPa. In order to prevent bonding defects caused by such warping of the package substrate, a package using glass, whose physical properties are similar to those of silicon, is desired.

[0008] Furthermore, Patent Document 3 shows an example of a package substrate using glass, but glass is a brittle material. It has been confirmed that when the same design concept and process as those for glass epoxy substrates are applied to glass substrates, cracks occur in the glass near the wiring layer due to stress caused by the difference in linear expansion coefficient between the material used in the wiring layer and the glass. Furthermore, when the glass substrate is singulated using the same process (blade dicing) as that for glass epoxy substrates, stress concentrates on microcracks that occur on the end surfaces of the singulated substrates, causing the glass to break. For this reason, there are still issues regarding the reliability of glass substrates when used as package substrates. Furthermore, dicing a package substrate made of ceramic material while the wiring layers are stacked is difficult, resulting in challenges in singulating multilayer wiring substrates made of ceramic material.

[0009] Therefore, an object of the present invention is to provide a multilayer wiring board capable of suppressing warpage and having high reliability, and a method for manufacturing the multilayer wiring board.

[0010] In order to solve the above problem, one representative multilayer wiring board of the present invention is characterized by comprising an inorganic substrate having a first surface, a second surface opposite to the first surface, and a side surface connecting the peripheral portion of the first surface with the peripheral portion of the second surface, and in which at least one through hole is formed penetrating from the first surface to the second surface; a protective resin portion that is disposed in the through hole of the inorganic substrate and is disposed so as to cover the side surface of the inorganic substrate; and a through electrode that includes a conductor portion extending into the through hole and electrically connects between the first surface and the second surface.

[0011] Furthermore, one representative method for manufacturing a multilayer wiring board of the present invention includes a first step of dividing a base substrate into individual pieces to form an inorganic substrate having a first surface, a second surface opposite to the first surface, and a side surface connecting a peripheral portion of the first surface with a peripheral portion of the second surface, and having at least one through-hole formed therethrough from the first surface to the second surface; and a second step of placing the inorganic substrate on a glass epoxy substrate that has been processed to have a window cut out, placing a resin material on the first surface, the second surface, the side surface, and in the through-hole of the inorganic substrate, forming a first-surface first layer on the first surface, and forming a second-surface first layer on the second surface. a third step of forming a sub-through hole, which is a through hole formed in the resin material, within the through hole using a laser; a fourth step of arranging a conductor portion in the sub-through hole, the first surface first layer, and the second surface first layer; a fifth step of forming at least two wiring layers in addition to the first surface first layer on the first surface side, and at least two wiring layers in addition to the second surface first layer on the second surface side; and a sixth step of dicing the inorganic substrates arranged on the glass epoxy substrate by blade dicing to separate the substrates into individual pieces.

[0012] According to the present invention, it is possible to provide a multilayer wiring board that can suppress warpage and has high reliability, and a method for manufacturing the multilayer wiring board. Problems, configurations, and effects other than those described above will become clear from the description of the following embodiments of the invention.

[0013] FIG. 1 is a cross-sectional view showing an example of a multilayer wiring board according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing an example of a semiconductor device including a multilayer wiring board. FIG. 3 is a view showing a modified example of a multilayer wiring board according to an embodiment of the present invention. FIG. 4 is a view showing a process of preparing a base substrate. FIG. 5 is a view showing a process of forming a through hole in the base substrate. FIG. 6 is a cross-sectional view showing an enlarged view of a through hole formed in the base substrate. FIG. 7 is a cross-sectional view showing another example of a through hole formed in the base substrate. FIG. 8 is a view showing a process of arranging a singulated inorganic substrate on a glass epoxy substrate with a window cutout. FIG. 9 is a view showing a process of laminating a resin material on the glass epoxy substrate. FIG. 10 is a cross-sectional view showing a state in which an inorganic substrate 10 is placed on a glass epoxy substrate with a window cutout and then filled with resin material. FIG. 11 is a view showing a third process of forming a sub-through hole, which is a through hole formed in the resin material, using a laser within the through hole. FIG. 12 is a cross-sectional view showing an example of the processed shape of the sub-through hole. FIG. 13 is a view showing a fourth process of arranging conductors in the sub-through hole, the first surface first layer, and the second surface first layer. Fig. 14 is a diagram showing a process (fifth process) of forming at least two wiring layers in addition to the first surface first layer on the first surface side, and forming at least two wiring layers in addition to the second surface first layer on the second surface side. Fig. 15 is a diagram showing a glass epoxy substrate and an alignment mark used in dicing. Fig. 16 is a cross-sectional view of a multilayer wiring board of Comparative Example 1. Fig. 17 is a cross-sectional view of a multilayer wiring board of Comparative Example 2.

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the embodiments and examples shown below are merely examples of embodiments of the present invention, and the present invention should not be construed as being limited to these embodiments and examples. Note that in the drawings referred to in the embodiments of the present invention, identical or similar symbols (symbols consisting of a number followed by A, B, etc.) are used for identical parts, and repeated explanations may be omitted. Furthermore, explanations of dimensions and ratios in the drawings may differ from actual ratios or may be omitted from some of the configurations for convenience of explanation or notation.

[0015] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0016] In this disclosure, the term "surface" may refer not only to the surface of a plate-shaped member, but also to the interface of a layer contained in the plate-shaped member that is approximately parallel to the surface of the plate-shaped member. Furthermore, the terms "upper surface" and "lower surface" refer to the surface shown at the top or bottom of a drawing when a plate-shaped member or a layer contained in the plate-shaped member is illustrated. The "upper surface" and "lower surface" may also be referred to as the "first surface" and the "second surface."

[0017] Furthermore, "side" refers to the surface or thickness of a layer of a plate-like member or a layer contained in the plate-like member. Furthermore, a portion of the surface and the side surface may be collectively referred to as "end." Furthermore, "side surface of a through hole" refers to the interface on the object that forms the through hole, in the case of a through hole provided in an object. Furthermore, "upper" refers to the vertically upward direction when the plate-like member or layer is placed horizontally. Furthermore, "upper" and its opposite, "lower," are sometimes referred to as the "positive Z-axis direction" and the "negative Z-axis direction," and the horizontal direction is sometimes referred to as the "X-axis direction" and the "Y-axis direction."

[0018] Furthermore, the distance in the Z-axis direction is referred to as "height," and the distance on the XY plane defined by the X-axis and Y-axis directions is referred to as "width." Furthermore, when referring to a layered object, the height is also referred to as "thickness." Furthermore, "through electrode 15" refers to a conductive path provided to electrically connect the first and second surfaces of a glass substrate when the glass substrate is used as part of the multilayer wiring substrate 1, and does not necessarily have to completely penetrate the glass substrate with a single conductive material. As long as the conductive path from the first surface and the conductive path from the second surface are connected, they are included in the through electrode 15. Furthermore, the form of the through electrode 15 may be a filled structure in which the through hole is filled with a conductive material, or a conformal structure in which only the sidewall portion of the through hole is covered with a conductive material.

[0019] Furthermore, "planar shape" and "plan view" refer to the shape of a surface or layer when viewed from above. Furthermore, "cross-sectional shape" and "cross-sectional view" refer to the shape of a plate-like member or layer when cut in a specific direction and viewed from the horizontal direction. Furthermore, "center" refers to the center, not the peripheral part, of a surface or layer. And "central direction" refers to the direction from the peripheral part of a surface or layer toward the center of the planar shape of the surface or layer.

[0020] Furthermore, when a range of values ​​is expressed as "a range of 3 to 10 ppm / °C," this means a range of 3 ppm / °C or more and 10 ppm / °C or less. The same applies to other ranges of values.

[0021] 1 is a cross-sectional view showing an example of a multilayer wiring board 1 according to an embodiment of the present invention. Also, FIG. 2 is a cross-sectional view showing an example of a semiconductor device 200 including the multilayer wiring board 1.

[0022] 1, a multilayer wiring board 1 according to an embodiment of the present invention includes an inorganic substrate 10 having a first surface 10a, a second surface 10b opposite to the first surface 10a, and a side surface 10c connecting the peripheral edge of the first surface 10a with the peripheral edge of the second surface 10b, the inorganic substrate 10 having at least one through hole 11 formed therein that penetrates from the first surface 10a to the second surface 10b, a protective resin portion 25 disposed in the through hole 11 of the inorganic substrate 10 and arranged so as to cover the side surface 10c of the inorganic substrate 10, and a through electrode 15 including a conductor portion extending into the through hole 11 and electrically connecting the first surface 10a and the second surface 10b. The length of the multilayer wiring board 1 is denoted as L.

[0023] (Configuration of inorganic substrate 10) The first surface 10a of inorganic substrate 10 extends in a direction parallel to the XY plane and is located in the positive direction of the Z axis, while the second surface 10b of inorganic substrate 10 extends in a direction parallel to the XY plane and is located in the negative direction of the Z axis. Furthermore, the side surface 10c of inorganic substrate 10 is a surface connecting the peripheral portion of the first surface 10a with the peripheral portion of the second surface 10b. In the cross-sectional views of Figures 1 and 2, this corresponds to the surfaces of inorganic substrate 10 located at both ends in the X axis direction and extending in the Z axis direction. Although Figures 1 and 2 show eight through holes 11 and through electrodes 15 formed in inorganic substrate 10, the number of through holes 11 and through electrodes 15 is not limited to the number shown in the drawings. The arrangement of through holes 11 and through electrodes 15 varies depending on how the cross section is set. When viewed from the Z axis direction, multilayer wiring substrate 1 and semiconductor device 200 are generally rectangular.

[0024] The inorganic substrate 10 is made of glass or ceramic material. Materials used include quartz, alkali-free glass, alkali glass, and Al. ２ O ３ , SiO ２ , CaO, MgO, SrO, BaO, ZrO ２ The inorganic substrate 10 is a composite material containing at least one of the above. The main physical properties of the inorganic substrate 10 are a linear expansion coefficient in the range of 3 to 10 ppm / °C and a modulus of elasticity of 40 GPa or more, preferably about 60 GPa, and the composition ratio can be set appropriately. The thickness of the inorganic substrate 10 is designated as T1. Since the inorganic substrate 10 constitutes the base of the multilayer wiring substrate 1, it is sometimes referred to as the "core substrate."

[0025] (Configuration of the through electrode) In the through hole 11, the conductor portion is covered with a protective resin portion 25. The conductor portion of the through electrode 15 is provided to electrically connect the first surface 10a and the second surface 10b of the inorganic substrate 10, and is made of at least one metal material. Typical metal materials include Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, and Cu. ３ N ４A single material or a combination of multiple materials from these can be used. The conductor portion is formed by forming a seed layer by electroless plating, sputtering, or the like, followed by electroplating. The linear expansion coefficient of the conductor portion is desirably equal to or greater than the expansion coefficient of the inorganic substrate 10 and equal to or less than the expansion coefficient of the insulating resin 25, and is preferably in the range of 11 to 18 ppm / °C. Within the above range, the linear expansion coefficient of the conductor layer can be appropriately set.

[0026] The structure of the conductive portion of the through electrode 15 can be selected from a filled structure in which the conductive material is filled inside the through hole 11, or a conformal structure in which the conductive material is formed only on the wall surface portion of the through hole 11. For the filled or conformal structure, an appropriate structure can be selected in accordance with the operating frequency, resistance value, impedance matching, etc. of the semiconductor device 200 including the multilayer wiring substrate 1.

[0027] In the through-hole 11 of the inorganic substrate 10, the thickness d1 of the protective resin portion 25 disposed between the inorganic substrate 10 and the conductor portion is at least 10 μm. If the thickness of the protective resin portion 25 is less than 10 μm, the protective resin portion 25 may be damaged when forming the through-hole 12 in the protective resin portion 25 filled in the through-hole 11, as described below, potentially compromising the effectiveness of protecting the side surface of the inorganic substrate 10. Furthermore, if the conductor portion is disposed in the through-hole 12 while the protective resin portion 25 is damaged, it becomes difficult to ensure adhesion between the conductor portion and the protective resin portion 25. Furthermore, when the protective resin portion 25 is damaged, the electrical characteristics change, making it difficult to obtain the desired electrical characteristics (transmission characteristics) of the multilayer wiring substrate 1. Therefore, the thickness d1 of the protective resin portion 25 between the through-hole 11 of the inorganic substrate 10 and the conductor portion must be at least 10 μm. Note that although the through-hole 11 and the through-electrode 15 are shown as being rectangular in FIGS. 1 and 2 , details of their shapes will be described later. The thickness d1 is the length at the narrowest point between the through electrode 15 and the through hole 11.

[0028] (Configuration of First Surface Layer Structure 21 and Second Surface Layer Structure 22) The multilayer wiring board 1 further includes a first surface layer structure 21 formed on the first surface 10a of the inorganic substrate 10 and a second surface layer structure 22 formed on the second surface 10b of the inorganic substrate 10, each of which has two or more wiring layers, and the first surface first layer 21a included in the first surface layer structure 21 and formed on the inorganic substrate 10, and the second surface first layer 22a included in the second surface layer structure 22 and formed on the inorganic substrate 10, do not have metal wiring, and metal wiring is formed in the wiring layers included in the first surface layer structure 21 excluding the first surface first layer 21a and the wiring layers included in the second surface layer structure 22 excluding the second surface first layer 22a. Specifically, the first surface layer structure 21 has an outermost layer 21g including six wiring layers from the first surface first layer 21a to the first surface sixth layer 21f as wiring layers, and a solder resist layer 40. The first-surface first layer 21a is disposed on the first surface 21a of the inorganic substrate 10 and has a layer structure formed by a protective resin portion 25. The first-surface first layer 21a has portions through which the through electrodes 15 penetrate, but the protective resin portion 25 is disposed in portions covering the inorganic substrate 10 and the through holes 11. The first-surface second layer 21b is disposed on the first-surface first layer 21a and has a layer structure filled with the protective resin portion 25 and including metal wiring 21b1 and 21b2. The metal wiring 21b1 and 21b2 have a predetermined wiring pattern when viewed from the Z-axis direction. A filled-type through electrode extending in the Z-axis direction is disposed between the metal wiring 21b1 and the metal wiring 21b2. The first-surface third layer 21c is disposed on the first-surface second layer 21b and has a layer structure filled with the protective resin portion 25 and including metal wiring 21c1. The metal wiring 21c1 has a predetermined wiring pattern when viewed from the Z-axis direction. A filled electrode extending in the Z-axis direction is disposed between the metal wiring 21c1 and the metal wiring 21b2 of the first-surface second layer 21b. Similarly, the first-surface fourth layer 21d has a layer structure including a metal wiring 21d1, a protective resin portion 25, and a filled electrode. The first-surface fifth layer 21e has a layer structure including a metal wiring 21e1, a protective resin portion 25, and a filled electrode. The first-surface sixth layer 21f has a layer structure including a metal wiring 21f1, a protective resin portion 25, and a filled electrode.A solder resist layer 40 and solder bumps 50 are formed on the outermost layer 21g, which is the outermost layer on the first surface 10a side.

[0029] The second-surface layer structure 22 has a similar structure to the first-surface layer structure 21. Specifically, the second-surface layer structure 22 includes six wiring layers, from the second-surface first layer 22a to the second-surface sixth layer 22f, and a solder resist layer 40. Of the six wiring layers, the second-surface first layer 22a is disposed on the second surface 10b of the inorganic substrate 10 and has a layer structure formed by a protective resin portion 25. The second-surface second layer 22b has a layer structure including metal wiring 22b1, metal wiring 22b2, the protective resin portion 25, and a filled electrode. The second-surface third layer 22c has a layer structure including metal wiring 22c1, the protective resin portion 25, and a filled electrode. The second-surface fourth layer 22d has a layer structure including metal wiring 22d1, the protective resin portion 25, and a filled electrode. The second-surface fifth layer 22e has a layer structure including metal wiring 22e1, the protective resin portion 25, and a filled electrode. The sixth layer 22f on the second surface 10b has a layer structure including metal wiring 22f1, a protective resin portion 25, and a filled electrode. A solder resist layer 40 is formed on the outermost layer 22g on the second surface 10b side.

[0030] (Effects of not arranging metal wiring in the wiring layer on inorganic substrate 10) When metal wiring is formed on inorganic substrate 10, stress from the laminated material of first surface layer structure 21 and second surface layer structure 22 is concentrated at the end of the metal wiring, causing cracks to occur in inorganic substrate 10 at the end of the wiring. By not providing metal wiring in the first layer of the wiring layers of first surface layer structure 21 and second surface layer structure 22 on inorganic substrate 10 but arranging metal wiring from the second layer, it is possible to alleviate stress in the wiring layer and prevent cracks from occurring in inorganic substrate 10.

[0031] (Configuration of the protective resin portion 25) The protective resin portion 25 covers the first surface 10a, the second surface 10b, the side surfaces of the through holes 11, and the side surfaces 10c of the inorganic substrate 10, and is also a component of the wiring layer formed on the first surface 10a and the second surface 10b. In other words, the resin material filling the through holes 11 and covering the side surfaces of the inorganic substrate 10 and the resin material contained in the wiring layer are the same resin material. The resin material is mixed in a range of 40 wt% to 80 wt% and contains a filler having an average particle size in a range of 0.3 μm to 1.0 μm. The resin material can also contain build-up resin or glass cloth, as long as it is within the above material range.

[0032] Regarding the resin material, if the filler content in the resin material is 40 wt % or less, the linear expansion coefficient of the resin material will be 40 ppm or more and its elastic modulus will be 5 MPa or less. This means that stress resulting from the difference in the linear expansion coefficient between the resin material and inorganic materials such as the metal wiring and the through electrode 15 may cause cracks in the inorganic material. Furthermore, if the filler content is 80 wt % or more, the contact area between the filler and the inorganic material increases, making it more likely that delamination will occur between the resin material and the inorganic material. As long as the filler content in the resin material is in the range of 40 wt % or more and 80 wt % or less, it can be appropriately set depending on the number of wiring layers on the first surface 10a and the second surface 10b of the multilayer wiring board 1.

[0033] The protective resin portion 25 is made of a material obtained by adding a filler such as silica, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide to a resin mixture of at least one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and polyamide resin, for example. By setting the elastic modulus of the protective resin portion 25 to a range of 6 to 15 GPa and the linear expansion coefficient to a range of 11 to 30 ppm / Deg.C, it becomes possible to alleviate stress on the inorganic substrate 10.

[0034] The thickness d2 of the protective resin portion 25 disposed on the side surface 10c of the inorganic substrate 10 is at least 50 μm. The thickness d2 refers to the length of the protective resin portion 25 measured in a direction perpendicular to the side surface 10c of the inorganic substrate 10 (the x-axis direction in the figure). The protective resin portion 25 disposed on the side surface 10c functions to relieve stress on the inorganic substrate 10 and is formed of the same resin material as the first-surface first layer 21a disposed on the first surface 10a and the second-surface first layer 22a disposed on the second surface 10b. If the thickness of the protective resin portion 25 formed on the side surface 10c of the inorganic substrate 10 is 50 μm or less, it is difficult to sufficiently relieve stress in the wiring layers on the first surface 10a and the second surface 10b, and the inorganic substrate 10 may be damaged by the stress. Therefore, it is desirable to set the thickness of the protective resin portion 25 on the side surface 10c of the inorganic substrate 10 to at least 50 μm.

[0035] (Configuration of Multilayer Wiring Board 1) The outer periphery of multilayer wiring board 1 is covered by insulating resin portion 25 and peripheral protective portion 30. As described below, after multilayer wiring board 1 is divided into individual pieces during manufacturing, inorganic substrate 10 is not exposed on the side surfaces of multilayer wiring board 1. The outer periphery is the portion in the xy plane, and as described below, peripheral protective portion 30 is a portion separated from the glass epoxy substrate. While insulating resin portion 25 of at least 50 μm is disposed on side surface 10 c of inorganic substrate 10, if only protective resin portion 25 is present, deformation (warping / waviness) of multilayer wiring board 1 will occur due to the thermal history when semiconductor element 100 is bonded to multilayer wiring board 1. By disposing peripheral protective portion 30 on the outer periphery of multilayer wiring board 1, deformation due to the thermal history when multilayer wiring board 1 and semiconductor element 100 are bonded can be suppressed. As long as the protective resin portion 25 is formed on the side surface 10c of the inorganic substrate 10 to a thickness of 50 μm or more, the position where the peripheral protective portion 30 is disposed can be arbitrarily set according to the thickness and size of the multilayer wiring board 1. Furthermore, by disposing the peripheral protective portion 30 on the periphery of the multilayer wiring board 1, it is possible to suppress exposure of the inorganic substrate 10 at the end face of the multilayer wiring board 1, and the reliability of the multilayer wiring board 1 can be ensured.

[0036] (Example of Use of Multilayer Wiring Board 1) As shown in FIG. 2 , the semiconductor device 200 has at least one semiconductor element 100 mounted on the multilayer wiring board 1 via an interposer board. Specifically, the semiconductor element 100 is connected to the multilayer wiring board 1 via a silicon interposer 90 made of silicon, for example, to transmit signals between the multilayer wiring board 1 and the semiconductor element 100. As shown in FIG. 2 , the solder bumps 50 in FIG. 1 are connected to electrodes of the semiconductor element 100 via the silicon interposer 90. The silicon interposer 90 has a fine wiring layer and connects the semiconductor element 100 to the multilayer wiring board 1. The semiconductor element 100 and the silicon interposer 90, and the silicon interposer 90 and the multilayer wiring board 1, are connected using solder such as Sn, SnAg, Ni / Sn, Ni / SnAg, Ni / Cu / Sn, or Ni / Cu / SnAg.

[0037] (Modification of Multilayer Wiring Board) Next, a modification of the embodiment of the present invention shown in FIG. 3 will be described. FIG. 3 is a diagram showing a modification of the multilayer wiring board according to the embodiment of the present invention. In the multilayer wiring board 1 shown in FIGS. 1 and 2, no metal wiring is formed on the first surface 10a or the second surface 10b of the inorganic substrate 10, and no metal wiring is included in the first surface first layer 21a or the second surface first layer 22a. Therefore, for example, as in the multilayer wiring board 1a shown in FIG. 3, it is possible to arrange circuit components such as a capacitor 60 on the inorganic substrate 10. By arranging the capacitor 60 on the inorganic substrate 10, the connection distance between the semiconductor element 100 and the capacitor 60 is shortened compared to the connection distance between the semiconductor element 100 and the capacitor when arranged on the multilayer wiring board 1. By shortening the connection distance, the stability of the power supply voltage of the semiconductor element 100 can be improved.

[0038] <Method for Manufacturing Multilayer Wiring Board 1 in the Embodiment of the Present Invention> A method for manufacturing multilayer wiring board 1 in the embodiment of the present invention will be described with reference to FIGS. 4 to 15. FIG.

[0039] The thickness T1A of the base substrate 10A can be appropriately set depending on the application, taking into consideration the thickness T1 of the inorganic substrate 10 after the etching step for forming the through holes. For example, T1A is in the range of 300 to 500 μm, and T1 is in the range of 200 to 300 μm.

[0040] (Configuration of Through Holes) FIG. 4 is a diagram showing a process of preparing a base substrate 10A. FIG. 5 is a diagram showing a process of forming through holes 11 in the base substrate 10A. FIGS. 4 and 5 show a first process of singulating the base substrate 10A to form inorganic substrates 10 each having a first surface 10a, a second surface 10b facing the first surface 10a, and a side surface 10c connecting the peripheral edge of the first surface 10a with the peripheral edge of the second surface 10b, and having at least one through hole 11 formed therein that penetrates from the first surface 10a to the second surface 10b. The base substrate 10A is singulated (separated), and a portion of the singulated base substrate 10A becomes the inorganic substrate 10. The first surface 10a of the inorganic substrate 10 is the surface that is exposed by etching the first surface of the base substrate 10A, and the second surface 10b of the inorganic substrate 10 is the surface that is exposed by etching the second surface of the base substrate 10A. Therefore, in the description of the base substrate 10A, the notation of the first surface 10a and the second surface 10b is used.

[0041] A through hole 11 is formed in the base substrate 10A shown in Fig. 4 as shown in Fig. 5. The through hole 11 can be formed, for example, by forming the starting point of the through hole by laser processing and then enlarging it by etching. For the laser processing, when a femtosecond laser or a picosecond laser is used, it is preferable to use one of the oscillation wavelengths of 1064 nm, 532 nm, and 355 nm. Alternatively, a CO ２The starting points of the through holes 11 can also be formed by laser processing or electrical discharge machining. After laser processing, the base material substrate 10A is immersed in hydrogen fluoride or a high-concentration alkaline etching solution (e.g., a sodium hydroxide aqueous solution or a potassium hydroxide aqueous solution) to etch the base material substrate 10A along the starting points of the through holes 11, thereby forming the through holes 11. Generally, etching progresses isotropically in the xy plane, and the rate of etching varies depending on the thickness direction (Z-axis direction) of the inorganic substrate 10. Therefore, the cylindrical spaces formed in the base material substrate 10A after etching become the through holes 11. After the through holes 11 are formed, the base material substrate 10A is singulated to form the inorganic substrates 10. The base material substrate 10A can be singulated by, for example, dicing using a dicing blade, scribing, laser scribing, or the like. Other singulation methods can also be appropriately selected.

[0042] FIG. 6 is an enlarged cross-sectional view of a through hole 11 formed in the base substrate 10A. FIG. 6( a) shows a cross-sectional view of the through hole 11, and FIG. 6( b) shows a diagram illustrating the inclination angle of the through hole 11. A method for measuring the inclination angle will be described later. FIG. 7 is an enlarged cross-sectional view of another example of a through hole formed in the base substrate 10A. FIG. 7( a) shows a cross-sectional view of another example of the through hole, and FIG. 7( b) shows a diagram illustrating the inclination angle of another example of the through hole. The cross-sections of the through hole 11 shown in FIGS. 6 and 7 were obtained by cleaving (cutting) the base substrate 10A in the thickness direction by a scribe to expose the cross-section (cut surface) of the through hole 11, and analyzing the SEM image observed with an SEM (Scanning Electron Microscope) using image analysis software. The through holes 11 formed in the base substrate 10A may be, for example, a truncated cone shape as shown in Fig. 6, in which the angle of the side surfaces of the through holes 11 is constant, or an hourglass shape as shown in Fig. 7, in which the angle of the side surfaces of the through holes 11 is inverted upside down from the 50% position at the center. The shape of the through holes 11 is not limited to the above shapes, and any shape can be set as appropriate as long as they penetrate the first surface 10a and the second surface 10b of the base substrate 10A. The shape of the through holes 11 is an example of a through hole that can be obtained by laser processing and etching, and the present disclosure is not limited to the above shapes.

[0043] The through hole 11 shown in FIG. 6 has a truncated cone shape, and the diameter, which is the length of the through hole 11 in a direction parallel to the xy plane, has a maximum value on the first surface 10a side, decreases as it approaches the second surface 10b from the first surface 10a, and reaches a minimum value on the second surface 10b side. The scale of 5%, 10%, ... 95% shown in FIG. 6(b) indicates the length from the first surface 10a to the second surface 10b of the inorganic substrate 10 as a percentage. Furthermore, regarding the inclination angle of the side surface of the through hole 11, a center line TC is drawn at the center of the opening on the second surface 10b side of the inorganic substrate 10 so as to be perpendicular to the second surface 10b. Next, as shown by arrow A1, the center line TC is translated toward either side of the through hole 11 until it contacts the point where the diameter of the through hole 11 reaches its minimum value, and the point of contact is designated as a reference point RP. Then, a tangent line ss is drawn from the reference point RP to the side surface corresponding to each of the positions from 5% to 95% on the scale, and the inclination angle θ of the tangent line ss (i.e., an angle equal to the angle between the center line TC and the tangent line ss) is measured. This inclination angle θ is defined as the inclination angle at each of the positions from 5% to 95% on the cross section. Note that the inclination angle θ is positive in the direction in which the diameter of the through hole 11 widens upward. As shown in FIG. 6(b), the inclination angle θ is approximately between 14° and 15° at all positions from 5% to 95%.

[0044] The shape of the through hole 11 shown in FIG. 7(a) has a nearly vertically symmetrical structure at the 50% mark on the scale. Regarding the method for measuring the inclination angle of the side surface of the through hole 11, for the section from 5% to 50% distance from the first surface 10a, as shown in FIG. 7(b), a center line TC is drawn perpendicular to the first surface 10a at the center of the opening on the first surface 10a side of the inorganic substrate 10. Next, as indicated by arrow A1, the center line TC is translated toward both sides of the through hole 11 until it contacts the point where the diameter of the through hole 11 is at its minimum value, and the contact point is designated as the reference point RP. Then, a tangent line ss is drawn from the reference point RP to the side surface corresponding to each position from 5% to 50% on the scale, and the inclination angle θ of the tangent line ss is measured. This inclination angle θ is designated as the inclination angle at each cross-sectional position from 5% to 50%. The inclination angle θ is defined as positive in the direction in which the diameter of the through hole 11 expands upward. Furthermore, for the section from 50% to 95% distance from the first surface 10a, the center line TC is translated to the reference point RP, and a tangent line ss is drawn on the side surface corresponding to each of the positions from 50% to 95% on the scale. The inclination angle θ of the tangent line ss is then measured, and this inclination angle θ is defined as the inclination angle at each of the cross-sectional positions from 50% to 95%. The inclination angle θ is defined as negative when the diameter of the through hole 11 widens downward. As shown in FIG. 7B, the inclination angle θ changes sign from positive to negative at the 50% position, and the absolute value of the inclination angle θ is approximately between 14° and 15°.

[0045] The minimum diameter of the through-hole 11 is designated as Φ1, and the maximum diameter is designated as Φ2. In the case of FIG. 6(a), Φ1 is the opening on the second surface 10b side, and Φ2 is the opening on the first surface 10a side. In the case of FIG. 7(a), Φ1 is the diameter near the middle of the thickness T1, and Φ2 is the opening on the second surface 10b side. Φ1 is in the range of 25 to 100 μm, and Φ2 is in the range of 75 to 300 μm.

[0046] (Window Cutout Processing of Glass Epoxy Substrate) Next, FIG. 8 illustrates a process of placing a singulated inorganic substrate 10 on a windowed glass epoxy substrate. The inorganic substrate 10, with through holes 11 formed therein, is singulated (divided) into a predetermined shape using a scribe, a laser, or the like. As shown in FIG. 8 , a glass epoxy substrate 30A having the same thickness as the inorganic substrate 10 (thickness T1) is windowed, and the singulated inorganic substrate 10 is placed in the space formed by the window cutout (hereinafter also referred to as the "window cutout portion"). In the glass epoxy substrate 30A, a gap G1 is left between the window cutout portions. The gap G1 can also refer to the distance between the inorganic substrates 10 arranged on the glass epoxy substrate 30A, and is at least 50 μm or more. The window cutout processing is performed so that a gap G2 of, for example, 100 μm or more is formed between the inorganic substrate 10 and the glass epoxy substrate 30, relative to the size of the singulated inorganic substrate 10. A router, a laser, or the like is used for the window cutout processing. The window cutout portion is also countersunk. The above processing method is an example, and other processing methods may be selected as appropriate. When the base substrate 10A is cut into individual multilayer wiring substrates 1, the outer periphery protection portion 30 of the multilayer wiring substrate 1 is formed by a portion separated from the glass epoxy substrate 30A.

[0047] (Placement of Protective Resin Portion) Next, FIG. 9 illustrates a process for laminating a resin material on a glass epoxy substrate 30A. Specifically, FIG. 9 illustrates a second process in which an inorganic substrate 10 is placed on a window-cut glass epoxy substrate 30A, and a resin material is placed on the first surface 10a, second surface 10b, side surface 10c, and through-hole 11 of the inorganic substrate 10 to form a first-surface first layer 21a on the first surface 10a and a second-surface first layer 22a on the second surface 10b. As illustrated in FIG. 9, the glass epoxy substrate 30A on which the inorganic substrate 10 is placed is filled with resin material from both sides in the positive and negative Z-axis directions. By filling with resin material, a protective resin portion 25 is laminated. The resin material is, for example, at least one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and polyamide resin, to which fillers such as silica, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide are added. The material has an elastic modulus of 6 to 15 GPa and a linear expansion coefficient of 11 to 30 ppm / deg.C. It is preferably a thermosetting resin. Materials containing glass cloth may also be used if necessary. Methods for filling the resin material into the glass epoxy substrate 30A include, for example, vacuum pressure pressing, heat pressing, compression molding, and transfer molding. As long as the resin material can be filled without bubbles into the gap G1 between the window-cut glass epoxy substrate 30 and the inorganic substrate 10, any suitable processing method can be used. Preferably, filling is performed using a vacuum pressure pressing method, and it is desirable to select a processing method that simultaneously applies heat and pressure under vacuum. It should be noted that, prior to the process shown in FIG. 9, when inorganic substrate 10 is placed on windowed glass epoxy substrate 30A, capacitor 60 can be placed on inorganic substrate 10 and then filled with a resin material to form multilayer wiring substrate 1a incorporating capacitor 60 as shown in FIG. 3.

[0048] FIG. 10 is a cross-sectional view of a window-cut glass epoxy substrate 30A after the inorganic substrate 10 has been placed on it and filled with resin material. FIG. 10 is, for example, a cross-sectional view taken along the AA line in FIG. 9 . Because the resin material is a part of the protective resin portion 25, it is shown as the protective resin portion 25 in FIG. 10 . The resin material placed on the first surface 10a of the inorganic substrate 10 forms the first-surface first layer 21a. The resin material placed on the second surface 10b of the inorganic substrate 10 forms the second-surface first layer 22a. As shown in FIG. 10 , the gap G2 between the glass epoxy substrate 30A and the inorganic substrate 10 and the through-hole 11 formed in the inorganic substrate 10 are filled with resin material. To ensure adhesion between the inorganic substrate 10 and the protective resin portion 25 and between the glass epoxy substrate 30A and the protective resin portion 25, the inorganic substrate 10 and the glass epoxy substrate 30A can be treated with a silane coupling agent or the like to improve adhesion. The silane coupling agent can be appropriately selected depending on the resin material used. Furthermore, if silane coupling treatment is not performed, the surfaces of the inorganic substrate 10 and the glass epoxy substrate 30A may be roughened and then subjected to an adhesion treatment using the anchor effect. The adhesion treatment can be appropriately set depending on the application of the multilayer wiring substrate 1. Note that the glass epoxy substrate 30A is countersunk when opening a window, resulting in a roughened surface in the region Rc of the glass epoxy substrate 30A. Countersunk processing can also improve adhesion between the glass epoxy substrate 30A and the resin material. Furthermore, while FIG. 10 shows a case where resin material is left on the surface of the inorganic substrate 10 as the first-side first layer 21a and the second-side first layer 22a, the resin material on the surface of the inorganic substrate 10 may not be present. As long as the through-hole 11 is filled with resin material, the first-side first layer 21a and the second-side first layer 22a may be absent, or only one of them may be present (the same applies to the disclosures below relating to FIG. 11 and subsequent figures).

[0049] FIG. 11 is a diagram showing a third step of forming a sub-through hole 12, which is a through hole formed in a resin material, using a laser within the through hole 11. The sub-through hole 12 penetrates a protective resin portion 25 filled in the through hole 11 of the inorganic substrate 10. The sub-through hole 12 can be formed by, for example, drilling, in addition to laser processing. When forming the sub-through hole 12 in the protective resin portion 25, the through hole 11 formed in the inorganic substrate 10 is used as an alignment mark for alignment. The processing diameter of the sub-through hole 12 formed in the protective resin portion 25 is smaller than the processing diameters Φ1 and Φ2 of the through holes 11 formed in the inorganic substrate 10, and is set so that a thickness of at least 10 μm of resin remains around the sub-through hole 12 relative to Φ1, which is the smallest value of the processing diameters of the through holes 11. When forming the sub-through hole 12 by laser processing, CO ２ A laser or a UV laser can be used. In order to penetrate the protective resin portion 25, processing may be performed multiple times.

[0050] Next, with reference to FIG. 12 , the relationship between the processed shapes of the through hole 11 formed in the inorganic substrate 10 and the sub-through hole 12 formed in the protective resin portion 25 will be described. FIG. 12 is a cross-sectional view showing an example of the processed shape of the sub-through hole 12. The shape of the through hole 11 formed in the inorganic substrate 10 can be a truncated cone shape or an hourglass shape, and the shape of the sub-through hole 12 formed in the protective resin portion 25 is a truncated cone shape. Possible combinations of the through hole 11 and the sub-through hole 12 include the combinations shown in (a) to (f) of FIG. 12 . FIG. 12 (a) shows a case where the through hole 11 is hourglass-shaped and the sub-through hole 12 is a truncated cone shape whose diameter narrows in the negative Z-axis direction. FIG. 12 (b) shows a case where the through hole 11 is a truncated cone shape whose diameter narrows in the negative Z-axis direction, and the sub-through hole 12 is a truncated cone shape whose diameter narrows in the negative Z-axis direction. 12(c) shows a case where the through hole 11 has a truncated cone shape whose diameter narrows in the positive direction of the Z axis, and the sub-through hole 12 has a truncated cone shape whose diameter narrows in the negative direction of the Z axis. 12(d) to 12(f) correspond to 12(a) to 12(c), respectively, and show a case where the narrowing direction of the sub-through hole 12 is changed to the positive direction of the Z axis.

[0051] The sub-through holes 12 are formed to accommodate through electrodes 15 that electrically connect the first surface 10a and the second surface 10b of the inorganic substrate 10. As long as the through electrodes 15 are electrically connectable and connection reliability can be ensured, the combination of the processed shapes of the through holes 11 and the sub-through holes 12 can be appropriately set. The processed diameters of the through holes 11 and the sub-through holes 12 (in other words, the opening diameters of the sub-through holes 12 in the yz plane) and the processed pitch (in other words, the distance between adjacent through holes 12) can be set according to the wiring densities of the first surface layer structure 21 and the second surface layer structure 22 of the multilayer wiring substrate 1. As shown in FIG. 12 , the thickness d1 of the protective resin portion 25 is the thickness at the point where the distance between the through holes 11 and 12 is smallest. In the cases of Figures 12(a) and 12(d), thickness d1 is located approximately in the middle of the inorganic substrate 10, in the cases of Figures 12(b) and 12(e) it is located on the second surface 10b side, and in the cases of Figures 12(c) and 12(f) it is located on the first surface 10a side.

[0052] Furthermore, with regard to the combination of the processed shapes of the through hole 11 and the sub-through hole 12, when the distance between the sub-through hole 12 and the through hole 11 is small (in other words, when the thickness d1 of the protective resin portion 25 between the sub-through hole 12 and the through hole 11 is small), the possibility of failure increases due to the influence of stress generated by the difference in the linear expansion coefficient between the wiring layer and the semiconductor element and the protective resin portion 25. Among the relationships shown in Figure 12, combinations (a), (b), (d), and (f) are preferred, and when considering the routing of the wiring between the semiconductor element and the wiring layer, combinations (d) and (f) are more preferred. The above combination shapes can be set appropriately depending on the application.

[0053] Referring to FIG. 13 , a process for forming a conductor in the through hole 12 of the insulating resin 25 filled in the through hole 11 of the inorganic substrate 10 will be described. FIG. 13 is a diagram showing a fourth process for disposing a conductor in the sub-through hole 12, the first surface first layer 21a, and the second surface first layer 22a. The conductor is disposed in the through hole 12 by forming a seed layer in the through hole 12 using an electroless plating process, then forming a wiring pattern by photolithography, and then forming the conductor by electrolytic plating. Generally, a sputtering process or the like is used to form a seed layer in a through hole. However, for through holes with a high aspect ratio, it is difficult to form a sputtered seed layer (seed layer formed by sputtering) that covers the entire through hole (without gaps throughout the entire through hole). If a seed layer is to be formed in the through hole 11 of the inorganic substrate 10, a sputtered seed layer may be formed, followed by electroless Ni plating to form a new seed layer over the entire through hole 11. A method that combines a sputter seed layer and electroless plating is adopted because it is difficult to form an electroless plating film on the inorganic substrate 10. In the structure of the present invention, in order to form a seed layer in the sub-through hole 12, the seed layer is formed on the protective resin part 25, and as a result, the formation of the seed layer by the electroless plating method is adopted.

[0054] Examples of materials for the metal seed layer formed inside the sub-through hole 12 by electroless plating include Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, and Pt, but Cu is preferred. The solution composition includes, for example, copper salts such as copper sulfate and copper chloride, Rossel salt for retaining copper ions, EDTA (ethylenediaminetetraacetic acid), and formalin. The solution composition can be adjusted appropriately depending on the chemical resistance of the insulating resin used. The thickness of the metal seed layer formed by electroless plating is preferably at least 0.3 μm inside the sub-through hole 12. If the thickness is 0.3 μm or less, the coverage of the metal seed layer formed by electroless plating is insufficient, resulting in discontinuous conductive layers formed by electrolytic plating. If the thickness of the metal seed layer formed by electroless plating is 0.3 μm or more, the thickness of the metal seed layer can be adjusted appropriately.

[0055] After forming a metal seed layer inside the sub-through hole 12 by electroless plating, a resist pattern is formed by photolithography, and then the through electrode 15, metal wiring 21b1, and metal wiring 22b1 are formed by electroplating. The resist pattern is formed by photolithography, for example, by laminating a dry film resist, drawing a pattern by exposure, and developing. The resist pattern is formed by photolithography using materials generally used in the wiring formation process for FC-BGAs. The resist pattern is peeled off after electroplating, and excess seed layer is removed by etching. Note that the conductor portion is not formed in the area where dicing is performed (hereinafter also referred to as the "dicing area"). Specifically, the "dicing area" refers to the portion of the wiring layer that overlaps the region Rd where dicing is performed on the glass epoxy substrate 30A, and also refers to the portion of the wiring layer corresponding to the position where the alignment mark, described below, is formed. The dicing area is, for example, the position where the dicing blade passes or the position where scribing is performed. No seed layer is formed in the dicing process portion, and no metal wiring is formed. The same applies to the other wiring layers included in the first surface layer structure 21 and the second surface layer structure 22. Because the metal material is removed from the workpiece that is diced, it is possible to reduce the impact on the processability of the multilayer wiring board in the singulation process described below.

[0056] The materials for the through electrodes 15, metal wiring 21b1, and metal wiring 22b1 formed in the sub-through holes 12 by electroplating include, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, and Pt, but Cu is preferred. The plating solution is primarily composed of copper sulfide pentahydrate, sulfuric acid, and chloride ions. To ensure uniformity of the plating film, the through electrodes 15, metal wiring 21b1, and metal wiring 22b1 are formed using a plating solution containing at least one additive. The through electrodes 15, metal wiring 21b1, and metal wiring 22b1 are preferably formed to a thickness of at least 2 μm or more. If the thickness is less than 2 μm, the conductive layer becomes discontinuous, resulting in increased resistance when electrically connecting the wiring layers on the first surface 10a and the second surface 10b via the through electrodes 15. Therefore, when the thickness of the conductive layer is formed to be at least 2 μm or more, the thickness can be set appropriately.

[0057] Next, referring to FIG. 14, the wiring layer formation process (fourth process) of the first surface layer structure 21 and the second surface layer structure 22 of the multilayer wiring board 1 will be described. FIG. 14 is a diagram showing a process (fifth process) in which at least two wiring layers are formed on the first surface 10a side in addition to the first surface first layer 21a, and at least two wiring layers are formed on the second surface 10b side in addition to the second surface first layer 22a. After forming the through electrodes 15, metal wiring 21b1, and metal wiring 22b1 shown in FIG. 13, a resin material is placed on the first surface 10a side and the second surface 10b side, vias are formed by laser processing, a seed layer is formed by electroless plating or sputtering, and a resist pattern is formed by photolithography. Using the formed resist pattern, a wiring pattern is formed by electroplating, and then the resist pattern is peeled off and the excess seed layer is removed by etching. This forms the first-surface second layer 21b, which includes the through-hole electrodes and metal wiring 21b2 connected to the metal wiring 22b1, and the second-surface second layer 22b, which includes the through-hole electrodes and metal wiring 22b2 connected to the metal wiring 22b1. The above process is then repeated depending on the number of layers required. In the example shown in FIG. 14, a total of six wiring layers (21a to 21f, 22a to 22f) are formed on the first surface 10a and the second surface 10b, respectively. The outermost layers 21g and 22g have solder resist layers 40 formed thereon. The outermost layer 21g has insertion openings for connection terminals of the semiconductor element 100, and solder bumps 50, such as Sn, SnAg, Ni / Sn, Ni / SnAg, Ni / Cu / Sn, or Ni / Cu / SnAg, are formed in the insertion openings. The order of forming the wiring layers is not limited to the above. After forming the wiring layers 21a to 21f and the outermost layer 21g on the first surface 10a side, the wiring layers 22a to 22f and the outermost layer 22g on the second surface 10b side may be formed.

[0058] The resin material used for the wiring layers (21a to 21f, 22a to 22f) included in the first surface layer structure 21 and the second surface layer structure 22 is the same as the resin material filled in the through holes 11. The method for laminating the resin material can be selected from vacuum pressure pressing, heat pressing, compression molding, transfer molding, etc., but vacuum pressure pressing is preferably used. However, the method is not limited to the above-described content, and the process and method can be appropriately changed as needed.

[0059] Next, referring to FIG. 15 , the singulation process of the multilayer wiring substrate 1 will be described. FIG. 15 is a diagram schematically illustrating a glass epoxy substrate 30A and alignment marks used in the dicing process. In FIG. 15 , the alignment marks 31 are indicated by dashed lines. The alignment marks 31 are arranged at the interval G1 of the glass epoxy substrate 30A. The alignment marks 31 are formed, for example, on the solder resist layer 40 of the first surface layer structure 21 in FIG. 14 . After the alignment marks 31 are formed, a sixth process is performed in which the inorganic substrates 10 arranged on the glass epoxy substrate 30A are diced by blade dicing to singulate the spaces between the inorganic substrates 10. Specifically, the multilayer wiring substrate 1 is separated from the glass epoxy substrate 30A by dicing along the alignment marks 31 using a dicing blade. Because the process is performed along the glass epoxy substrate 30A, it is possible to obtain the multilayer wiring substrate 1 without contacting the inorganic substrates 10 with the blade. Note that the dicing process is not limited to the method described above. It is also possible to form alignment marks on the solder resist layers 40 of both the first surface layer structure 21 and the second surface layer structure 22 and perform dicing in both the positive and negative Z-axis directions.

[0060] <Examples and Comparative Examples According to Embodiments of the Present Invention> Multilayer wiring boards are fabricated and evaluated. In the following description, multilayer wiring boards 1 according to embodiments of the present invention are referred to as Examples 1 to 3, and comparative examples are referred to as Comparative Examples 1 to 3. Examples 1 to 3 correspond to the configuration of multilayer wiring board 1 shown in FIG. 1. Comparative Example 1 corresponds to the configuration of FIG. 16. Comparative Examples 2 and 3 correspond to the configuration of FIG. 17.

[0061] Example 1 In Example 1, glass having a linear expansion coefficient of 3.1 ppm / °C, an elastic modulus of 77 GPa, and a thickness T1 of 0.7 mm was used as the inorganic substrate 10. Furthermore, a glass epoxy substrate (E-705G, manufactured by Resonac Inc.) having a thickness of 0.7 mm, the same thickness T1 as the inorganic substrate 10, was used as the glass epoxy substrate 30A. A material having a linear expansion coefficient of 20 ppm / °C, an elastic modulus of 7.5 MPa, and a filler content of 72 wt% was used as the resin material constituting the protective resin portion 25. The first surface layer structure 21 contained eight wiring layers, and the second surface layer structure 22 also contained eight wiring layers. Furthermore, when viewed from above (i.e., when viewed from the positive Z-axis direction), the multilayer wiring substrate 1 had a square shape and a length L of 120 mm. (Production conditions of Example 1) Inorganic substrate 10: glass with linear expansion coefficient of 3.1 ppm / °C, elastic modulus of 77 GPa, and thickness T1 = 0.7 mm Resin material: linear expansion coefficient of 20 ppm / °C, elastic modulus of 7.5 MPa, filler content 72 wt% Glass epoxy substrate: E-705G with a thickness of 0.7 mm (manufactured by Resonac Inc.) Size (dimensions in the xy plane): 120 × 120 mm Number of wiring layers included in first surface layer structure 21 and second surface layer structure 22: 8 layers Average remaining copper ratio of wiring layers included in first surface layer structure 21: 84% Average remaining copper ratio of wiring layers included in second surface layer structure: 76%

[0062] Example 2 In Example 2, ceramics with a linear expansion coefficient of 6.1 ppm / °C, an elastic modulus of 57 GPa, and a thickness T1 of 0.7 mm were used as the inorganic substrate 10. Other than this, the configuration was the same as in Example 1. (Production conditions for Example 2) Inorganic substrate 10: ceramics with a linear expansion coefficient of 6.1 ppm / °C, an elastic modulus of 57 GPa, and a thickness T1 of 0.7 mm Resin material: linear expansion coefficient of 20 ppm / °C, an elastic modulus of 7.5 MPa, and a filler content of 72 wt% Glass epoxy substrate: E-705G (manufactured by Resonac Inc.) with a thickness of 0.7 mm Size (dimensions in the xy plane): 120 x 120 mm Number of wiring layers included in the first surface layer structure 21 and the second surface layer structure 22: 8 layers Average remaining copper ratio of the wiring layers included in the first surface layer structure 21: 84% Average remaining copper ratio of the wiring layers included in the second surface layer structure 22: 76%

[0063] A comparative example of the multilayer wiring board 1 according to the embodiment of the present invention will be described with reference to FIGS. 16 and 17. FIG.

[0064] 16 is a cross-sectional view of a multilayer wiring board of Comparative Example 1. Multilayer wiring board 1-1 of Comparative Example 1 differs from Examples 1 and 2 in that an organic substrate 10-1 is used as a core substrate instead of inorganic substrate 10, through electrodes 15 are formed in through holes of organic substrate 10-1 without disposing a resin material therein, first-surface first layer 21a-1 and second-surface first layer 22a-1 include metal wiring, and metal wiring is disposed on organic substrate 10-1, and a configuration corresponding to peripheral protective portion 30 is not included. In the following description, descriptions of components that are the same as or equivalent to those of Examples 1 and 2 described above will be simplified or omitted.

[0065] In Comparative Example 1, a glass epoxy substrate 30 (E-705G, manufactured by Resonac Inc.) having a thickness T1-1 of 1.2 mm was used as the organic substrate 10-1. A material with a linear expansion coefficient of 20 ppm / °C, an elastic modulus of 7.5 MPa, and a filler content of 72 wt% was used as the resin material constituting the first surface layer structure 21-1 and the second surface layer structure 22-1. A multilayer wiring substrate 1 having the structure shown in FIG. 17 was formed. The multilayer wiring substrate 1 was configured as follows: (Production conditions for Comparative Example 1) Organic substrate 10-1: E-705G (manufactured by Resonac Inc.) having a thickness of 1.2 mm Resin material: Linear expansion coefficient 20 ppm / °C, elastic modulus 7.5 MPa, filler content 72 wt% Size (dimensions in the xy plane): 120 x 120 mm Number of wiring layers included in first surface layer structure 21-1 and second surface layer structure 22-2: 7 layers Average remaining copper ratio of wiring layers included in first surface layer structure 21-1: 84% Average remaining copper ratio of wiring layers included in second surface layer structure 22-1: 76%

[0066] 17 is a cross-sectional view of a multilayer wiring board 1-2 of Comparative Example 2. The multilayer wiring board 1-2 of Comparative Example 2 differs from Examples 1 and 2 in that the through electrodes 15 are formed without disposing a resin material in the through holes of the inorganic substrate 10-2, that the first-surface first layer 21a-2 and the second-surface first layer 22a-2 include metal wiring, and the metal wiring is disposed on the inorganic substrate 10-2, and that the multilayer wiring board 1-2 does not include a configuration corresponding to the peripheral protection portion 30. In the following description, descriptions of components that are the same as or equivalent to those of Examples 1 and 2 described above will be simplified or omitted.

[0067] In Comparative Example 2, glass with a linear expansion coefficient of 3.1 ppm / °C, an elastic modulus of 77 GPa, and a thickness of 0.7 mm was used as the inorganic substrate 10-2. Furthermore, a material with a linear expansion coefficient of 20 ppm / °C, an elastic modulus of 7.5 MPa, and a filler content of 72 wt % was used as the resin material constituting the first surface layer structure 21-2 and the second surface layer structure 22-2. The configurations of the wiring layers included in the first surface layer structure 21-2 and the second surface layer structure 22-2 were the same as in Comparative Example 1. (Production conditions for Comparative Example 2) Inorganic substrate 10-2: glass with a linear expansion coefficient of 3.1 ppm / °C, an elastic modulus of 77 GPa, and a thickness T1 of 0.7 mm Resin material: a linear expansion coefficient of 20 ppm / °C, an elastic modulus of 7.5 MPa, and a filler content of 72 wt% Size (dimensions in the xy plane): 120 x 120 mm Number of wiring layers included in first surface layer structure 21-2 and second surface layer structure 22-2: 7 layers Average remaining copper ratio of wiring layers included in first surface layer structure 21-2: 84% Average remaining copper ratio of wiring layers included in second surface layer structure 22-2: 76%

[0068] Comparative Example 3 Comparative Example 3 has the same configuration as the structure shown in Fig. 17. It differs from Comparative Example 2 in that ceramics with a linear expansion coefficient of 6.1 ppm / °C, an elastic modulus of 57 GPa, and a thickness of 0.7 mm were used as the inorganic substrate 10-2. All other points were the same as Comparative Example 2. (Production conditions for Comparative Example 3) Inorganic substrate 10-2: ceramics with a linear expansion coefficient of 6.1 ppm / °C, an elastic modulus of 57 GPa, and a thickness T1 = 0.7 mm Resin material: linear expansion coefficient of 20 ppm / °C, an elastic modulus of 7.5 MPa, filler content 72 wt% Size (dimensions in the xy plane): 120 x 120 mm Number of wiring layers included in the first surface layer structure 21-2 and the second surface layer structure 22-2: 7 layers Average remaining copper ratio of wiring layers included in the first surface layer structure 21-2: 84% Average remaining copper ratio of wiring layers included in the second surface layer structure 22-2: 76%

[0069] <Evaluation Results> Table 1 shows the failure rate in the singulation process when multilayer wiring boards of each Example and Comparative Example were produced. Dicing was performed under the conditions shown below for each Example and Comparative Example. The number n of multilayer wiring boards produced by dicing was 200. <Dicing Conditions> Dicing blade: R07-SD600-BB200-75, 56 x 0.15A2 x 40 (manufactured by Disco Corporation) Blade rotation speed: 30,000 rpm Blade feed speed: 10 mm / sec

[0070] As shown in Table 1, no failures occurred during the singulation process in Examples 1 and 2 and Comparative Example 1, whereas failures occurred at a rate of 96.7% in Comparative Example 1 and 75.2% in Comparative Example 2. In Comparative Examples 1 and 2, the glass and ceramics are directly processed by the dicing blade, resulting in a reduced grinding amount compared to when the glass epoxy substrate 30A is diced as in Examples 1 and 2, and there is a possibility of chipping or cracking occurring on the processed surface. The failure rates shown in Table 1 include cases where chipping or cracking occurs during dicing, and cases where cracks occur in the core substrate due to stress caused by the difference in linear expansion coefficients between the wiring layers included in the first and second surface layer structures and the core substrate (inorganic substrates 10 and 10-2, organic substrate 10-1).

[0071] Table 2 shows the amount of warpage of the multilayer wiring boards of each example and comparative example that were subjected to thermal history with the semiconductor element 100 mounted on them. The thermal history with the semiconductor element 100 mounted was performed by heating from room temperature (RT) to 260°C and then cooling back to RT, and the warpage of the multilayer wiring board was evaluated at 10°C intervals. Ten samples were evaluated, and the average amount of warpage was calculated. The amount of warpage shown in Table 2 is the amount of warpage when maintained at 260°C, and a smaller amount of warpage is desirable for a multilayer wiring board. As shown in Table 2, the warpage was 66.4 μm in Example 1, 89.7 μm in Example 2, 213.1 μm in Comparative Example 1, and 71.5 μm in Comparative Example 3. Comparative Example 2 had a high failure rate during the singulation process and was therefore unsatisfactory. Comparative Example 3 showed a good result of 71.5 μm, but the failure rate during the singulation process was high, making it unfeasible for industrial use. The warpage of the multilayer wiring board 1 in Examples 1 and 2 was smaller than that in Comparative Example 1, being 100 μm or less, and it can be determined that the structure is excellent. The warpage was measured by the shadow amortization method using a Thermoray manufactured by AcroMetrix.

[0072] Table 3 shows the reliability evaluation results of the temperature cycle test for each example and comparative example. The temperature cycle test consisted of a cycle in which the temperature was raised from −55°C to RT, then to 125°C, and then back to RT and −55°C. Each temperature was maintained for 30 minutes. After a predetermined number of cycles, visual inspections for chips and cracks and predetermined electrical characteristic tests were performed. Furthermore, before entering the temperature cycle test, reflow at 260°C was performed three times. Visual inspections and electrical characteristic tests were also performed before entering the temperature cycle test (referred to as “after singulation” in the table) and after reflow (referred to as “multiple reflow” in the table). The number of samples evaluated was 20. If 90% of the samples passed both the visual inspection and the electrical characteristic test, the test was marked “Passed.” Otherwise, the test was marked “Failed.” As shown in Table 3, Example 1, Example 2, and Comparative Example 1 passed the test and ensured reliability even after 2000 cycles, but Comparative Examples 2 and 3 failed to pass the inspection before and after the temperature cycle test, and did not ensure reliability.

[0073] <Actions and Effects> As described above, according to the embodiment of the present invention, it is possible to suppress warpage and achieve high reliability. As a result, it is possible to provide a multilayer wiring board 1 that is capable of suppressing warpage and has high reliability.

[0074] <Industrial Applicability> The present invention makes it possible to provide a multilayer wiring board 1 that is capable of suppressing warpage and has high reliability. This makes it possible to mount multiple semiconductor elements, which can contribute to improving the performance of semiconductor devices such as GPUs and CPUs. It can also be used as a photoelectric conversion package used in optical data communications and a multilayer wiring board for optical disaggregated computing, which can contribute to the realization of a data communications society and Society 5.0.

[0075] The scope of the present invention is not limited to the exemplary embodiments shown and described, but includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0076] The following are some non-limiting aspects of the present invention. (Aspect 1) A multilayer wiring board comprising: an inorganic substrate having a first surface, a second surface opposite the first surface, and a side surface connecting a peripheral edge of the first surface with a peripheral edge of the second surface, the inorganic substrate having at least one through hole formed therein and penetrating from the first surface to the second surface; a protective resin portion disposed in the through hole of the inorganic substrate and covering the side surface of the inorganic substrate; and a through electrode including a conductor portion extending into the through hole and electrically connecting the first surface with the second surface. (Aspect 2) The multilayer wiring board according to Aspect 1, wherein the conductor portion is covered by the protective resin portion in the through hole. (Aspect 3) The multilayer wiring board according to Aspect 1 or Aspect 2, wherein the protective resin portion disposed between the inorganic substrate and the conductor portion in the through hole has a thickness of at least 10 μm. (Aspect 4) A multilayer wiring board according to any one of Aspects 1 to 3, further comprising: a first surface layer structure formed on the first surface of the inorganic substrate; and a second surface layer structure formed on the second surface of the inorganic substrate; each of the first surface layer structure and the second surface layer structure has two or more wiring layers; a first surface first layer included in the first surface layer structure and formed on the inorganic substrate, and a second surface first layer included in the second surface layer structure and formed on the inorganic substrate, do not have metal wiring; and metal wiring is formed in the wiring layer included in the first surface layer structure excluding the first surface first layer and the wiring layer included in the second surface layer structure excluding the second surface first layer. (Aspect 5) The multilayer wiring board according to any one of Aspects 1 to 4, characterized in that the protective resin portion is made of the same resin material as the resin material used for the wiring layers included in the first surface layer structure and the second surface layer structure, the resin material is mixed in a range of 40 wt% to 80 wt% and contains a filler having an average particle diameter in a range of 0.3 μm to 1.0 μm, and further contains a build-up resin or glass cloth.(Aspect 6) The multilayer wiring board according to any one of Aspects 1 to 5, wherein the thickness of the protective resin portion arranged on the side surface of the inorganic substrate is at least 50 μm. (Aspect 7) The multilayer wiring board according to any one of Aspects 1 to 6, wherein the outer periphery of the multilayer wiring board is covered by an outer periphery protective portion formed by separating a portion of the protective resin portion and the glass epoxy substrate. (Aspect 8) The multilayer wiring board according to any one of Aspects 1 to 7, wherein a capacitor is arranged on the inorganic substrate. (Aspect 9) The multilayer wiring board according to any one of Aspects 1 to 8, wherein the inorganic substrate is made of glass or a ceramic material. (Aspect 10) A semiconductor device comprising at least one semiconductor element mounted on the multilayer wiring board according to any one of Aspects 1 to 9 via an interposer substrate. (Aspect 11) A first step of singulating a base substrate to form an inorganic substrate having a first surface, a second surface opposite the first surface, and a side surface connecting a peripheral portion of the first surface with a peripheral portion of the second surface, and having at least one through hole formed therein penetrating from the first surface to the second surface; a second step of arranging the inorganic substrate on a windowed glass epoxy substrate, and disposing a resin material on the first surface, the second surface, the side surface, and in the through hole of the inorganic substrate, to form a first-surface first layer on the first surface, and a second-surface first layer on the second surface; a third step of forming a sub-through hole, which is a through hole formed in the resin material, using a laser in the through hole; a fourth step of arranging a conductor in the sub-through hole, the first-surface first layer, and the second-surface first layer; and a fifth step of forming at least two wiring layers in addition to the first-surface first layer on the first surface side, and forming at least two wiring layers in addition to the second-surface first layer on the second surface side. a sixth step of dicing the spaces between the inorganic substrates arranged on the glass epoxy substrate by blade dicing to separate the substrates into individual pieces.(Aspect 12) The method for manufacturing a multilayer wiring board according to Aspect 11, wherein in the second step, the inorganic substrates arranged on the glass epoxy substrate are spaced apart by at least 50 μm. (Aspect 13) The method for manufacturing a multilayer wiring board according to Aspect 11 or Aspect 12, wherein in the fourth step, a seed layer is formed by electroless copper plating, and the conductor portion is formed by electrolytic plating. (Aspect 14) The method for manufacturing a multilayer wiring board according to any one of Aspects 11 to 13, wherein in the first step and the second step, a capacitor is arranged on the inorganic substrate. (Aspect 15) The method for manufacturing a multilayer wiring board according to any one of Aspects 11 to 14, wherein the inorganic substrate is made of glass or a ceramic material. (Aspect 16) The method for manufacturing a multilayer wiring board according to any one of Aspects 11 to 15, wherein in the fourth step, the conductor portion is not formed in a location where the dicing process is performed.

[0077] 1, 1-1, 1-2, 1a: multilayer wiring substrate, 10, 10-2: inorganic substrate, 10-1: organic substrate, 10A: base substrate, 11: through hole, 12: sub-through hole, 15: through electrode, 21: first surface layer structure, 22: second surface layer structure, 25: protective resin part, 30: peripheral protection part, 30A: glass epoxy substrate, 40: solder resist layer, 50: solder bump, 60: capacitor, 100: semiconductor element, 200: semiconductor device, TC: center line of through hole 11, SS: tangent line between through hole 11 and side surface

Claims

1. A multilayer wiring board comprising: an inorganic substrate having a first surface, a second surface opposite the first surface, and a side surface connecting a peripheral portion of the first surface with a peripheral portion of the second surface, the inorganic substrate having at least one through hole formed therein penetrating from the first surface to the second surface; a protective resin portion disposed in the through hole of the inorganic substrate and disposed so as to cover the side surface of the inorganic substrate; and a through electrode including a conductive portion extending into the through hole, electrically connecting the first surface and the second surface.

2. The multilayer wiring board according to claim 1, wherein in said through hole, said conductor portion is covered with said protective resin portion.

3. The multilayer wiring board according to claim 2, characterized in that the thickness of the protective resin portion disposed between the inorganic substrate and the conductor portion in the through hole is at least 10 μm.

4. The multilayer wiring board according to claim 1, further comprising: a first surface layer structure formed on the first surface of the inorganic substrate; and a second surface layer structure formed on the second surface of the inorganic substrate, wherein both the first surface layer structure and the second surface layer structure have two or more wiring layers, a first surface first layer included in the first surface layer structure and formed on the inorganic substrate, and a second surface first layer included in the second surface layer structure and formed on the inorganic substrate do not have metal wiring, and metal wiring is formed in the wiring layer included in the first surface layer structure excluding the first surface first layer and the wiring layer included in the second surface layer structure excluding the second surface first layer.

5. The multilayer wiring board according to claim 4, characterized in that the protective resin portion is made of the same resin material as that used for the wiring layers included in the first surface layer structure and the second surface layer structure, the resin material contains a filler mixed in a range of 40 wt % or more and 80 wt % or less and having an average particle size in a range of 0.3 μm or more and 1.0 μm or less, and further contains a build-up resin or a glass cloth.

6. The multilayer wiring board according to claim 1, characterized in that the thickness of the protective resin portion disposed on the side surface of the inorganic substrate is at least 50 μm.

7. The multilayer wiring board according to claim 1, characterized in that the outer periphery of the multilayer wiring board is covered with a protective resin part and an outer periphery protection part formed by separating a part from the glass epoxy board.

8. The multilayer wiring board according to claim 1, wherein the inorganic substrate is made of glass or a ceramic material.

9. A semiconductor device comprising: at least one semiconductor element mounted on the multilayer wiring board according to any one of claims 1 to 8 via an interposer substrate.

10. A first step of singulating a base substrate to form an inorganic substrate having a first surface, a second surface opposite to the first surface, and a side surface connecting a peripheral portion of the first surface with a peripheral portion of the second surface, and in which at least one through hole is formed penetrating from the first surface to the second surface; a second step of disposing the inorganic substrate on a windowed glass epoxy substrate, disposing a resin material on the first surface, the second surface, the side surface and in the through hole of the inorganic substrate, forming a first surface first layer on the first surface, and forming a second surface first layer on the second surface; a third step of forming a sub-through hole, which is a through hole formed in the resin material, in the through hole using a laser; a fourth step of disposing a conductor portion in the sub-through hole, the first surface first layer and the second surface first layer; a fifth step of forming at least two wiring layers in addition to the first surface first layer on the first surface side, and forming at least two wiring layers in addition to the second surface first layer on the second surface side. a sixth step of dicing the gaps between the inorganic substrates arranged on the glass epoxy substrate by blade dicing to separate the substrates.

11. The method for manufacturing a multilayer wiring board according to claim 10, wherein in the second step, the distance between the inorganic substrates arranged on the glass epoxy substrate is at least 50 μm or more.

12. The method for manufacturing a multilayer wiring board according to claim 10, characterized in that in the fourth step, a seed layer is formed by electroless copper plating, and the conductor portion is formed by electrolytic plating.

13. The method for manufacturing a multilayer wiring board according to claim 10, wherein the inorganic substrate is made of glass or a ceramic material.

14. The method for manufacturing a multilayer wiring board according to claim 10, characterized in that in the fourth step, the conductive portion is not formed in a location where the dicing process is performed.

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