Ad conversion device, integrated circuit, and electronic apparatus

Abstract

An AD conversion device according to the present disclosure is provided with: a first analog-to-digital (AD) conversion unit that executes a first AD conversion on an input voltage that is sampled at a fixed cycle; a second AD conversion unit that executes a second AD conversion on the basis of a residual error of the first AD conversion executed by the first AD conversion unit in an immediately preceding cycle; and an encoding unit that generates an output signal by AD-converting the input voltage sampled in the immediately preceding cycle on the basis of an AD conversion result obtained by the first AD conversion unit in the immediately preceding cycle and an AD conversion result obtained by the second AD conversion unit.

Description

AD conversion device, integrated circuit and electronic device

[0001] The present disclosure relates to an AD conversion device, an integrated circuit, and an electronic device.

[0002] In recent years, the data rate of a sensor signal output from an image sensor has become extremely high due to an increase in the number of pixels of the image sensor and a high frame rate.

[0003] Modulation methods called PAM4 (Pulse Amplitude Modulation 4) and PAM8 are being introduced that can effectively improve data rates by converting data into multi-values, in contrast to commonly used systems that transmit data in binary form, such as LVDS (Low Voltage Differential Signaling) and MIPI D-PHY (Mobile Industry Processor Interface D-PHY).

[0004] As a means for receiving signals modulated by PAM4 or PAM8, a method using a high-speed AD (Analog to Digital) converter has been proposed. Patent Document 1 describes a technology in which a SAR-ADC (Successive Approximation Register - Analog to Digital Converter) converts the higher-order bits, and a time measurement ADC converts the lower-order bits. Patent Document 1 makes it possible to shorten the total conversion time by utilizing the feature that the time measurement ADC has a higher operating frequency than the SAR-ADC.

[0005] JP 2013-251700 A

[0006] In Patent Document 1, the residual voltage generated by the SAR-ADC is used to perform AD conversion processing by a time measurement ADC. That is, according to the configuration described in Patent Document 1, the SAR-ADC and the time measurement ADC operate in time series, which causes an issue of increased conversion time. In Patent Document 1, this issue becomes more pronounced when AD conversion processing is performed with high resolution.

[0007] The AD conversion device according to the present disclosure includes a first AD conversion unit that performs a first AD (Analog to Digital) conversion on an input voltage sampled at a constant period; a second AD conversion unit that performs a second AD conversion based on a residual of the first AD conversion in a immediately preceding period by the first AD conversion unit; and an encoding unit that generates an output signal obtained by AD converting the input voltage sampled in the immediately preceding period based on the AD conversion result by the first AD conversion unit in the immediately preceding period and the AD conversion result by the second AD conversion unit.

[0008] An object of the present disclosure is to provide an AD conversion device, an integrated circuit, and an electronic device that are capable of performing AD conversion processing at higher speed.

[0009] 1 is a circuit diagram showing a configuration of an example of an SAR-ADC applicable to each embodiment of the present disclosure. 2 is a timing chart showing an example of operation by an SAR-ADC applicable to each embodiment of the present disclosure. 3 is a circuit diagram showing a configuration of an example of a time measurement ADC applicable to each embodiment of the present disclosure. 4 is a timing chart showing an example of operation of a time measurement ADC applicable to each embodiment of the present disclosure. 5 is a block diagram showing a schematic configuration of an example of an AD conversion device that serially processes an SAR-ADC and a time measurement ADC according to an existing technology. 6 is a timing chart showing an example of operation of an AD conversion device that serially processes an SAR-ADC and a time measurement ADC according to an existing technology. 7 is a block diagram showing a configuration of an example of an AD conversion device with a pipeline configuration according to an existing technology. 8 is a timing chart for explaining operation with a pipeline configuration according to an existing technology. 9 is a circuit diagram showing a schematic configuration of an AD conversion device according to an embodiment of the present disclosure. 10 is a timing chart showing an example of operation of an AD conversion device according to an embodiment of the present disclosure. 11 is a circuit diagram showing a configuration of an AD conversion device according to a first embodiment. 12 is a timing chart showing an example of operation of an AD conversion device according to the first embodiment. FIG. 1 is a circuit diagram illustrating an example of a configuration of an AD conversion device according to a second embodiment; FIG. 2 is a timing chart illustrating an example of an operation of the AD conversion device according to the second embodiment; FIG. 3 is a circuit diagram illustrating an example of a configuration of an AD conversion device according to a third embodiment; FIG. 4 is a timing chart illustrating an example of an operation of the AD conversion device according to the third embodiment; and FIG. 5 is a block diagram illustrating an example of a configuration of an electronic device to which the AD conversion devices according to each embodiment of the present disclosure can be applied.

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same components are denoted by the same reference numerals, and redundant description will be omitted.

[0011] Hereinafter, embodiments of the present disclosure will be described in the following order: 1. Technologies applicable to the present disclosure 2. Existing technologies 3. Overview of embodiments of the present disclosure 4. First embodiment of the present disclosure 5. Second embodiment of the present disclosure 6. Third embodiment of the present disclosure 7. Fourth embodiment of the present disclosure

[0012] The present disclosure relates to an AD (Analog to Digital) conversion device capable of higher speed operation, which employs a configuration combining a successive conversion type ADC (Analog to Digital Converter) and a time measurement ADC (Analog to Digital Converter). In the present disclosure, the successive conversion type ADC and the time measurement ADC are operated complementarily to achieve higher speed AD conversion.

[0013] In the following description, the successive conversion type ADC is referred to as a SAR-ADC (Successive Approximation Register ADC).

[0014] (1. Technology Applicable to the Present Disclosure) Technology applicable to embodiments according to the present disclosure will be briefly described.

[0015] (About SAR-ADC) First, we will provide an overview of SAR-ADC. SAR-ADC converts an analog input signal into a digital signal by successively comparing a reference voltage for a sampled input signal, starting from the MSB (Most Significant Bit), using a binary search.

[0016] Fig. 1 is a circuit diagram showing the configuration of an example of an SAR-ADC applicable to each embodiment of the present disclosure. In the example of Fig. 1, the SAR-ADC 100 includes a capacitance DAC (Digital to Analog Converter) 110, a switch 120, a comparator 130, and a logic circuit 140. Note that in Fig. 1 and in each figure described below, the "capacitive DAC" is referred to as "CDAC."

[0017] 1 , the capacitive DAC 110 includes a capacitor group 111 made up of multiple capacitors whose capacitances increase (decrease) in a binary fashion. In the example of FIG. 1 , the capacitors included in the capacitor group 111 have capacitances of C, 2C (=2×C), 4C (=4×C), and 8C (=8×C), which increase in a binary fashion (by a factor of two) from the side closest to the comparator 130. Each capacitor included in the capacitor group 111 has one end connected to a common node 113 and the other end connected to either a lower limit voltage VRB or an upper limit voltage VRT by two switches included in the switch group 112. The open / closed state of each switch included in the switch group 112 is controlled by a DAC control signal from the logic circuit 140.

[0018] One end of a common node 113 in the capacitive DAC 110 is connected to one input end of the comparator 130, and the other end is connected to one end of the switch 120. A voltage Vin (hereinafter referred to as input voltage Vin) generated by an input signal is input to the other end of the switch 120. The open / closed state of the switch 120 is controlled by a signal S supplied from the logic circuit 140. For example, the switch 120 is closed when the signal S is high, and is open when the signal S is low.

[0019] A reference voltage Vref is input to the other input terminal of the comparator 130. A clock signal C_CLK for controlling the comparison operation of the comparator 130 is also supplied to the comparator 130 from the logic circuit 140.

[0020] Fig. 2 is a timing chart illustrating an example of the operation of the SAR-ADC applicable to each embodiment of the present disclosure shown in Fig. 1. Note that one cycle of the clock signal C_CLK is from one falling edge to the next falling edge.

[0021] The logic circuit 140 generates a signal S in response to the clock signal C_CLK. The logic circuit 140 sets the signal S to a high state in the clock cycle at the start of the AD conversion process for one sample, and closes the switch 120. When the switch 120 is closed, the input voltage Vin is applied to each capacitor included in the capacitor group 111, and the input signal is sampled.

[0022] The logic circuit 140 samples the input signal and controls each switch included in the switch group 112 so that the other end of the capacitor with a capacitance of 8 C among the capacitors included in the capacitor group is connected to the upper limit voltage VRT and the other ends of the other capacitors are connected to the lower limit voltage VRB. With the switch 120 in an open state, the comparator 130 compares the voltage of the common node 113 in the capacitive DAC 110 with a reference voltage Vref and outputs a value of "1" or "0". The logic circuit 140 stores the value "1" or "0" output from the comparator 130 as a bit value of the MSB (Most Significant Bit) in, for example, a register included in the logic circuit 140.

[0023] Furthermore, if the output of the comparator 130 is "1", the reference voltage Vref is subtracted from the voltage of the capacitor group 111, and if the output is "0", the reference voltage Vref is added to the voltage of the capacitor group 111, which is used as the residual voltage for that bit.

[0024] In the next cycle of the clock signal C_CLK, the logic circuit 140 controls each switch included in the switch group 112 so that the other end of the next capacitor (a capacitor with a capacitance of 4C) in the capacitor group 111 is connected to the upper limit voltage VRT and the other ends of the remaining capacitors are connected to the lower limit voltage VRB. The comparator 130 compares the voltage of the common node 113 in the capacitive DAC 110 with the reference voltage Vref and outputs a value of "1" or "0". The logic circuit 140 stores the value of "1" or "0" output from the comparator 130 in, for example, a register as the bit value next to the MSB.

[0025] Furthermore, depending on the comparison result of the comparator 130, the reference voltage Vref is subtracted from or added to the voltage of the capacitor group 111 to obtain a residual voltage for the bit.

[0026] The logic circuit 140 sequentially repeats this operation up to the capacitor with the smallest capacitance in the capacitor group 111 (in this example, the capacitor with a capacitance of C), acquires the value of each bit up to the LSB (Least Significant Bit), and stores each acquired bit value in a register. A bit string based on each bit value read from the register of the logic circuit 140 is used as an output signal Dout of the AD conversion corresponding to the input voltage Vin. Furthermore, the voltage when the LSB bit is acquired in the capacitor group 111 is used as a residual voltage in the AD conversion.

[0027] The SAR-ADC 100 can obtain high resolution, but when the resolution is high, the number of comparisons by the comparator 130 increases, which causes a problem that the sampling frequency when obtaining a bit string becomes lower.

[0028] (Regarding Time Measurement ADC) Next, an outline of a time measurement ADC will be described. A time measurement ADC converts an analog input signal into a digital signal by converting a sampled voltage of the input signal into a time and measuring the time.

[0029] 3 is a circuit diagram showing an example of a configuration of a time measurement ADC applicable to each embodiment of the present disclosure. In FIG. 3, a time measurement ADC 200 includes a voltage to time converter (VTC) 201 and a time to digital converter (TDC) 202.

[0030] The VTC 201 includes a switch 210, a capacitor CS, a constant current source 211, and a comparator 212. The open / close state of the switch 210 is controlled by a signal S, and an input voltage Vin is input to one end of the switch 210. The other end is connected to one end of the capacitor CS, the constant current source 211, and one input end of the comparator 212. A reference voltage Vref is input to the other input end of the comparator 212. The comparator 212 compares the voltage Vd input to one input end with the reference voltage Vref input to the other input end, and outputs a signal Tdelay according to the comparison result to the TDC 202.

[0031] The TDC 202 includes a plurality of unit delay circuits UD, UD, ..., UD, each of which latches an input in accordance with a clock using a flip-flop (FF) circuit, and an encoding circuit 220 to which the outputs of the unit delay circuits UD, UD, ..., UD are input.

[0032] FIG. 4 is a timing chart illustrating an example of the operation of the time measurement ADC shown in FIG. 3 and applicable to each embodiment of the present disclosure.

[0033] The VTC 201 operates the switch 210 by the signal S from the start point of FIG. 100 The VTC 201 keeps the input terminal closed until the input voltage Vin is equal to the reference voltage Vref, and samples the input voltage Vin using the capacitor CS. After sampling the input voltage Vin, the VTC 201 subtracts the sampled input voltage Vin at a constant voltage slope using a constant current source 211, and inputs the subtracted voltage Vd to one input terminal of a comparator 212. The comparator 212 compares the voltage Vd with the reference voltage Vref, which is input to the other input terminal, as a threshold, and determines the time t when the voltage Vd and the reference voltage Vref match. 101 The signal Tdelay rises.

[0034] On the other hand, the TDC 202 delays the falling timing of the signal S by each unit delay using each unit delay circuit UD1, UD2, ..., UD7, and latches the rising timing of the signal Tdelay. In the example of Figure 4, the rising of the signal Tdelay is latched in the unit delay circuit UD6, and the outputs of the unit delay circuits UD1 to UD5 are each set to "0", and the outputs of the unit delay circuits after UD5 (unit delay circuits UD6 and onwards) are each set to "1".

[0035] The encoding circuit 220 encodes the output of each unit delay circuit UD1, UD2, . . . , UD7, and converts the signal Tdelay into a digital value in accordance with the rising timing.

[0036] The resolution of the AD conversion of the time measurement ADC 200 increases as a power of 2. That is, in order to increase the resolution of the time measurement ADC 200, it is necessary to increase the unit delay circuit UD by a power of 2, and the amount of delay for the signal Tdelay also increases. Therefore, similar to the above-described SAR-ADC 100, when the resolution is high, the time measurement ADC 200 also has the problem that the amount of delay for the signal Tdelay increases and the sampling frequency decreases.

[0037] (2. Existing Technology) Next, for ease of understanding, an outline of AD conversion processing using existing technology will be explained.

[0038] (Regarding serial processing of SAR-ADC and time measurement ADC) As one of the existing technologies, a configuration in which a SAR-ADC and a time measurement ADC are serially processed has been proposed. Fig. 5 is a block diagram showing a schematic configuration of an example of an AD conversion device in accordance with the existing technology that serially processes a SAR-ADC and a time measurement ADC. Fig. 6 is an example timing chart showing the operation of the configuration of Fig. 5.

[0039] 5, an AD conversion apparatus 1000 includes an SAR-ADC 1010, a time measurement ADC 1020 (shown as TADC 1020 in the figure), and an encoding circuit 1030. The SAR-ADC 1010 may have the configuration of the SAR-ADC 100 described with reference to FIGS. 1 and 2. The time measurement ADC 1020 may have the configuration of the time measurement ADC 200 described with reference to FIGS. 3 and 4.

[0040] 5, an input voltage Vin is input to the SAR-ADC 1010. The SAR-ADC 1010 samples the input voltage Vin in accordance with an external clock (Ext-CLK), as shown in Sample(k) in Fig. 6. The SAR-ADC 1010 sequentially performs AD conversion processing on Sample(k) for m bits starting from the MSB side, bit by bit, as described with reference to Figs. 1 and 2, and outputs the output signal ADout(m) that is the conversion result to the encoding circuit 1030.

[0041] In the example of Fig. 6, the SAR-ADC 1010 sequentially compares each of the four bits from the MSB to obtain the bit values ​​"0", "1", "0", and "1". Therefore, the output signal ADout(m) has a value of "4b'0101". Note that "4b'" indicates that the following numeric string is a four-digit binary number.

[0042] Furthermore, the SAR-ADC 1010 outputs a residual voltage resulting from the least significant bit generation process in the SAR-ADC 1010 to the time measurement ADC 1020. The time measurement ADC 1020 uses the residual voltage output from the SAR-ADC 1010 as an input voltage Vin to perform AD conversion process on n bits from the (m+1) bit to the LSB side, as described with reference to Figures 3 and 4, and outputs an output signal ADout(n) that is the conversion result to the encoding circuit 1030. In the example of Figure 6, the output signal ADout(n) has a value of "4b'1100".

[0043] The encoding circuit 1030 arranges the output signal ADout(m) output from the SAR-ADC 1010 and the output signal ADout(n) output from the time measurement ADC 1020 in bit order, generates and outputs an output signal ADout(m+n) in which Sample(k) has been AD converted.

[0044] The configuration in Figure 5 utilizes the feature that the operating frequency of the time measurement ADC is faster than that of the SAR-ADC to shorten the total conversion time. However, in the configuration in Figure 5, the SAR-ADC and the time measurement ADC operate in time series, so the total conversion time increases relative to the conversion times of the SAR-ADC and the time measurement ADC. This becomes more noticeable when the resolution is high.

[0045] (Regarding Pipeline Processing of SAR-ADC and Time Measurement ADC) In the configuration using the SAR-ADC and time measurement ADC described above, it is possible to improve throughput by adopting a pipeline configuration as one of the existing technologies. Fig. 7 is a block diagram showing the configuration of an example of an AD conversion device with a pipeline configuration according to the existing technology.

[0046] 7, an AD conversion device 1001 includes an SAR-ADC 1010, a time measurement ADC 1020 (shown as TADC 1020 in the figure), an encoding circuit 1040, and an SH (Sample & Hold) circuit 1050.

[0047] 7, the SAR-ADC 1010 samples the input voltage Vin(k), sequentially performs AD conversion processing on the sampled input voltage Vin(k) bit by bit, as described with reference to FIGS. 1 and 2, and outputs the upper bits (k) of the conversion result to the encoding circuit 1040, and also outputs a residual voltage (k) from the AD conversion processing to the SH circuit 1050. The encoding circuit 1040 stores the upper bits (k) supplied from the SAR-ADC 1010 in, for example, a register.

[0048] The SH circuit 1050 holds the residual voltage (k) in the AD conversion process supplied from the SAR-ADC 1010. The time measurement ADC 1020 uses the residual voltage (k) held by the SH circuit 1050 as an input voltage to perform AD conversion of the lower bits (k) of the higher bits (k) of the SAR-ADC 1010, as described with reference to FIGS. 3 and 4 , and outputs the lower bits (k) of the conversion result to the encoding circuit 1040.

[0049] The encoding circuit 1040 arranges the lower bits (k) output from the time measurement ADC 1020 and the upper bits (k) stored in the register in bit order to generate and output an output signal Dout(k) obtained by AD converting the sampled input voltage Vin(k).

[0050] While the time measurement ADC 1020 is performing AD conversion processing using the residual voltage (k) corresponding to the input voltage Vin(k) held in the SH circuit 1050, the SAR-ADC 1010 samples the next input voltage Vin(k+1) and performs AD conversion processing on the sampled input voltage Vin(k+1).

[0051] Fig. 8 is a timing chart for explaining operation with a pipeline configuration according to existing technology. Section (a) of Fig. 8 shows a time chart of operation by the AD conversion device 1000 in which the SAR-ADC and time measurement ADC shown in Fig. 5 are serially processed, for example. Section (b) of Fig. 8 shows a time chart of operation by the AD conversion device 1001 with the pipeline configuration shown in Fig. 7. In addition, in section (b), the upper chart shows operation of the SAR-ADC 1010 of the AD conversion device 1001, and the lower chart shows operation of the time measurement ADC 1020 of the AD conversion device 1001.

[0052] As shown in sections (a) and (b), in the AD conversion devices 1000 and 1001, the leading time t 110 ~t 111The input voltage Vin(k) is sampled at time t 111 ~t 112 Then, the SAR-ADC 1010 performs AD conversion processing on Sample(k).

[0053] As shown in section (a) of FIG. 8, the AD conversion apparatus 1000 112 After the AD conversion process by the SAR-ADC 1010 is completed, the residual voltage by the AD conversion process is used to calculate the time t 112 From time t 113 The time measurement ADC 1020 performs AD conversion during the period t 110 ~t 113 is the conversion time for serial processing.

[0054] On the other hand, as shown in the lower chart of section (b), in the AD conversion device 1001, the time measurement ADC 1020 performs AD conversion processing based on Sample(k-1) immediately before Sample(k) on which the SAR-ADC 1010 is performing AD conversion processing. 112 ~t 113 During this period, Sample(k+1) next to Sample(k) is sampled, and AD conversion processing is performed on Sample(k+1) by the SAR-ADC 1010, and AD conversion processing based on Sample(k) is performed in the time measurement ADC 1020.

[0055] Therefore, the pipeline process takes place within a time t 110 ~t 112 is the conversion time, and time t 110 ~t 113 Compared to serial processing where the conversion time is 1, the sampling frequency can be made higher and throughput is improved.

[0056] However, in a pipeline configuration, as shown in FIG. 7, an SH circuit 1050 is required, and the mounting area and power consumption of the SH circuit 1050 increase compared to, for example, a serial processing configuration.

[0057] (Regarding other methods based on existing technology) One method for directly improving the sampling frequency in AD conversion processing is to provide two ADCs and perform AD conversion processing by interleaving the two ADCs. However, this method has the problem that the performance of the AD conversion processing rapidly deteriorates if there is an offset error or gain error between the two ADCs.

[0058] 9 is a circuit diagram illustrating an example of a configuration of an AD conversion device according to an embodiment of the present disclosure.

[0059] 9, the AD conversion device 1a according to the embodiment includes a SAR-ADC 100, a VTC 201a and a TDC 202 that constitute a time measurement ADC, a switch 210, and an encoding circuit 300. The configuration shown in FIG. 9 also includes one input channel using an input voltage Vin as an input channel to which an input voltage is input.

[0060] 1 and 2 can be applied to the SAR-ADC 100, and therefore a description thereof will be omitted. Similarly, the TDC 202 can be applied to the TDC 202, and therefore a description thereof will be omitted.

[0061] 9, the open / closed state of a switch 210 is controlled by a signal S supplied from a logic circuit 140, similar to the switch 120 shown in FIG. 1. An input voltage Vin is input to one end of the switch 210, and the other end is connected to one end of a common node 113a to which one end of each capacitor included in the capacitor group 111 in the SAR-ADC 100 is connected. Furthermore, the reference voltage Vref input to the other input end of the comparator 212 is omitted.

[0062] In FIG. 9, the VTC 201a includes a constant current source 211 and a comparator 212, as well as switches 213a, 213b, 213c and 213d and capacitors CS1 and CS2.

[0063] One end of capacitor CS1 is connected to the ground voltage, and the other end is connected to one end of switches 213a and 213b. Capacitor CS2 is connected to the ground voltage, and the other end is connected to one end of switches 213c and 213d. The other end of switch 213a and the other end of switch 213c are connected to common node 113a, and the other end of switch 213b and the other end of switch 213d are connected to constant current source 211 and one input end of comparator 212. The open / closed states of switches 213a and 213d are controlled by signal S1, and the open / closed states of switches 213b and 213c are controlled by signal S2.

[0064] The switches 213a and 213d, and the switches 213b and 213c are mutually exclusively controlled in their open / closed states by signals S1 and S2.

[0065] That is, if the switches 213a and 213d are controlled to be in a closed state by the signal S1, the switches 213b and 213c are controlled to be in an open state by the signal S2. In this case, the capacitor CS1 is connected to the common node 113a and the connection to the constant current source 211 and the comparator 212 is cut off, and the capacitor CS2 is connected to the constant current source 211 and the comparator 212 and the connection to the common node 113a is cut off.

[0066] On the other hand, if the switches 213a and 213d are controlled to be open by the signal S1, the switches 213b and 213c are controlled to be closed by the signal S2. In this case, the capacitor CS1 is connected to the constant current source 211 and the comparator 212 and the connection to the common node 113a is cut off, and the capacitor CS2 is connected to the common node 113a and the connection to the constant current source 211 and the comparator 212 is cut off.

[0067] In this way, the capacitors CS1 and CS2 are exclusively connected to the constant current source 211, the comparator 212, and the common node 113a under the control of the signals S1 and S2.

[0068] The signals S1 and S2, and the signal S, are generated by the logic circuit 140 based on, for example, an externally supplied clock signal. However, without being limited to this, all or any of the signals S1 and S2, and the signal S may be generated by an external control circuit.

[0069] FIG. 10 is a timing chart illustrating an example of the operation of the AD conversion device 1a according to the embodiment of the present disclosure illustrated in FIG.

[0070] The logic circuit 140 detects the time t 10 ~t 11 The signal S is set to a high state during the period of time t 10 ~t 12 The logic circuit 140 sets the signal S1 to a high state for a period of time t 12 The low state is maintained until the signal S is made high again at time t 10 ~t 11 The switch 210 is closed during the period t 10 ~t 12 During this period, the switches 213a and 213d are closed, and the switches 213b and 213c are open.

[0071] The period during which the signal S is in a high state (time t 10 ~t 11 At time t, the input voltage Vin is sampled as Sample(k) by the capacitor CS1 via the switches 210 and 213a. 11 When the signal S is set to a low state and the switch 210 is closed, the SAR-ADC 100 performs AD conversion processing (k) of the most significant bits based on the input voltage Vin(Sample(k)) sampled by the capacitor CS1 and supplied via the switch 213a. The conversion result of the AD conversion processing (k) by the SAR-ADC 100 is stored in, for example, the encoding circuit 300.

[0072] Also, the time t when the signal S1 is in a high state 10 ~t 12 During this period, the capacitor CS2 is connected to the constant current source 211 and the comparator 212 via the switch 213d. As a result, the VTC 201a and the TDC 202 perform AD conversion processing (k-1) of the lower bits based on the residual voltage by the SAR-ADC 100 that was written to the capacitor CS2 in the previous sampling period.

[0073] The encoding circuit 300 outputs the AD conversion result for Sample(k-1) as an output signal Dout(k-1) based on the conversion result of the AD conversion process (k-1) of the lower bits by the VTC 201a and the TDC 202 and the AD conversion process (k-1) of the higher bits performed by the SAR-ADC 100 in the previous sampling period.

[0074] The logic circuit 140 detects the time t 12 ~t 13 The signal S is set to a high state during the period of time t 12 ~t 14 During the period t, the signal S1 is in a low state and the signal S2 is in a high state. 12 ~t 13 The switch 210 is closed during the period t 12 ~t 14 During this period, the switches 213a and 213d are in an open state, and the switches 213b and 213c are in a closed state.

[0075] The period during which the signal S is in a high state (time t 12 ~t 13 At time t, the input voltage Vin is sampled as Sample(k+1) by the capacitor CS2 via the switches 210 and 213c. 13 When the signal S is set to a low state and the switch 210 is closed, the SAR-ADC 100 performs an AD conversion process (k+1) of the most significant bits based on the input voltage Vin(Sample(k+1)) sampled in the capacitor CS2 and supplied via the switch 213c.

[0076] Also, the time t when the signal S2 is in a high state 12~t 14 During this period, the capacitor CS1 is connected to the constant current source 211 and the comparator 212 via the switch 213b. As a result, the VTC 201a and the TDC 202 perform AD conversion processing (k) of the lower bits based on the residual voltage by the SAR-ADC 100 that was written to the capacitor CS1 in the previous sampling period.

[0077] In this way, the AD conversion device 1a according to an embodiment of the present disclosure performs AD conversion processing of the higher-order bits by the SAR-ADC 100 and AD conversion processing of the lower-order bits by the time measurement ADCs (VTC 201a and TDC 202) in a complementary manner with different sampling periods. Therefore, the AD conversion device 1a according to an embodiment of the present disclosure can output the output signal Dout at a period shorter than the sampling period in existing technology that serially processes AD conversion processing of the higher-order bits by the SAR-ADC and AD conversion processing of the lower-order bits by the time measurement ADC.

[0078] (4. First Embodiment of the Present Disclosure) Next, a first embodiment of the present disclosure will be described. The first embodiment of the present disclosure is an example in which an SAR-ADC has two capacitive DACs, and these two capacitive DACs are switched for each sampling period to perform complementary AD conversion processing between the SAR-ADC and the time measurement ADC.

[0079] 11 is a circuit diagram illustrating an example of the configuration of the AD conversion apparatus according to the first embodiment. The circuit diagram illustrated in FIG. 11 is shown as a differential circuit that corresponds to processing using input voltages VinP and VinN, which are generated based on the input voltage Vin and have inverted polarities. That is, the configuration illustrated in FIG. 11 has two input channels, one for the input voltage VinP and the other for the input voltage VinN, as input channels to which the input voltages are input.

[0080] 11, the AD conversion device 1b includes capacitive DACs 110pn1 and 110pn2 (also shown as CDAC(1) and CDAC(2) in the figure, respectively), a comparator 130a, a logic circuit 140a, a VTC 201a, a TDC 202, and an encoding circuit 300. Of these, the capacitive DACs 110pn1 and 110pn2, the comparator 130a, and the logic circuit 140a form an SAR-ADC. Furthermore, the VTC 201a and the TDC 202 form a time measurement ADC.

[0081] In FIG. 11, the AD conversion device 1b further includes switches 230aP and 230aN, switches 230bP and 230bN, switches 231aP1 and 231aN1, switches 231aP2 and 231aN2, switches 231bP1 and 231bN1, and switches 231bP2 and 231bN2.

[0082] The open / closed states of switches 230aP and 230aN are controlled by a signal S1. The open / closed states of switches 230bP and 230bN are controlled by a signal S2. The open / closed states of switches 231aP1 and 231aN1, and switches 231bP1 and 231bN1 are controlled by a signal H1. The open / closed states of switches 231aP2 and 231aN2, and switches 231bP2 and 231bN2 are controlled by a signal H2.

[0083] In FIG. 11, the capacitive DACs 110pn1 and 110pn2 include the same configuration as the capacitive DAC 110 shown in FIG. 1 for the input voltages VinP and VinN, respectively.

[0084] The capacitive DAC 110pn1 is configured to respond to the input voltage VinP by including a capacitor group 111aP made up of a plurality of capacitors, each of which has a capacitance that increases (decreases) in a binary manner and one end of which is connected to a common node 113P1, and a switch group 112aP made up of switches, two of which are connected to the other end of each capacitor.Similarly, the capacitive DAC 110pn1 is configured to respond to the input voltage VinN by including a capacitor group 111aN made up of a plurality of capacitors, each of which has a capacitance that increases (decreases) in a binary manner and one end of which is connected to a common node 113N1, and a switch group 112aN made up of switches, two of which are connected to the other end of each capacitor.

[0085] The capacitive DAC 110pn2 has a configuration similar to that of the capacitive DAC 110pn1 described above. That is, the capacitive DAC 110pn2 includes, as a configuration for the input voltage VinP, a capacitor group 111bP made up of a plurality of capacitors, each of which has a capacitance that increases (decreases) in a binary manner and one end of which is connected to a common node 113P2, and a switch group 112bP made up of switches, two of which are connected to the other end of each capacitor. Similarly, the capacitive DAC 110pn2 includes, as a configuration for the input voltage VinN, a capacitor group 111bN made up of a plurality of capacitors, each of which has a capacitance that increases (decreases) in a binary manner and one end of which is connected to a common node 113N2, and a switch group 112bN made up of switches, two of which are connected to the other end of each capacitor.

[0086] As described above, the configurations corresponding to the input voltages VinP and VinN of the capacitive DAC 110pn1 and the configurations corresponding to the input voltages VinP and VinN of the capacitive DAC 110pn2 are equivalent, so the configuration corresponding to the input voltage VinP of the capacitive DAC 110pn1 will be described in detail.

[0087] In a configuration corresponding to the input voltage VinP of the capacitive DAC 110pn1, the capacitors included in the capacitor group 111aP have capacitances of C, 2C (=2×C), 4C (=4×C), and 8C (=8×C), which increase in binary (by a factor of two) from the side closest to the comparator 130a. Each capacitor included in the capacitor group 111aP has one end connected to a common node 113P1 and the other end connected to either a lower limit voltage VRB or an upper limit voltage VRT by two switches included in the switch group 112aP. The open / closed state of each switch included in the switch group 112aP is controlled by a DAC control signal from the logic circuit 140a.

[0088] An input voltage VinP is input to one end of each of switches 230aP and 230bP. The other end of switch 230aP is connected to a common node 113P1, and the other end of common node 113P1 is connected to one end of each of switches 231aP1 and 231aP2. The other end of switch 230bP is connected to one end of common node 113P2. The other end of common node 113P2 is connected to one end of each of switches 231bP1 and 231bP2. The other ends of switches 231aP1 and 231bP2 are connected to a first input end of comparator 130a.

[0089] Similarly, the input voltage VinN is input to one end of each of the switches 230aN and 230bN. The other end of the switch 230aN is connected to a common node 113N1, and the other end of the common node 113N1 is connected to one end of each of the switches 231aN1 and 231aN2. The other end of the switch 230bN is connected to one end of the common node 113N2. The other end of the common node 113N2 is connected to one end of each of the switches 231bN1 and 231bN2. The other end of the switch 231aN1 and the other end of the switch 231bN2 are connected to a second input end of the comparator 130a.

[0090] The comparator 130a performs a comparison operation in accordance with a clock signal C_CLK supplied from the logic circuit 140a. That is, the comparator 130a calculates the difference between the signal input to the first input terminal and the signal input to the second input terminal, compares this difference with a reference voltage Vref input to a third input terminal (not shown) of the comparator 130a, and outputs a value of "1" or "0" to the logic circuit 140a.

[0091] The logic circuit 140a generates the AD conversion result of the most significant bits based on the output of the comparator 130a. The processing by the logic circuit 140a is the same as the processing described with reference to Figures 1 and 2, so a description thereof will be omitted here.

[0092] The other ends of the switches 231aP and 231bP are input to the VTC 201a, and are connected to a constant current source 211P and one input end of a comparator 212P. The comparator 212P compares the voltage input to one input end with a reference voltage Vref input to the other input end (not shown), and outputs the comparison result VTCp to the TDC 202.

[0093] The other ends of the switches 231aN2 and 231bN1 are input to the VTC 201a, and are connected to a constant current source 211N and one input end of a comparator 212N. The comparator 212N compares the voltage input to one input end with a reference voltage Vref input to the other input end (not shown), and outputs the comparison result VTCn to the TDC 202.

[0094] The TDC 202 performs AD conversion processing based on the comparison results VTCp and VTCn based on the input voltages VinP and VinN, using the delay of each unit delay circuit UD, as described with reference to Figures 3 and 4, to generate an AD conversion result for the lower bits.

[0095] The encoding circuit 300 outputs an output signal Dout obtained by AD converting the input voltage Vin based on the AD conversion result of the higher order bits generated by the logic circuit 140a and the AD conversion result of the lower order bits generated by the TDC 202.

[0096] FIG. 12 is a timing chart illustrating an example of the operation of the AD conversion device 1b according to the first embodiment.

[0097] The example of Figure 12 shows, from the top, signals S1, S2, H1 and H2, voltages CDAC1p, CDAC1n, CDAC2p and CDAC2n of common nodes 113P1, 113N1, 113P2 and 113N2, respectively, and comparison results VTCp and VTCn of comparators 212P and 212N in VTC 201a.

[0098] In FIG. 12, time t 20 ~t 21 The signal S1 is set to a high state during the period t 20 At time t 21 ~t 24 During this period, the signal H1 is set to a high state.

[0099] The time t when the signal S1 becomes high 20 ~t 21 In the capacitive DAC 110pn1, input voltages VinP and VinN are input to the capacitive DAC 110pn1. In the capacitive DAC 110pn1, the input voltage VinP is supplied to a common node 113P1 via a switch 230aP and applied to each capacitor of the capacitor group 111aP. Also, the input voltage VinN is supplied to a common node 113N1 via a switch 230aN and applied to each capacitor of the capacitor group 111aN.

[0100] The time t when signal H1 is in a high state 21 ~t 24 During this period, the logic circuit 140a controls the switches included in the switch groups 112aP and 112aN to perform an operation by the SAR-ADC (referred to as an SAR operation). The voltages CDAC1p and CDAC1n generated by this SAR operation are input to the first and second input terminals of the comparator 130a via the common nodes 113P1 and 113N1 and the switches 231aP1 and 231aN1, respectively.

[0101] The capacitive DAC 110pn2 is 20 ~t 24Since the signal S2 is in a low state during the period t 21 ~t 24 Since the switches 231bP and 231bN are kept in a high state during this period, the residual voltages due to the immediately preceding SAR operation, which are stored in the capacitors of the capacitor groups 111bP and 111bN in the capacitive DAC 110pn2, are supplied to the VTC 201a via the switches 231bP and 231bN, respectively, as voltages CDAC2p and CDAC2n at the common nodes 113P2 and 113N2.

[0102] The VTC 201a subtracts these voltages CDAC2p and CDAC2n with a constant voltage slope by constant current sources 211P and 211N, and compares them with a reference voltage Vref by comparators 212P and 212N. 23 At time t 22 At this time t, the voltage CDAC2n and the reference voltage Vref match, and the comparison result VTCn is set to a high state. 22 ~t 23 The comparison results VTCp and VTCn during this period are used as TDC inputs, and AD conversion processing of the lower bits is performed.

[0103] Time t 24 At time t, the signal H1 transitions from a high state to a low state, and the SAR operation by the capacitive DAC 110pn1 ends. 24 ~t 25 The signal S2 is in a high state during the period t 24 At time t 25 ~t 28 During this period, the signal H2 is set to a high state.

[0104] Time t 24 ~t 28 In the period, by controlling the signals S1, S2, H1 and H2 in this way, for example, 20 ~t 24For the operation in the period, the SAR operation and the VTC operation are switched between the capacitive DACpn1 and the capacitive DACpn2.

[0105] The time t when the signal S2 becomes high 24 ~t 25 In the capacitive DAC 110pn2, input voltages VinP and VinN are input to the capacitive DAC 110pn2. In the capacitive DAC 110pn2, the input voltage VinP is supplied to a common node 113P2 via a switch 230bP and applied to each capacitor of the capacitor group 111bP. Also, the input voltage VinN is supplied to a common node 113N2 via a switch 230bN and applied to each capacitor of the capacitor group 111bN.

[0106] The time t when signal H2 is in a high state 25 ~t 28 During this period, the logic circuit 140a controls the switches included in the switch groups 112bP and 112bN to perform an operation by the SAR-ADC (referred to as an SAR operation). The voltages CDAC2p and CDAC2n generated by this SAR operation are input to the first and second input terminals of the comparator 130a via the common nodes 113P2 and 113N2 and the switches 231bP2 and 231bN2, respectively.

[0107] The capacitive DAC 110pn2 is 24 ~t 28 Since the signal S1 is in a low state during the period t 25 ~t 28 Since the signal is in a high state during the period t 21 ~t 24 ) are supplied to the VTC 201a as voltages CDAC1p and CDAC1n at common nodes 113P1 and 113N1 via switches 231aP1 and 231aN1, respectively.

[0108] The VTC 201a subtracts these voltages CDAC1p and CDAC1n with a constant voltage slope by constant current sources 211P and 211N, and compares the resulting voltages with a reference voltage Vref by comparators 212P and 212N. 27 At time t 26 At this time t 26 ~t 27 The comparison results VTCp and VTCn during this period are used as TDC inputs, and AD conversion processing of the lower bits is performed.

[0109] In the configuration of serially processing the SAR-ADC and the time measurement ADC according to the existing technology, in the example of FIG. 12, for example, the time t 20 ~t 28 The period corresponding to this is the sampling period.

[0110] In contrast, in the AD conversion device 1b according to the first embodiment, the input voltages VinP and VinN are sampled in the capacitive DACs 110pn1 and 110pn2 at a time t 20 ~t 24 Therefore, the sampling period is the time t 20 ~t 24 By applying the first embodiment, the sampling period can be shortened compared to the case of serial processing using existing technology.

[0111] In addition, in FIG. 11, the AD conversion device 1b is shown as including two capacitive DACs 110pn1 and 110pn2, but this is not limited to this example, and the AD conversion device 1b may include three or more capacitive DACs.

[0112] (5. Second Embodiment of the Present Disclosure) Next, a second embodiment of the present disclosure will be described. The second embodiment of the present disclosure corresponds to the configuration described using Fig. 9 and is an example in which the SAR-ADC is performed using one capacitive DAC, and the AD conversion process of the higher bits by the SAR-ADC and the AD conversion process of the lower bits by the time measurement ADC are performed complementarily with different sampling periods.

[0113] 13 is a circuit diagram illustrating an example of the configuration of an AD conversion apparatus according to the second embodiment. As described above, the circuit diagram illustrated in Fig. 13 is illustrated as a differential circuit that supports processing using input voltages VinP and VinN that are inverted from each other and are generated based on the input voltage Vin.

[0114] 13, the AD conversion device 1c includes a capacitive DAC 110pn (also shown as CDAC in the figure), a comparator 130a, a logic circuit 140b, a VTC 201a, a TDC 202, and an encoding circuit 300. Of these, the capacitive DAC 110pn, the comparator 130a, and the logic circuit 140b configure an SAR-ADC. Furthermore, the VTC 201a and the TDC 202 configure a time measurement ADC.

[0115] 13, the AD conversion device 1c further includes switches 210P and 210N, switches 230aP1 and 230aP2, switches 230bP1 and 230bP2, switches 230aN1 and 230aN2, switches 230bN1 and 230bN2, capacitors CS1p and CS2p, and capacitors CS1n and CS2n.

[0116] The open / closed states of the switches 210P and 210N are each controlled by a signal S. The open / closed states of the switches 230aP1 and 230aP2, and the switches 230aN1 and 230aN2 are each controlled by a signal S1. The open / closed states of the switches 230bP1 and 230bP2, and the switches 230bN1 and 230bN2 are each controlled by a signal S2.

[0117] 13, the capacitive DAC 110pn has the same configuration as the capacitive DAC 110pn1 shown in Fig. 11. That is, the capacitive DAC 110pn includes, as a configuration for the input voltage VinP, a capacitor group 111P made up of a plurality of capacitors, each of which has a capacitance that increases (decreases) in a binary manner and one end of which is connected to a common node 113P, and a switch group 112P made up of switches, two of which are connected to the other end of each capacitor. Similarly, the capacitive DAC 110pn includes, as a configuration for the input voltage VinN, a capacitor group 111N made up of a plurality of capacitors, each of which has a capacitance that increases (decreases) in a binary manner and one end of which is connected to a common node 113N, and a switch group 112N made up of switches, two of which are connected to the other end of each capacitor.

[0118] An input voltage VinP is input to one end of a switch 210P. The other end of the switch 210P is connected to a common node 113P, and the other end of the common node 113P is connected to a first input end of the comparator 130a. Similarly, an input voltage VinN is input to one end of a switch 210N. The other end of the switch 210N is connected to a common node 113N, and the other end of the common node 113N is connected to a second input end of the comparator 130a.

[0119] The comparator 130a performs a comparison operation in accordance with the clock signal C_CLK supplied from the logic circuit 140b, in the same manner as the operation described with reference to Fig. 11. That is, the comparator 130a calculates the difference between the signal input to the first input terminal and the signal input to the second input terminal, compares this difference with a reference voltage Vref input to a third input terminal (not shown) of the comparator 130a, and outputs a value "1" or "0" to the logic circuit 140b.

[0120] The logic circuit 140b generates the AD conversion result of the most significant bits based on the output of the comparator 130a. The processing by the logic circuit 140b is the same as the processing described with reference to Figures 1 and 2, so a description thereof will be omitted here.

[0121] One end of the capacitor CS1p is connected to the ground potential, and the other end is connected to one end of each of the switches 230aP1 and 230bP1. The other end of the switch 230aP1 is connected to the common node 113P. The other end of the switch 230bP1 is input to the VTC 201a and is connected to the constant current source 211P and one input end of the comparator 212P.

[0122] One end of the capacitor CS2p is connected to the ground potential, and the other end is connected to one end of each of the switches 230aP and 230bP. The other end of the switch 230bP is connected to the common node 113P. The other end of the switch 230aP is input to the VTC 201a and is connected to the constant current source 211P and one input end of the comparator 212P.

[0123] The comparator 212P compares the voltage (voltage VC1p or VC2p) input to one input terminal with a reference voltage Vref input to the other input terminal (not shown), and outputs the comparison result VTCp to the TDC 202.

[0124] One end of the capacitor CS1n is connected to ground potential, and the other end is connected to one end of each of the switches 230aN1 and 230bN1. The other end of the switch 230aN1 is connected to the common node 113N. The other end of the switch 230bN1 is input to the VTC 201a and is connected to a constant current source 211N and one input end of a comparator 212N.

[0125] One end of the capacitor CS2n is connected to the ground potential, and the other end is connected to one end of each of the switches 230aN2 and 230bN2. The other end of the switch 230bN2 is connected to the common node 113N. The other end of the switch 230aN2 is input to the VTC 201a and is connected to the constant current source 211N and one input end of the comparator 212N.

[0126] The comparator 212N compares the voltage (voltage VC1n or VC2n) input to one input terminal with a reference voltage Vref input to the other input terminal (not shown), and outputs the comparison result VTCn to the TDC 202.

[0127] The TDC 202 performs AD conversion processing on the lower bits based on the comparison result VTCp from the comparator 212P and the comparison result VTCn from the comparator 212N.

[0128] FIG. 14 is a timing chart illustrating an example of the operation of the AD conversion device 1c according to the second embodiment.

[0129] In the example of Figure 14, from the top, signals S, S1, and S2, voltages VC1p and VC1n of capacitors CS1p and CS1n, voltages VC2p and VC2n of capacitors CS2p and CS2n, and comparison results VTCp and VTCn of comparators 212P and 212N in VTC 201a are shown.

[0130] In FIG. 14, time t 30 ~t 31 , t 34 ~t 35 The signal S is set to a high state during the period t 30 ~t 34 During this period, the signal S1 is set to a high state and the signal S2 is set to a low state.

[0131] Since the processing for the input voltage VinP and the operation for the input voltage VinN are the same, the description of the operation for the input voltage VinN will be omitted as appropriate.

[0132] With respect to the input voltage VinP, time t 30 ~t 31 The switches 230aP1 and 230aP2 are closed during the period t 34 It is maintained until time t 30 ~t 31 During the period, the input voltage VinP is applied to the capacitor CS1p and the input voltage VinP is sampled.

[0133] Also, time t 30 ~t 34 During the period t30 ~t 34 During this period, the logic circuit 140a controls each switch included in the switch group 112P to perform the SAR operation. The voltage VC1p generated by this SAR operation is input to the first input terminal of the comparator 130a via the common node 113P.

[0134] A voltage VC1n generated by a similar SAR operation using a capacitor CS1n based on the input voltage VinN is input to a second input terminal of the comparator 130a via a common node 113N.

[0135] Also, time t 30 ~t 34 During this period, the residual voltage stored in capacitor CS2p due to the previous SAR operation is supplied to VTC 201a via switch 230aP2. Since switch 230bP2 was closed during the previous SAR operation, this residual voltage is the same as voltage VC2p at the other end of capacitor CS2p. VTC 201a subtracts this residual voltage (voltage VC2p) using a constant voltage slope with constant current source 211P, and compares it with reference voltage Vref using comparator 212P.

[0136] Similarly, in the comparator 212N, the residual voltage (voltage VC2n) due to the immediately preceding SAR operation is subtracted by the constant current source 211N with a constant voltage slope, and the result is compared with the reference voltage Vref.

[0137] As a result of the comparison, the comparator 212P determines that the time t 33 At time t 32 Assume that the voltage VC2n and the reference voltage Vref match at time t and the comparison result VTCn is set to a high state. 32 ~t 33 The comparison results VTCp and VTCn during this period are used as TDC inputs, and AD conversion processing of the lower bits is performed.

[0138] Time t 34At time t, the signal S1 transitions from a high state to a low state, and the SAR operation by the capacitive DAC 110pn ends. 34 ~t 35 The signal S is in a high state during the period t 34 ~t 38 During this period, the signal S2 is set to a high state.

[0139] With respect to the input voltage VinP, time t 34 ~t 35 The switches 230bP1 and 230bP2 are closed during the period t 38 It is maintained until time t 34 ~t 35 During the period, the input voltage VinP is applied to the capacitor CS2p and the input voltage VinP is sampled.

[0140] Also, time t 34 ~t 38 During the period t 34 ~t 38 During this period, the logic circuit 140a controls each switch included in the switch group 112P to perform the SAR operation. The voltage VC2p generated by this SAR operation is input to the first input terminal of the comparator 130a via the common node 113P.

[0141] A voltage VC2n generated by a similar SAR operation using a capacitor CS2n based on the input voltage VinN is input to a second input terminal of the comparator 130a via a common node 113N.

[0142] Also, time t 34 ~t 38 During the period, the voltage of the previous SAR operation (time t 31 ~t 34The residual voltage resulting from the SAR operation during the period (before the voltage Vc1p is applied) is supplied to the VTC 201a via the switch 230bP1. In the immediately preceding SAR operation, the switch 230aP1 is closed, so this residual voltage is the same as the voltage VC1p at the other end of the capacitor CS1p. The VTC 201a subtracts this residual voltage (voltage VC1p) using a constant voltage slope with the constant current source 211P, and compares it with the reference voltage Vref with the comparator 212P.

[0143] Similarly, in the comparator 212N, the residual voltage (voltage VC1n) due to the immediately preceding SAR operation is subtracted by the constant current source 211N with a constant voltage slope, and the result is compared with the reference voltage Vref.

[0144] As a result of the comparison, the comparator 212P determines that the time t 37 At time t 36 Assume that the voltage VC1n and the reference voltage Vref match at time t and the comparison result VTCn is set to a high state. 36 ~t 37 The comparison results VTCp and VTCn during this period are used as TDC inputs, and AD conversion processing of the lower bits is performed.

[0145] In the AD conversion device 1c according to the second embodiment, as in the first embodiment, the input voltages VinP and VinN are sampled in the capacitive DAC 110pn at a time t 30 ~t 34 Therefore, the sampling period is the time t 30 ~t 34 By applying the second embodiment, the sampling period can be shortened compared to the case of serial processing using existing technology, as in the first embodiment.

[0146] In the second embodiment, a single capacitive DAC is used to achieve complementary operation between the SAR-ADC and the time measurement ADC, making it possible to reduce the mounting area compared to the configuration of the first embodiment.

[0147] (6. Third Embodiment of the Present Disclosure) Next, a third embodiment of the present disclosure will be described. The third embodiment is an example in which, in contrast to the configuration of the second embodiment described above, capacitors included in the capacitor group for SAR operation are also used as capacitors for sampling the input voltages VinP and VinN.

[0148] 15 is a circuit diagram illustrating an example of the configuration of an AD conversion apparatus according to the third embodiment. As described above, the circuit diagram illustrated in Fig. 15 is illustrated as a differential circuit that supports processing using input voltages VinP and VinN that are inverted from each other and are generated based on the input voltage Vin.

[0149] 15, the AD conversion device 1d includes a capacitive DAC 160, a comparator 130a, a logic circuit 140c, a VTC 201a, a TDC 202, and an encoding circuit 300. Of these, the capacitive DAC 160, the comparator 130a, and the logic circuit 140c form an SAR-ADC. The VTC 201a and the TDC 202 form a time measurement ADC. The AD conversion device 1d also includes switches 210P and 210N whose open / closed states are controlled by a signal S.

[0150] The capacitive DAC 160 includes a capacitor group consisting of a plurality of capacitors whose capacitances increase (decrease) in binary on the side corresponding to the input voltage VinP (upper side of the figure). In the example of Figure 15, the capacitor group is configured to include three capacitor groups 111P1, 111P2, and 111P3.

[0151] In this example, the capacitor group 111P1 includes three capacitors, each having a capacitance of C, 2C (=2×C), and 4C (=4×C) that increase in binary (by a factor of two) from the side closest to the comparator 130a. Each capacitor included in the capacitor group 111P1 has one end connected to a common node 113P′ and the other end connected to either a lower limit voltage VRB or an upper limit voltage VRT by two switches included in the switch group 112P1.

[0152] The capacitor groups 111P2 and 111P3 each include one capacitor having a capacitance of 8 C. The capacitors with a capacitance of 8 C included in the capacitor groups 111P2 and 111P3 are also used as capacitors for sampling the input voltage VinP, and therefore will be referred to as capacitors CS1p and CS2p, respectively, as appropriate.

[0153] One end of capacitor CS1p is connected to one end of switches 232aP1 and 232bP2, and the other end is connected to either the lower limit voltage VRB or the upper limit voltage VRT by two switches included in switch group 112P3. Similarly, one end of capacitor CS2p is connected to one end of switches 232aP2 and 232bP1, and the other end is connected to either the lower limit voltage VRB or the upper limit voltage VRT by two switches included in switch group 112P2.

[0154] The other ends of the switches 232aP1 and 232aP2 are connected to the common node 113P'. The other ends of the switches 232bP1 and 232bP2 are connected to the input of the VTC 201a, and to a constant current source 211P and one input of a comparator 212P.

[0155] The comparator 212P compares the voltage (voltage VC1p or VC2p) input to one input terminal with a reference voltage Vref input to the other input terminal (not shown), and outputs the comparison result VTCp to the TDC 202.

[0156] The open / closed states of the switches included in the switch groups 112P1, 112P2, and 112P3, and the switch groups 112N1, 112N2, and 112N3 described below, are controlled by DAC control signals from the logic circuit 140c.

[0157] On the other hand, the open / closed states of switch 232aP1 and a switch 232aN1 (described later) are controlled by signal S1. The open / closed states of switch 232aP2 and a switch 232aN2 (described later) are controlled by signal S2. The open / closed states of switches 232bP1 and 232bN1 are controlled by signal H1. Furthermore, the open / closed states of switch 232bP2 and a switch 232bN2 (described later) are controlled by signal H2.

[0158] The signals S, S1 and S2, and H1 and H2 are generated by the logic circuit 140c based on, for example, an externally supplied clock signal. However, without being limited to this, all or any of the signals S, S1 and S2, and H1 and H2 may be generated by an external control circuit.

[0159] The configuration of the side of the capacitive DAC 160 corresponding to the input voltage VinN (the lower side of the figure) is the same as the configuration for the input voltage VinP described above. That is, the capacitive DAC 160 is configured to correspond to the input voltage VinN by including capacitor groups 111N1, 111N2, and 111N3, each of which has a capacitance that increases (decreases) in binary.

[0160] In this example, the capacitor group 111N1 includes three capacitors, each having a capacitance of C, 2C (=2×C), and 4C (=4×C) that increase in binary (by a factor of two) from the side closest to the comparator 130a. Each capacitor included in the capacitor group 111N1 has one end connected to a common node 113N′ and the other end connected to either a lower limit voltage VRB or an upper limit voltage VRT by two switches included in the switch group 112N1.

[0161] The capacitor groups 111N2 and 111N3 each include one capacitor having a capacitance of 8 C. The capacitors with a capacitance of 8 C included in the capacitor groups 111N2 and 111N3 are also used as capacitors for sampling the input voltage VinN, and therefore will be referred to as capacitors CS1n and CS2n, respectively, as appropriate.

[0162] One end of capacitor CS1n is connected to one end of switches 232aN1 and 232bN2, and the other end is connected to either the lower limit voltage VRB or the upper limit voltage VRT by two switches included in switch group 112N3. Similarly, one end of capacitor CS2n is connected to one end of switches 232aN2 and 232bN1, and the other end is connected to either the lower limit voltage VRB or the upper limit voltage VRT by two switches included in switch group 112N2.

[0163] The open / closed states of the switches included in the switch groups 112N1, 112N2, and 112N3 are controlled by DAC control signals from the logic circuit 140c.

[0164] The other ends of the switches 232aN1 and 232aN2 are connected to the common node 113N'. The other ends of the switches 232bN1 and 232bN2 are connected to the input of the VTC 201a, and to a constant current source 211N and one input of a comparator 212N.

[0165] The comparator 212N compares the voltage (voltage VC1n or VC2n) input to one input terminal with a reference voltage Vref input to the other input terminal (not shown), and outputs the comparison result VTCn to the TDC 202.

[0166] The TDC 202 performs AD conversion processing on the lower bits based on the comparison result VTCp from the comparator 212P and the comparison result VTCn from the comparator 212N.

[0167] FIG. 16 is a timing chart illustrating an example of the operation of the AD conversion device 1d according to the third embodiment.

[0168] In the example of Figure 16, from the top, signals S, S1, S2, H1 and H2, voltages VC1p and VC1n of capacitors CS1p and CS1n, voltages VC2p and VC2n of capacitors CS2p and CS2n, and comparison results VTCp and VTCn of comparators 212P and 212N in VTC 201a are shown.

[0169] In FIG. 16, time t 40 ~t41 , t 44 ~t 45 The signal S is set to a high state during the period t 40 ~t 44 The signal S1 is in a high state and the signal S2 is in a low state during the period t 40 ~t 41 is held low for a period of time t 41 ~t 44 The signal is set to a high state for a period of time t 40 ~t 45 During this period, the signal H2 is set to a low state.

[0170] Since the processing for the input voltage VinP and the operation for the input voltage VinN are the same, the description of the operation for the input voltage VinN will be omitted as appropriate.

[0171] With respect to the input voltage VinP, time t 40 ~t 41 The switch 210P and the switch 230aP1 are both closed during the period t 44 It is maintained until time t 40 ~t 41 During the period, the input voltage VinP is applied to the capacitor CS1p and the input voltage VinP is sampled.

[0172] Also, time t 40 ~t 44 During the period t, the input voltage VinP is applied to each capacitor included in the capacitor group 111P1 of the capacitive DAC 160. 40 ~t 44 During this period, the logic circuit 140a controls the switches included in the switch groups 112P, 112P, and 112P to perform the SAR operation. The voltage VC1p generated by this SAR operation is input to the first input terminal of the comparator 130a via the common node 113P'.

[0173] A voltage VC1n generated by a similar SAR operation using a capacitor CS1n based on the input voltage VinN is input to a second input terminal of the comparator 130a via a common node 113N'.

[0174] Also, time t 41 ~t 44 During this period, the residual voltage stored in capacitor CS2p due to the previous SAR operation is supplied to VTC 201a via switch 230bP1. Because switch 230bP1 was closed during the previous SAR operation, this residual voltage is the same as voltage VC2p at the other end of capacitor CS2p. VTC 201a subtracts this residual voltage (voltage VC2p) using a constant voltage slope with constant current source 211P, and compares it with reference voltage Vref using comparator 212P.

[0175] Similarly, in the comparator 212N, the residual voltage (voltage VC2n) due to the immediately preceding SAR operation is subtracted by the constant current source 211N with a constant voltage slope, and the result is compared with the reference voltage Vref.

[0176] As a result of the comparison, the comparator 212P determines that the time t 43 At time t 42 Assume that the voltage VC2n and the reference voltage Vref match at time t and the comparison result VTCn is set to a high state. 42 ~t 43 The comparison results VTCp and VTCn during this period are used as TDC inputs, and AD conversion processing of the lower bits is performed.

[0177] Time t 44 At time t, the signal S1 transitions from a high state to a low state, and the SAR operation by the capacitive DAC 160 ends. 44 ~t 45 The signal S is in a high state during the period t 44 ~t 48 The signal S2 is in a high state for a period of time t 44 ~t 49 and the signal H2 is in a low state for a period of time t 45 ~t48 The signal is held low for a period of time.

[0178] With respect to the input voltage VinP, time t 44 ~t 45 The switch 210P and the switch 230aP2 are both in a closed state during the period t 48 It is maintained until time t 44 ~t 45 During the period, the input voltage VinP is applied to the capacitor CS2p and the input voltage VinP is sampled.

[0179] Also, time t 44 ~t 48 During the period t, the input voltage VinP is applied to each capacitor included in the capacitor group 111P1 of the capacitive DAC 160. 44 ~t 48 During this period, the logic circuit 140a controls the switches included in the switch groups 112P, 112P, and 112P to perform the SAR operation. The voltage VC2p generated by this SAR operation is input to the first input terminal of the comparator 130a via the common node 113P′.

[0180] A voltage VC2n generated by a similar SAR operation using a capacitor CS2n based on the input voltage VinN is input to a second input terminal of the comparator 130a.

[0181] Also, time t 45 ~t 48 During this period, the residual voltage stored in capacitor CS1p due to the previous SAR operation is supplied to VTC 201a via switch 230bP2 and common node 113P'. Because switch 230bP2 was closed during the previous SAR operation, this residual voltage is the same as voltage VC1p at the other end of capacitor CS1p. VTC 201a subtracts this residual voltage (voltage VC1p) with a constant voltage slope using constant current source 211P, and compares it with reference voltage Vref using comparator 212P.

[0182] Similarly, in the comparator 212N, the residual voltage (voltage VC1n) due to the immediately preceding SAR operation is subtracted by the constant current source 211N with a constant voltage slope, and the result is compared with the reference voltage Vref.

[0183] As a result of the comparison, the comparator 212P determines that the time t 47 At time t 46 Assume that the voltage VC1n and the reference voltage Vref match at time t and the comparison result VTCn is set to a high state. 46 ~t 47 The comparison results VTCp and VTCn during this period are used as TDC inputs, and AD conversion processing of the lower bits is performed.

[0184] In the AD conversion device 1d according to the third embodiment, as in the first embodiment, the input voltages VinP and VinN are sampled in the capacitive DAC 160 at a time t 40 ~t 44 Therefore, the sampling period is the time t 40 ~t 44 By applying the third embodiment, the sampling period can be shortened compared to the case of serial processing using existing technology, as in the first embodiment.

[0185] In the third embodiment, the capacitors included in the capacitor group for SAR operation are also used as capacitors for sampling the input voltage, which makes it possible to reduce the number of capacitors compared to the configuration of the second embodiment described above, thereby further reducing the mounting area.

[0186] (7. Fourth Embodiment of the Present Disclosure) Next, a fourth embodiment of the present disclosure will be described. The fourth embodiment is an example in which the AD conversion device 1a according to the above-described embodiment and any of the AD conversion devices 1b to 1d according to the first to fourth embodiments are applied to an electronic device. Note that, hereinafter, unless otherwise specified, the AD conversion devices 1a to 1d will be collectively described as the AD conversion device 1.

[0187] 17 is a block diagram showing an example of a configuration of an electronic device to which the AD conversion device 1 according to each embodiment of the present disclosure can be applied. In FIG. 17 , an electronic device 2000 includes an image sensor 2100 and an application processor 2200.

[0188] The image sensor 2100 includes a sensor unit 2110 , a signal processing unit 2120 , and a modulation driver 2130 .

[0189] The sensor unit 2110 includes a pixel array in which pixels that convert received light into electrical signals are arranged in a matrix, and a drive circuit that drives the pixel array. The sensor unit 2110 generates an image signal based on the electrical signal read from each pixel, and outputs the generated image signal to the signal processing unit 2120.

[0190] The signal processing unit 2120 performs predetermined signal processing such as gain adjustment and noise reduction on the image signal output from the sensor unit 2110. The signal processing unit 2120 also has an AD converter and performs AD conversion on the analog image signal that has undergone signal processing to generate image data. The signal processing unit 2120 may further perform compression encoding, encryption, and other processing on the image data. The signal processing unit 2120 outputs the image data to the modulation driver 2130.

[0191] The modulation driver 2130 modulates the image data output from the signal processing unit 2120 using a modulation method suitable for transmission to the application processor 2200. The modulation driver 2130 may use, for example, PAM4 (Pulse Amplitude Modulation 4) or PAM8 as the modulation method for the image data. The image data is modulated into an analog modulation signal. The modulation driver 2130 transmits the modulation signal obtained by modulating the image data to the application processor 2200.

[0192] The application processor 2200 includes an AD converter 2210 , a clock recovery processing unit 2220 , a PLL (Phase Locked Loop) 2230 , and a signal processing unit 2240 .

[0193] The PLL 2230 generates a clock signal. The clock recovery processing unit 2220 corrects the clock signal generated by the PLL 2230 based on the output of the AD converter 2210, and supplies the corrected clock signal to the AD converter 2210.

[0194] The AD converter 2210 receives the modulated signal transmitted from the image sensor 2100 as an input signal in accordance with the clock signal supplied from the clock recovery processing unit 2220, samples this input signal as an input voltage Vin, and performs AD conversion to restore image data. The AD converter 2210 may be an AD conversion device 1 according to each embodiment of the present disclosure. The AD converter 2210 outputs image data obtained by AD converting the modulated signal transmitted from the image sensor 2100 to the signal processing unit 2240.

[0195] The signal processing unit 2240 performs predetermined signal processing on the image data output from the AD converter 2210. The type of signal processing performed by the signal processing unit 2240 is not particularly limited, but may include compression encoding, decoding of encrypted image data, recognition processing based on image data, processing of image data, etc. The image data signal-processed by the signal processing unit 2240 or the processing results are output to the outside of the application processor 2200, for example.

[0196] The application processor 2200 may be an integrated circuit in which the AD converter 2210, the clock recovery processing unit 2220, the PLL 2230, and the signal processing unit 2240 are configured in a single package.

[0197] By applying the AD conversion device 1 according to each embodiment of the present disclosure to the AD converter 2210, it becomes possible to perform the AD conversion process in the application processor 2200 more stably, even if the data transfer rate from the image sensor 2100 to the application processor 2200 is increased.

[0198] Note that the AD conversion device 1 according to each embodiment of the present disclosure is not limited to a configuration that performs AD conversion processing on signals transmitted from the image sensor 2100, but is also applicable to other electronic devices that perform AD conversion processing.

[0199] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0200] The present technology may also be configured as follows: (1) An AD conversion device comprising: a first AD conversion unit that performs a first AD (Analog to Digital) conversion on an input voltage sampled at a constant period; a second AD conversion unit that performs a second AD conversion based on a residual of the first AD conversion in a immediately preceding period by the first AD conversion unit; and an encoding unit that generates an output signal by AD-converting the input voltage sampled in the immediately preceding period based on a result of the AD conversion by the first AD conversion unit in the immediately preceding period and a result of the AD conversion by the second AD conversion unit. (2) The AD conversion device according to (1), wherein the first AD conversion unit is a successive approximation type AD converter using a plurality of capacitors whose capacitances differ by two times and performs AD conversion of higher-order bits of the input voltage, and the second AD conversion unit is a time measurement AD converter that performs AD conversion of lower-order bits of the input voltage. (3) The AD conversion device according to (2), further comprising: two capacitors provided in one channel to which the input voltage is input, wherein the two capacitors are exclusively switched for each cycle between being connected to a common node to which the input voltage is connected and to which the plurality of capacitors of the first AD conversion unit are commonly connected, or to the second AD conversion unit. (4) The AD conversion device according to (3), wherein the two capacitors are exclusively switched for each cycle between being connected to the common node as one of the plurality of capacitors of the first AD conversion unit, or to the second AD conversion unit. (5) The AD conversion device according to (2), wherein the first AD conversion unit has: a plurality of capacitor groups each including the plurality of capacitors; and a comparator that sequentially compares the voltages of the plurality of capacitors in each of the plurality of capacitor groups; and wherein a common node to which the input voltage is connected in each of the plurality of capacitor groups and to which the plurality of capacitors are commonly connected is exclusively switched for each of the cycles between being connected to the comparator or the second AD conversion unit.(6) The AD conversion device according to any one of (1) to (5), wherein the first AD conversion unit performs the first conversion differentially on the input voltages of two channels having inverted polarities, and the second AD conversion unit performs the second AD conversion based on each of the residuals corresponding to the input voltages of the two channels by the first AD conversion unit. (7) An integrated circuit including an AD conversion device comprising: a first AD conversion unit that performs first AD (Analog to Digital) conversion on an input voltage sampled at a constant period, a second AD conversion unit that performs second AD conversion based on a residual of the first AD conversion in a immediately preceding period by the first AD conversion unit, and an encoding unit that generates an output signal obtained by AD converting the input voltage sampled in the immediately preceding period based on a result of the AD conversion by the first AD conversion unit in the immediately preceding period and a result of the AD conversion by the second AD conversion unit. (8) An electronic device including: an AD conversion device including: a first AD conversion unit that performs a first AD (Analog to Digital) conversion on an input voltage sampled at a constant period; a second AD conversion unit that performs a second AD conversion based on a residual of the first AD conversion in a immediately preceding period by the first AD conversion unit; and an encoding unit that generates an output signal obtained by AD converting the input voltage sampled in the immediately preceding period based on a result of the AD conversion by the first AD conversion unit in the immediately preceding period and a result of the AD conversion by the second AD conversion unit; a signal processing unit that performs predetermined signal processing on the output signal generated by the encoding unit; and a signal generating unit that generates the input voltage. (9) The electronic device according to (8), wherein the signal generating unit is an image sensor. (10) The electronic device according to (8) or (9), wherein the AD conversion device and the signal processing unit are configured within a single integrated circuit.

[0201] 1, 1a, 1b, 1c, 1d, 1000 AD conversion device 100, 1010 SAR-ADC 110, 110pn1, 110pn2 Capacitive DAC 111, 111aP, 111aN, 111bP, 111bN, 111N, 111N1, 111N2, 111N3, 111P, 111P1, 111P2, 111P3 Capacitor group 112, 112aP, 112aN, 112bP, 112bN, 112N, 112N1, 112N2, 112N3, 112P, 112P1, 112P2, 112P3 Switch group 113, 113a, 113N, 113N', 113P, 113P' common node 120, 210, 210N, 210P, 213a, 213b, 213c, 213d, 230aN, 230aN1, 230aN2, 230bP, 230aP, 230aP1, 230aP2, 230bN, 230bN1, 230bN2, 230bP1, 230bP2, 231aN1, 231aN2, 231aP1, 231aP2, 231bN1, 231bN2, 231bP1, 231bP2, 232aN1, 232aN2, 232aP1, 232aP2, 232bN1, 232bN2, 232bP1, 232bP2 Switch 130, 130a, 212, 212P, 212N Comparators 140, 140a, 140b, 140c Logic circuits 200, 1020 Time measurement ADC 201, 201a VTC 202 TDC 211, 211P, 211N Constant current source 220, 300, 1030, 1040 Encoding circuit 2000 Electronic device 2100 Image sensor 2110 Sensor unit 2120 Signal processing unit 2130 Modulation driver 2200 Application processor 2210 AD converter 2220 Clock recovery processing unit 2230 PLL 2240 Signal processing unit

Claims

1. An AD conversion device comprising: a first AD conversion unit that performs a first AD (Analog to Digital) conversion on an input voltage sampled at a constant period; a second AD conversion unit that performs a second AD conversion based on a residual of the first AD conversion in a immediately preceding period by the first AD conversion unit; and an encoding unit that generates an output signal by AD converting the input voltage sampled in the immediately preceding period based on the AD conversion result by the first AD conversion unit in the immediately preceding period and the AD conversion result by the second AD conversion unit.

2. The AD conversion device according to claim 1, wherein the first AD conversion unit is a successive approximation type AD converter using a plurality of capacitors whose capacitances differ by two and performs AD conversion of the most significant bits of the input voltage, and the second AD conversion unit is a time measurement AD converter and performs AD conversion of the least significant bits of the input voltage.

3. The AD conversion device according to claim 2, further comprising: two capacitors provided in one channel to which the input voltage is input, wherein the two capacitors are exclusively switched for each period between being connected to a common node to which the input voltage is connected and to which the multiple capacitors of the first AD conversion unit are commonly connected, or to the second AD conversion unit.

4. The AD conversion device described in claim 3, wherein the two capacitors are exclusively switched for each period between being connected to the common node as one of the multiple capacitors of the first AD conversion unit, or being connected to the second AD conversion unit.

5. The AD conversion device described in claim 2, wherein the first AD conversion unit has: a plurality of capacitor groups each including a plurality of the capacitors; and a comparator which successively compares the voltages of the respective capacitors in each of the plurality of capacitor groups, and wherein a common node to which the input voltage is connected in each of the plurality of capacitor groups and to which the plurality of capacitors are commonly connected is exclusively switched for each period between being connected to the comparator or to the second AD conversion unit.

6. The AD conversion device described in claim 1, wherein the first AD conversion unit performs the first AD conversion differentially on the input voltages of two channels having inverted polarities with respect to each other, and the second AD conversion unit performs the second AD conversion based on each of the residuals corresponding to the input voltages of the two channels by the first AD conversion unit.

7. An integrated circuit including an AD conversion device comprising: a first AD conversion unit that performs a first AD (Analog to Digital) conversion on an input voltage sampled at a constant period; a second AD conversion unit that performs a second AD conversion based on a residual of the first AD conversion in a immediately preceding period by the first AD conversion unit; and an encoding unit that generates an output signal by AD converting the input voltage sampled in the immediately preceding period based on the AD conversion result by the first AD conversion unit in the immediately preceding period and the AD conversion result by the second AD conversion unit.

8. An AD conversion device comprising: a first AD conversion unit that performs a first AD (Analog to Digital) conversion on an input voltage sampled at a constant period; a second AD conversion unit that performs a second AD conversion based on a residual of the first AD conversion in a immediately preceding period by the first AD conversion unit; and an encoding unit that generates an output signal obtained by AD converting the input voltage sampled in the immediately preceding period based on the AD conversion result by the first AD conversion unit in the immediately preceding period and the AD conversion result by the second AD conversion unit; a signal processing device that performs a predetermined signal processing on the output signal generated by the encoding unit; and a signal generating device that generates the input voltage.

9. The electronic device according to claim 8, wherein the signal generating device is an image sensor.

10. The electronic device according to claim 8, wherein the AD conversion device and the signal processing device are configured within a single integrated circuit.

Images