Method and apparatus for dynamically allocating SRAM array to cache mode and SPM mode

Abstract

The present disclosure relates to a method and an apparatus for dynamically allocating an SRAM array to a cache mode and a scratched pad memory (SPM) mode. According to one aspect of the present disclosure, the method for dynamically allocating an SRAM array is provided, the method comprising: an SPM request reception step of receiving an SPM request message; an SPM area acquisition step, according to the SPM request message, of acquiring, as a first cache line, a cache line that can be used as an SPM from among a plurality of cache lines of n cache ways constituting an n-way set-associative cache, thereby setting the first cache line as a first SPM line; an access information recording step of recording access information related to an access occurrence message for the first SPM line if the access occurrence message is received; and a cache line restoration step of restoring the first SPM line to the cache line if it is confirmed on the basis of the access information that the use of the first SPM line is complete.

Description

Method and device for dynamically allocating SRAM arrays in CACHE mode and SPM mode

[0001] The present disclosure relates to a method and device for dynamically allocating a Static Random Access Memory (SRAM) array to a Cache mode and an SPM mode.

[0002] The content described below merely provides background information related to the present embodiment and does not constitute prior art.

[0003] Traditionally, while a kernel is running, the on-chip SRAM (Static Random Access Memory) memory is statically divided into a cache area and an SPM (scratched pad memory) area. In other words, before the kernel starts running, the SRAM array area that can be used as shared memory can be divided into a cache area and an SPM area, and the smallest unit of configuration for dividing these areas can be seen as a kernel unit.

[0004] If a portion of the cache area within the RAM array can be dynamically changed into the SPM area as needed within the kernel's operation, the cache area can be used efficiently.

[0005] The main purpose of the present disclosure is to provide a method and device for dynamically allocating an SRAM array to a cache mode and an SPM mode.

[0006] The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

[0007] According to one aspect of the present disclosure, a method for dynamically allocating an SRAM array is provided, including: an SPM request receiving process for receiving an SPM request message; an SPM area obtaining process for obtaining a cache line usable as an SPM (scratched pad memory) from among a plurality of cache lines of n cache ways constituting an n-way set-associative cache as a first cache line according to the SPM request message and setting the first cache line as a first SPM line; an access information recording process for recording access information related to an access occurrence message when an access occurrence message for the first SPM line is received; and a cache line restoration process for restoring the first SPM line to a cache line when it is confirmed based on the access information that use of the first SPM line is completed.

[0008] A computer program stored in a computer-readable recording medium is provided to execute each process included in the above SRAM array dynamic allocation method.

[0009] According to another aspect of the present disclosure, there is provided an SRAM array dynamic allocation device, comprising: an SPM request receiving unit for receiving an SPM request message; an SPM area obtaining unit for obtaining, as a first cache line, a cache line usable as an SPM (scratched pad memory) from among a plurality of cache lines of n cache ways constituting an n-way set-associative cache according to the SPM request message, and setting the first cache line as a first SPM line; an access information recording unit for recording access information related to an access occurrence message when an access occurrence message for the first SPM line is received; and a cache line restoration unit for restoring the first SPM line to a cache line when it is confirmed based on the access information that use of the first SPM line is completed.

[0010] According to an embodiment of the present disclosure, there is an effect of efficiently using the cache area by dynamically changing a part of the cache area within the RAM array into an SPM area as needed even in a running kernel.

[0011] The effects of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

[0012] FIG. 1 is a block diagram illustrating the configuration of an SRAM array dynamic allocation device (100) according to one embodiment of the present disclosure.

[0013] Figure 2 is a diagram illustrating n cache ways that constitute an n-way set associative cache.

[0014] Figure 3 is a diagram illustrating an SPM information table.

[0015] FIG. 4 is a flowchart illustrating a SRAM array dynamic allocation method according to one embodiment of the present disclosure.

[0016] Hereinafter, some embodiments of the present disclosure will be described in detail using exemplary drawings. When designating components in each drawing, it should be noted that, where possible, identical components are given the same reference numerals, even if they appear in different drawings. Furthermore, when describing the present disclosure, detailed descriptions of related known structures or functions will be omitted if they are deemed to obscure the gist of the present disclosure.

[0017] In describing components of embodiments according to the present disclosure, symbols such as first, second, i), ii), a), b) may be used. These symbols are only for distinguishing the components from other components, and the nature, order, or sequence of the components are not limited by the symbols. When a part in the specification is said to "include" or "have" a component, this does not mean that other components are excluded, but rather that other components may be included, unless explicitly stated otherwise.

[0018] The detailed description set forth below, together with the accompanying drawings, is intended to explain exemplary embodiments of the present disclosure and is not intended to represent the only embodiments in which the present disclosure may be practiced.

[0019] FIG. 1 is a block diagram illustrating the configuration of an SRAM array dynamic allocation device (100) according to one embodiment of the present disclosure.

[0020] As illustrated in FIG. 1, the SRAM array dynamic allocation device (100) according to the present embodiment may be implemented by including an SPM request receiving unit (110), an SPM area obtaining unit (120), an access information recording unit (130), and a cache line restoring unit (140). The SRAM array dynamic allocation device (100) according to the present embodiment may be implemented by omitting some of the components illustrated in FIG. 1 or by adding other components not illustrated in FIG. 1.

[0021] An SRAM array dynamic allocation device (100) according to one embodiment of the present disclosure operates the SRAM array dynamic allocation device (100) according to the present embodiment during operation of a first kernel (hereinafter referred to as a first kernel) that executes a program in an execution environment including an n-way set-associative cache.

[0022] The SRAM array dynamic allocation device (100) may be implemented as a component of the first kernel, but depending on the embodiment, the SRAM array dynamic allocation device (100) may be implemented as a separate component from the first kernel.

[0023] Hereinafter, the SRAM array dynamic allocation device (100) is described as being implemented as a separate component from the first kernel and implemented to exchange necessary messages with the first kernel during operation.

[0024] Figure 2 is a diagram illustrating n cache ways that constitute an n-way set associative cache.

[0025] An n-way set associative cache (200) is composed of n cache ways, i.e., way 0 (210), way 1 (220), ..., way (n-2) (230), way (n-1) (240), and each cache way includes m cache lines (set 0, set 1, ..., set (m-1)).

[0026] Here, each cache line has a capacity of a certain size, for example, 64 bytes.

[0027] The SPM request receiving unit (110) receives an SPM request message from the additional SPM area securing function of the first kernel. The additional SPM area securing function of the first kernel is a function for securing additional SPM areas required during program execution in the first kernel. Since the details of the additional SPM area securing function are outside the scope of the present invention, a detailed description thereof will be omitted.

[0028] An SPM request message may include the number of cache lines required for use by the SPM. Multiple cache lines may be required for use by the SPM, but the following description assumes that only one cache line is required.

[0029] In the n cache ways (210, 220, 230, 240), each cache way can be preset to have the same maximum number of cache lines available to the SPM (i.e., the same capacity).

[0030] The SPM area acquisition unit (120) acquires a cache line usable as an SPM as the first cache line among the multiple cache lines of n cache ways (210, 220, 230, 240) constituting the n-way collective associative cache (200) according to the SPM request message.

[0031] The SPM area acquisition unit (120) acquires the first cache line from the first cache way among n cache ways (210, 220, 230, 240) that has the largest capacity used as an SPM area. For example, if way n (240) has the largest capacity used as an SPM area, the SPM area acquisition unit (120) sets way n (240) as the first cache way and acquires the first cache line from the first cache way, i.e., way n (240).

[0032] The SPM area acquisition unit (120) sets the acquired first cache line as an SPM area.

[0033] In the following description, unless otherwise stated, the SPM area established from the first cache line is referred to as the first SPM line, and the SPM area obtained from one cache line is referred to as one SPM line.

[0034] When the SPM area acquisition unit (120) acquires one first cache line, it transmits address information corresponding to the first cache line to the SPM management function (not shown) of the first kernel to notify that the first cache line has been allocated as the first SPM line.

[0035] Since the SPM management function (not shown) is outside the scope of the present invention, a detailed description thereof is omitted.

[0036] Figure 3 is a diagram illustrating an SPM information table.

[0037] The SPM information table (300) includes SPM line information corresponding to each SPM line in use, and each SPM line information includes information such as a corresponding SPM line address field, a remaining access count field, etc.

[0038] The SPM information table (300) is stored corresponding to each of n cache ways (210, 220, 230, 240), and thus a total of n SPM information tables are stored.

[0039] The SPM area acquisition unit (120) can check each SPM information table (300) corresponding to n cache ways (210, 220, 230, 240) to check how many cache lines are allocated as SPM lines for each of n cache ways (210, 220, 230, 240).

[0040] For example, since the SPM information table (300) stores information on four SPM lines, the SPM area acquisition unit (120) can know that there are four SPM lines in the cache way corresponding to the SPM information table (300).

[0041] The SPM area acquisition unit (120) checks each SPM information table (300) and sets the cache way (e.g., way n (240)) with the largest capacity used as an SPM line as the first cache way.

[0042] In this embodiment, it is assumed that the number of SPM lines for each cache way (210, 220, 230, 240) is checked by checking the SPM information table (300) for each n cache way (210, 220, 230, 240), but the present invention is not limited thereto.

[0043] Additionally, the SPM area acquisition unit (120) may be implemented to determine the first cache way based on the sum of the values ​​of the remaining access count field of the SPM line information stored in each SPM information table (300).

[0044] In other words, the SPM area acquisition unit (120) may be implemented to determine the cache way with the largest sum of the values ​​of the remaining access count field of each SPM line information stored in each SPM information table (300) as the first cache way.

[0045] For example, if the number of SPM line information of way 0 (210) is 3, the number of SPM line information of way 1 (220) is 0, the number of SPM line information of way (n-2) (230) is 0, and the number of SPM line information of way n (240) is 4, the SPM area acquisition unit (120) compares cache ways in which the number of SPM line information is 1 or more for each SPM information table (300).

[0046] At this time, if the values ​​of the remaining access count fields in the three SPM line information of way 0 (210) are 3, 2, and 4, respectively, the sum of the values ​​of the remaining access count fields becomes 9. In addition, if the values ​​of the remaining access count fields in the four SPM line information of way n (240) are 1, 2, 1, and 1, respectively, the sum of the values ​​of the remaining access count fields becomes 5. In this case, the SPM area acquisition unit (120) may determine way 0 (210) with the largest sum of the values ​​of the remaining access count fields of the SPM line information among way 0 (210) and way n (240) as the first cache way.

[0047] The reason why the cache way with the largest sum of values ​​in the remaining access count field of the SPM line information is determined as the first cache way is that the cache way with a smaller sum of values ​​in the remaining access count field of the SPM line information has a higher probability of having its SPM line accessed more quickly, thus increasing the likelihood that the SPM line will be deleted.

[0048] If way n (240) is determined as the first cache way, the SPM area acquisition unit (120) acquires the cache line with the largest address in the first cache way as the first cache line. That is, the SPM area acquisition unit (120) acquires the cache line corresponding to the last address among the cache lines that are not set as SPM lines in the first cache way as the first cache line. That is, as illustrated in FIG. 2, the first cache line is acquired from the last address of way n (240). By acquiring the first cache line from the last address of way n (240) in this way, fragmentation of the SPM area can be minimized.

[0049] The SPM area acquisition unit (120) stores information indicating that the first cache line is in SPM mode, sets the first cache line as the first SPM line, and stores usage count information related to the first SPM line in the SPM information table (300).

[0050] The SPM area acquisition unit (120) sets a mode field in the tag area of ​​the first cache line and stores information indicating that it is in SPM mode in the mode field. For example, if the mode field is 0, it indicates that the first cache line is in cache mode, and if the mode field is 1, it indicates that the first cache line is in SPM mode.

[0051] The SPM area acquisition unit (120) generates one SPM line information corresponding to the first SPM line in the SPM information table (300), stores the address of the first cache line in the SPM line address field of the corresponding SPM line information, and stores usage count information in the remaining access count field.

[0052] Meanwhile, in this embodiment, the SPM request message is described assuming that the number of cache lines required to be used as an SPM is one, but if the SPM request message received by the SPM request receiving unit (110) means that the number of cache lines required to be used as an SPM is multiple (e.g., k), the SPM area acquisition unit (120) may be implemented to repeat the operation of determining the first cache way one by one k times corresponding to the number of required cache lines, or may be implemented to determine the first cache way once according to the SPM request message and acquire k first cache lines from the determined first cache way.

[0053] In a case where the SPM request message is implemented to acquire k first cache lines from one cache way, the SPM area acquisition unit (120) acquires all k first cache lines required for use as SPM from the first cache way after determining the first cache way.

[0054] The access information recording unit (130) receives and records an access occurrence message for the first SPM line.

[0055] An access occurrence message for the first SPM line indicates that the first SPM line has been accessed once. This means that the first SPM line has been accessed once, either by reading, writing, or updating the first SPM line, and then the access operation has been completed.

[0056] The access information recorder (130) receives an access occurrence message for the first SPM line from the first kernel or a program running in the first kernel.

[0057] When an access occurrence message is received, the access information recorder (130) searches for the first SPM line corresponding to the access occurrence message within the SPM information table (300), and updates the remaining access occurrence field by decreasing the value of the remaining access occurrence field of the first SPM line by 1.

[0058] When the cache line restoration unit (140) confirms that the use of the first SPM line is completed based on the access information of the first SPM line, i.e., the value of the remaining access count field corresponding to the first SPM line, the cache line restoration unit restores the first SPM line to the cache line.

[0059] The cache line restoration unit (140) restores the first SPM line to the cache area when the remaining access count information corresponding to the first SPM line in the SPM information table (300) is 0.

[0060] At this time, the cache line restoration unit (140) obtains the SPM line address field of the SPM line information corresponding to the first SPM line from the SPM information table (300), stores information indicating that it is a cache mode in the mode field of the first SPM line area corresponding to the location of the address corresponding to the SPM line address field, and deletes the SPM line information corresponding to the first SPM line from the SPM information table (300), thereby restoring the first SPM line to the cache area.

[0061] FIG. 4 is a flowchart illustrating a SRAM array dynamic allocation method according to one embodiment of the present disclosure.

[0062] A SRAM array dynamic allocation method according to one embodiment of the present disclosure is performed by an SRAM array dynamic allocation device (100).

[0063] The SPM request receiving unit (110) performs an SPM request receiving process for receiving an SPM request message (S410).

[0064] The SPM area acquisition unit (120) performs an SPM area acquisition process in which, according to an SPM request message, a cache line usable as an SPM among multiple cache lines of n cache ways constituting an n-way collective associative cache is acquired as the first cache line and the first cache line is set as the first SPM line (S420).

[0065] When an access occurrence message for the first SPM line is received, the access information recording unit (130) performs an access information recording process for recording access information related to the access occurrence message (S430).

[0066] When the cache line restoration unit (140) confirms that the use of the first SPM line is completed based on access information, it performs a cache line restoration process to restore the first SPM line to a cache line (S440).

[0067] Each component of the device or method according to the present invention may be implemented in hardware, software, or a combination of hardware and software. Furthermore, the functions of each component may be implemented in software, with a microprocessor executing the software functions corresponding to each component.

[0068] Various implementations of the systems and techniques described herein may be implemented as digital electronic circuits, integrated circuits, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include implementations of one or more computer programs executable on a programmable system. The programmable system includes at least one programmable processor (which may be a special purpose processor or a general purpose processor) coupled to receive data and instructions from and transmit data and instructions to a storage system, at least one input device, and at least one output device. Computer programs (also known as programs, software, software applications, or code) include instructions for the programmable processor and are stored on a "computer-readable recording medium."

[0069] A computer-readable recording medium includes any type of recording device that stores data that can be read by a computer system. Such a computer-readable recording medium may be a non-volatile or non-transitory medium such as a ROM, CD-ROM, magnetic tape, floppy disk, memory card, hard disk, magneto-optical disk, storage device, and may further include a transitory medium such as a data transmission medium. Furthermore, the computer-readable recording medium may be distributed across network-connected computer systems, so that computer-readable code can be stored and executed in a distributed manner.

[0070] Although the flowchart / timing diagram of this specification describes each process as being executed sequentially, this is merely an illustrative description of the technical idea of ​​one embodiment of the present disclosure. In other words, a person of ordinary skill in the art to which one embodiment of the present disclosure belongs may modify and apply various modifications and variations by changing the order described in the flowchart / timing diagram without departing from the essential characteristics of one embodiment of the present disclosure, or by executing one or more of the processes in parallel. Therefore, the flowchart / timing diagram is not limited to a chronological order.

[0071] The above description is merely an example of the technical idea of ​​the present embodiment, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential characteristics of the present embodiment. Therefore, the present embodiments are not intended to limit the technical idea of ​​the present embodiment, but rather to explain it, and the scope of the technical idea of ​​the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be interpreted by the claims below, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of rights of the present embodiment.

[0072] [Explanation of symbols]

[0073] 100: SRAM array dynamic allocation unit 110: SPM request receiving unit

[0074] 120: SPM area acquisition section 130: Access information record section

[0075] 140: Cache line restoration unit 200: n-way set associative cache

[0076] 300: SPM Information Table

[0077]

[0078] Statement regarding sponsored research or development

[0079] The present invention is a result of a research project (Project Unique Number: 1711195786, Subproject Number: 00226492, Ministry of Science and ICT, Project Management (Specialized) Agency: National IT Industry Promotion Agency, Research Project Name: ICT Convergence Industry Innovation Technology Development Project, Research Project Name: Development of Chiplet Heterogeneous Integration Ultra-High-Performance AI Semiconductor, Contribution Ratio: 1 / 1, Project Performing Organizations: Nepes Co., Ltd., Sapion Korea Co., Ltd., Research Period: 2023.04.01 ~ 2027.12.31).

[0080]

[0081] CROSS-REFERENCE TO RELATED APPLICATION

[0082] This patent application claims priority to Korean Patent Application No. 10-2023-0147139, filed in Korea on October 30, 2023, and Korean Patent Application No. 10-2023-0182303, filed in Korea on December 14, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. SPM request reception process for receiving SPM request messages; A process of acquiring an SPM area, which acquires a cache line usable as an SPM (scratched pad memory) among a plurality of cache lines of n cache ways constituting an n-way set-associative cache as a first cache line and sets the first cache line as a first SPM line, according to the above SPM request message; An access information recording process for recording access information related to an access occurrence message when an access occurrence message for the first SPM line is received; and A cache line restoration process that restores the first SPM line to a cache line when it is confirmed that the use of the first SPM line is completed based on the access information. A method for dynamically allocating an SRAM array including:

2. In paragraph 1, The above SPM request reception process is: A method for dynamically allocating an SRAM array, characterized in that the request for securing is received from a kernel that executes a program in an execution environment including the n-way collective associative cache during the operation of the kernel.

3. In paragraph 1, The above SPM area acquisition process is: A method for dynamically allocating an SRAM array, characterized in that the first cache line is acquired from the first cache way having the largest capacity used as an SPM line among the n cache ways.

4. In paragraph 3, The above SPM area acquisition process is: A method for dynamically allocating an SRAM array, characterized in that the cache line having the largest address among the cache lines not set as an SPM line in the first cache way is acquired as the first cache line.

5. In paragraph 1, The above SPM area acquisition process is: A method for dynamically allocating an SRAM array, characterized in that the first cache line is set as the first SPM line by storing information indicating that the first cache line is in SPM mode.

6. In paragraph 1, The above SPM area acquisition process is: A method for dynamically allocating an SRAM array, characterized in that it stores information on the number of remaining accesses related to the first SPM line.

7. In paragraph 6, The above cache line restoration process is: A SRAM array dynamic allocation method characterized in that the first SPM line is restored to a cache area when the remaining access count information of the first SPM line is 0.

8. In paragraph 6, The above cache line restoration process is: A method for dynamically allocating an SRAM array, characterized in that the first SPM line is restored to a cache line by storing information indicating that the first SPM line is in cache mode in a mode field of the first SPM area.

9. A computer program stored on a computer-readable recording medium for executing each process included in the SRAM array dynamic allocation method according to any one of claims 1 to 8.

10. SPM request receiving unit that receives SPM request messages; An SPM area acquisition unit that acquires a cache line usable as an SPM (scratched pad memory) among a plurality of cache lines of n cache ways constituting an n-way set-associative cache as a first cache line according to the above SPM request message and sets the first cache line as a first SPM line; An access information recording unit that records access information related to an access occurrence message when an access occurrence message for the first SPM line is received; and A cache line restoration unit that restores the first SPM line to a cache line when it is confirmed that the use of the first SPM line is completed based on the access information. An SRAM array dynamic allocation device characterized by including:

11. In paragraph 10, The above SPM area acquisition unit is, An SRAM array dynamic allocation device characterized in that the first cache line is acquired from the first cache way having the largest capacity used as an SPM line among the n cache ways.

12. In paragraph 10, The above SPM area acquisition unit is, An SRAM array dynamic allocation device characterized by storing remaining access count information related to the first SPM line.

13. In paragraph 12, The above cache line restoration process is: An SRAM array dynamic allocation device characterized in that the first SPM line is restored to a cache area when the remaining access count information of the first SPM line is 0.

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