Array substrate, manufacturing method therefor, display panel and display apparatus

Abstract

Provided are an array substrate, a manufacturing method therefor, a display panel and a display apparatus. The array substrate comprises: a base substrate (10), which comprises a display area (11) and a binding area (C), the binding area (C) comprising a first binding area (C1) and a second binding area (C2); a first group of bonding pads (PG1), which are located in the first binding area (C1); a second group of bonding pads (PG2), which are located in the second binding area (C2); a signal line (20); a planarization layer (30) having a recess (R), the planarization layer being located on the side of the signal line (20) away from the base substrate (10), the orthographic projection of the binding area (C) on the base substrate (10) being located within the orthographic projection of the recess (R) on the base substrate (10); an insulating layer (40), which is located on the side of the planarization layer (30) away from the base substrate (10); and a plurality of connecting members (CM), which are located on the side of the insulating layer (40) away from the base substrate (10), each connecting member (CM) being connected to a corresponding bonding pad in the first group of bonding pads (PG1) by means of a corresponding first connecting line (CL1 / CL1'), and being connected to a corresponding bonding pad in the second group of bonding pads (PG2) by means of a corresponding second connecting line (CL2 / CL2'), the orthographic projection of each connecting member (CM) on the base substrate (10) overlapping the orthographic projection of the signal line (20) on the base substrate, and the orthographic projection of each connecting member on the base substrate not overlapping the orthographic projection of the recess (R) on the base substrate (10).

Description

Array substrate and manufacturing method thereof, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, a display panel, and a display device. Background Art

[0002] TDDI (Touch and Display Driver Integration) display products integrate touch chips and display chips into a single chip, which helps reduce the thickness of display products, increase the brightness of display products, and facilitate the design of narrow bezels of display products.

[0003] With the development of display technology, people have higher and higher requirements on the display quality of display products such as TDDI products.

[0004] Summary of the Invention

[0005] According to a first aspect of an embodiment of the present disclosure, there is provided an array substrate, comprising: a base substrate, comprising a display area and a binding area located on one side of the display area, the binding area comprising a first binding area and a second binding area located on a side of the first binding area away from the display area; a first group of pads located in the first binding area; a second group of pads located in the second binding area; a signal line located on one side of the base substrate; a planarization layer located on a side of the signal line away from the base substrate, the planarization layer having a groove, the orthographic projection of the binding area on the base substrate being located within the orthographic projection of the groove on the base substrate; an insulating layer located on a side of the planarization layer away from the base substrate; and a plurality of connectors located on a side of the insulating layer away from the base substrate, each of the plurality of connectors being connected to a corresponding pad in the first group of pads via a corresponding first connecting line, and being connected to a corresponding pad in the second group of pads via a corresponding second connecting line, wherein the orthographic projection of each of the plurality of connectors on the base substrate overlaps with the orthographic projection of the signal line on the base substrate, and does not overlap with the orthographic projection of the groove on the base substrate.

[0006] In some embodiments, an orthographic projection of the signal line on the substrate overlaps with an orthographic projection of the groove on the substrate.

[0007] According to a second aspect of an embodiment of the present disclosure, an array substrate is provided, comprising: a base substrate comprising a display area and a binding area located on one side of the display area, the binding area comprising a first binding area and a second binding area located on a side of the first binding area away from the display area; a first group of pads located in the first binding area; a second group of pads located in the second binding area; a signal line located on one side of the base substrate; a planarization layer located on a side of the signal line away from the base substrate, the planarization layer having a groove, the orthographic projection of the binding area on the base substrate being located within the orthographic projection of the groove on the base substrate; an insulating layer located on a side of the planarization layer away from the base substrate; and a plurality of connectors located on a side of the insulating layer away from the base substrate, each of the plurality of connectors being connected to a corresponding pad in the first group of pads via a corresponding first connecting line, and being connected to a corresponding pad in the second group of pads via a corresponding second connecting line, wherein a portion where the orthographic projections of the signal line and the groove on the base substrate overlap does not overlap with the orthographic projection signal line of each of the plurality of connectors on the base substrate.

[0008] In some embodiments, the plurality of connections include a first connection configured to be applied with a low-level voltage signal in at least one phase.

[0009] In some embodiments, the plurality of connectors further includes a second connector configured to be applied with a common voltage signal in the at least one phase.

[0010] According to a third aspect of an embodiment of the present disclosure, an array substrate is provided, comprising: a base substrate comprising a display area and a binding area located on one side of the display area, the binding area comprising a first binding area and a second binding area located on a side of the first binding area away from the display area; a first group of pads located in the first binding area; a second group of pads located in the second binding area; a signal line located on one side of the base substrate; a planarization layer located on a side of the signal line away from the base substrate, the planarization layer having a groove, the orthographic projection of the binding area on the base substrate being located within the orthographic projection of the groove on the base substrate; an insulating layer located on a side of the planarization layer away from the base substrate; and a first connector located on a side of the insulating layer away from the base substrate, configured to be applied with a low-level voltage signal in at least one stage, the first connector being connected to a corresponding pad in the first group of pads via a corresponding first connecting line, and being connected to a corresponding pad in the second group of pads via a corresponding second connecting line, wherein the orthographic projection of the first connector on the base substrate overlaps with the orthographic projection of the signal line on the base substrate, and does not overlap with the orthographic projection of the groove on the base substrate.

[0011] In some embodiments, an orthographic projection of the signal line on the substrate overlaps with an orthographic projection of the groove on the substrate.

[0012] According to a fourth aspect of an embodiment of the present disclosure, an array substrate is provided, comprising: a base substrate comprising a display area and a binding area located on one side of the display area, the binding area comprising a first binding area and a second binding area located on a side of the first binding area away from the display area; a first group of pads located in the first binding area; a second group of pads located in the second binding area; a signal line located on one side of the base substrate; a planarization layer located on a side of the signal line away from the base substrate, the planarization layer having a groove, the orthographic projection of the binding area on the base substrate being located within the orthographic projection of the groove on the base substrate; an insulating layer located on a side of the planarization layer away from the base substrate; and a first connector located on a side of the insulating layer away from the base substrate, configured to be applied with a low-level voltage signal in at least one stage, the first connector being connected to a corresponding pad in the first group of pads via a corresponding first connecting line, and being connected to a corresponding pad in the second group of pads via a corresponding second connecting line, wherein a portion where the orthographic projections of the signal line and the groove on the base substrate overlap does not overlap with the orthographic projection of the first connector on the base substrate.

[0013] In some embodiments, the array substrate further includes: a second connecting member, located on a side of the insulating layer away from the base substrate, configured to be applied with a common voltage signal in at least one stage, the second connecting member being connected to a corresponding pad in the first group of pads via a corresponding first connecting line, and being connected to a corresponding pad in the second group of pads via a corresponding second connecting line; wherein the orthographic projection of the second connecting member on the base substrate overlaps with the orthographic projection of the signal line on the base substrate, and does not overlap with the orthographic projection of the groove on the base substrate.

[0014] In some embodiments, the array substrate further includes: a second connecting member, located on a side of the insulating layer away from the base substrate, configured to be applied with a common voltage signal in at least one stage, the second connecting member being connected to a corresponding pad in the first group of pads via a corresponding first connecting line, and being connected to a corresponding pad in the second group of pads via a corresponding second connecting line; wherein the overlapping portion of the orthographic projection of the signal line and the groove on the base substrate does not overlap with the orthographic projection of the second connecting member on the base substrate.

[0015] In some embodiments, the array substrate further includes: a touch signal line located in the display area; and a switch, wherein the gate of the switch is connected to the first connector via a first pad in the first group of pads, the first electrode of the switch is connected to the second connector via a second pad in the first group of pads, and the second electrode of the switch is connected to the touch signal line.

[0016] In some embodiments, the orthographic projection of the first connector on the base substrate is located between the orthographic projection of the second connector on the base substrate and the bonding area.

[0017] In some embodiments, the at least one phase is a phase in a long-term reliability test.

[0018] In some embodiments, the array substrate further includes: a gate driving circuit configured to provide a gate driving signal to the sub-pixels located in the display area; and the signal line is configured to provide a signal to the gate driving circuit.

[0019] In some embodiments, the array substrate further includes touch electrodes, which are reused as common electrodes.

[0020] In some embodiments, the first bonding area is an integrated circuit bonding area; and the second bonding area is a circuit board bonding area.

[0021] In some embodiments, at least one connecting member is located on the same layer as one of the pixel electrode and the common electrode in the array substrate.

[0022] In some embodiments, the material of at least one connector includes a transparent conductive oxide.

[0023] According to a fifth aspect of the embodiments of the present disclosure, a display panel is provided, comprising: the array substrate described in any one of the above embodiments; a color filter substrate; and a liquid crystal layer located between the array substrate and the color filter substrate.

[0024] According to a sixth aspect of the embodiments of the present disclosure, a display device is provided, comprising: the display panel described in any one of the above embodiments.

[0025] According to a seventh aspect of an embodiment of the present disclosure, a method for manufacturing an array substrate is provided, comprising: providing a substrate substrate, the substrate substrate comprising a display area and a binding area located on one side of the display area, the binding area comprising a first binding area and a second binding area located on a side of the first binding area away from the display area; forming a first group of pads located in the first binding area; forming a second group of pads located in the second binding area; forming a signal line on one side of the substrate substrate; forming a planarization layer on a side of the signal line away from the substrate substrate, the planarization layer having a groove, the orthographic projection of the binding area on the substrate substrate being located within the orthographic projection of the groove on the substrate substrate; forming an insulating layer on a side of the planarization layer away from the substrate substrate; and forming a plurality of connectors on a side of the insulating layer away from the substrate substrate, each of the plurality of connectors being connected to a corresponding pad in the first group of pads via a corresponding first connecting line, and being connected to a corresponding pad in the second group of pads via a corresponding second connecting line, wherein the orthographic projection of each of the plurality of connectors on the substrate substrate overlaps with the orthographic projection of the signal line on the substrate substrate, and does not overlap with the orthographic projection of the groove on the substrate substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0027] The present disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0028] FIG1 is a schematic structural diagram illustrating an array substrate according to some embodiments of the present disclosure;

[0029] FIG2 is a schematic structural diagram showing a portion of an array substrate corresponding to a display area according to some embodiments of the present disclosure;

[0030] FIG3 is a schematic diagram showing a partial structure of an array substrate according to some embodiments of the present disclosure;

[0031] FIG4 is a schematic cross-sectional view taken along line AA' shown in FIG3;

[0032] FIG5 is a schematic cross-sectional view taken along line BB' shown in FIG3;

[0033] FIG6 is a schematic cross-sectional view taken along line CC' shown in FIG3;

[0034] FIG7 is a schematic cross-sectional view taken along line DD' shown in FIG3;

[0035] FIG8A is a partial schematic diagram illustrating an array substrate of the related art;

[0036] FIG8B is a partial schematic diagram illustrating an array substrate according to some embodiments of the present disclosure;

[0037] FIG9 is a schematic structural diagram illustrating a display panel according to some embodiments of the present disclosure;

[0038] FIG10 is a schematic flow chart illustrating a method for manufacturing an array substrate according to some embodiments of the present disclosure;

[0039] FIG. 11 is a schematic flow chart illustrating a method for manufacturing an array substrate according to other embodiments of the present disclosure.

[0040] It should be understood that the same or similar reference numerals denote the same or similar components. DETAILED DESCRIPTION

[0041] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the present disclosure, its application, or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete and to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that unless otherwise specifically stated, the relative arrangement of parts and steps, the composition of materials, numerical expressions, and numerical values ​​set forth in these embodiments should be interpreted as being merely exemplary and not as limiting.

[0042] The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish between different parts. Terms such as "include" or "comprises" mean that the elements preceding the term encompass the elements listed after the term, and do not exclude the possibility of also encompassing other elements. Terms such as "upper," "lower," and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0043] In the present disclosure, when a specific component is described as being located between a first component and a second component, there may or may not be an intervening component between the specific component and the first component or the second component. When a specific component is described as being connected to another component, the specific component may be directly connected to the other component without an intervening component, or may not be directly connected to the other component but have an intervening component.

[0044] All terms (including technical or scientific terms) used in this disclosure have the same meaning as those understood by one of ordinary skill in the art to which this disclosure belongs, unless otherwise specifically defined. It should also be understood that terms defined in, for example, general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined herein.

[0045] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0046] The inventors have noticed that some display products (such as small-size TDDI products) may exhibit screen distortion and display defects during long-term reliability testing.

[0047] In response to this problem, the inventors found after research that the location where the poor display occurs is near the integrated circuit (IC) binding area. Further analysis found that the location where the poor display occurs is at the boundary of the groove of the planarization layer. After further analysis using FIB (focused ion beam) technology, it was found that the boundary of the groove of the planarization layer is bridged by a connector for transmitting signals, and the signal line under the connector bridged at the boundary of the groove is corroded, resulting in signal abnormality, resulting in poor display. In the case where the signal line is used to transmit signals to the gate drive circuit (GOA), the signal is corroded, resulting in abnormal signal output of the gate drive circuit, which leads to poor display of the screen.

[0048] After further analysis, the inventors found that the insulating layer between the connector and the signal line is easily damaged in electrostatic discharge (ESD) or high temperature and high humidity environments. For example, ESD easily accumulates at the climbing position of the groove, thereby breaking down the insulating layer. Because there is no flattening layer between the portion of the signal line that bridges the groove of the flattening layer and the connector, the thickness of the insulating layer between the two is relatively small, making the insulating layer more susceptible to breakdown. When a voltage signal is applied to the connector, a voltage difference exists between the connector and the signal line, which easily causes electrochemical corrosion, thereby corroding the signal line.

[0049] In view of this, the embodiments of the present disclosure propose the following technical solutions, which can at least reduce the corrosion of the signal lines to improve the problem of poor display.

[0050] Figure 1 is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Figure 2 is a schematic diagram illustrating the structure of a portion of an array substrate corresponding to a display area according to some embodiments of the present disclosure. Figure 3 is a schematic diagram illustrating a partial structure of an array substrate according to some embodiments of the present disclosure. Figure 4 is a schematic cross-sectional view taken along line AA' in Figure 3.

[0051] Next, the array substrate according to some embodiments of the present disclosure will be introduced with reference to FIG. 1 to FIG. 4 .

[0052] As shown in FIG. 1 to FIG. 4 , the array substrate includes a base substrate 10 , a first group of pads PG1 , a second group of pads PG2 , a signal line 20 , a planarization layer 30 and an insulating layer 40 .

[0053] First, the base substrate 10 , the first group of pads PG1 and the second group of pads PG2 are introduced with reference to FIG. 1 and FIG. 3 .

[0054] 1 , the base substrate 10 includes a display area 11 and a peripheral area 12. The peripheral area 12 includes a binding area C located on one side of the display area 11. It should be understood that the peripheral area 12 may also include other peripheral areas, for example, a peripheral area arranged opposite to the binding area C (i.e., a peripheral area located below the display area 11), and a peripheral area adjacent to the binding area C (i.e., a peripheral area located on the left and right sides of the display area 11). For example, the base substrate 10 is a glass substrate. It should be noted that although the display area 11 shown in FIG1 is rectangular, this is not restrictive. In some embodiments, the corners of the display area 11 may have a curvature, such as a circular arc, etc.; accordingly, the corners of the peripheral area 12 may also have a curvature.

[0055] 1 and 3 , the binding area C includes a first binding area C1 and a second binding area C2 located on a side of the first binding area C1 away from the display area 11. In some embodiments, the first binding area C1 is an integrated circuit (IC) binding area, and the integrated circuit binding area can be provided with an integrated circuit, such as a TDDI circuit. The TDDI circuit can implement display and touch driving. In some embodiments, the second binding area C2 is a circuit board binding area, and the circuit board binding area can be provided with a circuit board, such as a flexible printed circuit board (FPC). The circuit board can be connected to an external control device.

[0056] The first pad group PG1 is located in the first bonding area C1, and the second pad group PG2 is located in the second bonding area C2. For example, an integrated circuit can be bonded to the first pad group PG1 to transmit signals through the first pad group PG1, and a circuit board can be bonded to the second pad group PG2. In some embodiments, both the first pad group PG1 and the second pad group PG2 can include multiple pads. In some embodiments, one or more pads in the first pad group PG1 can be connected to one or more pads in the second pad group PG2.

[0057] For example, the first pad group PG1 includes a first subgroup pad PG11 and a second subgroup pad PG12, with the first subgroup pad PG11 located between the second subgroup pad PG12 and the second pad group PG2. One or more pads of the second pad group PG2 are connected in a one-to-one correspondence with one or more pads of the first subgroup pad PG11 to input signals to the integrated circuit; the second subgroup pad PG12 can output signals from the integrated circuit. The first subgroup pad PG11 can also be referred to as a signal input pad, and the second subgroup pad PG12 can also be referred to as a signal output pad.

[0058] It should be noted that the second sub-group of pads PG12 shown in FIG. 3 only schematically shows a row of pads. In some embodiments, the second sub-group of pads PG12 may include multiple rows of pads.

[0059] 1 also schematically illustrates a common voltage line COM, a data line DL, a gate line GL, a touch signal line Tx, and a gate drive circuit GOA, which will be described below in conjunction with different embodiments. For example, the common voltage line COM is located in the peripheral area 12 and is disposed around the display area 11.

[0060] Next, the structure of the array substrate located in the display area 11 will be described with reference to FIG. 2 .

[0061] Referring to FIG. 2 , a subpixel P includes a pixel driving circuit, which includes a transistor T. Transistor T includes a gate G, an active layer AT, a first electrode E1, and a second electrode E2. One of the first electrode E1 and the second electrode E2 is a source electrode, and the other is a drain electrode. It should be understood that the pixel driving circuit also includes other transistors and a storage capacitor not shown in FIG. 2 . It should also be understood that the position of the gate G of transistor T is merely schematic; in some embodiments, the active layer AT is closer to the substrate 10 than the gate G.

[0062] The pixel electrode PE is connected to the second electrode E2. For example, the pixel electrode PE is connected to the second electrode E2 through a via hole penetrating the planarization layer 30. The material of the planarization layer 30 includes, for example, an organic material such as polyimide (PI). The common electrode CE and the pixel electrode PE are separated by an insulating layer 40. The material of the insulating layer 40 includes, for example, an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0063] In some embodiments, referring to FIG. 2 , the pixel electrode PE is located on the surface of the planarization layer 30 away from the base substrate 10 , and the common electrode CE is located on the surface of the insulating layer 40 away from the base substrate 10 ; in other embodiments, the pixel electrode PE is located on the surface of the insulating layer 40 away from the base substrate 10 , and the common electrode CE is located on the surface of the planarization layer 30 away from the base substrate 10 .

[0064] In some embodiments, the common electrode CE is multiplexed as the touch electrode TE. For example, the common electrode CE is located on the surface of the insulating layer 40 away from the base substrate 10. In this case, the common electrode CE is connected to the touch signal line Tx through a via hole penetrating the insulating layer 40 and the planarization layer 30. In another example, the common electrode CE is located on the surface of the planarization layer 30 away from the base substrate 10. In this case, the common electrode CE is connected to the touch signal line Tx through a via hole penetrating the planarization layer 30.

[0065] Next, the positional relationship between the signal line 20, the planarization layer 30, and the insulating layer 40 will be described with reference to Figure 4. It is understood that the planarization layer 30 and the insulating layer 40 shown in Figure 4 can extend from the display area 11 shown in Figure 2 to the binding area C.

[0066] 4 , the signal line 20 is located on one side of the base substrate 10, the planarization layer 30 is located on the side of the signal line 20 away from the base substrate 10, and the insulating layer 40 is located on the side of the planarization layer 30 away from the base substrate 10. In some embodiments, the signal line 20 includes only a single metal layer. In other embodiments, the signal line 20 includes multiple metal layers, such as a first metal layer 21 and a second metal layer 22, with an insulating layer GI disposed between the first metal layer 21 and the second metal layer 22. In some implementations, the first metal layer 21 is located on the same layer as the gate G of the transistor T shown in FIG. 2 , and the second metal layer 22 is located on the same layer as the first electrode E1 and the second electrode E2 of the transistor T shown in FIG. 2 .

[0067] It should be noted that, in the embodiments of the present disclosure, multiple components located on the same layer means that the multiple components are formed by patterning the same material layer. Therefore, the multiple components located on the same layer are made of the same material.

[0068] 3 and 4 , the planarization layer 30 has a groove R. It should be understood that the groove R extends through the planarization layer 30. The orthographic projection of the bonding region C on the base substrate 10 is located within the orthographic projection of the groove R on the base substrate 10. In one or more implementations, the orthographic projection of the signal line 20 on the base substrate 10 overlaps with the orthographic projection of the groove R of the planarization layer 30 on the base substrate 10.

[0069] Different embodiments of array substrates capable of improving the problem of poor display are introduced below.

[0070] According to some embodiments of the present disclosure, in addition to the base substrate 10 , the first group of pads PG1 , the second group of pads PG2 , the signal line 20 , the planarization layer 30 , and the insulating layer 40 described above, the array substrate further includes a plurality of connectors CM.

[0071] The following describes multiple connectors CM in conjunction with FIG. 3 and FIG. 4 .

[0072] 3 , each of the plurality of connectors CM is connected to a corresponding pad in the first group of pads PG1 via a corresponding first connection line CL1 / CL1 ′, and is connected to a corresponding pad in the second group of pads PG2 via a corresponding second connection line CL2 / CL2 ′.

[0073] In some embodiments, the plurality of connectors CM include a first connector CM1. For example, the first connector CM1 is configured to be applied with a low-level voltage signal in at least one phase. For example, the first connector CM1 is connected to a corresponding first pad P1 in the first group of pads PG1 via a corresponding first connection line CL1, and is connected to a corresponding third pad P3 in the second group of pads PG2 via a corresponding second connection line CL2.

[0074] In some other embodiments, the plurality of connectors CM further include a second connector CM2. For example, the second connector CM2 is configured to be applied with a common voltage signal in at least one phase. The second connector CM2 is connected to a corresponding second pad P2 in the first pad group PG1 via a corresponding first connection line CL1', and is connected to a corresponding fourth pad P4 in the second pad group PG2 via a corresponding second connection line CL2'.

[0075] 4 , a plurality of connectors CM (eg, a first connector CM1 and a second connector CM2 ) are located on a side of the insulating layer 40 away from the base substrate 10 .

[0076] Different implementations when the array substrate includes multiple connectors CM are described below.

[0077] As some implementations, referring to FIG3 , the orthographic projection of each of the multiple connectors CM on the base substrate 10 overlaps with the orthographic projection of the signal line 20 on the base substrate 10, and does not overlap with the orthographic projection of the recess R of the planarization layer 30 on the base substrate 10. In this manner, an insulating layer 40 and a planarization layer 30 are present between each connector CM and the signal line 20. Compared to a case where only the insulating layer 40 exists between a portion of the connector CM and the signal line 20, the presence of both the insulating layer 40 and the planarization layer 30 makes the signal line 20 less susceptible to ESD breakdown and electrochemical corrosion, thereby helping to improve display quality issues.

[0078] As another implementation, referring to FIG3 , the overlapped portion of the orthographic projection of the signal line 20 on the base substrate 10 and the orthographic projection of the groove R on the base substrate 10 does not overlap the orthographic projection of each connector CM on the base substrate 10 of the signal line 20. In this manner, there is no connector CM directly above the overlapped portion of the signal line 20 and the groove R of the planarization layer 30. Even if the insulating layer above the signal line 20 is broken down, the overlapped portion of the signal line 20 and the groove R is less susceptible to electrochemical corrosion, thereby helping to improve display defects.

[0079] As another implementation, referring to FIG3 , the orthographic projection of each of the plurality of connectors CM on the base substrate 10 overlaps with the orthographic projection of the signal line 20 on the base substrate 10, and does not overlap with the orthographic projection of the groove R of the planarization layer 30 on the base substrate 10. The orthographic projection of the signal line 20 on the base substrate 10 overlaps with the orthographic projection of the groove R on the base substrate 10. In this manner, when the signal line 20 overlaps with the groove R, the display problem can be improved without further changing the position of the signal line 20.

[0080] In some embodiments, at least one of the multiple connectors CM shown in Figures 3 and 4 is located on the same layer as one or more components located in the display area 11. For example, at least one connector is located on the same layer as one of the pixel electrode PE and the common electrode CE shown in Figure 2. This helps simplify the manufacturing process of the array substrate. For example, the first connector M1 and the second connector M2 are both located on the same layer as the common electrode CE. For another example, when the pixel electrode PE is closer to the base substrate 10 than the common electrode CE, the first connector M1 and the second connector M2 are both located on the same layer as the pixel electrode PE.

[0081] In some embodiments, a material of at least one of the plurality of connectors CM shown in FIG. 3 and FIG. 4 includes a transparent conductive material, such as indium tin oxide (ITO).

[0082] The inventors noticed that a low-level voltage signal may be applied to the connector at certain stages (for example, during long-term reliability testing). In this case, there is a greater voltage difference between the connector and the signal line, making electrochemical corrosion more likely to occur, thereby causing the signal line to be more easily corroded.

[0083] In view of this, the present disclosure also proposes the following technical solutions.

[0084] According to other embodiments of the present disclosure, in addition to the base substrate 10, the first group of pads PG1, the second group of pads PG2, the signal line 20, the planarization layer 30, and the insulating layer 40 described above, the array substrate further includes a first connector CM1. The first connector CM1 is configured to be applied with a low-level voltage signal during at least one phase. In some embodiments, the at least one phase is a phase in a long-term reliability test.

[0085] The first connecting member CM1 is described below with reference to FIG. 3 and FIG. 4 .

[0086] 3 , the first connector CM1 is connected to a corresponding pad in the first pad group PG1 (eg, first pad P1 ) via a corresponding first connection line CL1 , and is connected to a corresponding pad in the second pad group PG2 (eg, third pad P3 ) via a corresponding second connection line CL2 .

[0087] 4 , the first connector CM1 is located on a side of the insulating layer 40 away from the base substrate 10 .

[0088] Different implementations of the case where the array substrate includes the first connecting member CM1 are described below.

[0089] As some implementations, referring to FIG3 , the orthographic projection of the first connector CM1 on the base substrate 10 overlaps with the orthographic projection of the signal line 20 on the base substrate 10, but does not overlap with the orthographic projection of the groove R on the base substrate 10. This ensures the presence of the insulating layer 40 and the planarization layer 30 between the first connector CM1, to which the low-level voltage signal is applied, and the signal line 20, making the signal line 20 less susceptible to electrochemical corrosion and effectively improving display defects.

[0090] As another implementation, referring to FIG3 , the overlapping portion of the orthographic projection of the signal line 20 and the groove R on the base substrate 10 does not overlap with the orthographic projection of the first connector CM1 on the base substrate 10. In this manner, the first connector CM1, to which the low-level voltage signal is applied, does not exist directly above the overlapping portion of the signal line 20 and the groove R of the planarization layer 30. Therefore, even if the insulating layer 40 above the signal line 20 is broken down, the overlapping portion of the signal line 20 and the groove R is less susceptible to electrochemical corrosion, which helps to effectively improve the problem of poor display.

[0091] As another implementation, referring to FIG3 , the orthographic projection of the first connector CM1 on the base substrate 10 overlaps with the orthographic projection of the signal line 20 on the base substrate 10, but does not overlap with the orthographic projection of the groove R on the base substrate 10. The orthographic projection of the signal line 20 on the base substrate 10 overlaps with the orthographic projection of the groove R on the base substrate 10. In this manner, when the signal line 20 overlaps with the groove R, the problem of poor display can be improved without further changing the position of the signal line 20.

[0092] In some embodiments, in addition to the first connector CM1, the array substrate further includes a second connector CM2. The second connector CM2 is configured to be applied with a common voltage signal during at least one of the aforementioned stages. For example, when a low-level voltage signal is applied to the first connector CM1, the second connector CM2 is applied with a common voltage signal. In some implementations, during at least one of the aforementioned stages, the voltage of the signal applied to the second connector CM2 (e.g., 0V) is greater than the voltage of the signal applied to the first connector CM1 (e.g., a negative voltage).

[0093] Some implementations of the second connector CM2 are described below with reference to FIG. 3 and FIG. 4 .

[0094] 3 , the second connector CM2 is connected to a corresponding pad in the first group of pads PG1 (eg, the second pad P2 ) via a corresponding first connection line CL1 ′, and is connected to a corresponding pad in the second group of pads PG2 (eg, the fourth pad P4 ) via a corresponding second connection line CL2 ′.

[0095] 4 , the second connector CM2 is located on a side of the insulating layer 40 away from the base substrate 10 .

[0096] As some implementations, referring to FIG3 , the orthographic projection of the second connector CM2 on the base substrate 10 overlaps with the orthographic projection of the signal line 20 on the base substrate 10, but does not overlap with the orthographic projection of the groove R on the base substrate 10. In this manner, the insulating layer 40 and the planarization layer 30 are present between the second connector CM2, to which the common voltage signal is applied, and the signal line 20, making the signal line 20 less susceptible to electrochemical corrosion, thereby further improving the problem of poor display.

[0097] As another implementation, referring to FIG3 , the overlapping portion of the orthographic projection of the signal line 20 and the groove R on the base substrate 10 does not overlap with the orthographic projection of the second connector CM2 on the base substrate 10. In this manner, the second connector CM2 for applying the common voltage signal does not exist directly above the overlapping portion of the signal line 20 and the groove R of the planarization layer 30. Even if the insulating layer above the signal line 20 is broken down, the overlapping portion of the signal line 20 and the groove R is less susceptible to electrochemical corrosion, which helps to further reduce the problem of display defects.

[0098] In some embodiments, referring to FIG. 3 , the orthographic projection of the first connector CM1 on the base substrate 10 is located between the orthographic projection of the second connector CM2 on the base substrate 10 and the binding region C.

[0099] Next, array substrates according to some other embodiments of the present disclosure are introduced.

[0100] In one or more embodiments, referring to FIG1 , the array substrate further includes a gate drive circuit GOA, which is configured to provide a gate drive signal to the sub-pixel P located in the display area 11. In this case, the signal line 20 is configured to provide a signal to the gate drive circuit GOA. For example, the signal line 20 is connected to a pad in the first group of pads PG1 (e.g., the first sub-group of pads PG11). When the technical solutions of the above embodiments are adopted, the signal line 20 is less susceptible to electrochemical corrosion, thereby helping to improve the problem of poor display caused by abnormal signals provided to the gate drive circuit GOA.

[0101] 1 , the gate driving circuit GOA is located in the peripheral area 12. In some implementations, the peripheral areas 12 on opposite sides of the display area 11 may be respectively provided with a gate driving circuit GOA.

[0102] In one or more embodiments, referring to Figures 2 and 3 , the array substrate further includes a touch signal line Tx and a switch K. In some embodiments, the touch signal line Tx and the switch K correspond one to one.

[0103] The touch signal line Tx is located in the display area 11. In some implementations, the touch signal line Tx is located in the same layer as the first electrode E1 and the second electrode E2 of the transistor T shown in FIG2 . In other implementations, the touch signal line Tx includes multiple metal layers, for example, a first metal layer 21 located in the same layer as the first electrode E1 and the second electrode E2 of the transistor T, and a second metal layer 22 located in the same layer as the gate G of the transistor T.

[0104] The gate G' of the switch K is connected to the first connector CM1 via the first pad P1 in the first pad group PG1. The first electrode E1' of the switch K is connected to the second connector CM2 via the second pad P2 in the first pad group PG1. The second electrode E2' of the switch K is connected to the touch signal line Tx. The first electrode E1' and the second electrode E2' can include a single metal layer or a double metal layer.

[0105] It should be noted that the position of the switch K shown in FIG. 3 is schematic. For example, the switch K may be located between the display area 11 and the first binding area C1 .

[0106] During at least one phase, a low-level voltage signal is applied to the gate G' of the switch K. For example, the switch K is an n-type transistor; when a low-level voltage signal is applied to the gate G', the switch K is off; when a high-level voltage signal is applied to the gate G', the switch K is on.

[0107] For example, in the first stage, a high-level voltage signal is applied to the gate G' of the switch K, the switch K is turned on, and a touch signal is applied to the touch signal line Tx to perform a touch test; in the second stage, a low-level voltage signal is applied to the gate G' of the switch K, the switch K is turned off to perform other tests.

[0108] The gate G' of switch K connected to touch signal line Tx needs to be applied with a low-level signal at some point during testing, so the first connector CM1 connected to gate G' of switch K also needs to be applied with a low-level signal. In this case, as previously analyzed, the voltage difference between the first connector CM1 and signal line 20 is greater, making signal line 20 more susceptible to corrosion. By ensuring that the orthographic projections of the first connector CM1 and recess R on the substrate do not overlap, or by ensuring that the orthographic projections of the signal line 20 and recess R on the substrate do not overlap with the orthographic projection of the first connector CM1 on the substrate, the risk of corrosion of the signal line 20 can be reduced, thereby more effectively improving display defects.

[0109] Next, some embodiments of the array substrate are further described with reference to Figures 5 to 7. In Figures 5 to 7, as some implementations, the first metal layer 21 is located on the same layer as the gate G of the transistor T shown in Figure 2, and the second metal layer 22 is located on the same layer as the first electrode E1 and the second electrode E2 of the transistor T shown in Figure 2.

[0110] FIG. 5 is a schematic cross-sectional view taken along line BB′ shown in FIG. 3 .

[0111] In some embodiments, as shown in FIG5 , the first connection member CM1 can be connected to the first connection line CL1 via a first via V1 penetrating the insulating layer 40, the planarization layer 30, and the insulating layer GI, and the first connection member CM1 can be connected to the second connection line CL2 via a second via V1 penetrating the insulating layer 40, the planarization layer 30, and the insulating layer GI. In some implementations, the first connection line CL1 and the second connection line CL2 both include the first metal layer 21, and the first connection line CL1′ and the second connection line CL2′ both include the first metal layer 21.

[0112] 5 schematically shows only the first connection line CL1', but not the second connection line CL2'. The positional relationship between the second connection line CL2' and other layers can refer to the positional relationship between the first connection line CL1' and other layers.

[0113] Fig. 6 is a schematic cross-sectional view taken along line CC' shown in Fig. 3. Fig. 7 is a schematic cross-sectional view taken along line DD' shown in Fig. 3.

[0114] In some embodiments, as shown in Figures 3, 6, and 7, each pad of the first group of pads PG1 is covered with a first connection electrode CM3, and each pad of the second group of pads PG1 is covered with a second connection electrode CM4. The first connection electrode CM3 and the second connection electrode CM4 can protect the pads. In some embodiments, the first connection electrode CM3 and the second connection electrode CM4 are located on the same layer as the connector CM. In some embodiments, the first connection electrode CM3 and the second connection electrode CM4 are located on the same layer as the common electrode CE or the pixel electrode PE that is farther away from the base substrate 10.

[0115] In some embodiments, as shown in FIG. 6 , the first connection electrode CM3 is connected to a pad (eg, the first pad P1 or the second pad P2 ) in the first group of pads PG1 through a via hole.

[0116] FIG6 shows three connection modes, which are described below respectively.

[0117] 6 , the pads in the first pad group PG1 include the first metal layer 21. In this case, the first connection electrode CM3 is connected to the first metal layer 21 as the pad through a via penetrating the insulating layer 40 and the insulating layer GI.

[0118] As another implementation, as shown in the middle diagram of FIG6 , the pads in the first group of pads PG1 include a first metal layer 21 and a second metal layer 22. In this case, the first connection electrode CM3 is connected to the second metal layer 22 in the pad through a via penetrating the insulating layer 40, and the first connection electrode CM3 is connected to the first metal layer 21 in the pad through a via penetrating the insulating layer 40 and the insulating layer GI.

[0119] 6 , the pads in the first pad group PG1 include the second metal layer 22. In this case, the first connection electrode CM3 is connected to the second metal layer 22 as the pad through a via hole penetrating the insulating layer 40.

[0120] In some embodiments, some pads in the first group of pads PG1 use a single layer of metal (see the leftmost or rightmost diagram in FIG6 ), and other pads use a double layer of metal (see the middle diagram in FIG6 ). In some implementations, one of adjacent pads (e.g., laterally adjacent pads) in the first group of pads PG1 uses a single layer of metal, and the other pad uses a double layer of metal.

[0121] In some embodiments, as shown in FIG. 7 , the second connection electrode CM4 is connected to a pad (eg, the third pad P3 or the fourth pad P4 ) in the second group of pads PG2 through a via hole.

[0122] Similar to FIG6 , FIG7 also shows three connection modes, which are described below respectively.

[0123] 7 , the pads in the second pad group PG2 include the first metal layer 21. In this case, the second connection electrode CM4 is connected to the first metal layer 21 as the pad through a via penetrating the insulating layer 40 and the insulating layer GI.

[0124] As another implementation, as shown in the middle diagram of FIG7 , the pads in the second group of pads PG2 include a first metal layer 21 and a second metal layer 22. In this case, the second connection electrode CM4 is connected to the second metal layer 22 in the pad through a via hole penetrating the insulating layer 40, and the second connection electrode CM4 is connected to the first metal layer 21 in the pad through a via hole penetrating the insulating layer 40 and the insulating layer GI.

[0125] 7 , the pads in the second pad group PG2 include the second metal layer 22. In this case, the second connection electrode CM4 is connected to the second metal layer 22 as the pad through a via penetrating the insulating layer 40.

[0126] In some embodiments, some pads in the second group of pads PG2 use a single layer of metal (see the leftmost or rightmost diagram in FIG7 ), and other pads use a double layer of metal (see the middle diagram in FIG7 ). In some implementations, one of adjacent pads (e.g., laterally adjacent pads) in the second group of pads PG2 uses a single layer of metal, and the other pad uses a double layer of metal.

[0127] The first group of pads PG1 can be connected to the second group of pads PG2 via a third connection line CL3 and a fourth connection line CL4, respectively. For example, one pad in the first group of pads PG1 is connected to one pad in the second group of pads PG2 via the third connection line CL3; another pad in the first group of pads PG1 is connected to another pad in the second group of pads PG2 via the fourth connection line CL4. In some implementations, the third connection line CL3 includes a first metal layer 21, and the fourth connection line CL4 includes a first metal layer 21 and a second metal layer 22.

[0128] To highlight certain components, each of Figures 4-7 schematically illustrates multiple, spaced-apart sections. For example, Figures 4 and 5 illustrate four sections, Figure 6 illustrates three sections, and Figure 7 illustrates two sections. It should be noted that layers labeled with the same reference number in different sections of each figure are continuous.

[0129] Fig. 8A is a partial schematic diagram illustrating an array substrate of the related art. Fig. 8B is a partial schematic diagram illustrating an array substrate according to some embodiments of the present disclosure.

[0130] As shown in FIG. 8A , in the related art, the first connector CM1 is connected across the boundary of the groove R, which causes the signal line 20 to be easily corroded, resulting in poor display.

[0131] As shown in FIG. 8B , in some embodiments of the present disclosure, the first connector CM1 is not connected across the boundary of the groove R, so the signal line 20 is not easily corroded, thereby improving the problem of poor display.

[0132] FIG. 9 is a schematic structural diagram illustrating a display panel according to some embodiments of the present disclosure.

[0133] As shown in Figure 9 , the display panel includes an array substrate TA, a color filter substrate TB, and a liquid crystal layer LL located between the array substrate TA and the color filter substrate TB. The array substrate TA can be the array substrate of any of the aforementioned embodiments. It should be noted that Figure 9 only schematically illustrates the base substrate BS, black matrix BA, filter FR, and optical adhesive OA within the color filter substrate TB. It is understood that the color filter substrate TB may also include other components, such as polarizers.

[0134] In some embodiments, the array substrate TA and the color filter substrate TB may be bonded together by a sealing adhesive CL.

[0135] FIG10 is a schematic flow chart illustrating a method for manufacturing an array substrate according to some embodiments of the present disclosure;

[0136] In step 1002, a base substrate is provided, which includes a display area and a binding area located on one side of the display area, wherein the binding area includes a first binding area and a second binding area located on a side of the first binding area away from the display area.

[0137] In step 1004 , a first set of pads is formed at a first bonding region.

[0138] In step 1006 , a second set of pads is formed at the second bonding region.

[0139] In step 1008 , a signal line is formed on one side of the base substrate.

[0140] In step 1010 , a planarization layer is formed on a side of the signal line away from the base substrate. The planarization layer has a groove, and the orthographic projection of the bonding region on the base substrate is located within the orthographic projection of the groove on the base substrate.

[0141] In step 1012 , an insulating layer is formed on a side of the planarization layer away from the substrate.

[0142] At step 1014, a plurality of connectors are formed on a side of the insulating layer away from the substrate, wherein each connector is connected to a corresponding pad in the first group of pads via a corresponding first connection line and to a corresponding pad in the second group of pads via a corresponding second connection line.

[0143] In some embodiments, the orthographic projection of each of the plurality of connectors on the substrate overlaps the orthographic projection of the signal line on the substrate, but does not overlap the orthographic projection of the groove on the substrate. In this manner, an insulating layer and a planarization layer are present between each connector and the signal line. Compared to a situation where only an insulating layer exists between a portion of the connector and the signal line, since both the insulating layer and the planarization layer are less susceptible to ESD breakdown, the signal line is less susceptible to electrochemical corrosion, thereby helping to improve display defects.

[0144] In other embodiments, the overlapping portion of the orthographic projection of the signal line and the groove on the substrate does not overlap the orthographic projection of each of the multiple connectors on the substrate. In this manner, no connector exists directly above the overlapping portion of the signal line and the groove of the planarization layer. Even if the insulating layer above the signal line is broken down, the overlapping portion of the signal line and the groove is less susceptible to electrochemical corrosion, which helps to improve display problems.

[0145] FIG. 11 is a schematic flow chart illustrating a method for manufacturing an array substrate according to other embodiments of the present disclosure.

[0146] In step 1102 , a base substrate is provided. The base substrate includes a display area and a binding area located on one side of the display area. The binding area includes a first binding area and a second binding area located on a side of the first binding area away from the display area.

[0147] At step 1104 , a first set of pads is formed at a first bonding region.

[0148] At step 1106 , a second set of pads is formed at the second bonding region.

[0149] In step 1108, signal lines are formed on one side of the base substrate.

[0150] In step 1110 , a planarization layer is formed on a side of the signal line away from the base substrate. The planarization layer has a groove, and the orthographic projection of the bonding region on the base substrate is located within the orthographic projection of the groove on the base substrate.

[0151] In step 1112 , an insulating layer is formed on a side of the planarization layer away from the substrate.

[0152] At step 1114, a first connector is formed on a side of the insulating layer away from the substrate. The first connector is configured to be applied with a low-level voltage signal in at least one phase, and the first connector is connected to a corresponding pad in the first group of pads via a corresponding first connection line, and is connected to a corresponding pad in the second group of pads via a corresponding second connection line.

[0153] In some embodiments, the orthographic projection of the first connector on the substrate overlaps with the orthographic projection of the signal line on the substrate, but does not overlap with the orthographic projection of the groove on the substrate. This ensures that an insulating layer and a planarization layer exist between the first connector, to which a low-level voltage signal is applied, and the signal line, making the signal line less susceptible to electrochemical corrosion and effectively improving display quality issues.

[0154] In other embodiments, the overlapping portion of the orthographic projection of the signal line and the groove on the base substrate does not overlap with the orthographic projection of the first connector on the base substrate. In this manner, the first connector, to which the low-level voltage signal is applied, does not exist directly above the overlapping portion of the signal line and the groove of the planarization layer. Even if the insulating layer above the signal line is broken down, the overlapping portion of the signal line and the groove is less susceptible to electrochemical corrosion, which helps to effectively improve the problem of poor display.

[0155] It should be noted that the steps shown in Figures 10 and 11 are not necessarily executed in the order shown. In some embodiments, some steps can be executed in parallel. For example, multiple steps in step 1004, step 1006, and step 1008 can be executed in parallel, and multiple steps in step 1104, step 1106, and step 1108 can be executed in parallel.

[0156] The present disclosure further provides a display device, which may include the array substrate of any of the aforementioned embodiments. In some embodiments, the display device may be, for example, a mobile terminal, a television, a monitor, a laptop computer, a tablet computer, a digital photo frame, a navigation system, an electronic paper, or any other product or component with a display function.

[0157] In some embodiments, the display device is a TDDI display device.

[0158] Thus far, various embodiments of the present disclosure have been described in detail. To avoid obscuring the concept of the present disclosure, some details known in the art have not been described. Based on the above description, those skilled in the art can fully understand how to implement the technical solutions disclosed herein.

[0159] Although some specific embodiments of the present disclosure have been described in detail through examples, those skilled in the art will understand that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. Those skilled in the art will understand that the above embodiments may be modified or some technical features may be replaced with equivalents without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. An array substrate, include: A substrate, comprising a display area and a binding area located at one side of the display area, wherein the binding area comprises a first binding area and a second binding area located at a side of the first binding area away from the display area; A first group of pads, located in the first binding area; A second group of pads, located in the second bonding area; A signal line, located on one side of the substrate; A planarization layer is located on a side of the signal line away from the substrate, the planarization layer has a groove, and the orthographic projection of the binding area on the substrate is located within the orthographic projection of the groove on the substrate; An insulating layer, located on a side of the planarization layer away from the substrate; as well as A plurality of connectors are located on a side of the insulating layer away from the substrate, each of the plurality of connectors is connected to a corresponding pad in the first group of pads via a corresponding first connecting line, and is connected to a corresponding pad in the second group of pads via a corresponding second connecting line, The orthographic projection of each of the plurality of connectors on the base substrate overlaps with the orthographic projection of the signal line on the base substrate, and does not overlap with the orthographic projection of the groove on the base substrate.

2. The array substrate according to claim 1, in, An orthographic projection of the signal line on the base substrate overlaps with an orthographic projection of the groove on the base substrate.

3. An array substrate, include: A substrate, comprising a display area and a binding area located at one side of the display area, wherein the binding area comprises a first binding area and a second binding area located at a side of the first binding area away from the display area; A first group of pads, located in the first binding area; A second group of pads, located in the second bonding area; A signal line, located on one side of the substrate; A planarization layer is located on a side of the signal line away from the substrate, the planarization layer has a groove, and the orthographic projection of the binding area on the substrate is located within the orthographic projection of the groove on the substrate; An insulating layer, located on a side of the planarization layer away from the substrate; as well as A plurality of connectors are located on a side of the insulating layer away from the substrate, each of the plurality of connectors The connecting members are respectively connected to corresponding pads in the first group of pads via corresponding first connecting wires, and are respectively connected to corresponding pads in the second group of pads via corresponding second connecting wires, Wherein, a portion where the signal line and the groove are overlapped by their orthographic projections on the substrate does not overlap with a signal line of the orthographic projection of each of the plurality of connectors on the substrate.

4. The array substrate according to any one of claims 1 to 3, in, The plurality of connections include a first connection configured to be applied with a low-level voltage signal in at least one phase.

5. The array substrate according to claim 4, in, The plurality of connectors further includes a second connector configured to be applied with a common voltage signal in the at least one phase.

6. An array substrate, include: A substrate, comprising a display area and a binding area located at one side of the display area, wherein the binding area comprises a first binding area and a second binding area located at a side of the first binding area away from the display area; A first group of pads, located in the first binding area; A second group of pads, located in the second bonding area; A signal line, located on one side of the substrate; A planarization layer is located on a side of the signal line away from the substrate, the planarization layer has a groove, and the orthographic projection of the binding area on the substrate is located within the orthographic projection of the groove on the substrate; An insulating layer, located on a side of the planarization layer away from the substrate; as well as a first connecting member, located on a side of the insulating layer away from the substrate, configured to be applied with a low-level voltage signal in at least one stage, the first connecting member being connected to a corresponding pad in the first group of pads via a corresponding first connecting line, and being connected to a corresponding pad in the second group of pads via a corresponding second connecting line, The orthographic projection of the first connecting member on the base substrate overlaps with the orthographic projection of the signal line on the base substrate, and does not overlap with the orthographic projection of the groove on the base substrate.

7. The array substrate according to claim 6, in, An orthographic projection of the signal line on the base substrate overlaps with an orthographic projection of the groove on the base substrate.

8. An array substrate, include: A substrate, comprising a display area and a binding area located at one side of the display area, wherein the binding area comprises a first binding area and a second binding area located at a side of the first binding area away from the display area; A first group of pads, located in the first binding area; A second group of pads, located in the second bonding area; A signal line, located on one side of the substrate; A planarization layer is located on a side of the signal line away from the substrate, the planarization layer has a groove, and the orthographic projection of the binding area on the substrate is located within the orthographic projection of the groove on the substrate; An insulating layer, located on a side of the planarization layer away from the substrate; as well as a first connecting member, located on a side of the insulating layer away from the substrate, configured to be applied with a low-level voltage signal in at least one stage, the first connecting member being connected to a corresponding pad in the first group of pads via a corresponding first connecting line, and being connected to a corresponding pad in the second group of pads via a corresponding second connecting line, The overlapping portion of the orthographic projections of the signal line and the groove on the base substrate does not overlap with the orthographic projection of the first connecting member on the base substrate.

9. The array substrate according to any one of claims 6 to 8, further comprising: include: A second connecting member, located on a side of the insulating layer away from the substrate, configured to be applied with a common voltage signal in the at least one stage, the second connecting member being connected to a corresponding pad in the first group of pads via a corresponding first connecting line, and being connected to a corresponding pad in the second group of pads via a corresponding second connecting line; The orthographic projection of the second connecting member on the base substrate overlaps with the orthographic projection of the signal line on the base substrate, and does not overlap with the orthographic projection of the groove on the base substrate.

10. The array substrate according to any one of claims 6 to 8, further comprising: include: A second connecting member, located on a side of the insulating layer away from the substrate, configured to be applied with a common voltage signal in the at least one stage, the second connecting member being connected to a corresponding pad in the first group of pads via a corresponding first connecting line, and being connected to a corresponding pad in the second group of pads via a corresponding second connecting line; Wherein, a portion where the orthographic projections of the signal line and the groove on the base substrate overlap does not overlap with an orthographic projection of the second connecting member on the base substrate.

11. The array substrate according to claim 5, 9 or 10, further comprising: include: A touch signal line, located in the display area; as well as A switch, wherein the gate of the switch is connected to the first connector via a first solder pad in the first group of solder pads, the first electrode of the switch is connected to the second connector via a second solder pad in the first group of solder pads, and the second electrode of the switch is connected to the touch signal line.

12. The array substrate according to any one of claims 5, 9 to 11, in, The orthographic projection of the first connecting member on the base substrate is located between the orthographic projection of the second connecting member on the base substrate and the binding area.

13. The array substrate according to any one of claims 4 to 12, in, The at least one phase is a phase in a long-term reliability test.

14. The array substrate according to any one of claims 1 to 13, further comprising: include: A gate driving circuit configured to provide a gate driving signal to the sub-pixels located in the display area; The signal line is configured to provide a signal to the gate driving circuit.

15. The array substrate according to claim 1-14, further comprising: include: Touch control electrodes, wherein the touch control electrodes are multiplexed as common electrodes.

16. The array substrate according to any one of claims 1 to 15, in: The first bonding area is an integrated circuit bonding area; and The second binding area is a circuit board binding area.

17. The array substrate according to any one of claims 1 to 16, in, At least one connecting member is located at the same layer as one of the pixel electrode and the common electrode in the array substrate.

18. The array substrate according to any one of claims 1 to 17, in, The material of at least one of the connecting elements includes a transparent conductive oxide.

19. A display panel, include: The array substrate according to any one of claims 1 to 18; Color film substrate; as well as The liquid crystal layer is located between the array substrate and the color filter substrate.

20. A display device, include: The display panel as claimed in claim 19.

Images