Real-time simulation data transmission method, apparatus and device, and storage medium

By deploying FPGAs between real-time simulation nodes, and using DMA operations and fiber optic communication technology, combined with the frame-end sequence number detection method, the shortcomings of data communication in the prior art in microsecond real-time are solved, and more efficient data transmission is achieved.

WO2025102607A1PCT designated stage expired Publication Date: 2025-05-22ELECTRIC POWER RES INST CHINA SOUTHERN POWER GRID CO LTD
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Patent Information

Application Number
PCT/CN2024/089462
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2023-11-16
Filing Date
2024-04-24
Publication Date
2025-05-22

AI Technical Summary

Technical Problem

The data communication between existing real-time simulation nodes has insufficient microsecond real-time performance, resulting in large jitter in data transmission and reception time, which cannot meet higher transmission needs.

Method used

Real-time transmission and reception of data frames are achieved by deploying FPGAs on the simulation sending and receiving side, and using DMA operations and fiber optic communication technology. At the same time, data detection is performed using the end of the frame sequence number to reduce the time jitter caused by interrupt switching.

Benefits of technology

It improves the real-time nature of data transmission, reduces time jitter, and can meet higher data transmission needs.

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Abstract

A real-time simulation data transmission method, apparatus and device, and a storage medium, relating to the technical field of data transmission. The method comprises: determining whether a simulation sending side has a data frame to be sent, and if yes, increasing a frame tail serial number of the data frame to be sent of a sending buffer area by 1; by means of an FPGA of the simulation sending side and on the basis of a DMA operation and the optical fiber communication technology, sending the data frame to be sent to a simulation receiving side to obtain a received data frame; and by means of an FPGA of the simulation receiving side, determining whether the frame tail serial number of the received data frame is increased, and if yes, extracting the received data frame from a receiving buffer area and storing same. The simulation receiving side may directly detect new data by polling whether the frame tail serial number is increased, without interrupting operation, thereby reducing time jitter caused by CPU process switching due to an interrupt. Therefore, the present application can solve the technical problems of large time jitter and difficulty in meeting higher transmission requirements of existing data caused by not considering microsecond-level real-time performance during existing data transceiving.
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Description

A real-time simulation data transmission method, device, equipment and storage medium

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 16, 2023, with application number 202311534087.6 and invention name “A real-time simulation data transmission method, device, equipment and storage medium”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of data transmission technology, and in particular to a real-time simulation data transmission method, device, equipment and storage medium. Background Art

[0003] Currently, data communication between different real-time simulation nodes often uses Ethernet, which can be a standard network cable or optical fiber. However, real-time simulation nodes may not use a real-time operating system (RTOS), use third-party network cards, and use Ethernet card drivers that don't consider real-time performance. This can lead to significant jitter in data transmission and reception, failing to meet microsecond-level real-time requirements.

[0004] Summary of the Invention

[0005] The present application provides a real-time simulation data transmission method, apparatus, device and storage medium for solving the technical problem that existing data transmission and reception do not take microsecond-level real-time performance into consideration, have large time jitter, and are unable to meet the higher transmission requirements of existing data.

[0006] In view of this, the first aspect of the present application provides a real-time simulation data transmission method, comprising:

[0007] Determine whether there is a data frame to be sent on the simulated sending side, and if so, increase the frame tail sequence number of the data frame to be sent in the sending buffer by 1;

[0008] The FPGA of the simulated sending side sends the data frame to be sent to the simulated receiving side based on DMA operation and optical fiber communication technology to obtain a received data frame;

[0009] The FPGA on the simulated receiving side is used to determine whether the frame tail sequence number of the received data frame is increased. If so, the received data frame is extracted and saved in the receiving buffer.

[0010] Preferably, the step of determining whether there is a data frame to be sent on the simulated sending side, and if so, increasing the frame tail sequence number of the data frame to be sent in the sending buffer by 1, further includes:

[0011] A fixed-size buffer is allocated to the simulated sending side and the simulated receiving side to obtain a sending buffer and a receiving buffer.

[0012] Preferably, the step of sending the data frame to be sent to the simulation receiving side based on DMA operation and optical fiber communication technology through the FPGA of the simulation sending side to obtain the received data frame includes:

[0013] Initiate a DMA operation by the FPGA of the simulated sending side to read the data frame to be sent in the sending buffer into the FPGA through the pice8x interface;

[0014] The optical fiber communication technology of the multi-channel Aurora protocol is used to send the data frame to be sent in the FPGA to the simulation receiving side to obtain a received data frame.

[0015] Preferably, the FPGA on the simulated receiving side is used to determine whether the frame tail sequence number of the received data frame is increased, and if so, extracting and saving the received data frame in the receiving buffer, which also includes:

[0016] The DMA operation is initiated by the FPGA on the simulated receiving side to read the received data frame in the receiving buffer into the FPGA through the pice8x interface.

[0017] A second aspect of the present application provides a real-time simulation data transmission device, comprising:

[0018] a tail frame processing unit, configured to determine whether there is a data frame to be sent on the simulated sending side, and if so, to increase the tail frame sequence number of the data frame to be sent in the sending buffer by 1;

[0019] A data sending unit is used to send the to-be-sent data frame to the simulation receiving side through the FPGA of the simulation sending side based on DMA operation and optical fiber communication technology to obtain a received data frame;

[0020] The receiving judgment unit is used to judge whether the frame tail sequence number of the received data frame is increased through the FPGA of the simulated receiving side, and if so, extract the received data frame in the receiving buffer and save it.

[0021] Preferably, it also includes:

[0022] The buffer configuration unit is used to allocate fixed-size buffers to the simulated sending side and the simulated receiving side to obtain a sending buffer and a receiving buffer.

[0023] Preferably, the data sending unit is specifically used to:

[0024] Initiate a DMA operation by the FPGA of the simulated sending side to read the data frame to be sent in the sending buffer into the FPGA through the pice8x interface;

[0025] The optical fiber communication technology of the multi-channel Aurora protocol is used to send the data frame to be sent in the FPGA to the simulation receiving side to obtain a received data frame.

[0026] Preferably, it also includes:

[0027] The data reading unit is used to initiate a DMA operation through the FPGA of the simulated receiving side to read the received data frame in the receiving buffer into the FPGA through the pice8x interface.

[0028] A third aspect of the present application provides a real-time simulation data transmission device, the device comprising a processor and a memory;

[0029] The memory is used to store program code and transmit the program code to the processor;

[0030] The processor is configured to execute the real-time simulation data transmission method described in the first aspect according to instructions in the program code.

[0031] A fourth aspect of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium is used to store program code, and the program code is used to execute the real-time simulation data transmission method described in the first aspect.

[0032] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0033] In the present application, a real-time simulation data transmission method is provided, including: judging whether there is a data frame to be sent on the simulation sending side, and if so, increasing the frame tail sequence number of the data frame to be sent in the sending buffer by 1; sending the data frame to be sent to the simulation receiving side based on DMA operation and optical fiber communication technology through the FPGA of the simulation sending side to obtain a received data frame; judging whether the frame tail sequence number of the received data frame is increased through the FPGA of the simulation receiving side, and if so, extracting the received data frame in the receiving buffer and saving it.

[0034] The real-time simulated data transmission method provided by this application allows the simulated sending side to determine in real time whether there is a data frame to be sent, place a sequence number at the end of the frame, and increase the sequence number at the end of the frame by 1 before sending the data. The simulated receiving side can directly detect new data by polling whether the sequence number at the end of the frame has increased without interrupting the operation, thereby reducing the time jitter caused by interrupting the switching of CPU processes and improving the real-time performance of data transmission. Therefore, this application can solve the technical problem that existing data transmission and reception do not consider microsecond-level real-time performance, have large time jitter, and are difficult to meet the higher transmission requirements of existing data. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 is a flow chart of a real-time simulation data transmission method provided by an embodiment of the present application;

[0036] FIG2 is a schematic structural diagram of a real-time simulation data transmission device provided in an embodiment of the present application;

[0037] FIG3 is a structural diagram of a real-time simulation data transmission system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to help those skilled in the art better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0039] For ease of understanding, please refer to FIG1 , which shows an embodiment of a real-time simulation data transmission method provided by the present application, including:

[0040] Step 101: Determine whether the simulated sending side has a data frame to be sent. If so, increase the frame tail sequence number of the data frame to be sent in the sending buffer by 1.

[0041] Furthermore, before step 101, the following steps are also included:

[0042] A fixed-size buffer is allocated to the simulated sending side and the simulated receiving side to obtain a sending buffer and a receiving buffer.

[0043] It should be noted that the simulated sending side can determine whether there are data frames to be sent in real time, and the simulated sending side pre-configures a buffer to store the data to be sent. To avoid time jitter caused by memory reallocation during data transmission, this embodiment uses a fixed-size buffer allocation method to determine the size of the simulated sending side's send buffer. Similarly, the simulated receiving side also uses this principle to allocate buffers, resulting in a fixed-size receive buffer.

[0044] Placing the sequence number at the end of the data frame to be sent and increasing the sequence number of the end frame by 1 allows the receiving side to quickly and efficiently determine whether a new frame of data has been received by simply detecting whether the sequence number of the end frame has increased. This simple operation and efficient detection method can avoid time jitter caused by complex process switching, thereby improving the efficiency of real-time data transmission.

[0045] Step 102: The data frame to be sent is sent to the simulated receiving side based on DMA operation and optical fiber communication technology through the FPGA of the simulated sending side to obtain a received data frame.

[0046] Furthermore, step 102 includes:

[0047] By simulating the FPGA on the sending side, a DMA operation is initiated to read the data frames to be sent in the sending buffer into the FPGA through the pice8x interface;

[0048] The optical fiber communication technology of the multi-channel Aurora protocol is used to send the data frame to be sent in the FPGA to the simulation receiving side to obtain the received data frame.

[0049] Both the simulated sending and receiving sides are equipped with FPGAs, and both can read data and transmit and receive data based on DMA operations. Based on the received control instructions, the FPGA can determine the packet size of the data frame to be sent and the location of the data buffer (i.e., the memory address). It then actively initiates a DMA operation to read the data to be sent into the FPGA via the pice8x interface. During the data reading process, the data frames to be sent can be simultaneously transmitted to the simulated receiving side via multiple fiber-optic communications based on the Aurora protocol, generating received data frames. It is also understood that the received data frames are stored in the receive buffer, and the simulated receiving side can determine information such as the packet size and memory address based on the received data frames in the receive buffer.

[0050] Step 103: Determine whether the frame tail sequence number of the received data frame increases by simulating the FPGA on the receiving side. If so, extract the received data frame in the receiving buffer and save it.

[0051] Furthermore, before step 103, the following steps are also included:

[0052] By simulating the FPGA on the receiving side, a DMA operation is initiated to read the received data frame in the receiving buffer into the FPGA through the pice8x interface.

[0053] The simulated receiving side is configured with a real-time process for detecting received data, namely, receiving data frames. The simulated receiving side also actively initiates a DMA operation after receiving control instructions through the FPGA to read the received data frames in the receive buffer through the pice8x interface to the corresponding FPGA. It then judges and analyzes the tail frame sequence number of the received data frame. If the tail frame sequence number increases, the received data frame in the receive buffer is extracted. The extracted received data frame can be saved or copied to a specified area. The specific subsequent processing is not limited here. It is understandable that as long as the data in the receive buffer is not completely written, the tail frame sequence number will not increase. Detecting an increase in the tail frame sequence number indicates that a new frame of data has been received.

[0054] Furthermore, during this process, the simulated receiving side can also allocate a CPU core for data transmission and reception, enabling both data production and consumption. This ensures that data transmission and reception are not occupied by other computing tasks, thereby improving the real-time performance of data transmission and reception. Furthermore, disabling Hyper-Threading on the simulated receiving side can also improve real-time data transmission and reception, reducing the time jitter caused by Hyper-Threading switching.

[0055] For easier understanding, please refer to Figure 3, which shows an application example of a real-time simulation data transmission system. The real-time simulation node on the left is the simulation transmitter, and the real-time simulation node on the right is the simulation receiver. If the left real-time simulation node needs to send a new frame of data, it increments the end-of-frame sequence number by 1 and then sends a control command to the left FPGA. The control command contains the packet size and the memory address of the data. After receiving the control command, the left FPGA initiates a DMA operation to quickly read the data frame from the real-time simulation node into the FPGA via the PCIe 8x interface. While receiving the data frame from the real-time simulation node, the left FPGA transmits the received data frame to the right FPGA via multiple fiber-optic communications using the Aurora protocol. After receiving the frame, the right FPGA initiates a DMA operation to send the frame data to the right real-time simulation node via the PCIe x8 interface. The right real-time simulation node then checks the end-of-frame sequence number of the received data frame to determine whether it has received a new data frame. The right real-time simulation node has a real-time process that detects the newly received frame of data.

[0056] The real-time simulated data transmission method provided by the embodiment of the present application allows the simulated sending side to determine in real time whether there is a data frame to be sent, place a sequence number at the end of the frame, and increase the sequence number at the end of the frame of the data frame to be sent by 1 before sending the data. The simulated receiving side can directly detect new data by polling whether the sequence number at the end of the frame has increased without interrupting the operation, thereby reducing the time jitter caused by interrupting the switching of CPU processes and improving the real-time performance of data transmission. Therefore, the embodiment of the present application can solve the technical problem that existing data transmission and reception do not take into account microsecond-level real-time performance, have large time jitter, and are difficult to meet the higher transmission requirements of existing data.

[0057] For ease of understanding, please refer to FIG2 . This application provides an embodiment of a real-time simulation data transmission device, including:

[0058] The tail frame processing unit 201 is used to determine whether there is a data frame to be sent on the simulated sending side, and if so, increase the tail frame sequence number of the data frame to be sent in the sending buffer by 1;

[0059] The data sending unit 202 is configured to send the data frame to be sent to the simulated receiving side through the FPGA of the simulated sending side based on DMA operation and optical fiber communication technology to obtain a received data frame;

[0060] The receiving judgment unit 203 is used to judge whether the frame tail sequence number of the received data frame increases by simulating the FPGA of the receiving side. If so, the received data frame is extracted and stored in the receiving buffer.

[0061] Furthermore, it also includes:

[0062] The buffer configuration unit 204 is configured to allocate fixed-size buffers to the simulated sending side and the simulated receiving side to obtain a sending buffer and a receiving buffer.

[0063] Furthermore, the data sending unit 202 is specifically configured to:

[0064] By simulating the FPGA on the sending side, a DMA operation is initiated to read the data frames to be sent in the sending buffer into the FPGA through the pice8x interface;

[0065] The optical fiber communication technology of the multi-channel Aurora protocol is used to send the data frame to be sent in the FPGA to the simulation receiving side to obtain the received data frame.

[0066] Furthermore, it also includes:

[0067] The data reading unit 205 is used to initiate a DMA operation by simulating the FPGA on the receiving side to read the received data frame in the receiving buffer into the FPGA through the pice8x interface.

[0068] The present application also provides a real-time simulation data transmission device, the device including a processor and a memory;

[0069] The memory is used to store program codes and transmit the program codes to the processor;

[0070] The processor is used to execute the real-time simulation data transmission method in the above method embodiment according to the instructions in the program code.

[0071] The present application also provides a computer-readable storage medium, which is used to store program code, and the program code is used to execute the real-time simulation data transmission method in the above method embodiment.

[0072] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0073] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0074] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0075] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for executing all or part of the steps of the method described in each embodiment of the present application through a computer device (which can be a personal computer, server, or network device, etc.). The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (English full name: Read-Only Memory, English abbreviation: ROM), random access memory (English full name: Random Access Memory, English abbreviation: RAM), disk or optical disk and other media that can store program code.

[0076] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A real-time simulation data transmission method, characterized in that: include: Determine whether there is a data frame to be sent on the simulated sending side, and if so, increase the frame tail sequence number of the data frame to be sent in the sending buffer by 1; The FPGA of the simulation sending side sends the data frame to be sent to the simulation receiving side based on DMA operation and optical fiber communication technology to obtain a received data frame; The FPGA on the simulated receiving side determines whether the frame tail sequence number of the received data frame increases. If so, the received data frame is extracted and saved in the receiving buffer.

2. The real-time simulation data transmission method according to claim 1, characterized in that: The step of determining whether there is a data frame to be sent on the simulated sending side, and if so, increasing the frame tail sequence number of the data frame to be sent in the sending buffer by 1, further includes: A fixed-size buffer is allocated to the simulated sending side and the simulated receiving side to obtain a sending buffer and a receiving buffer.

3. The real-time simulation data transmission method according to claim 1, characterized in that: The method of sending the data frame to be sent to the simulation receiving side based on DMA operation and optical fiber communication technology through the FPGA of the simulation sending side to obtain the received data frame includes: Initiate a DMA operation through the FPGA of the simulated sending side to read the data frame to be sent in the sending buffer into the FPGA through the pice8x interface; The optical fiber communication technology of the multi-channel Aurora protocol is used to send the data frame to be sent in the FPGA to the simulation receiving side to obtain a received data frame.

4. The real-time simulation data transmission method according to claim 1, characterized in that: The FPGA of the simulated receiving side is used to determine whether the frame tail sequence number of the received data frame is increased, and if so, the received data frame is extracted and saved in the receiving buffer, and the above also includes: The FPGA at the simulated receiving side initiates a DMA operation to read the received data frame in the receiving buffer into the FPGA through the pice8x interface.

5. A real-time simulation data transmission device, characterized in that: include: The tail frame processing unit is used to determine whether there is a data frame to be sent on the simulated sending side, and if so, increase the frame tail sequence number of the data frame to be sent in the sending buffer by 1; A data transmission unit is used to transmit data through the FPGA of the emulation transmission side based on DMA operation and The optical fiber communication technology sends the data frame to be sent to the simulated receiving side to obtain a received data frame; The receiving judgment unit is used to judge whether the frame tail sequence number of the received data frame is increased through the FPGA of the simulated receiving side, and if so, extract the received data frame in the receiving buffer and save it.

6. The real-time simulation data transmission device according to claim 5, characterized in that: Also includes: The buffer configuration unit is used to allocate a fixed-size buffer to the simulated sending side and the simulated receiving side to obtain a sending buffer and a receiving buffer.

7. The real-time simulation data transmission device according to claim 5, characterized in that: The data sending unit is specifically used for: Initiate a DMA operation through the FPGA of the simulated sending side to read the data frame to be sent in the sending buffer into the FPGA through the pice8x interface; The optical fiber communication technology of the multi-channel Aurora protocol is used to send the data frame to be sent in the FPGA to the simulation receiving side to obtain a received data frame.

8. The real-time simulation data transmission device according to claim 5, characterized in that: Also includes: The data reading unit is used to initiate a DMA operation through the FPGA of the simulated receiving side to read the received data frame in the receiving buffer into the FPGA through the pice8x interface.

9. A real-time simulation data transmission device, characterized in that: The device comprises a processor and a memory; The memory is used to store program code and transmit the program code to the processor; The processor is used to execute the real-time simulation data transmission method according to any one of claims 1 to 4 according to the instructions in the program code.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store program codes, and the program codes are used to execute the real-time simulation data transmission method according to any one of claims 1 to 4.

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