Semiconductor structure and preparation method therefor

Abstract

A semiconductor structure and a preparation method therefor. The semiconductor structure comprises: a substrate; a patterned stack structure located on the substrate and comprising first dielectric layers and first conductive layers that are alternately stacked; and a step structure located on the substrate and comprising a plurality of stacked step layer groups, wherein the plurality of step layer groups form a plurality of steps distributed in a second direction, and each step layer group comprises a second dielectric layer, a second conductive layer and a third dielectric layer; in the same step layer group, the third dielectric layer and the second conductive layer are arranged in the second direction, and the orthographic projections of the two on the substrate overlap with the orthographic projection of the second dielectric layer on the substrate; and the orthographic projections of a plurality of second conductive layers of the plurality of step layer groups on the substrate have the same area.

Description

Semiconductor structure and preparation method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 17, 2023, with application number 202311549929.5 and application name “Semiconductor Structure and Preparation Method Thereof”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the technical field of integrated circuits, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0003] With the development of semiconductor technology, three-dimensional memory devices have emerged. In three-dimensional memory devices, signals of conductive lines (such as bit lines and word lines) of each layer of the memory device are usually led out through a stepped structure.

[0004] However, when a conventional step structure is used to lead out signals, as the number of stacked layers increases, there is a large RC delay problem between the conductive lines (such as bit lines and word lines) of each layer of memory devices.

[0005] Summary of the Invention

[0006] Based on this, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, so as to effectively improve the RC delay problem between conductive lines (such as bit lines and word lines) in each layer.

[0007] A semiconductor structure comprising:

[0008] substrate;

[0009] a graphic stacked structure located on the substrate, comprising a first dielectric layer and a first conductive layer alternately stacked and having overlapping orthographic projections on the substrate, wherein the first conductive layer comprises a wire connection portion and a first conductive line, wherein the first conductive line is connected to the wire connection portion in a first direction;

[0010] A step structure is located on the substrate and on a side of the wire connection portion away from the first conductive wire along the first direction, including a plurality of stacked step layer groups, the plurality of step layer groups forming a plurality of steps distributed along the second direction, and the step layer group includes a second dielectric layer, a second conductive layer, and a third dielectric layer, the second conductive layer is connected to the wire connection portion in the first direction, and within the same step layer group, the third dielectric layer and the second conductive layer are arranged along the second direction, and their orthographic projections on the substrate overlap with the orthographic projection of the second dielectric layer on the substrate, the orthographic projection areas of the plurality of second conductive layers in the plurality of step layer groups on the substrate are the same, and the second direction intersects with the first direction.

[0011] In one embodiment, within the same step layer group, relative to the second conductive layer and the third dielectric layer, the second dielectric layer is farther away from the substrate.

[0012] In one embodiment, the step structure has a first step area, a non-step area and a second step area, the first step area and the second step area are located on both sides of the non-step area in the second direction, the multiple step layer groups constitute the multiple steps in the first step area and the second step area, and within the same step layer group, a second conductive layer is set in the first step area and / or the second step area.

[0013] In one embodiment, within the same stepped layer group, the second conductive layer is located on both sides of the third dielectric layer in the second direction.

[0014] In one embodiment, within the same step layer group, the second conductive layer is located only on one side of the third dielectric layer in the second direction, and along the direction perpendicular to the substrate, the second conductive layers in adjacent step layer groups are located on opposite sides in the second direction.

[0015] In one embodiment, the semiconductor structure further includes a plurality of conductive plugs, each of which penetrates the multiple steps and connects to the corresponding second conductive layer, and the conductive plugs penetrating the odd-numbered steps are located in the first step area, and the conductive plugs penetrating the even-numbered steps are located in the second step area.

[0016] In one embodiment, the plurality of second conductive layers of the plurality of step layer groups are completely staggered in sequence along the second direction.

[0017] In one embodiment, the plurality of second conductive layers of the plurality of step layer groups are partially staggered in sequence along the second direction.

[0018] In one embodiment, the first conductive line is provided with the wire connection portion on both sides in the first direction, and the patterned stacking structure is provided with the step structure on both sides in the first direction.

[0019] A method for preparing a semiconductor structure, comprising:

[0020] providing a substrate;

[0021] forming a patterned stacked structure on the substrate, the patterned stacked structure comprising a first dielectric layer and a first conductive layer alternately stacked and having overlapping orthographic projections on the substrate, the first conductive layer comprising a wire connection portion and a first conductive line, the first conductive line being connected to the wire connection portion in a first direction;

[0022] A step structure is formed on the substrate on a side of the wire connection portion away from the first conductive wire along the first direction, the step structure including a plurality of stacked step layer groups, the plurality of step layer groups constituting a plurality of steps distributed along a second direction, and the step layer group including a second dielectric layer, a second conductive layer, and a third dielectric layer, the second conductive layer connecting the wire connection portion in the first direction, and within the same step layer group, the third dielectric layer and the second conductive layer are arranged along the second direction, and their orthographic projections on the substrate overlap with the orthographic projection of the second dielectric layer on the substrate, the orthographic projection areas of the plurality of second conductive layers in the plurality of step layer groups on the substrate are the same, and the second direction intersects with the first direction.

[0023] In one embodiment, forming a patterned stacked structure on the substrate includes:

[0024] Alternatingly stacking a first dielectric material layer and a sacrificial material layer on the substrate;

[0025] Performing patterning on the first dielectric material layer and the sacrificial material layer, whereby the remaining first dielectric material layer forms the first dielectric layer, and the remaining sacrificial material layer forms a sacrificial layer;

[0026] The sacrificial layer is removed, and the first conductive layer is formed in the removed area of ​​the sacrificial layer.

[0027] In one embodiment, the material of the first dielectric material layer includes silicon oxide, and the material of the sacrificial material layer includes silicon nitride.

[0028] In one embodiment, forming a step structure on the substrate on a side of the wire connecting portion away from the first conductive line along the first direction includes:

[0029] forming a step initial structure on the substrate on a side of the wire connecting portion away from the first conductive wire along the first direction, the step initial structure comprising a plurality of stacked step initial layer groups, the widths of the plurality of step initial layer groups in the second direction decreasing sequentially with stacking height to form a plurality of steps distributed along the second direction, and the step initial layer groups comprising a third dielectric initial layer and a second dielectric layer formed sequentially, wherein within the same step initial layer group, an orthographic projection of the third dielectric initial layer on the substrate overlaps with an orthographic projection of the second dielectric layer on the substrate;

[0030] Laterally etching the third dielectric initial layer to form a hollow region, and the remaining third dielectric initial layer forms the third dielectric layer;

[0031] The second conductive layer is formed in the hollow area.

[0032] In one embodiment, forming a stepped initial structure on the substrate on a side of the wire connecting portion away from the first conductive line along the first direction includes:

[0033] Alternately stacking a second dielectric material layer and a third dielectric material layer on the substrate;

[0034] The second dielectric material layer and the third dielectric material layer are etched to form the stepped initial structure. The third dielectric material layer remaining after etching forms the third dielectric initial layer, and the second dielectric material layer remaining after etching forms the second dielectric layer.

[0035] In one embodiment, the material of the second dielectric material layer includes silicon oxide, and the material of the third dielectric material layer includes silicon nitride.

[0036] In one embodiment, after forming the step structure on the substrate on the side of the wire connecting portion away from the first conductive line along the first direction, the method further includes:

[0037] forming a plurality of contact holes respectively penetrating the plurality of steps;

[0038] A conductive plug is formed in the contact hole, and the conductive plug on each step is connected to the second conductive layer corresponding to the step.

[0039] In one embodiment, the step structure has a first step area, a non-step area and a second step area, the first step area and the second step area are located on both sides of the non-step area in the second direction, the multiple step layer groups constitute the multiple steps in the first step area and the second step area, and within the same step layer group, a second conductive layer is set in the first step area and / or the second step area.

[0040] In one embodiment, the conductive plugs respectively penetrate the multiple steps and connect to the corresponding second conductive layer, and the conductive plugs penetrating the odd-numbered steps are located in the first step area, and the conductive plugs penetrating the even-numbered steps are located in the second step area.

[0041] In one embodiment, the plurality of second conductive layers of the plurality of step layer groups are completely staggered in sequence along the second direction.

[0042] In one embodiment, the plurality of second conductive layers of the plurality of step layer groups are partially staggered in sequence along the second direction.

[0043] In one embodiment, the first conductive line is provided with the wire connection portion on both sides in the first direction, and the patterned stacking structure is provided with the step structure on both sides in the first direction.

[0044] In the aforementioned semiconductor structure and fabrication method, the first conductive lines of each layer of the memory device are connected to a second conductive layer of the same area via corresponding wire connections, thereby routing signals through the second conductive layer of the same area. This effectively reduces RC delay between the first conductive lines of each layer. Furthermore, the multiple steps are distributed along the second direction, effectively saving area in the step structure and thereby improving storage density. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] FIG1 is a schematic diagram of a three-dimensional structure of a semiconductor structure provided in one embodiment;

[0047] FIG2( a ) is a schematic top view of the related structures of the first conductive layer and the second conductive layer provided in one embodiment;

[0048] FIG2( b ) is a schematic top view of the structure of a first dielectric layer provided in one embodiment;

[0049] FIG3 is a schematic diagram of a three-dimensional structure of a semiconductor structure provided in another embodiment;

[0050] FIG4 is a flow chart of a method for preparing a semiconductor structure provided in one embodiment;

[0051] 5 is a schematic diagram of a three-dimensional structure of a structure obtained by alternately stacking first dielectric material layers and sacrificial material layers in a method for preparing a semiconductor structure provided in one embodiment;

[0052] FIG6( a ) is a schematic top view of the structure of a first dielectric layer obtained after patterning the first dielectric material layer and the sacrificial material layer in a method for preparing a semiconductor structure provided in one embodiment;

[0053] FIG6( b ) is a schematic top view of the structure of a sacrificial layer obtained after patterning the first dielectric material layer and the sacrificial material layer in a method for preparing a semiconductor structure provided in one embodiment;

[0054] FIG7 is a schematic diagram of the three-dimensional structure of the B area in FIG6(a) and FIG6(b);

[0055] FIG8 is a schematic diagram of the three-dimensional structure of the structure obtained after removing the sacrificial layer in FIG7;

[0056] FIG9 is a schematic diagram of the three-dimensional structure of the structure obtained after forming the first conductive layer in FIG8;

[0057] FIG10 is a schematic diagram of a partial three-dimensional structure after forming a stepped initial structure in a method for preparing a semiconductor structure provided in one embodiment;

[0058] FIG11 is a schematic diagram of a partial three-dimensional structure after a hollow region is formed in a method for preparing a semiconductor structure provided in one embodiment;

[0059] FIG12 is a schematic diagram of a partial three-dimensional structure after forming a second conductive layer in a method for preparing a semiconductor structure provided in one embodiment;

[0060] 13 is a schematic top view of the related structures of the first conductive layer and the second conductive layer after forming contact holes in a method for preparing a semiconductor structure provided in one embodiment;

[0061] FIG14 is a schematic diagram of a partial three-dimensional structure after a conductive plug is formed in a method for preparing a semiconductor structure provided in one embodiment;

[0062] FIG15 is a schematic diagram of a three-dimensional structure of a semiconductor structure provided in yet another embodiment.

[0063] Explanation of the accompanying drawings: 100-substrate; 200-patterned stacking structure; 210-first dielectric layer; 2101-first dielectric material layer; 220-first conductive layer; 221-wire connection portion; 222-first conductive line; 230-sacrificial layer; 2301-sacrificial material layer; 300-step structure; 3001-step initial structure; 310-step layer group; 3101-step initial layer group; 311-second dielectric layer; 312-second conductive layer; 313-third dielectric layer; 3131-third dielectric initial layer; 400-conductive plug; 500-storage array; 10-contact hole; 20-conductive line hole. DETAILED DESCRIPTION

[0064] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0066] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0067] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0068] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0069] As mentioned in the background technology, when using a traditional step structure to lead out signals, as the number of stacked layers increases, there is a large RC delay problem between the conductive lines (such as bit lines and word lines) of each layer of memory devices.

[0070] Based on this, embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the semiconductor structure. The semiconductor structure can be, but is not limited to, fabricated using the semiconductor structure fabrication methods described in the following embodiments. Furthermore, the semiconductor structure and method for fabricating the semiconductor structure provided by embodiments of the present disclosure can be, but are not limited to, applied to the fabrication of three-dimensional dynamic random access memory (DRAM) devices.

[0071] In one embodiment, referring to FIG1 , a semiconductor structure is provided, which includes a substrate 100 , a patterned stacked structure 200 , and a stepped structure 300 . The patterned stacked structure 200 and the stepped structure 300 are located in different regions on the substrate 100 .

[0072] It should be noted that, in FIG1 , for clarity of the drawing, the substrate 100 below the step structure 300 is not shown, but in fact the step structure 300 is also formed on the substrate 100 .

[0073] The base 100 may include a substrate. The substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate may also include a Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator substrate. Therefore, the type of substrate should not limit the scope of protection of the present disclosure.

[0074] As an example, the substrate 100 may further include a peripheral circuit structure (not shown), which may be formed based on a semiconductor substrate. Of course, the peripheral circuit structure is located on a side of the stepped structure 300 away from the substrate 100, which is not limited here.

[0075] The patterned stacked structure 200 includes alternating first dielectric layers 210 and first conductive layers 220. The bottom layer of the patterned stacked structure can be either the first dielectric layer 210 or the first conductive layer 220. The top layer of the patterned stacked structure can be either the first dielectric layer 210 or the first conductive layer 220.

[0076] Referring to FIG. 2( a ), the first conductive layer 220 includes a wire connecting portion 221 and a first conductive line 222 . The first conductive line 222 is connected to the wire connecting portion 221 in a first direction.

[0077] The material of the first conductive layer 220 may include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).

[0078] As an example, the first conductive line 222 may be a bit line or a word line of a memory cell. The first conductive layer 220 may include multiple first conductive lines 222. The multiple first conductive lines 222 may be arranged along a second direction. The second direction intersects the first direction. For example, the second direction may be perpendicular to the first direction. Furthermore, multiple first conductive lines 222 may be connected to the same wire connection portion 221 on the same side in the first direction.

[0079] Referring to FIG. 2( b ), the first dielectric layer 210 and the first conductive layer 220 are alternately stacked and have the same shape, and their orthographic projections on the substrate 100 overlap.

[0080] It is understood that the term "orthographic projection overlap" herein refers to the fact that the orthographic projections have consistent outlines and overlap with each other. Furthermore, "orthographic projection overlap" is a broad term that allows for certain process errors in actual production processes.

[0081] The material of the first dielectric layer 210 includes but is not limited to silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ) or silicon oxynitride (SiON).

[0082] Furthermore, the opening region of the patterned stacked structure 200 may be filled with a fourth dielectric layer (not shown), and a memory cell (e.g., a transistor, a capacitor, etc.) located within the fourth dielectric layer may be provided in the opening region. The memory cell may be connected to the first conductive line 222. Furthermore, a plurality of memory cells may be arranged in an array to form a memory array 500, as shown in FIG2(a). For clarity of the drawings, FIG2(a) illustrates the memory array 500 in block diagram form.

[0083] 1 and 2( a ), the step structure 300 is located on a side of the wire connecting portion 221 away from the first conductive line 222 along the first direction. That is, the step structure 300 and the first conductive line 222 are respectively disposed on two opposite sides of the wire connecting portion 221 in the first direction.

[0084] 1 , the step structure 300 includes a plurality of stacked step layer groups 310. The stacked step layer groups 310 form a plurality of steps distributed along the second direction.

[0085] Each stepped layer group 310 includes a second dielectric layer 311 , a second conductive layer 312 and a third dielectric layer 313 .

[0086] In the same stepped layer group 310 , the third dielectric layer 313 and the second conductive layer 312 are arranged along the second direction, and thus are located at the same film layer position.

[0087] As an example, within the same stepped layer group 310, the second dielectric layer 311 can be located farther away from the substrate 100 than the second conductive layer 312 and the third dielectric layer 313. In this case, the third dielectric layer 313 and the second conductive layer 312 can both be located at the bottom layer of the stepped layer group 310, and the second dielectric layer 311 can be located at the top layer of the stepped layer group 310.

[0088] Alternatively, within the same stepped layer group 310, the second dielectric layer 311 may be closer to the substrate 100 than the second conductive layer 312 and the third dielectric layer 313. In this case, the third dielectric layer 313 and the second conductive layer 312 may both be located at the upper layer of the stepped layer group 310, and the second dielectric layer 311 may be located at the lower layer of the stepped layer group 310.

[0089] At the same time, within the same stepped layer group 310 , the orthographic projections of the third dielectric layer 313 and the second conductive layer 312 on the substrate 100 overlap with the orthographic projection of the second dielectric layer 311 on the substrate 100 .

[0090] 1 and 2(a), the second conductive layer 312 is connected to the wire connection portion 221 in the first direction, and is further electrically connected to the first conductive line 222 through the wire connection portion 221. The projections of the multiple second conductive layers 312 of the multiple stepped layer groups 310 on the substrate 100 can be at least partially staggered along the second direction, thereby facilitating the extraction of signals from the first conductive line 222 through each layer of the second conductive layer 312 and effectively reducing parasitic capacitance between the layers of the second conductive layer 312.

[0091] As an example, the projections of the multiple second conductive layers 312 of the multiple stepped layer groups 310 on the substrate 100 can be staggered along the second direction and completely staggered in sequence. Alternatively, the projections of the multiple second conductive layers 312 of the multiple stepped layer groups 310 on the substrate 100 can also be staggered along the second direction and partially staggered in sequence.

[0092] The material of the second conductive layer 312 may include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al). The material of the second conductive layer 312 may be the same as or different from the material of the first conductive layer 220, which is not limited herein.

[0093] At the same time, in the first direction, the third dielectric layer 313 can also be connected to the wire connection portion 221, and the second dielectric layer 311 can be connected to the first dielectric layer 210. Moreover, the thickness of the third dielectric layer 313 and the second conductive layer 312 can be the same as the thickness of the first conductive layer 220, and the thickness of the second dielectric layer 311 can be the same as the thickness of the first dielectric layer 210.

[0094] The material of the third dielectric layer 313 and / or the second dielectric layer 311 may include, but is not limited to, a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), an aluminum oxide (Al2O3), or a silicon oxynitride layer (SiON). As an example, the material of the second dielectric layer 311 may be the same as that of the first dielectric layer 210, and different from that of the third dielectric layer 313. For example, the material of the second dielectric layer 311 and the material of the first dielectric layer 210 may be silicon oxide, and the material of the third dielectric layer 313 may be silicon nitride.

[0095] At the same time, the orthographic projection areas of the plurality of second conductive layers 312 of the plurality of stepped layer groups 310 on the substrate 100 are the same, that is, the area of ​​each second conductive layer 312 is the same.

[0096] In this embodiment, a plurality of step layer groups 310 are provided to form a plurality of steps distributed along the second direction. The distribution direction of the steps is provided in another direction intersecting with the first direction, rather than in the first direction (the connection direction between the second conductive layer 312 and the first conductive layer 220). Therefore, the length of the second conductive layer 312 in the first direction does not need to increase with the increase in the number of stacked layers. At the same time, in each step layer group 310, a third dielectric layer 313 is provided at the same film layer position as the second conductive layer 312, and the third dielectric layer 313 and the second conductive layer 312 are arranged along the second direction. Therefore, the length of the second conductive layer 312 in the second direction does not need to increase with the increase in the number of stacked layers, so that the area of ​​each second conductive layer 312 can be set to be the same. At the same time, the second conductive layer 312 is provided to connect the wire connection portion 221 in the first direction. At this time, the first conductive line 222 can be effectively electrically connected to the second conductive layer 312 through the wire connection portion 221.

[0097] At this time, the first conductive lines 222 of each layer of storage devices are connected to the second conductive layer 312 of the same area through the corresponding wire connection part 221, so that the signal is led out through the second conductive layer 312 of the same area, thereby effectively reducing the RC delay between the first conductive lines 222 of each layer.

[0098] Furthermore, in this embodiment, the multiple steps are distributed along the second direction, thereby effectively saving the area of ​​the step structure 300 and further facilitating improvement of storage density.

[0099] In one embodiment, referring to FIG1 , the stepped structure 300 includes a first stepped region A1, a non-stepped region A2, and a second stepped region A3. The first stepped region A1, the non-stepped region A2, and the second stepped region A3 may be arranged sequentially along the second direction. That is, the first stepped region A1 and the second stepped region A3 are located on both sides of the non-stepped region A2 in the second direction.

[0100] The plurality of stepped layer groups 310 form multiple steps in both the first step region A1 and the second step region A3. In the same stepped layer group 310, a second conductive layer 312 may be provided in the first step region A1 and / or the second step region A3.

[0101] At this time, the first conductive lines 222 (bit lines or word lines) of different layers can lead out signals through the second conductive layer 312 located in the first step area A1 and the second step area A3 respectively, thereby reducing signal interference between the first conductive lines 222 of different layers.

[0102] In one embodiment, referring to FIG. 1 , when the plurality of step layer groups 310 form multiple steps in both the first step area A1 and the second step area A3 , within the same step layer group 310 , the second conductive layer 312 is located on both sides of the third dielectric layer 313 along the second direction.

[0103] For each stepped layer group 310, second conductive layers 312 can be symmetrically disposed on both sides of the third dielectric layer 313 along the second direction. Within each stepped layer group 310, the second conductive layers 312 located on both sides of the third dielectric layer 313 along the second direction can be located at the step positions of the first step region A1 and the second step region A3, respectively. This facilitates the processing and preparation of the stepped layer group 310.

[0104] Of course, in other embodiments, the arrangement of the second conductive layer 312 and the third dielectric layer 313 within the step layer group 310 is not limited to this. For example, referring to FIG15 , within the same step layer group 310, the second conductive layer 312 is located only on one side of the third dielectric layer 313 in the second direction. In a direction perpendicular to the substrate 100, the second conductive layers 312 within adjacent step layer groups 310 are located on opposite sides in the second direction. In this case, within adjacent step layer groups 310 in the direction perpendicular to the substrate 100, the second conductive layer 312 can be disposed in the first step region A1 and the second step region A3, respectively.

[0105] In one embodiment, referring to FIG3 , the semiconductor structure further includes a plurality of conductive plugs 400 , each of which extends through the plurality of steps and connects to the corresponding second conductive layer 312 . Furthermore, the conductive plugs 400 can extend into a peripheral circuit structure within the substrate 100 , thereby electrically connecting the conductive plugs 400 to the peripheral circuit structure. It should be noted that in FIG3 , the substrate 100 below the stepped structure 300 is shifted downward for clarity. However, in the actual structure, the substrate 100 below the stepped structure 300 is the same substrate as the substrate 100 below the patterned stacked structure 200 .

[0106] Of course, a peripheral circuit structure may also be provided on top of the conductive plug 400 , so that the conductive plug 400 is electrically connected to the peripheral circuit structure.

[0107] When multiple conductive plugs 400 penetrate multiple steps and connect to the corresponding second conductive layer 312, the conductive plug 400 can penetrate the second conductive layer 312 at each step and connect thereto. Of course, the connection between the conductive plug 400 and the second conductive layer 312 is not limited to this. For example, in some embodiments, the second conductive layer 312 can be provided with a third dielectric layer 313 (not shown) on both sides along the second direction. In this case, the conductive plug 400 can also penetrate the third dielectric layer 313 and connect to the second conductive layer 312 in the second direction. Alternatively, the conductive plug 400 can penetrate both the third dielectric layer 313 and the second conductive layer 312.

[0108] Meanwhile, multiple step layer groups 310 are provided to form multiple steps in both the first step area A1 and the second step area A3. The conductive plugs 400 passing through the odd-numbered steps are located in the first step area A1, and the conductive plugs 400 passing through the even-numbered steps are located in the second step area A3.

[0109] At this time, the conductive plugs 400 that lead out the signals of the first conductive lines 222 (bit lines or word lines) of different layers can be respectively set in the first step area A1 and the second step area A3, thereby reducing the arrangement density of the conductive plugs 400 and effectively preventing the risk of short circuit between the conductive plugs 400.

[0110] In one embodiment, referring to FIG. 1 and FIG. 2( a ), wire connection portions 221 are provided on both sides of the first conductive line 222 in the first direction, and step structures 300 are provided on both sides of the patterned stack structure 200 in the first direction.

[0111] At this time, as an example, referring to FIG. 2( a ), the semiconductor structure may include two wire connection portions 221 extending along the second direction, and the two wire connection portions 221 are disposed opposite to each other in the first direction.

[0112] A plurality of first conductive lines 222 (eg, bit lines or word lines) arranged along the second direction are disposed between the two conductive line connecting portions 221. Each first conductive line 222 is configured to connect to two conductive line connecting portions 221 on both sides thereof in the first direction.

[0113] At this time, different layers of first conductive lines 222 (bit lines or word lines) can be connected to different second conductive layers 312 in the stepped structures 300 through different wire connections 221 to lead out signals, thereby reducing signal interference between different layers of first conductive lines 222. At the same time, the conductive plugs 400 provided on the second conductive layer 312 can be distributed on the stepped structures 300 on both sides of the patterned stacked structure 200 in the first direction, thereby reducing the arrangement density of the conductive plugs 400 and effectively preventing the risk of short circuits between the conductive plugs 400.

[0114] In one embodiment, referring to FIG. 4 , a method for preparing a semiconductor structure is also provided, comprising the following steps:

[0115] Step S10, providing a substrate 100;

[0116] Step S20, forming a patterned stacked structure 200 on the substrate 100, wherein the patterned stacked structure 200 includes a first dielectric layer 210 and a first conductive layer 220 that are alternately stacked and overlap with each other in their orthographic projections on the substrate 100, the first conductive layer 220 including a wire connection portion 221 and a first conductive line 222, the first conductive line 222 being connected to the wire connection portion 221 in a first direction;

[0117] In step S30, a step structure 300 is formed on the substrate 100 on a side of the wire connection portion 221 away from the first conductive wire 222 along the first direction. The step structure 300 includes a plurality of stacked step layer groups 310. The plurality of step layer groups 310 constitute a plurality of steps distributed along the second direction. The step layer group 310 includes a second dielectric layer 311, a second conductive layer 312, and a third dielectric layer 313. The second conductive layer 312 is connected to the wire connection portion 221 in the first direction. Within the same step layer group 310, the third dielectric layer 313 and the second conductive layer 312 are arranged along the second direction, and their orthographic projections on the substrate 100 overlap with the orthographic projection of the second dielectric layer 311 on the substrate 100. The orthographic projections of the plurality of second conductive layers 312 in the plurality of step layer groups 310 on the substrate 100 have the same area, and the second direction intersects with the first direction.

[0118] In step S10, the base 100 may include a substrate. The substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate may also include a Si / SiGe, Si / SiC, a silicon-on-insulator (SOI) substrate, or a silicon germanium-on-insulator substrate. Therefore, the type of substrate should not limit the scope of protection of the present disclosure.

[0119] As an example, the substrate 100 may further include a peripheral circuit structure, which may be formed based on a semiconductor substrate. Of course, the peripheral circuit structure may also be formed after the stepped structure 300 is formed, which is not limited here.

[0120] In step S20, referring to Figures 5 and 9 , a patterned stacked structure 200 may be formed in the first area A4 on the substrate 100 through a patterning process. The patterned stacked structure 200 includes a first dielectric layer 210 and a first conductive layer 220. The bottom layer of the patterned stacked structure may be either the first dielectric layer 210 or the first conductive layer 220. The top layer of the patterned stacked structure may be either the first dielectric layer 210 or the first conductive layer 220.

[0121] The first dielectric layer 210 and the first conductive layer 220 are alternately stacked and have the same shape, and their orthographic projections on the substrate 100 overlap.

[0122] It is understood that the term "orthographic projection overlap" herein refers to the fact that the orthographic projections have consistent outlines and overlap with each other. Furthermore, "orthographic projection overlap" is a broad term that allows for certain process errors in actual production processes.

[0123] The material of the first conductive layer 220 may include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).

[0124] The first conductive layer 220 includes a wire connecting portion 221 and a first conductive line 222 . The first conductive line 222 is connected to the wire connecting portion 221 in a first direction.

[0125] As an example, the first conductive line 222 may be a bit line or a word line of a memory cell. The first conductive layer 220 may include multiple first conductive lines 222. The multiple first conductive lines 222 may be arranged along a second direction. The second direction intersects the first direction. For example, the second direction may be perpendicular to the first direction. Furthermore, multiple first conductive lines 222 may be connected to the same wire connection portion 221 on the same side in the first direction.

[0126] The material of the first dielectric layer 210 includes but is not limited to silicon oxide layer (SiO2), silicon nitride layer (Si3N4), aluminum oxide (A l2 O3) or silicon oxynitride layer (SiON).

[0127] In step S30, referring to Figures 5 and 12, a stepped structure 300 may be formed in a second region A5 on the substrate 100. The second region A5 is connected to the first region A4 in the first direction. As an example, the second region A5 is located at an edge of the substrate 100 in the first direction.

[0128] Before forming the stepped structure 300, the opening area of ​​the patterned stacked structure 200 in the first area A4 may be filled with a fourth dielectric layer to level the first area A4. The material of the fourth dielectric layer may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), or silicon oxynitride (SiON).

[0129] The fourth dielectric layer may be a single-layer structure or a multi-layer structure.

[0130] As an example, before forming the stepped structure 300, in addition to filling the opening region of the patterned stacked structure 200 with a fourth dielectric layer, a memory cell (e.g., including a transistor, a capacitor, etc.) can be formed within the fourth dielectric layer in the opening region. The memory cells can be arranged in an array to form a memory array.

[0131] After filling the fourth dielectric layer, the step structure 300 is formed, so that the formation of the step structure 300 does not affect the structure in the first area A4.

[0132] After the step structure 300 is formed, a plurality of stacked step layer groups 310 are formed. At the same time, the stacked plurality of step layer groups 310 form a plurality of steps distributed along the second direction.

[0133] Each stepped layer group 310 includes a second dielectric layer 311 , a second conductive layer 312 and a third dielectric layer 313 .

[0134] In the same stepped layer group 310 , the third dielectric layer 313 and the second conductive layer 312 are arranged along the second direction, and thus are located at the same film layer position.

[0135] As an example, within the same stepped layer group 310, the second dielectric layer 311 can be located farther away from the substrate 100 than the second conductive layer 312 and the third dielectric layer 313. In this case, the third dielectric layer 313 and the second conductive layer 312 can both be located at the bottom layer of the stepped layer group 310, and the second dielectric layer 311 can be located at the top layer of the stepped layer group 310.

[0136] Alternatively, within the same stepped layer group 310, the second dielectric layer 311 may be closer to the substrate 100 than the second conductive layer 312 and the third dielectric layer 313. In this case, the third dielectric layer 313 and the second conductive layer 312 may both be located at the upper layer of the stepped layer group 310, and the second dielectric layer 311 may be located at the lower layer of the stepped layer group 310.

[0137] At the same time, within the same stepped layer group 310 , the orthographic projections of the third dielectric layer 313 and the second conductive layer 312 on the substrate 100 overlap with the orthographic projection of the second dielectric layer 311 on the substrate 100 .

[0138] The second conductive layer 312 is connected to the wire connection portion 221 in the first direction, and is further electrically connected to the first conductive line 222 through the wire connection portion 221. The projections of the multiple second conductive layers 312 of the multiple stepped layer groups 310 on the substrate 100 can be at least partially staggered along the second direction, thereby facilitating the extraction of signals from the first conductive line 222 through each layer of the second conductive layer 312 and effectively reducing parasitic capacitance between each layer of the second conductive layer 312.

[0139] As an example, the projections of the multiple second conductive layers 312 of the multiple stepped layer groups 310 on the substrate 100 can be staggered along the second direction and completely staggered in sequence. Alternatively, the projections of the multiple second conductive layers 312 of the multiple stepped layer groups 310 on the substrate 100 can also be staggered along the second direction and partially staggered in sequence.

[0140] The material of the second conductive layer 312 may include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al). The material of the second conductive layer 312 may be the same as or different from the material of the first conductive layer 220, which is not limited herein.

[0141] At the same time, in the first direction, the third dielectric layer 313 can also be connected to the wire connection portion 221, and the second dielectric layer 311 can be connected to the first dielectric layer 210. Moreover, the thickness of the third dielectric layer 313 and the second conductive layer 312 can be the same as the thickness of the first conductive layer 220, and the thickness of the second dielectric layer 311 can be the same as the thickness of the first dielectric layer 210.

[0142] The material of the third dielectric layer 313 and / or the second dielectric layer 311 may include, but is not limited to, a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), an aluminum oxide (Al2O3), or a silicon oxynitride layer (SiON). As an example, the material of the second dielectric layer 311 may be the same as that of the first dielectric layer 210, and different from that of the third dielectric layer 313. For example, the material of the second dielectric layer 311 and the material of the first dielectric layer 210 may be silicon oxide, and the material of the third dielectric layer 313 may be silicon nitride.

[0143] At the same time, the orthographic projection areas of the plurality of second conductive layers 312 of the plurality of stepped layer groups 310 on the substrate 100 are the same, that is, the area of ​​each second conductive layer 312 is the same.

[0144] In this embodiment, the first conductive lines 222 of each layer of storage devices are connected to the second conductive layer 312 of the same area through corresponding wire connections 221, thereby leading the signal out through the second conductive layer 312 of the same area. This effectively reduces the RC delay between the first conductive lines 222 of each layer. Furthermore, the multiple steps are distributed along the second direction, which effectively saves the area of ​​the step structure 300, thereby facilitating an increase in storage density.

[0145] In one embodiment, step S20 includes:

[0146] Step S21 , alternately stacking first dielectric material layers 2101 and sacrificial material layers 2301 on the substrate 100 , see FIG. 5 ;

[0147] Step S22 , patterning the first dielectric material layer 2101 and the sacrificial material layer 2301 , whereby the remaining first dielectric material layer 2101 forms the first dielectric layer 210 , as shown in FIG. 6( a ), and the remaining sacrificial material layer 2301 forms the sacrificial layer 230 , as shown in FIG. 6( b );

[0148] In step S23 , the sacrificial layer 230 is removed, and the first conductive layer 220 is formed in the removed region of the sacrificial layer 230 , as shown in FIG. 7 to FIG. 9 .

[0149] 5 , a first dielectric material layer 2101 and a sacrificial material layer 2301 may be deposited on the substrate 100. For example, the first dielectric material layer 2101 may include silicon oxide, and the sacrificial material layer 2301 may include silicon nitride.

[0150] The deposition process may include, but is not limited to, one or more of a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition (HDP), a plasma enhanced deposition process, and a spin-on dielectric layer (SOD).

[0151] As an example, a first dielectric material layer 2101 can be first formed on the surface of the substrate 100, followed by a sacrificial material layer 2301. The first dielectric material layer 2101 and the sacrificial material layer 2301 can then be alternately formed repeatedly. In this case, after the first conductive layer 220 is formed in step S23, the first conductive layer 220 can be effectively isolated from the substrate 100 by the first dielectric layer 210. Of course, in other examples, the sacrificial material layer 2301 can also be first formed on the surface of the substrate 100. This is not a limitation herein.

[0152] As an example, after the first dielectric material layer 2101 and the sacrificial material layer 2301 are alternately stacked on the substrate 100, the top layer of the stacked layer may be the first dielectric material layer 2101. In this case, after the sacrificial layer 230 is removed in the subsequent step S23, the top layer, the first dielectric layer 210, can be effectively retained. Of course, in other examples, after the first dielectric material layer 2101 and the sacrificial material layer 2301 are alternately stacked on the substrate 100, the top layer of the stacked layer may also be the sacrificial material layer 2301. This is not a limitation herein.

[0153] In step S22, a patterned photoresist may be formed on the alternating first dielectric material layers 2101 and sacrificial material layers 2301. The alternating first dielectric material layers 2101 and sacrificial material layers 2301 are then dry-etched based on the patterned photoresist to form the first dielectric layer 210 and the sacrificial layer 230 (see FIG6( a ) and FIG6( b )). The patterned photoresist may then be removed.

[0154] In step S23 , the sacrificial layer 230 may be dry-etched from the region where the first dielectric material layer 2101 and the sacrificial material layer 2301 are etched away, thereby removing the sacrificial layer 230 , as shown in FIG. 7 and FIG. 8 .

[0155] Then, the first conductive layer 220 may be formed in the removed area of ​​the sacrificial layer 230 by electroplating or chemical vapor deposition, as shown in FIG. 9 .

[0156] In this embodiment, by first alternately stacking the first dielectric material layer 2101 and the sacrificial material layer 2301, good etching and patterning are facilitated during the formation of the patterned stacked structure 200. Of course, in other embodiments, during the formation of the patterned stacked structure 200, the first dielectric material layer 2101 and the first conductive material layer may be directly alternately stacked and then patterned to form the first dielectric layer 210 and the first conductive layer 220.

[0157] In one embodiment, step S30 includes:

[0158] Step S31, referring to FIG. 10 , forms a stepped initial structure 3001 on the substrate 100 on a side of the wire connecting portion 221 away from the first conductive wire 222 along the first direction. The stepped initial structure 3001 includes a plurality of stacked stepped initial layer groups 3101. The widths of the plurality of stepped initial layer groups 3101 in the second direction decrease sequentially with the stacking height, forming a plurality of steps distributed along the second direction. The stepped initial layer groups 3101 include a third dielectric initial layer 3131 and a second dielectric layer 311 formed sequentially. Within the same stepped initial layer group 3101, the orthographic projection of the third dielectric initial layer 3131 on the substrate 100 overlaps with the orthographic projection of the second dielectric layer 311 on the substrate 100.

[0159] Step S32, referring to FIG. 11 , the third dielectric initial layer 3131 is laterally etched to form a hollow region, and the remaining third dielectric initial layer 3131 forms the third dielectric layer 313;

[0160] In step S33 , referring to FIG. 12 , a second conductive layer 312 is formed in the hollow region.

[0161] In step S31, referring to Figure 10, the third dielectric initial layer 3131 can be disposed opposite to the first conductive layer 220, and the thickness of the first dielectric layer 3131 and the second dielectric layer 311 can be disposed opposite to the first dielectric layer 21 ...

[0162] As an example, step S31 may include:

[0163] Step S311 , alternately stacking a second dielectric material layer and a third dielectric material layer on the substrate 100 ;

[0164] In step S312 , the second dielectric material layer and the third dielectric material layer are etched to form a stepped initial structure 3001 . The remaining third dielectric material layer after etching forms a third dielectric initial layer 3131 , and the remaining second dielectric material layer after etching forms a second dielectric layer 311 .

[0165] In step S311 , a second dielectric material layer and a third dielectric material layer may be alternately stacked sequentially on the substrate 100 through a deposition process.

[0166] As an example, the material of the second dielectric material layer includes silicon oxide, and the material of the third dielectric material layer includes silicon nitride.

[0167] In step S312 , the second dielectric material layer and the third dielectric material layer may be etched using a method such as cyclic shrink photoresist, thereby forming a stepped initial structure 3001 .

[0168] As an example, the stepped initial structure 3001 may include two groups of multi-step steps symmetrically arranged in the second direction.

[0169] In step S32 , referring to FIG. 10 and FIG. 11 , the third dielectric initial layer 3131 may be wet-etched, thereby laterally etching the third dielectric initial layer 3131 to form a hollow region.

[0170] When the stepped initial structure 3001 may include two groups of multi-steps symmetrically arranged in the second direction, both sides of the third dielectric initial layer 3131 in the second direction may be laterally etched to form symmetrical hollow regions.

[0171] In step S33 , referring to FIG. 12 , a second conductive layer 312 may be formed in the hollow region by electroplating or chemical vapor deposition.

[0172] When a symmetrical hollow region is formed, symmetrical second conductive layers 312 may be formed on both sides of the third dielectric layer 313 along the second direction.

[0173] In this embodiment, a hollow region is formed by lateral etching, and then a second conductive layer 312 is formed within the hollow region. Currently, lateral etching technology is mature and controllable, effectively ensuring that the orthographic projection areas of the different second conductive layers 312 in different step layer groups 310 on the substrate 100 are the same, thereby effectively reducing RC delay. Furthermore, the steps of the semiconductor structure can be fabricated monolithically, reducing wafer processing costs.

[0174] In one embodiment, after step S30, the method further includes:

[0175] Step S40, forming a plurality of contact holes 10 respectively penetrating the plurality of steps, see FIG. 13;

[0176] In step S50 , a conductive plug 400 is formed in the contact hole 10 . The conductive plug 400 on each step is connected to the second conductive layer 312 corresponding to the step, as shown in FIG. 14 .

[0177] In step S40, multiple contact holes 10 may penetrate the second conductive layer 312 corresponding to each step. The second conductive layer 312 may be completely staggered to facilitate forming mutually spaced contact holes 10. Of course, the second conductive layer 312 may also be partially staggered.

[0178] In step S50 , a plug material layer may be first deposited and then subjected to a chemical mechanical polishing (CMP) process to form the conductive plug 400 .

[0179] The conductive plug 400 may extend into the peripheral circuit structure within the substrate 100, thereby electrically connecting the conductive plug 400 to the peripheral circuit structure. Alternatively, after forming the conductive plug 400, a peripheral circuit structure may be formed on top of the conductive plug 400, thereby electrically connecting the conductive plug 400 to the peripheral circuit structure.

[0180] The material of the conductive plug 400 may include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al). The material of the conductive plug 400 may be the same as or different from the material of the second conductive layer 312.

[0181] As an example, when symmetrical second conductive layers 312 are formed on both sides of the third dielectric layer 313 along the second direction, the stepped structure 300 may include two sets of multi-step steps symmetrically arranged in the second direction. It is assumed that one set of multi-step steps is located in the first step area A1, and the other set of multi-step steps is located in the second step area A3, with the area between the two being the non-step area A2.

[0182] In this case, the contact holes 10 that pass through the odd-numbered steps can be located in the first step area A1, and the contact holes 10 that pass through the even-numbered steps can be located in the second step area A3. In this case, the density of the contact holes 10 can be effectively reduced, thereby reducing the density of the conductive plugs 400 formed subsequently, thereby preventing short circuits between the conductive plugs 400.

[0183] As an example, the second area A5 where the stepped structure 300 is formed may be located on both sides of the first area A4 where the patterned stacked structure 200 is formed, so that the stepped structures 300 are located on both sides of the patterned stacked structure 200 along the first direction.

[0184] At this time, the first conductive line 222 formed in the first area A4 can be led out from the second conductive layer 312 located on both sides thereof in the first direction, thereby improving the setting flexibility of the contact hole 10 and the conductive plug 400 on the second conductive layer 312 and reducing their setting density.

[0185] At the same time, as an example, while forming a plurality of contact holes 10 that penetrate the multiple steps, step S40 may also form a conductive line hole 20 that penetrates the patterned stacked structure 200. Step S50 simultaneously forms a conductive plug 400 within the contact hole 10 and forms a second conductive line (not shown) within the conductive line hole 20. One of the second conductive line and the first conductive line 222 is a bit line, and the other is a word line.

[0186] It should be understood that, although the various steps in the flowchart of FIG4 are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in FIG4 may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0187] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0188] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A semiconductor structure comprising: Base (100); A patterned stacked structure (200) is located on the substrate (100), comprising a first dielectric layer (210) and a first conductive layer (220) which are alternately stacked and overlap in orthographic projection on the substrate (100); the first conductive layer (220) comprises a wire connecting portion (221) and a first conductive line (222); the first conductive line (222) is connected to the wire connecting portion (221) in a first direction; The step structure (300) is located on the substrate (100) and on a side of the wire connection portion (221) away from the first conductive wire (222) along the first direction, and comprises a plurality of step layer groups (310) stacked and arranged, wherein the plurality of step layer groups (310) constitute a plurality of steps distributed along a second direction, and the step layer group (310) comprises a second dielectric layer (311), a second conductive layer (312) and a third dielectric layer (313), wherein the second conductive layer (312) is connected to the wire connection portion (221) in the first direction, and within the same step layer group (310), the third dielectric layer (313) and the second conductive layer (312) are arranged along the second direction and their orthographic projections on the substrate (100) overlap with the orthographic projection of the second dielectric layer (311) on the substrate (100), and the orthographic projection areas of the plurality of second conductive layers (312) of the plurality of step layer groups (310) on the substrate (100) are the same, and the second direction intersects with the first direction.

2. The semiconductor structure according to claim 1, wherein: In the same step layer group (310), relative to the second conductive layer (312) and the third dielectric layer (313), the second dielectric layer (311) is far away from the substrate (100).

3. The semiconductor structure according to claim 1, wherein: The step structure (300) comprises a first step area (A1), a non-step area (A2) and a second step area (A3); the first step area (A1) and the second step area (A3) are located on both sides of the non-step area (A2) in the second direction; the plurality of step layer groups (310) constitute the plurality of steps in both the first step area (A1) and the second step area (A3); and within the same step layer group (310), a second conductive layer (312) is provided in the first step area (A1) and / or the second step area (A3).

4. The semiconductor structure according to claim 3, wherein: In the same step layer group (310), the second conductive layer (312) is located on both sides of the third dielectric layer (313) in the second direction.

5. The semiconductor structure according to claim 3, wherein: In the same step layer group (310), the second conductive layer (312) is only located on one side of the third dielectric layer (313) in the second direction, and along a direction perpendicular to the substrate (100), the second conductive layers (312) in adjacent step layer groups (310) are located on two opposite sides in the second direction.

6. The semiconductor structure according to claim 3, wherein: The semiconductor structure further comprises a plurality of conductive plugs (400), wherein the plurality of conductive plugs (400) respectively penetrate the plurality of steps and connect the corresponding second conductive layer (312), and the conductive plugs (400) penetrating the odd-numbered steps are located in the first step area (A1), and the conductive plugs (400) penetrating the even-numbered steps are located in the second step area (A3).

7. The semiconductor structure according to any one of claims 1 to 6, wherein: The plurality of second conductive layers (312) of the plurality of step layer groups (310) are arranged in sequence and completely staggered along the second direction.

8. The semiconductor structure according to any one of claims 1 to 6, wherein: The plurality of second conductive layers (312) of the plurality of step layer groups (310) are partially staggered and arranged in sequence along the second direction.

9. The semiconductor structure according to any one of claims 1 to 6, wherein: The first conductive wire (222) is provided with the wire connecting portion (221) on both sides in the first direction, and the patterned stacked structure (200) is provided with the step structure (300) on both sides in the first direction.

10. A method for preparing a semiconductor structure, comprising: Providing a substrate (100); A patterned stacked structure (200) is formed on the substrate (100), the patterned stacked structure (200) comprising a first dielectric layer (210) and a first conductive layer (220) which are alternately stacked and overlap in orthographic projection on the substrate (100), the first conductive layer (220) comprising a wire connecting portion (221) and a first conductive line (222), the first conductive line (222) being connected to the wire connecting portion (221) in a first direction; A step structure (300) is formed on the substrate (100) on the side of the wire connecting portion (221) away from the first conductive wire (222) along the first direction, the step structure (300) comprising a plurality of step layer groups (310) stacked and arranged, the plurality of step layer groups (310) constituting a plurality of steps distributed along the second direction, and the step layer group (310) comprising a second dielectric layer (311), a second conductive layer (312) and a third dielectric layer (313), the second conductive layer (312) being disposed on the first conductive wire (222) and the second conductive layer (313) being disposed on the first conductive wire (221). The wire connection portion (221) is connected in the direction, and within the same step layer group (310), the third dielectric layer (313) and the second conductive layer (312) are arranged along the second direction and the orthographic projections of the third dielectric layer (313) and the second conductive layer (312) on the substrate (100) overlap with the orthographic projection of the second dielectric layer (311) on the substrate (100), the orthographic projection areas of the plurality of second conductive layers (312) of the plurality of step layer groups (310) on the substrate (100) are the same, and the second direction intersects with the first direction.

11. The method for preparing a semiconductor structure according to claim 10, wherein: The step of forming a patterned stacked structure (200) on the substrate (100) comprises: Alternatingly stacking a first dielectric material layer and a sacrificial material layer on the substrate (100); Performing a patterning process on the first dielectric material layer and the sacrificial material layer, wherein the remaining first dielectric material layer forms the first dielectric layer (210), and the remaining sacrificial material layer forms a sacrificial layer; The sacrificial layer is removed, and the first conductive layer (220) is formed in the removed region of the sacrificial layer.

12. The method for preparing a semiconductor structure according to claim 11, wherein: The material of the first dielectric material layer includes silicon oxide, and the material of the sacrificial material layer includes silicon nitride.

13. The method for preparing a semiconductor structure according to claim 10, wherein: The step structure (300) is formed on the substrate (100) on the side of the wire connecting portion (221) away from the first conductive line (222) along the first direction, comprising: A step initial structure (3001) is formed on the substrate (100) on the side of the wire connection portion (221) away from the first conductive wire (222) along the first direction, the step initial structure (3001) comprising a plurality of step initial layer groups (3101) stacked together, the widths of the plurality of step initial layer groups (3101) in the second direction decreasing in sequence with the stacking height to form a plurality of steps distributed along the second direction, and the step initial layer group (3101) comprises a third dielectric initial layer (3131) and a second dielectric layer (311) formed in sequence, and within the same step initial layer group (3101), the orthographic projection of the third dielectric initial layer (3131) on the substrate (100) overlaps with the orthographic projection of the second dielectric layer (311) on the substrate (100); Laterally etching the third dielectric initial layer (3131) to form a hollow region, and the remaining third dielectric initial layer (3131) forms the third dielectric layer (313); The second conductive layer (312) is formed in the hollow area.

14. The method for preparing a semiconductor structure according to claim 13, wherein: The step initial structure (3001) is formed on the substrate (100) on the side of the wire connecting portion (221) away from the first conductive line (222) along the first direction, comprising: Alternatingly stacking a second dielectric material layer and a third dielectric material layer on the substrate (100); The second dielectric material layer and the third dielectric material layer are etched to form the step initial structure (3001), and the third dielectric material layer remaining after etching forms the third dielectric initial layer (3131). The layer forms the second dielectric layer (311).

15. The method for preparing a semiconductor structure according to claim 10, wherein: After forming the step structure (300) on the substrate (100) on the side of the wire connecting portion (221) away from the first conductive line (222) along the first direction, the method further comprises: forming a plurality of contact holes (10) respectively penetrating the multi-step steps; A conductive plug (400) is formed in the contact hole (10), and the conductive plug (400) on each step is connected to the second conductive layer (312) corresponding to the step.

16. The method for preparing a semiconductor structure according to claim 15, wherein: The step structure (300) comprises a first step area (A1), a non-step area (A2) and a second step area (A3); the first step area (A1) and the second step area (A3) are located on both sides of the non-step area (A2) in the second direction; the plurality of step layer groups (310) constitute the plurality of steps in both the first step area (A1) and the second step area (A3); and within the same step layer group (310), a second conductive layer (312) is provided in the first step area (A1) and / or the second step area (A3).

17. The method for preparing a semiconductor structure according to claim 16, wherein: The conductive plugs (400) respectively penetrate the multiple steps and connect the corresponding second conductive layer (312), and the conductive plugs (400) that penetrate the odd-numbered steps are located in the first step area (A1), and the conductive plugs (400) that penetrate the even-numbered steps are located in the second step area (A3).

18. The method for preparing a semiconductor structure according to any one of claims 10 to 17, wherein: The plurality of second conductive layers (312) of the plurality of step layer groups (310) are arranged in sequence and completely staggered along the second direction.

19. The method for preparing a semiconductor structure according to any one of claims 10 to 17, wherein: The plurality of second conductive layers (312) of the plurality of step layer groups (310) are partially staggered and arranged in sequence along the second direction.

20. The method for preparing a semiconductor structure according to any one of claims 10 to 17, wherein: The first conductive wire (222) is provided with the wire connecting portion (221) on both sides in the first direction, and the patterned stacked structure (200) is provided with the step structure (300) on both sides in the first direction.

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