Array substrate and manufacturing method therefor, and display panel

Abstract

Disclosed in the present application are an array substrate and a manufacturing method therefor, and a display panel. The array substrate comprises a substrate, a buffer layer, a semiconductor layer, a gate insulating layer, a gate electrode, a first interlayer dielectric layer, a first electrode, a second interlayer dielectric layer, and a second electrode, wherein the first electrode comprises a first trace portion; the second interlayer dielectric layer covers the first trace portion and is provided with a recess; and the distance from an upper surface of the part of the second interlayer dielectric layer that is located above the first trace portion to an upper surface of the first interlayer dielectric layer is greater than the distance from a bottom wall of the recess to the upper surface of the first interlayer dielectric layer.

Description

Array substrate and manufacturing method thereof, and display panel

[0001] This application claims priority to Chinese patent application No. 202311528190.X filed on November 14, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, and a display panel. Background Art

[0003] Currently, users are increasingly demanding small-sized, high-resolution display panels. As the resolution of display panels increases, the pixel density (PPI) of the display panels also increases. For display panels with high pixel density, the source and drain electrodes on their array substrates are also very dense.

[0004] To further reduce the size of display panels and improve their resolution, the spacing between the source and drain electrodes on the array substrate needs to be reduced. However, due to the limited precision of traditional display panel manufacturing processes, if the mask used as a mask is misaligned during the process of forming the source and drain electrodes, the spacing between the source and drain electrodes can deviate from the preset value. When the spacing between the source and drain electrodes is smaller than the preset value, adjacent source and drain electrodes may even short-circuit, causing the array substrate to malfunction. SUMMARY OF THE INVENTION

[0005] The purpose of the present application is to provide an array substrate and a manufacturing method thereof, and a display panel, which can solve the problem of positional offset caused by mask alignment.

[0006] In a first aspect, the present application proposes an array substrate, comprising:

[0007] substrate;

[0008] a buffer layer, disposed on the substrate;

[0009] a semiconductor layer, disposed on the buffer layer;

[0010] a gate insulating layer, disposed on the buffer layer and covering the semiconductor layer;

[0011] a gate, disposed on the gate insulating layer;

[0012] a first interlayer dielectric layer, disposed on the gate insulating layer and covering the gate;

[0013] a first electrode comprising a first connecting portion and a first routing portion connected to each other, wherein the first routing portion is provided on the first interlayer dielectric layer, the first connecting portion passes through the first interlayer dielectric layer and the gate insulating layer, and is electrically connected to the semiconductor layer;

[0014] a second interlayer dielectric layer, provided on the first interlayer dielectric layer and covering the first wiring portion, wherein a surface of the second interlayer dielectric layer facing away from the substrate is provided with a groove; and

[0015] a second electrode comprising a second connecting portion and a second routing portion connected to each other, wherein the second routing portion is disposed in the groove, and the second connecting portion passes through the first interlayer dielectric layer, the second interlayer dielectric layer, and the gate insulating layer, and is electrically connected to the semiconductor layer;

[0016] The orthographic projection of the groove on the substrate and the orthographic projection of the first routing portion on the substrate do not overlap, and the distance from the upper surface of a portion of the second interlayer dielectric layer located above the first routing portion to the upper surface of the first interlayer dielectric layer is greater than the distance from the bottom wall of the groove to the upper surface of the first interlayer dielectric layer.

[0017] In a second aspect, the present application proposes a method for manufacturing an array substrate, comprising the following steps:

[0018] forming a buffer layer on the substrate;

[0019] forming a semiconductor layer on the buffer layer;

[0020] forming a gate insulating layer on the semiconductor layer, wherein the gate insulating layer covers the semiconductor layer;

[0021] forming a gate on the gate insulating layer;

[0022] forming a first interlayer dielectric layer on the gate insulating layer, wherein the first interlayer dielectric layer covers the gate;

[0023] forming a first electrode on the first interlayer dielectric layer, wherein the first electrode includes a first connecting portion and a first routing portion connected to each other, the first routing portion is provided on the first interlayer dielectric layer, the first connecting portion passes through the first interlayer dielectric layer and the gate insulating layer, and is electrically connected to the semiconductor layer;

[0024] forming a second interlayer dielectric layer on the first interlayer dielectric layer, wherein the second interlayer dielectric layer covers the first wiring portion, and a surface of the second interlayer dielectric layer facing away from the substrate is provided with a groove;

[0025] A second electrode is formed on the second interlayer dielectric layer, wherein the second electrode includes a second connecting portion and a second routing portion connected to each other, the second routing portion is arranged in the groove, and the second connecting portion passes through the second interlayer dielectric layer, the first interlayer dielectric layer and the gate insulating layer, and is electrically connected to the semiconductor layer.

[0026] In a third aspect, the present application further provides a display panel, which includes the array substrate described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG1 is a schematic diagram of a display panel provided in an embodiment of the present application.

[0028] FIG2 is a top view of an array substrate provided in an embodiment of the present application.

[0029] FIG3 is a cross-sectional view of the array substrate in FIG2 taken along the AA′ cross-sectional line.

[0030] FIG. 4 is a cross-sectional view of the array substrate in FIG. 2 taken along the BB′ cross-sectional line.

[0031] FIG5 is a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application.

[0032] 6A-6E are schematic diagrams of steps 108a-108e in a method for manufacturing an array substrate provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0033] The meanings of the terms used in this specification and claims correspond to those commonly understood by persons of ordinary skill in the art to which this application belongs. The terms used in this specification and claims are intended solely to facilitate the description and understanding of this application and are not intended to limit this application to the narrow interpretations of the specific terms used in the specification and claims. In this application, various embodiments may be combined with each other, but will not be described in detail here.

[0034] In some embodiments of the present application, the second interlayer dielectric layer includes:

[0035] a first insulating portion, disposed above the first wiring portion; and

[0036] a second insulating portion, provided on the first interlayer dielectric layer and located on one side of the first routing portion, the second insulating portion being connected to the first insulating portion, and the second insulating portion and two adjacent first insulating portions forming the groove;

[0037] The distance between a surface of the first insulating portion facing away from the substrate and a surface of the second insulating portion facing away from the substrate is in a range of 0.25 micrometers to 1 micrometer.

[0038] In some embodiments of the present application, the thickness of the first insulating portion is equal to the thickness of the second insulating portion, and the thickness of the first routing portion is in the range of 0.25 micrometers to 1 micrometer.

[0039] In some embodiments of the present application, the thickness of the second routing portion is smaller than the depth of the groove.

[0040] In some embodiments of the present application, the width of the groove is greater than the width of the second routing portion.

[0041] In some embodiments of the present application, a first via hole is formed in the first interlayer dielectric layer and the gate insulating layer, and a depth of the first via hole is in a range of 0.35 micrometers to 1 micrometer;

[0042] A second via hole is formed in the second interlayer dielectric layer, the first interlayer dielectric layer and the gate insulating layer, and the depth of the second via hole is in a range of 0.55 microns to 1.8 microns;

[0043] The first via hole and the second via hole are spaced apart from each other, the first connecting portion is provided in the first via hole, and the orthographic projection of the first via hole on the substrate is within the range of the orthographic projection of the first routing portion on the substrate;

[0044] The second connecting portion is provided in the second via hole, and an orthographic projection of the second via hole on the substrate is located within a range of an orthographic projection of the second routing portion on the substrate.

[0045] In some embodiments of the present application, the width of the first routing portion is in the range of 1 micron to 4 microns, the width of the second routing portion is in the range of 1 micron to 4 microns, and the spacing between the orthographic projection of the first routing portion on the substrate and the orthographic projection of the second routing portion on the substrate is in the range of 0.2 microns to 1.5 microns.

[0046] In the present application, the first electrode and the second electrode of the thin film transistor are arranged in layers, the first routing portion is arranged on the first interlayer dielectric layer, the second interlayer dielectric layer is arranged on the first interlayer dielectric layer and covers the first routing portion. Since the first routing portion has a certain thickness, it plays the role of raising part of the second interlayer dielectric layer. A groove is formed on the part of the second interlayer dielectric layer between the two adjacent first routing portions, and the second routing portion is formed in the groove, which reduces the influence of the mask alignment offset on the spacing between the source and the drain, improves the consistency of the source and the drain, and prevents the source and the drain from short-circuiting due to too short a spacing.

[0047] 1 , in a first aspect, the present application proposes a display panel 1000. The display panel 1000 is an accessory for a mobile phone, a laptop computer, or a tablet computer.

[0048] 2 to 4 , in a second aspect, the present application proposes an array substrate 100, comprising a substrate 10, a buffer layer 20, a semiconductor layer 31, a gate insulating layer 32, a gate 33, a first interlayer dielectric layer 40, a first electrode 34, a second interlayer dielectric layer 50, and a second electrode 35. The buffer layer 20 is disposed on the substrate 10. The semiconductor layer 31 is disposed on the buffer layer 20. The gate insulating layer 32 is disposed on the buffer layer 20 and covers the semiconductor layer 31. The gate 33 is disposed on the gate insulating layer 32. The first interlayer dielectric layer 40 is disposed on the gate insulating layer 32 and covers the gate 33. The first electrode 34 includes a first connecting portion 341 and a first routing portion 342 that are interconnected. The first routing portion 342 is disposed on the first interlayer dielectric layer 40. The first connecting portion 341 passes through the first interlayer dielectric layer 40 and the gate insulating layer 32 and is electrically connected to the semiconductor layer 31. The second interlayer dielectric layer 50 is disposed on the first interlayer dielectric layer 40 and covers the first routing portion 342. A groove 51 is provided on a surface of the second interlayer dielectric layer 50 facing away from the substrate 10. The second electrode 35 includes a second connecting portion 351 and a second routing portion 352 connected to each other. The second routing portion 352 is disposed in the groove 51. The second connecting portion 351 passes through the first interlayer dielectric layer 40, the second interlayer dielectric layer 50, and the gate insulating layer 32, and is electrically connected to the semiconductor layer 31. The orthographic projection of the groove 51 on the substrate 10 and the orthographic projection of the first routing portion 342 on the substrate 10 do not overlap. The distance D1 from the upper surface of the portion of the second interlayer dielectric layer 50 located above the first routing portion 342 to the upper surface of the first interlayer dielectric layer 40 is greater than the distance D2 from the bottom wall of the groove 51 to the upper surface of the first interlayer dielectric layer 40.

[0049] In the present application, the first electrode 34 and the second electrode 35 of the thin film transistor 30 are arranged in layers. The first routing portion 342 is arranged on the first interlayer dielectric layer 40. The second interlayer dielectric layer 50 is arranged on the first interlayer dielectric layer 40 and covers the first routing portion 342. Since the first routing portion 342 has a certain thickness, it plays the role of raising a portion of the second interlayer dielectric layer 50. A groove 51 is formed on the portion of the second interlayer dielectric layer 50 between two adjacent first routing portions 342. The second routing portion 352 is formed in the groove 51, which reduces the influence of the mask alignment offset on the spacing between the source and drain, improves the consistency of the source and drain, and prevents the source and drain from short-circuiting due to too short a spacing.

[0050] The portion of the second interlayer dielectric layer 50 located above the first routing portion 342 is the first insulating portion 52. The other portion of the second interlayer dielectric layer 50 located above the first interlayer dielectric layer 40 is the second insulating portion 53. The sum of the thickness of the first insulating portion 52 and the thickness of the first routing portion 342 is equal to the distance D1 from the upper surface of the portion of the second interlayer dielectric layer 50 located above the first routing portion 342 to the upper surface of the first interlayer dielectric layer 40. The thickness of the second insulating portion 53 is equal to the distance D2 from the bottom wall of the groove 51 to the upper surface of the first interlayer dielectric layer 40. Therefore, the sum of the thickness of the first insulating portion 52 and the thickness of the first routing portion 342 is greater than the thickness of the second insulating portion 53.

[0051] In some embodiments of the present application, the substrate 10 is a rigid substrate 10 , and the material of the substrate 10 is glass. In other embodiments of the present application, the substrate 10 is a flexible substrate 10 , and the material of the substrate 10 is polyimide (PI).

[0052] The first electrode 34 is a source electrode or a drain electrode, and the second electrode 35 is the other of the source electrode or the drain electrode. In the embodiment of the present application, the first electrode 34 is a source electrode, and the second electrode 35 is a drain electrode.

[0053] The semiconductor layer 31 , the first electrode 34 , the second electrode 35 , the gate insulating layer 32 , the gate 33 , the first interlayer dielectric layer 40 and the second interlayer dielectric layer 50 form a thin film transistor 30 .

[0054] The first routing portion 342 is disposed on the first interlayer dielectric layer 40, and the second interlayer dielectric layer 50 is disposed on the first interlayer dielectric layer 40 and covers the first routing portion 342. The first routing portion 342 serves to elevate the second interlayer dielectric layer 50. The array substrate 100 includes a plurality of thin-film transistors 30, each of which includes a first routing portion 342. The second interlayer dielectric layer 50 above adjacent first routing portions 342 is elevated, and the elevated second interlayer dielectric layer 50 and the unelevated second interlayer dielectric layer 50 form a groove 51. The second routing portion 352 is disposed within the groove 51. Because the orthographic projection of the groove 51 on the substrate 10 does not overlap with the orthographic projection of the first routing portion 342 on the substrate 10, the orthographic projection of the second routing portion 352 on the substrate 10 does not overlap with the orthographic projection of the first routing portion 342 on the substrate 10.

[0055] The thickness of the gate insulating layer 32 is in the range of 0.05 μm to 0.2 μm, and the thickness of the gate insulating layer 32 is one of 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, 0.1 μm, 0.11 μm, 0.12 μm, 0.13 μm, 0.14 μm, 0.15 μm, 0.16 μm, 0.17 μm, 0.18 μm, 0.19 μm, and 0.20 μm.

[0056] The thickness of the first interlayer dielectric layer 40 is in the range of 0.3 μm to 0.8 μm. The thickness of the first interlayer dielectric layer 40 is selected from 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, 0.5 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm, and 0.8 μm.

[0057] The thickness of the second interlayer dielectric layer 50 is in the range of 0.2 μm to 0.8 μm. The thickness of the second interlayer dielectric layer 50 is selected from 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, 0.5 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm, and 0.8 μm.

[0058] The spacing between the first wiring portion 342 and the second wiring portion 352 can be adjusted via the groove 51. Without shorting the first electrode 34 and the second electrode 35, the thickness of the second interlayer dielectric layer 50 can be further reduced. In some embodiments of the present application, the thickness of the second interlayer dielectric layer 50 is less than that of the first interlayer dielectric layer 40, thereby reducing the overall thickness of the array substrate 100.

[0059] In some embodiments of the present application, the radial length of the first connection portion 341 is the sum of the thickness of the gate insulation layer 32 and the thickness of the first interlayer dielectric layer 40. The radial length of the first connection portion 341 is in the range of 0.35 micrometers to 1 micrometer.

[0060] In some embodiments of the present application, the radial length of the second connecting portion 351 is the sum of the thickness of the gate insulating layer 32, the thickness of the first interlayer dielectric layer 40, and the thickness of the second interlayer dielectric layer 50. The radial length of the second connecting portion 351 is in the range of 0.55 microns to 1.8 microns.

[0061] The first routing portion 342 and the second routing portion 352 are arranged in different layers, which increases the density of the first electrode 34 and the second electrode 35. Part of the second routing portion 352 is located above the first routing portion 342. An insulating second interlayer dielectric layer 50 is formed between the first routing portion 342 and the second routing portion 352. A spike structure is formed on the edge of the first routing portion 342 facing the second routing portion 352. When the second interlayer dielectric layer 50 cannot cover the spike structure of the first routing portion 342, the spike structure of the first routing portion 342 will be exposed and short-circuited with the second routing portion 352 above it. In addition, the spike structure will produce a tip discharge phenomenon. Electrostatic discharge (ESD) is generated between the first routing portion 342 and the second routing portion 352, causing damage to the first electrode 34 or the second electrode 35. Therefore, even if the first routing portion 342 and the second routing portion 352 are arranged in different layers, it is still necessary to control the distance between the first routing portion 342 and the second routing portion 352 in a top view to prevent short circuit or electrostatic discharge between the first routing portion 342 and the second routing portion 352 and improve the stability of the array substrate 100.

[0062] The array substrate 100 further includes a light shielding layer 61 . The light shielding layer 61 is disposed on the substrate 10 . The buffer layer 20 covers the light shielding layer 61 .

[0063] In some embodiments of the present application, the array substrate is applied to small-sized products such as VR (Virtual Reality) and AR (Augmented Reality). In traditional array substrates, the spacing between the first routing portion and the second routing portion is extremely narrow, and the line width of the second routing portion is extremely thin, resulting in exceeding the exposure limit of the mask, causing the second routing portion to break during the preparation process. In the present application, a whole continuous metal layer is prepared on the second interlayer dielectric layer, and then the portion of the metal layer higher than the groove is etched away, leaving the metal layer in the groove to form the second routing portion. The structure of the present application can avoid the problem of broken wires in the second routing portion due to insufficient exposure limit in traditional array substrates, thereby improving the stability of the array substrate structure.

[0064] 2 to 4 , in an embodiment of the present application, the second interlayer dielectric layer 50 includes a first insulating portion 52 and a second insulating portion 53. The first insulating portion 52 is disposed above the first routing portion 342. The second insulating portion 53 is disposed on the first interlayer dielectric layer 40 and is located on one side of the first routing portion 342. The second insulating portion 53 is connected to the first insulating portion 52. The second insulating portion 53 forms a groove 51 with two adjacent first insulating portions 52. The distance between the first insulating portion 52 facing away from the surface of the substrate 10 and the second insulating portion 53 facing away from the surface of the substrate 10 is in a range of 0.25 microns to 1 micron.

[0065] The second interlayer dielectric layer 50 includes an integrally formed first insulating portion 52 and a second insulating portion 53. The first insulating portion 52 is disposed above the first routing portion 342. The second insulating portion 53 is disposed on the first interlayer dielectric layer 40. The first routing portion 342 serves to elevate the first insulating portion 52, thereby raising it above the second insulating portion 53.

[0066] 2 to 4 , in some embodiments of the present application, the thickness of the first insulating portion 52 is equal to the thickness of the second insulating portion 53 . Equal thickness refers to the fact that the thicknesses of the two portions are equal at the design level. However, due to errors in production equipment, it is impossible to achieve absolute equality of thickness between the two portions. In practice, the thickness of the first insulating portion 52 is substantially equal to the thickness of the second insulating portion 53 . Because the first wiring portion 342 raises the first insulating portion 52 , the depth of the groove 51 formed by the first and second insulating portions 52 , 53 is equal to the thickness of the first wiring portion 342 .

[0067] In other embodiments of the present application, the thickness of the first insulating portion 52 is greater than the thickness of the second insulating portion 53. In this embodiment, the depth of the groove 51 is relatively deep, which is suitable for the design of a thicker thickness of the second wiring portion 352.

[0068] In some other embodiments of the present application, the thickness of the first insulating portion 52 is less than the thickness of the second insulating portion 53. The thickness of the first insulating portion 52 and the first wiring portion 342 is greater than the thickness of the second insulating portion 53. In this embodiment, the depth of the groove 51 is relatively shallow, which is suitable for the design of a thinner second wiring portion 352.

[0069] The depth of the groove 51 is in the range of 0.25 μm to 1 μm. The depth of the groove 51 is selected from the group consisting of 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, 0.5 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm, 0.8 μm, 0.85 μm, 0.9 μm, 0.95 μm, and 1 μm.

[0070] 2 to 4 , in the embodiment of the present application, the thickness of the first insulating portion 52 is equal to the thickness of the second insulating portion 53. The thickness of the first routing portion 342 is in the range of 0.25 micrometers to 1 micrometer.

[0071] The thickness of the first insulating portion 52 is equal to the thickness of the second insulating portion 53. Equal thickness refers to the design-level thickness of the two. However, due to errors in production equipment, absolute equality of thickness cannot be achieved. In practice, the thickness of the first insulating portion 52 is essentially equal to the thickness of the second insulating portion 53. Because the first wiring portion 342 raises the first insulating portion 52, the depth of the groove 51 formed by the first and second insulating portions 52, 53 is equal to the thickness of the first wiring portion 342.

[0072] The thickness of the first trace portion 342 is in the range of 0.25 μm to 1 μm. The thickness of the first trace portion 342 is selected from the group consisting of 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, 0.5 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm, 0.8 μm, 0.85 μm, 0.9 μm, 0.95 μm, and 1 μm.

[0073] 2 to 4 , in the embodiment of the present application, the thickness of the second routing portion 352 is smaller than the depth of the groove 51 .

[0074] The second wiring portion 352 is formed only in the groove 51. The thickness of the second wiring portion 352 is in the range of 0.2 μm to 0.5 μm, wherein the thickness of the second wiring portion 352 is one of 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, and 0.5 μm.

[0075] In some embodiments of the present application, the thickness of the first insulating portion 52 is equal to the thickness of the second insulating portion 53, and the depth of the groove 51 depends on the thickness of the first routing portion 342. In one embodiment, the thickness of the second routing portion 352 is less than the thickness of the first routing portion 342.

[0076] The depth of the groove 51 is greater than the thickness of the second wiring portion 352 , so as to facilitate positioning when forming the second wiring portion 352 , thereby improving the yield rate of the array substrate 100 .

[0077] 2 to 4 , in the embodiment of the present application, the width of the groove 51 is greater than the width of the second wiring portion 352 .

[0078] The projection of the second routing portion 352 on the substrate 10 is within the range of the projection of the groove 51 on the substrate 10. The width of the groove 51 is greater than the width of the second routing portion 352. In this embodiment, the second routing portion 352 is only formed on the bottom wall of the groove 51. The edge of the second routing portion 352 does not cover the side wall of the groove 51. The structure of this embodiment prevents the edge of the second routing portion 352 from climbing on the side wall of the groove 51, resulting in the spacing between the first routing portion 342 and the second routing portion 352 being too small when viewed from above, causing electrostatic discharge to damage the first electrode 34 and the second electrode 35.

[0079] The width of the groove 51 is smaller than the distance between two adjacent first wiring portions 342 , and the width of the groove 51 is larger than the width of the second wiring portion 352 .

[0080] 2 to 4 , in the embodiment of the present application, a first via hole is formed in the first interlayer dielectric layer 40 and the gate insulating layer 32. The depth of the first via hole is in the range of 0.35 micrometers to 1 micrometer.

[0081] A second via hole is formed in the second interlayer dielectric layer 50, the first interlayer dielectric layer 40 and the gate insulating layer 32. The depth of the second via hole is in the range of 0.55 micrometers to 1.8 micrometers.

[0082] The first via and the second via are spaced apart. The first connecting portion 341 is disposed in the first via. The orthographic projection of the first via on the substrate 10 is within the range of the orthographic projection of the first routing portion 342 on the substrate 10. The second connecting portion 351 is disposed in the second via. The orthographic projection of the second via on the substrate 10 is within the range of the orthographic projection of the second routing portion 352 on the substrate 10.

[0083] The depth of the first via hole depends on the thickness of the gate insulating layer 32 and the thickness of the first interlayer dielectric layer 40. The depth of the first via hole is selected from 0.35 micrometers, 0.4 micrometers, 0.45 micrometers, 0.5 micrometers, 0.55 micrometers, 0.6 micrometers, 0.65 micrometers, 0.7 micrometers, 0.8 micrometers, 0.85 micrometers, 0.9 micrometers, 0.95 micrometers, and 1 micrometer.

[0084] The depth of the second via hole depends on the thickness of the gate insulating layer 32, the thickness of the first interlayer dielectric layer 40, and the thickness of the second interlayer dielectric layer 50. The depth of the second via hole is selected from 0.55 micrometers, 0.6 micrometers, 0.65 micrometers, 0.7 micrometers, 0.8 micrometers, 0.85 micrometers, 0.9 micrometers, 0.95 micrometers, 1 micrometer, 1.05 micrometers, 1.1 micrometers, 1.15 micrometers, 1.2 micrometers, 1.25 micrometers, 1.3 micrometers, 1.35 micrometers, 1.4 micrometers, 1.45 micrometers, 1.5 micrometers, 1.55 micrometers, 1.6 micrometers, 1.65 micrometers, 1.7 micrometers, 1.75 micrometers, and 1.8 micrometers.

[0085] The first connection portion 341 passes through the first via hole and is electrically connected to the semiconductor layer 31 . The second connection portion 351 passes through the second via hole and is electrically connected to the semiconductor layer 31 .

[0086] The orthographic projection of the first via hole on the substrate 10 is within the range of the orthographic projection of the first routing portion 342 on the substrate 10. The first routing portion 342 covers the first via hole, preventing the underlying semiconductor layer 31 from being exposed, thereby preventing the semiconductor layer 31 underneath the first routing portion 342 from being etched during the manufacturing process of the array substrate 100.

[0087] The orthographic projection of the second via hole on the substrate 10 is within the range of the orthographic projection of the second routing portion 352 on the substrate 10. The second routing portion 352 covers the second via hole, preventing the underlying semiconductor layer 31 from being exposed, thereby preventing the semiconductor layer 31 underneath the second routing portion 352 from being etched during the manufacturing process of the array substrate 100.

[0088] 2 to 4 , in the embodiment of the present application, the width of the first routing portion 342 is in the range of 1 to 4 microns. The width of the second routing portion 352 is in the range of 1 to 4 microns. The spacing between the orthographic projection of the first routing portion 342 and the orthographic projection of the second routing portion 352 on the substrate 10 is in the range of 0.2 to 1.5 microns.

[0089] In order to improve the resolution of the display panel 1000 and reduce the size of the display panel 1000, it is necessary to reduce the spacing between the source and drain electrodes on the array substrate 100 while controlling the critical dimension (CD) of the first trace portion 342 and the critical dimension (CD) of the second trace portion 352. The CD refers to the width of the metal trace.

[0090] In this embodiment, the width of the first routing portion 342 is one of 1 micron, 1.2 microns, 1.4 microns, 1.6 microns, 1.8 microns, 2 microns, 2.2 microns, 2.4 microns, 2.6 microns, 2.8 microns, 3 microns, 3.2 microns, 3.4 microns, 3.6 microns, 3.8 microns, and 4 microns.

[0091] The width of the second routing portion 352 is one of 1 micron, 1.2 microns, 1.4 microns, 1.6 microns, 1.8 microns, 2 microns, 2.2 microns, 2.4 microns, 2.6 microns, 2.8 microns, 3 microns, 3.2 microns, 3.4 microns, 3.6 microns, 3.8 microns, and 4 microns.

[0092] In a top view, the spacing between the first routing portion 342 and the second routing portion 352 is in a range of 0.2 μm to 1.5 μm. The spacing between the first routing portion 342 and the second routing portion 352 is selected from the group consisting of 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, 0.5 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm, 0.8 μm, 0.85 μm, 0.9 μm, 0.95 μm, 1 μm, 1.05 μm, 1.1 μm, 1.15 μm, 1.2 μm, 1.25 μm, 1.3 μm, 1.35 μm, 1.4 μm, 1.45 μm, and 1.5 μm.

[0093] The first routing portion 342 extends to the non-display area along the long side of the array substrate 100. The first routing portion 342 and the second routing portion 352 are spaced apart along the short side of the array substrate 100. The first routing portion 342 and the second routing portion 352 are alternately arranged along the short side of the array substrate 100.

[0094] In some embodiments of the present application, the first trace portion 342 and the second trace portion 352 are spaced apart along the short side of the array substrate 100. The angle between the length direction of the semiconductor layer 31 and the long side of the array substrate 100 is a. The angle between the length direction of the semiconductor layer 31 and the short side of the array substrate 100 is b. Here, a + b = 90° (the sum of a and b is 90 degrees).

[0095] 5 and 6A-6E , in a third aspect, the present application proposes a method for manufacturing an array substrate 100 , comprising the following steps:

[0096] Step 101 : forming a buffer layer 20 on a substrate 10 .

[0097] Step 102 : forming a semiconductor layer 31 on the buffer layer 20 .

[0098] Step 103 : forming a gate insulating layer 32 on the semiconductor layer 31 , wherein the gate insulating layer 32 covers the semiconductor layer 31 .

[0099] Step 104 : forming a gate 33 on the gate insulating layer 32 .

[0100] Step 105 : forming a first interlayer dielectric layer 40 on the gate insulating layer 32 , wherein the first interlayer dielectric layer 40 covers the gate 33 .

[0101] Step 106: Form a first electrode 34 on the first interlayer dielectric layer 40. The first electrode 34 includes a first connecting portion 341 and a first routing portion 342 that are interconnected. The first routing portion 342 is disposed on the first interlayer dielectric layer 40. The first connecting portion 341 passes through the first interlayer dielectric layer 40 and the gate insulating layer 32 and is electrically connected to the semiconductor layer 31.

[0102] A first via is formed in the first interlayer dielectric layer 40 and the gate insulating layer 32 by laser cutting or etching. A first connecting portion 341 passes through the first via and is electrically connected to the semiconductor layer 31. A first routing portion 342 is formed on the first interlayer dielectric layer 40. The first routing portion 342 covers the first via and is connected to the first connecting portion 341 in the first via. The first routing portion 342 has a certain thickness perpendicular to the plane of the substrate 10.

[0103] Step 107: forming a second interlayer dielectric layer 50 on the first interlayer dielectric layer 40. The second interlayer dielectric layer 50 covers the first wiring portion 342. A groove 51 is formed on a surface of the second interlayer dielectric layer 50 facing away from the substrate 10.

[0104] The first routing portion 342 has a certain thickness. The second interlayer dielectric layer 50 covers the first routing portion 342. The second interlayer dielectric layer 50 includes a first insulating portion 52 and a second insulating portion 53. The first insulating portion 52 is provided on the first routing portion 342. The second insulating portion 53 is provided on the first interlayer dielectric layer 40 and is located on one side of the first routing portion 342.

[0105] In this embodiment, there is a step between the first insulating portion 52 and the second insulating portion 53. The second insulating portion 53 and two adjacent first insulating portions 52 form a groove 51.

[0106] Step 108: Form a second electrode 35 on the second interlayer dielectric layer 50. The second electrode 35 includes a second connecting portion 351 and a second routing portion 352, which are connected to each other. The second routing portion 352 is disposed within the recess 51. The second connecting portion 351 passes through the second interlayer dielectric layer 50, the first interlayer dielectric layer 40, and the gate insulating layer 32, and is electrically connected to the semiconductor layer 31.

[0107] A second via is formed in the second interlayer dielectric layer 50, the first interlayer dielectric layer 40, and the gate insulating layer 32 by laser cutting or etching. The second connecting portion 351 passes through the second via and is electrically connected to the semiconductor layer 31. A second routing portion 352 is formed on the second interlayer dielectric layer 50. The second routing portion 352 covers the second via and is connected to the second connecting portion 351 in the second via. The second routing portion 352 is disposed within the recess 51.

[0108] 6A to 6E , in some embodiments of the present application, the step of forming the second electrode 35 on the second interlayer dielectric layer 50 includes:

[0109] 6A , step 108 a : forming a metal layer 70 on the second interlayer dielectric layer 50 .

[0110] A continuous metal layer 70 is formed on the upper surface and side surfaces of the first insulating portion 52 and the upper surface of the second insulating portion 53 .

[0111] 6B , step 108b: forming a first light blocking portion 81 and a second light blocking portion 82 of different thicknesses on the metal layer 70 . The first light blocking portion 81 is located above the first wiring portion 342 , and the second light blocking portion 82 is located above the second wiring portion 352 .

[0112] A photoresist is applied to the metal layer 70. The photoresist is leveled on the metal layer 70 to form a photoresist layer. The photoresist layer includes a first photoresist portion 81 and a second photoresist portion 82 of different thicknesses. The thickness of the first photoresist portion 81 is smaller than that of the second photoresist portion 82. The upper surface of the first photoresist portion 81 is flush with the upper surface of the second photoresist portion 82. The lower surface of the first photoresist portion 81 and the lower surface of the second photoresist portion 82 are stepped.

[0113] In this embodiment, the first light blocking portions 81 and the second light blocking portions 82 are connected to each other and are alternately arranged in the short side direction of the array substrate 100 .

[0114] 6C , step 108 c : peeling off the first photoresist portion 81 .

[0115] The photoresist layer is ashed to remove a portion of the photoresist layer. Since the thickness of the first photoresist portion 81 is smaller than that of the second photoresist portion 82, when the first photoresist portion 81 is peeled off from the metal layer 70 by ashing, the metal layer 70 on the first insulating portion 52 is exposed.

[0116] 6D , step 108 d : etching the portion of the metal layer 70 exposed outside the second photoresist portion 82 .

[0117] The portion of the metal layer 70 located on the first insulating portion 52 is removed by wet etching.

[0118] 6E , step 108 e : peeling off the second photoresist portion 82 .

[0119] The remaining photoresist layer is removed through exposure and development, forming a plurality of second wiring portions 352 spaced apart and located in the groove 51 .

[0120] The above describes in detail the specific embodiments of the present application. The above embodiments disclosed in this application are merely preferred embodiments of the present application. Those skilled in the art will appreciate that many variations and improvements can be made without departing from the spirit of the present application. These variations and improvements fall within the scope of protection defined by the claims of this application.

Claims

1. An array substrate, wherein: include: substrate; A buffer layer is disposed on the substrate; A semiconductor layer, disposed on the buffer layer; A gate insulating layer, disposed on the buffer layer and covering the semiconductor layer; A gate, disposed on the gate insulating layer; A first interlayer dielectric layer is disposed on the gate insulating layer and covers the gate; A first electrode, comprising a first connecting portion and a first wiring portion connected to each other, wherein the first wiring portion is disposed on the first interlayer dielectric layer, and the first connecting portion passes through the first interlayer dielectric layer and the gate insulating layer and is electrically connected to the semiconductor layer; A second interlayer dielectric layer is provided on the first interlayer dielectric layer and covers the first wiring portion, and a groove is provided on a surface of the second interlayer dielectric layer facing away from the substrate; and A second electrode comprises a second connecting portion and a second wiring portion connected to each other, the second wiring portion is arranged in the groove, the second connecting portion passes through the first interlayer dielectric layer, the second interlayer dielectric layer and the gate insulating layer, and is electrically connected to the semiconductor layer; The orthographic projection of the groove on the substrate and the orthographic projection of the first routing portion on the substrate do not overlap, and the distance from the upper surface of a portion of the second interlayer dielectric layer located above the first routing portion to the upper surface of the first interlayer dielectric layer is greater than the distance from the bottom wall of the groove to the upper surface of the first interlayer dielectric layer.

2. The array substrate according to claim 1, wherein: The second interlayer dielectric layer comprises: A first insulating portion, disposed above the first routing portion; and A second insulating portion is provided on the first interlayer dielectric layer and is located on one side of the first routing portion, the second insulating portion is connected to the first insulating portion, and the second insulating portion and two adjacent first insulating portions form the groove; A distance from a surface of the first insulating portion facing away from the substrate to a surface of the second insulating portion facing away from the substrate is in a range of 0.25 micrometers to 1 micrometer.

3. The array substrate according to claim 2, wherein: The thickness of the first insulating portion is equal to the thickness of the second insulating portion, and the thickness of the first routing portion is in a range of 0.25 micrometers to 1 micrometer.

4. The array substrate according to claim 1, wherein: The thickness of the second wiring portion is smaller than the depth of the groove.

5. The array substrate according to claim 1, wherein: The width of the groove is greater than the width of the second wiring portion.

6. The array substrate according to claim 5, wherein: The width of the groove is smaller than the distance between two adjacent first wiring portions.

7. The array substrate according to claim 1, wherein: A first via hole is formed in the first interlayer dielectric layer and the gate insulating layer, and a depth of the first via hole is in a range of 0.35 micrometers to 1 micrometer; A second via hole is formed in the second interlayer dielectric layer, the first interlayer dielectric layer and the gate insulating layer, and the depth of the second via hole is in the range of 0.55 micrometers to 1.8 micrometers; The first via hole and the second via hole are arranged at intervals, the first connecting portion is arranged in the first via hole, and the orthographic projection of the first via hole on the substrate is located within the range of the orthographic projection of the first routing portion on the substrate; The second connection portion is disposed in the second via hole, and an orthographic projection of the second via hole on the substrate is located within a range of an orthographic projection of the second routing portion on the substrate.

8. The array substrate according to claim 1, wherein: The width of the first routing portion is in the range of 1 micron to 4 microns, the width of the second routing portion is in the range of 1 micron to 4 microns, and the spacing between the orthographic projection of the first routing portion on the substrate and the orthographic projection of the second routing portion on the substrate is in the range of 0.2 microns to 1.5 microns.

9. The array substrate according to claim 1, wherein: The thickness of the first interlayer dielectric layer is in the range of 0.3 micrometer to 0.8 micrometer; The thickness of the second interlayer dielectric layer is smaller than the thickness of the first interlayer dielectric layer.

10. The array substrate according to claim 1, wherein: The radial length of the first connecting portion is the sum of the thickness of the gate insulating layer and the thickness of the first interlayer dielectric layer; The radial length of the first connecting portion is in a range of 0.35 micrometers to 1 micrometer.

11. The array substrate according to claim 1, wherein: The radial length of the second connecting portion is the sum of the thickness of the gate insulating layer, the thickness of the first interlayer dielectric layer and the thickness of the second interlayer dielectric layer; The radial length of the second connecting portion is in a range of 0.55 micrometers to 1.8 micrometers.

12. The array substrate according to claim 1, wherein: The depth of the groove is in the range of 0.25 micrometer to 1 micrometer.

13. The array substrate according to claim 1, wherein: In a top view, the first wiring portion extends along the long side direction of the array substrate, and the first wiring portion and the second wiring portion are arranged at intervals along the short side direction of the array substrate.

14. The array substrate according to claim 13, wherein: In a top view, the first wiring portions and the second wiring portions are alternately arranged along the short side direction of the array substrate.

15. The array substrate according to claim 13, wherein: The included angle between the length direction of the semiconductor layer and the long side direction of the array substrate is a; The length direction of the semiconductor layer and the short side direction of the array substrate are b; The sum of a and b equals 90 degrees.

16. A method for manufacturing an array substrate, wherein: The following steps are involved: forming a buffer layer on a substrate; forming a semiconductor layer on the buffer layer; forming a gate insulating layer on the semiconductor layer, wherein the gate insulating layer covers the semiconductor layer; forming a gate on the gate insulating layer; forming a first interlayer dielectric layer on the gate insulating layer, wherein the first interlayer dielectric layer covers the gate; forming a first electrode on the first interlayer dielectric layer, wherein the first electrode comprises a first connecting portion and a first routing portion connected to each other, the first routing portion is arranged on the first interlayer dielectric layer, the first connecting portion passes through the first interlayer dielectric layer and the gate insulating layer, and is electrically connected to the semiconductor layer; forming a second interlayer dielectric layer on the first interlayer dielectric layer, wherein the second interlayer dielectric layer covers the first wiring portion, and a surface of the second interlayer dielectric layer facing away from the substrate is provided with a groove; A second electrode is formed on the second interlayer dielectric layer, wherein the second electrode includes a second connecting portion and a second routing portion connected to each other, the second routing portion is arranged in the groove, the second connecting portion passes through the second interlayer dielectric layer, the first interlayer dielectric layer and the gate insulating layer, and is electrically connected to the semiconductor layer.

17. The method for manufacturing an array substrate according to claim 16, wherein: The step of forming a second electrode on the second interlayer dielectric layer comprises: forming a metal layer on the second interlayer dielectric layer; forming a first light-blocking portion and a second light-blocking portion with different thicknesses on the metal layer, wherein the first light-blocking portion is located above the first wiring portion, and the second light-blocking portion is located above the second wiring portion; peeling off the first photoresist portion; Etching a portion of the metal layer exposed outside the second photoresist portion; The second photoresist portion is peeled off.

18. The method for manufacturing an array substrate according to claim 17, wherein: The step of forming a first light blocking portion and a second light blocking portion with different thicknesses on the metal layer comprises: coating a photoresist on the metal layer; The photoresist is leveled on the metal layer to form a photoresist layer, wherein the photoresist layer includes the first photoresist portion and the second photoresist portion, and the thickness of the first photoresist portion is smaller than the thickness of the second photoresist portion.

19. The method for manufacturing an array substrate according to claim 18, wherein: The step of stripping the first light blocking portion comprises: The photoresist layer is ashed to remove the first photoresist portion.

20. A display panel, wherein: It comprises an array substrate as described in any one of claims 1 to 15.

Images