Communication method for single-line cascade circuit, single-line cascade circuit and display system

Abstract

The present invention provides a communication method for a single-line cascade circuit, a single-line cascade circuit and a display system. The method comprises: encoding a first data packet output by a main control unit in a BMC encoding mode, such that a transition edge will be generated at each joint between adjacent data bits of the first data packet; upon receiving an ith data packet, an ith driving unit detecting transition edges in non-preamble bit fields in the ith data packet; and when an initial transition edge in the ith data packet is detected, the ith driving unit outputting an (i+1)th data packet to an (i+1)th driving unit. In this way, it is ensured that the driving units transmitting signals can receive complete data packets, so as to achieve clock synchronization between adjacent driving units, thus eliminating the problems such as data catchup or data overwrite caused by asynchronous communication during cross-driving unit communication, and effectively increasing the success rate of communication in single-line cascade circuits.

Description

Communication method of single-line cascade circuit, single-line cascade circuit and display system Technical Field

[0001] The present invention relates to the field of communication, and in particular to a communication method of a single-line cascade circuit, a single-line cascade circuit and a display system. Background Art

[0002] Please refer to Figure 1, which shows the structure of a commonly used two-wire transmission and two-wire return cascade circuit in a display system. The system consists of a master control system and N slaves connected in series. The output of the master control system is connected to the input of the first slave, and the output of the Nth slave is connected to the input of the master control system. The master control system and each slave are connected via two wires. The communication process of this system is as follows: the master control system sends a data packet and a synchronization clock signal to the first slave via two wires. The first slave synchronizes its clock according to the synchronization clock signal to fully receive the data packet and perform the corresponding task based on the data packet's content. If a task is to read data from a slave, the first slave places the data to be read in the accompanying information field of the data packet. The first slave then outputs the data packet and synchronization clock to the second slave. This process repeats until the Nth slave completes its task and retransmits the data packet and synchronization clock signal back to the master control system. However, the problem with the two-wire transmission-two-wire return cascade circuit is that it requires two wires for communication, which increases the number of pins of a single slave, thereby greatly increasing the overall circuit area of ​​N slaves and increasing the circuit cost.

[0003] To address the circuit area issues associated with the aforementioned two-wire transmission-two-wire return cascade circuit, existing technology replaces the two-wire transmission-two-wire return cascade circuit with a single-wire cascade circuit. Compared to the two-wire transmission-two-wire return cascade circuit, the single-wire cascade circuit requires only one communication conductor for physical connection, reducing the number of pins on the slave device by half, significantly reducing the overall area of ​​the cascaded slave devices and, in turn, lowering circuit costs. This allows more slave devices to be placed in the same physical space.

[0004] However, since the single-line cascade circuit lacks a data line for transmitting a synchronous clock signal, solving the signal synchronization problem during the transmission process has become a technical problem that the industry urgently needs to solve.

[0005] Summary of the Invention

[0006] The present invention provides a communication method of a single-line cascade circuit, a single-line cascade circuit and a display system, so as to solve the signal synchronization problem of the single-line cascade circuit during the transmission process.

[0007] According to a first aspect of the present invention, a communication method for a single-line cascade circuit is provided, for implementing communication between a master control unit and N sequentially connected drive units in the single-line cascade circuit, wherein the output terminal of the master control unit is coupled to the input terminal of the first drive unit, and the output terminal of the Nth drive unit is coupled to the input terminal of the master control unit. The method comprises:

[0008] The main control unit outputs a first data packet to the first drive unit according to the BMC code; wherein the first data packet generates a transition edge at the intersection between adjacent data bits;

[0009] After receiving the i-th data packet, the i-th driving unit outputs the i+1-th data packet to the i+1-th driving unit when detecting an initial transition edge of a non-preamble bit field in the i-th data packet; wherein the preamble bit field is used to represent the first n bits of the i-th data packet;

[0010] After receiving the Nth data packet, the Nth driving unit transmits the Nth data packet to the main control unit; wherein i, n, and N are all positive integers, and n≥1, 1≤i<N.

[0011] Optionally, detecting an initial transition edge of a non-preamble bit field in the i-th data packet specifically includes:

[0012] When an initial transition edge occurs in the non-preamble bit field in the i-th data packet, the i-th driving unit generates a corresponding pulse signal.

[0013] Optionally, the i-th driving unit outputs the i+1-th data packet to the i+1-th driving unit, specifically comprising: according to the pulse signal, the i-th driving unit outputs the i+1-th data packet to the i+1-th driving unit.

[0014] Optionally, the i-th driving unit outputting the (i+1)-th data packet to the (i+1)-th driving unit further specifically includes:

[0015] During the process of outputting the (i+1)th data packet, the address bit field in the (i+1)th data packet is increased by 1 bit.

[0016] Optionally, after the (i+1)th driving unit receives the (i+1)th data packet, the method further includes:

[0017] Detect the address bit field in the (i+1)th data packet, edit its own address according to the address bit field, and store it.

[0018] Optionally, after editing the address itself according to the address bit field and storing it, the following is further included:

[0019] Detect whether there is an address lock signal in the valid data bit field of the i+1th data packet; if so, the i+1th driving unit locks the stored address; if not, the address stored in the i+1th driving unit can be re-edited.

[0020] Optionally, after editing the address itself according to the address bit field and storing it, the following is further included:

[0021] Detect whether there is a corresponding control signal in the valid data bit field of the i+1th data packet; if so, the i+1th driving unit uploads its own stored status information to the accompanying information bit field of the i+1th data packet according to the corresponding control signal.

[0022] Optionally, the (i+1)th data packet further includes at least a frame type bit field, a packet length bit field, a check bit field, and a padding data bit field.

[0023] According to a second aspect of the present invention, there is provided a single-line cascade circuit, comprising a main control unit;

[0024] N drive units are connected in series; the output end of each drive unit is connected to the input end of the next drive unit, the input end of the first drive unit is coupled to the output end of the main control unit, and the output end of the Nth drive unit is coupled to the input end of the main control unit; wherein N is a positive integer and N ≥ 1;

[0025] The main control unit and the N driving units connected in series in sequence communicate with each other through the communication method of the single-line cascade circuit provided by the first aspect and the optional solution of the present invention.

[0026] According to a third aspect of the present invention, a display system is provided, comprising the single-line cascade circuit provided by the second aspect of the present invention.

[0027] The present invention provides a communication method for a single-line cascade circuit, a single-line cascade circuit, and a display system. A first data packet output by a main control unit is encoded using a BMC encoding method, so that the first data packet generates a transition edge at the intersection between adjacent data bits; when a first driving unit receives the first data packet, it detects the transition edge of a non-leading code bit field in the first data packet; when an initial transition edge in the first data packet is detected, the second driving unit outputs a second data packet to the second driving unit; through the above method, it is ensured that the driving unit to which the signal is transmitted can receive a complete data packet, thereby achieving clock synchronization between adjacent driving units, thereby eliminating problems such as data chasing or data coverage caused by asynchronous communication during communication across driving units, and effectively improving the success rate of communication in the single-line cascade circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] FIG1 is a structural diagram of a dual-line transmission-dual-line return cascade circuit in the prior art;

[0030] FIG2 is a structural diagram of a single-line cascade circuit provided by a first embodiment of the present invention;

[0031] 3 is a flow chart of a communication method for a single-line cascade circuit provided by a second embodiment of the present invention;

[0032] FIG4 is a waveform diagram of a communication method of a single-line cascade circuit provided by a second embodiment of the present invention.

[0033] Reference numerals: IN—input; OUT—output. DETAILED DESCRIPTION

[0034] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way are interchangeable where appropriate so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products or devices.

[0035] Before describing the embodiments of the present invention, a brief description of the data transmission problem existing in the single-line cascade circuit is given:

[0036] Similar to the dual-line transmit / return cascade circuit, during the communication process in a single-line cascade circuit, the master control system also sends a data packet to the first slave. This data packet consists of different types of fields, including a preamble field, a frame type field, an associated information field, an address field, a packet length field, a valid data field, a checksum field, and a padding field. Specifically, the preamble field contains a fixed data sequence of fixed bits for transmission, which is used to calculate the bit rate of the transmitted data packet. The frame type field defines the operation type of the data packet, such as a configuration packet, a multicast packet, or a display data packet. The associated information field primarily stores critical information that the slave needs to upload to the master control system in real time. The address field is mapped one-to-one with the register address within the slave to store the address information corresponding to each slave. The packet length field defines the number of bytes of valid data in the data packet. The valid data field stores multiple valid data bytes; each valid data byte corresponds to a slave, and each slave performs a task based on the corresponding valid data byte. The check bit field is used to store the check result of the data packet. The padding data field is filled with a fixed length of fixed 0 / 1 sequence to align the data after the slave system is cascaded.

[0037] During data packet transmission, the receiving slave collects the preamble bits within the received packet and uses the collected data bits as the preamble bits for the packet to be transmitted. However, errors may occur during the slave's collection of the preamble bits. For example, the preamble bits in the received packet may be 10 bits, but the preamble bits collected by the slave are 9 bits, resulting in a 9-bit preamble bit field in the packet to be transmitted. When the number of bits in the packet to be transmitted is too long, data overruns may occur due to slow reception and fast transmission. Another example is when the preamble bits in the received packet are 10 bits, but the preamble bits collected by the slave are 11 bits, resulting in a 11-bit preamble bit field in the packet to be transmitted. When the number of bits in the packet to be transmitted is too long, data overruns may occur due to fast reception and slow transmission. The key to solving this problem lies in accurately knowing the number of bits in the preamble bit field within the packet or accurately capturing the data edge at the end of the preamble bit field.

[0038] Referring to FIG2 , a first embodiment of the present invention provides a single-line cascade circuit including:

[0039] Main control unit;

[0040] N driving units connected in series; the output terminal OUT of each driving unit is connected to the input terminal IN of the subsequent driving unit, and the input terminal IN of the first driving unit is coupled to the output terminal OUT of the main control unit, and the output terminal OUT of the Nth driving unit is coupled to the input terminal IN of the main control unit; wherein N is a positive integer and N ≥ 1;

[0041] The main control unit and the N driving units connected in series in sequence communicate with each other through the communication method of the single-line cascade circuit provided by the second embodiment of the present invention.

[0042] Referring to FIG3 , a second embodiment of the present invention provides a communication method for a single-line cascade circuit, which is used to implement the communication of the single-line cascade circuit provided by the first embodiment of the present invention, wherein the output terminal OUT of the main control unit is coupled to the input terminal IN of the first drive unit, and the output terminal OUT of the Nth drive unit is coupled to the input terminal IN of the main control unit. The method includes:

[0043] S1: The main control unit outputs a first data packet to the first driving unit according to the BMC code; wherein, the first data packet generates a transition edge at the junction between adjacent data bits.

[0044] S2: After the i-th driving unit receives the i-th data packet, when the initial transition edge of the non-leading code bit field in the i-th data packet is detected, the i-th driving unit outputs the i+1-th data packet to the i+1-th driving unit; wherein the leading code bit field is used to represent the first n bits of the i-th data packet.

[0045] S3: After receiving the Nth data packet, the Nth driving unit transmits the Nth data packet to the main control unit; wherein i, n, and N are all positive integers, and n≥1, 1≤i<N.

[0046] The second embodiment of the present invention, through the above technical solution, can achieve clock synchronization between adjacent drive units, thereby eliminating problems such as data chasing or data overwriting caused by asynchronous communication during communication between drive units, and effectively improving the communication success rate in a single-line cascade circuit. The specific principle is:

[0047] Before explaining the specific principles, let's briefly explain BMC (Biphase Mark Coding) coding: During positive BMC coding, if the transmitted data is low during a cycle, the output data after BMC positive coding remains low or high during the corresponding cycle. If the transmitted data is high during a cycle, the output data after BMC positive coding will be high first and then low, or low first and then high, with a 50% duty cycle. During negative BMC coding, if the transmitted data is low during a cycle, the output data after BMC negative coding will be high first and then low, or low first and then high, with a 50% duty cycle. If the transmitted data is high during a cycle, the output data after BMC negative coding will remain low or high during the corresponding cycle. Furthermore, the output data after BMC coding will always experience level flips between adjacent cycles, resulting in a jump edge at the boundary between adjacent cycles.

[0048] Therefore, when the driver unit detects the initial transition edge of the non-preamble bit field in the received data packet, it indicates that it has completed the reception of the preamble in the data packet and outputs the data packet to the next driver unit. Through the above method, each driver unit can accurately detect the end of the preamble in the received data packet and use this end as the beginning of the data packet output. This avoids the acquisition error of the preamble bit field in the existing technology, avoids data overlap and data catch-up, and thus achieves clock synchronization between adjacent driver units.

[0049] Other technical details of the communication method of the single-line cascade circuit are described below:

[0050] In a specific embodiment, detecting an initial transition edge in the non-preamble bit field of the i-th data packet in S2 specifically includes: the i-th driving unit detecting a transition edge in the non-preamble bit field of the i-th data packet; upon detecting the initial transition edge, the i-th driving unit begins generating a corresponding pulse signal. Thereafter, each time the i-th driving unit detects a transition edge, it generates a corresponding pulse signal.

[0051] As a specific implementation manner, the i-th driving unit in S2 outputs the i+1-th data packet to the i+1-th driving unit, specifically including: the i-th driving unit outputs the i+1-th data packet to the i+1-th driving unit according to the generated start pulse signal; wherein, in the process of outputting the i+1-th data packet, the i-th driving unit adds 1 extra bit to the address field of the i+1-th data packet compared to the i-th data packet.

[0052] As a supplementary explanation, after the i+1th drive unit receives the i+1th data packet, in addition to repeating the steps in S2, it also includes: the i+1th drive unit detects the address bit field in the i+1th data packet, and edits and stores its own address based on the address bit field. At the same time, the i+1th drive unit will also detect whether there is a corresponding address lock signal in the valid data bit field of the i+1th data packet; if it exists, the i+1th drive unit will lock the stored address, that is, it can no longer be edited; if it does not exist, the address stored by the i+1th drive unit can be re-edited. It should be noted that if the address of the drive unit is not locked, the drive unit will edit its own address according to the received data packet. Of course, whether to lock the address of the drive unit can be selected according to actual needs and is not limited here.

[0053] As a supplementary explanation, in addition to detecting whether there is a corresponding address lock signal in the valid data bit field, the i+1th drive unit will also detect whether there is a corresponding control signal in the valid data bit field of the i+1th data packet; if so, the i+1th drive unit will upload its own stored status information to the accompanying information bit field of the i+1th data packet according to the corresponding control signal.

[0054] As a supplementary explanation, the data packet sent by the main control unit can only address N drive units connected in series, and then send another data packet to control the drive unit that needs to be controlled; it can also achieve simultaneous addressing and control of N drive units connected in series. It should be noted that after completing the addressing of all drive units, the control object of the main control unit can be all drive units, or the i-th drive unit to the N-th drive unit; i and N are both positive integers, and 1≤i<N. The control object can be selected according to specific needs and is not limited here. However, it is not possible to control only the i-th drive unit, the i+2-th drive unit to the N-th drive unit, such objects with vacancies in the middle.

[0055] The following describes the workflow of the communication method for the single-line cascade circuit provided by the second embodiment of the present invention, and sets the preamble bit field of the data packet output by the main control unit to 4 bits:

[0056] Please refer to Figures 2 and 4. The main control unit outputs the first data packet to the first slave through BMC encoding, and the first slave receives the first data packet. When the 4 bits of the leading code bit field are received, the jumping edge at the junction of the leading code bit field and the next bit field will be detected by the first slave, and the first slave generates a corresponding pulse signal based on the detected jumping edge. At the same time, the first slave outputs the first data packet according to the generated start pulse signal, and adds 1 bit to the address bit field of the output data packet, that is, outputs the second data packet to the second slave. The second slave receives the second data packet. When the 4 bits of the leading code bit field are received, the jumping edge at the junction of the leading code bit field and the next bit field will be detected by the second slave, and the first slave generates a corresponding pulse signal based on the detected jumping edge. At the same time, the second slave outputs the second data packet according to the generated start pulse signal, and adds 1 bit to the address bit field of the output data packet, that is, outputs the third data packet to the third slave. Subsequent slaves repeat the above operations until the Nth slave receives the Nth data packet and transmits the Nth data packet back to the master control unit to complete the communication of the single-line cascade circuit.

[0057] In summary, the communication method of the single-line cascade circuit provided by the second embodiment of the present invention encodes the first data packet output by the main control unit through the BMC encoding method, so that the first data packet will generate a jump edge at the intersection between adjacent data bits; when the first drive unit receives the first data packet, it will detect the jump edge of the non-leading code bit field in the first data packet; when the initial jump edge in the first data packet is detected, the first drive unit will output the second data packet to the second drive unit; through the above method, it is ensured that the drive unit to which the signal is transmitted can receive a complete data packet, thereby achieving clock synchronization between adjacent drive units, so as to eliminate problems such as data chasing or data coverage caused by asynchronous communication during the communication process across drive units, and effectively improve the success rate of communication in the single-line cascade circuit. At the same time, the communication method of the single-line cascade circuit provided by the second embodiment of the present invention can also realize the address definition of each drive unit in the circuit, register reading and writing and other functions.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A communication method for a single-line cascade circuit, used to realize communication between a main control unit and N driving units connected in series in the single-line cascade circuit, wherein: The output end of the main control unit is coupled to the input end of the first driving unit, and the output end of the Nth driving unit is coupled to the input end of the main control unit. The method includes: The main control unit outputs a first data packet to the first driving unit according to the BMC code; wherein the first data packet generates a transition edge at the intersection between adjacent data bits; After the i-th driving unit receives the i-th data packet, when an initial transition edge of a non-leading code bit field in the i-th data packet is detected, the i-th driving unit outputs the i+1-th data packet to the i+1-th driving unit; wherein the leading code bit field is used to represent the first n bits of the i-th data packet; After receiving the Nth data packet, the Nth driving unit transmits the Nth data packet to the main control unit; wherein i, n, and N are all positive integers, and n≥1, 1≤i<N.

2. The communication method of the single-line cascade circuit according to claim 1, characterized in that: Detecting an initial transition edge of a non-preamble bit field in the i-th data packet specifically includes: When an initial transition edge appears in the non-preamble bit field in the i-th data packet, the i-th driving unit generates a corresponding pulse signal.

3. The communication method of the single-line cascade circuit according to claim 2, characterized in that: The i-th driving unit outputs the i+1-th data packet to the i+1-th driving unit, specifically comprising: according to the pulse signal, the i-th driving unit outputs the i+1-th data packet to the i+1-th driving unit.

4. The communication method of the single-line cascade circuit according to claim 2, characterized in that: The i-th driving unit outputs the i+1-th data packet to the i+1-th driving unit, further specifically comprising: In the process of outputting the (i+1)th data packet, the address bit field in the (i+1)th data packet is increased by 1 bit.

5. The communication method of the single-line cascade circuit according to claim 4, characterized in that: After the (i+1)th driving unit receives the (i+1)th data packet, the method further includes: Detect the address bit field in the (i+1)th data packet, edit its own address according to the address bit field, and store it.

6. The communication method of the single-line cascade circuit according to claim 5, characterized in that: After editing and storing the address itself according to the address bit field, it also includes: Detect whether there is an address lock signal in the valid data bit field of the i+1th data packet; if there is If yes, the (i+1)th driving unit will lock the stored address; if no, the address stored in the (i+1)th driving unit can be re-edited.

7. The communication method of the single-line cascade circuit according to claim 5, characterized in that: After editing and storing the address itself according to the address bit field, it also includes: Detect whether there is a corresponding control signal in the valid data bit field of the i+1th data packet; if so, the i+1th driving unit uploads its own stored status information to the accompanying information bit field of the i+1th data packet according to the corresponding control signal.

8. The communication method of the single-line cascade circuit according to claim 7, characterized in that: The (i+1)th data packet at least includes a frame type bit field, a packet length bit field, a check bit field, and a padding data bit field.

9. A single-line cascade circuit, characterized in that: include: Main control unit; N driving units are connected in series in sequence; the output end of each driving unit is connected to the input end of the next driving unit, and the input end of the first driving unit is coupled to the output end of the main control unit, and the output end of the Nth driving unit is coupled to the input end of the main control unit; wherein N is a positive integer, and N≥1; Wherein, the main control unit and the N driving units connected in series in sequence communicate with each other through the communication method of the single-line cascade circuit according to any one of claims 1 to 8.

10. A display system, characterized in that: The single-wire cascade circuit comprises the single-wire cascade circuit described in claim 9.

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