Pixel unit of CMOS image sensor and CMOS image sensor

Abstract

The present application belongs to the field of semiconductors. Disclosed are a pixel unit of a CMOS image sensor and a CMOS image sensor. In the present application, a PN diode and a reset transistor are added, the PN diode being used as an overflow device, and the reset transistor resetting the PN diode. An electron overflow channel is formed between a second P-type doped layer at the bottom of an N region of the PN diode and a photodiode. The potential of the second P-type doped layer is higher than that of other P-type doped layers adjacent to an N region of the photodiode, and therefore, before a transfer transistor transports electrons to a floating diffusion region, the electrons first overflow into the PN diode. The present application not only can store electrons which naturally overflow when the photodiode is about to be full, but also can avoid a dark current caused when electrons which are generated due to a non-sufficient negative bias of a transfer gate diffuse into the photodiode, thereby improving the dynamic range of the CMOS image sensor.

Description

Pixel unit of CMOS image sensor and CMOS image sensor

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 15, 2023, with application number 202311517902.8 and application name “Pixel unit of CMOS image sensor and CMOS image sensor”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductors, and in particular to a pixel unit of a CMOS image sensor and a CMOS image sensor. Background Art

[0003] When the transfer transistor in a pixel unit of a conventional CMOS (Complementary Metal Oxide Semiconductor) image sensor also serves as an overflow transistor, the potential of the silicon surface beneath the gate oxide layer of the transfer transistor must be high to ensure smooth overflow of electrons from the photodiode. Consequently, the interface states between the gate oxide layer and the silicon of the transfer transistor cannot be filled with holes to a very high level, and some of the electrons emitted from the interface states will enter the photodiode, generating dark current in the photodiode. The presence of this dark current partially reduces the dynamic range of the CMOS image sensor. Therefore, improving the dynamic range of CMOS image sensors is a technical problem currently being addressed by those skilled in the art.

[0004] Summary of the Invention

[0005] The purpose of the present application is to provide a pixel unit of a CMOS image sensor and a CMOS image sensor, wherein the pixel unit structure is used to improve the dynamic range of the CMOS image sensor.

[0006] To achieve the above-mentioned object, the present application provides a pixel unit of a CMOS image sensor, comprising: a substrate, on which a photodiode, an overflow device, and a reset transistor are disposed;

[0007] The overflow device includes a PN diode; the P region of the PN diode includes a first P-type doped layer and a second P-type doped layer; the doping concentration of the second P-type doped layer is lower than the doping concentration of the first P-type doped layer; the first P-type doped layer surrounds the N region of the PN diode; the second P-type doped layer is located at the bottom of the N region of the PN diode, so that the N region of the PN diode is connected to the N region of the photodiode through the second P-type doped layer;

[0008] Among all the P-type doped layers adjacent to the N region of the photodiode, the second P-type doped layer has the highest potential, so that electrons overflowing from the N region of the photodiode are transferred into the PN diode through the second P-type doped layer;

[0009] The PN diode is connected to the reset transistor through a metal line.

[0010] Optionally, the overflow device further includes a capacitor; the capacitor is connected in parallel with the PN diode; and the capacitor is connected to the reset transistor through the metal wire.

[0011] Optionally, the capacitor is a MIM capacitor; the positive electrode of the MIM capacitor is connected to the N region of the PN diode through a contact hole and the metal wire; the capacity of the MIM capacitor is greater than 100 times the capacity of the photodiode.

[0012] Optionally, the first P-type doped layer is a first P-type medium doped layer;

[0013] The second P-type doped layer is a P-type lightly doped layer with a preset thickness, and the doping concentration of the P-type lightly doped layer is lower than 1×1013 / cm3; or, the second P-type doped layer is a second P-type medium-doped layer; the second P-type medium-doped layer overlaps with the N region of the PN diode on one side close to the N region of the PN diode.

[0014] Optionally, the doping concentration of the second P-type doping layer is lower than 3×10 17 / cm 3 .

[0015] Optionally, the reset transistor is an NMOS transistor; the N region of the PN diode is connected to the source of the NMOS transistor through the metal wire.

[0016] Optionally, the second P-type doped layer is parallel to the surface of the substrate, so that electrons overflowing from the N region of the photodiode are transmitted into the PN diode through the second P-type doped layer in a direction perpendicular to the surface of the substrate.

[0017] Optionally, the PN diode is located in the N region of the photodiode away from the end connected to the transfer transistor;

[0018] Alternatively, the PN diode is located in an upper center region of the photodiode.

[0019] Optionally, the distance between the N region of the PN diode and the shallow trench isolation is greater than 0.15 μm; the shallow trench isolation is used to isolate active regions of adjacent pixel units.

[0020] Optionally, the N region of the PN diode includes an N-type heavily doped layer and an N-type medium doped layer;

[0021] The second P-type doping layer is located at the bottom of the N-type medium doping layer, so that the N-type medium doping layer is connected to the N region of the photodiode through the second P-type doping layer.

[0022] To achieve the above-mentioned purpose, the present application further provides a CMOS image sensor, comprising: a plurality of pixel units; the pixel units are the pixel units described in any one of the above-mentioned items.

[0023] The present application provides a pixel unit of a CMOS image sensor, comprising: a substrate, on which a photodiode, an overflow device, and a reset transistor are provided;

[0024] The overflow device includes a PN diode; the P region of the PN diode includes a first P-type doped layer and a second P-type doped layer; the doping concentration of the second P-type doped layer is lower than the doping concentration of the first P-type doped layer; the first P-type doped layer surrounds the N region of the PN diode; the second P-type doped layer is located at the bottom of the N region of the PN diode, so that the N region of the PN diode is connected to the N region of the photodiode through the second P-type doped layer;

[0025] Among all the P-type doped layers adjacent to the N region of the photodiode, the second P-type doped layer has the highest potential, so that electrons overflowing from the N region of the photodiode are transferred into the PN diode through the second P-type doped layer;

[0026] The PN diode is connected to the reset transistor through a metal line.

[0027] Obviously, the present application adds a PN diode as an overflow device, and uses a reset transistor to reset the PN diode. An electron overflow channel is formed between the second P-type doped layer at the bottom of the N region of the PN diode and the photodiode. Since the potential of the second P-type doped layer is higher than the potential of other P-type doped layers adjacent to the N region of the photodiode, the electrons will overflow into the PN diode before the transfer transistor transfers the electrons to the floating diffusion area. It can not only store the electrons that naturally overflow when the photodiode is about to be full, but also avoid the dark current caused by the electrons generated by the insufficient negative bias of the transmission gate diffusing into the photodiode, thereby improving the dynamic range of the CMOS image sensor; and the PN diode as an overflow device does not require additional control, and the control is relatively simple. The present application also provides a CMOS image sensor with the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1 is a cross-sectional schematic diagram of a pixel unit provided in an embodiment of the present application;

[0029] FIG2 is a circuit diagram of a pixel unit provided in an embodiment of the present application;

[0030] FIG3 is a schematic diagram of a cross-sectional potential barrier of a pixel unit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0032] Traditional CMOS image sensors use only a floating diffusion (FD) as a capacitor, making it difficult to achieve a dynamic range exceeding 100. Therefore, one solution for pixels with high dynamic range uses several capacitors of varying sizes, with the smallest capacitor used in low light and the sum of all capacitors in strong light. Through appropriate timing switches, different capacitor sizes are used in strong and low light conditions, respectively. High dynamic range is then achieved through circuit and algorithm processing. Due to the complexity of the control, it is difficult to use a large number of these capacitors to achieve near-continuous adjustment. At certain light intensities, the image may suddenly dim.

[0033] In traditional CMOS image sensors, the electrons in the N region of the photodiode are completely depleted after reset, leaving only space charge. When collecting photogenerated electrons, the transfer transistor applies a negative bias (V1) to the silicon oxide layer of the transfer transistor, so that the interface state is almost completely filled with holes, thereby preventing the electrons emitted from the interface state from entering the photodiode and becoming the dark current of the photodiode. Technically, the concentration of the P-type inversion layer is required to reach 10 18 / cm3, at this time the potential under the gate is slightly lower than that of the P-type substrate.

[0034] In a traditional HDR (High-Dynamic Range) pixel unit, after reset, a negative bias voltage with an absolute value lower than V1 is applied to the gate of the transfer transistor. After the photogenerated electrons fill the photodiode to the designed level, the additional photogenerated electrons in the photodiode naturally overflow to the FD and are then stored in a large capacitor connected to the FD through a transistor for subsequent use.

[0035] To allow electrons from the photodiode to overflow smoothly, the gate of the transfer transistor is biased more positively than V1, so that the potential of the silicon surface below the gate dielectric of the transfer transistor is higher than 0V. Since the P-type region around the photodiode is zero volts, in order to prevent electrical crosstalk between the photodiodes before overflowing to the FD, the potential of the silicon surface below the gate oxide layer of the transfer transistor is higher than 0.2V. In this way, the interface state between the gate oxide layer and the silicon of the transfer transistor cannot be filled with holes to a very high level, and the transfer transistor cannot be biased negatively enough to cause the hole concentration accumulated in the silicon below the gate to reach 1×10 18 / cm 3 As mentioned above, holes cannot fill the interface states at the interface between the gate oxide layer and the silicon, and some of the electrons emitted from the interface states will diffuse to the photodiode, causing dark current. This dark current will be sensed by the smallest FD capacitor, which reduces part of the dynamic range at the small signal end. The above problem is caused by the difficulty of the transfer transistor to simultaneously achieve a high filling level of interface state holes and assume the overflow function of the photodiode when the transfer transistor is negatively biased. Therefore, the present application provides a pixel unit of a CMOS image sensor and a CMOS image sensor, which adds a PN diode as an overflow device and uses a reset transistor to reset the PN diode. It can not only store the electrons that naturally overflow when the photodiode is about to be full, but also avoid the generation of dark current in the photodiode, thereby improving the dynamic range of the CMOS image sensor.

[0036] Please refer to FIG1 , which is a cross-sectional schematic diagram of a pixel unit of a CMOS image sensor provided in an embodiment of the present application. The pixel unit of the CMOS image sensor may include: a substrate on which a photodiode, an overflow device, and a reset transistor are disposed;

[0037] The overflow device includes a PN diode; the P region of the PN diode includes a first P-type doped layer 31 and a second P-type doped layer 32; the doping concentration of the second P-type doped layer 32 is lower than the doping concentration of the first P-type doped layer 31; the first P-type doped layer 31 surrounds the N region of the PN diode; the second P-type doped layer 32 is located at the bottom of the N region of the PN diode, so that the N region of the PN diode is connected to the N region 42 of the photodiode through the second P-type doped layer 32;

[0038] Among all the P-type doped layers adjacent to the N region 42 of the photodiode, the second P-type doped layer 32 has the highest potential, so that the electrons overflowing from the N region 42 of the photodiode are transferred into the PN diode through the second P-type doped layer 32;

[0039] The PN diode is connected to the reset transistor through a metal line.

[0040] It should be noted that the N region of the PN diode and the N region 42 of the photodiode are connected via the second P-type doped layer 32. After reset, an electron potential barrier exists between the second P-type doped layer 32 and the photodiode, which has reached the designed full-well state. Because the second P-type doped layer 32 has the highest potential among all P-type doped layers adjacent to the photodiode's N region 42, the electron potential barrier between the second P-type doped layer 32 and the photodiode's N region 42 is lower (by a few tenths of a volt) than the electron potential barrier between the photodiode's N region 42 and other adjacent P-type doped layers. Therefore, the second P-type doped layer 32 can serve as an electron overflow channel when the photodiode is nearly full. Because CMOS image sensors operate on the millisecond scale, the barrier channel will return to equilibrium during the reset and charging process. Using the N-type region as the barrier channel would introduce additional noise, but the equilibrium electron concentration in the second P-type doped layer 32 is already extremely low, thus avoiding such side effects.

[0041] After the photodiode is reset, the potential of its N region 42 is much higher than that of the second P-type doped layer 32. Therefore, photogenerated electrons gradually accumulate in the photodiode, and the potential of the photodiode decreases accordingly. The barrier difference between the photodiode and the second P-type doped layer 32 gradually decreases. When the barrier difference drops below a few tenths of a volt, subsequent electrons generated in the photodiode overflow through the second P-type doped layer 32 into the PN diode. The PN diode is a PN junction capacitor, so it can store the overflowed electrons for subsequent use by circuits and algorithms.

[0042] It should be noted that the PN diode and the reset transistor are not in the same region, so the PN diode is connected to the reset transistor through a metal wire.

[0043] This embodiment does not limit the specific type of the substrate, and the specific type of the substrate can be determined according to actual conditions. For example, the substrate can be a silicon wafer.

[0044] The pixel unit of the CMOS image sensor of this embodiment may include other devices in addition to the photodiode, the overflow device, and the reset transistor. This embodiment does not limit the specific types and specific connection methods of the other devices, and reference may be made to the pixel unit of a conventional CMOS image sensor.

[0045] Furthermore, to increase the storage capacity of the overflow device, the overflow device in this embodiment may further include a capacitor connected in parallel with the PN diode; the capacitor is connected to the reset transistor via a metal wire. It should be noted that both the capacitor and the PN diode are reset by the reset transistor.

[0046] This embodiment does not limit the specific type of capacitor; it can be any large-capacity capacitor, for example, a MIM capacitor; the positive electrode of the MIM capacitor is connected to the N region of the PN diode via a contact hole and a metal wire. Furthermore, to meet the requirements of high dynamic range, the capacitance of the MIM capacitor in this embodiment can be 100 times greater than that of the photodiode.

[0047] This embodiment does not limit the specific type of the second P-type doped layer 32. For example, the first P-type doped layer 31 is a first P-type medium doped layer 31; the second P-type doped layer 32 can be a P-type lightly doped layer with a preset thickness, and the doping concentration of the P-type lightly doped layer is lower than 1×10 13 / cm 3 Alternatively, the second P-type doped layer 32 may be a second P-type medium-doped layer 32; the side of the second P-type medium-doped layer 32 adjacent to the N-region of the PN diode overlaps with the N-region of the PN diode. It should be noted that the potential of the second P-type medium-doped layer 32 is modulated by both the N-region of the PN diode and the N-region 42 of the photodiode.

[0048] This embodiment does not limit the specific doping concentration of the second P-type doping layer 32. It only needs to ensure that the doping concentration of the second P-type doping layer 32 is less than the doping concentration of the first P-type doping layer 31. For example, the doping concentration of the second P-type doping layer 32 can be lower than 3×10 17 / cm 3 It should be noted that the second P-type doped layer 32 can be formed by implantation before gate oxidation.

[0049] This embodiment does not limit the specific type of the reset transistor, as long as it can ensure the reset of the PN diode and the capacitor. For example, the reset transistor can be an NMOS transistor; the N region of the PN diode is connected to the source of the NMOS transistor through a metal wire.

[0050] Furthermore, in this embodiment, the second P-type doped layer 32 can be parallel to the surface of the substrate, so that electrons overflowing from the N region 42 of the photodiode are transmitted into the PN diode through the second P-type doped layer 32 in a direction perpendicular to the surface of the substrate.

[0051] This embodiment does not limit the specific position of the PN diode. The specific position of the PN diode can be determined according to actual conditions. For example, the PN diode can be located in the N region 42 of the photodiode away from the end connected to the transfer transistor. When the design requires a high number of full well electrons per unit area, the PN diode can also be located in the area above the center of the photodiode.

[0052] It should be noted that shallow trench isolation (STI) is provided between the active areas of adjacent pixel units. The STI is used to isolate the active areas of adjacent pixel units. This embodiment does not limit the specific distance between the N region of the PN diode and the STI. The specific distance between the N region of the PN diode and the STI can be determined based on actual conditions. For example, the distance between the N region of the PN diode and the STI is greater than 0.15 μm.

[0053] Furthermore, to prevent fluctuations in doping concentration caused by the single-layer N-type heavily doped layer 44, which could lead to fluctuations in the potential barrier between the PN diode and the photodiode, and to improve the uniformity of the potential barrier within the chip, the N region of the PN diode in this embodiment may include an N-type heavily doped layer 44 and an N-type medium doped layer 43. The second P-type doped layer 32 is located at the bottom of the N-type medium doped layer 43, so that the N-type medium doped layer 43 is connected to the N region 42 of the photodiode through the second P-type doped layer 32. It should be noted that the N-type heavily doped layer 44 serves as an ohmic contact, and the N-type medium doped layer 43 is an extension of the N-type heavily doped layer 44, and can be prepared by sequential implantation using the same mask. The first P-type doped layer 31 is located around the N-type heavily doped layer 44, separating the N-type heavily doped layer 44 from direct contact with the shallow trench isolation. Below the N-type heavily doped layer 44, the N-type medium doped layer 43 is connected to the N region 42 of the photodiode through the second P-type doped layer 32.

[0054] Based on the above embodiment, the present application adds a PN diode as an overflow device, and uses a reset transistor to reset the PN diode. An electron overflow channel is formed between the second P-type doped layer 32 at the bottom of the N region of the PN diode and the photodiode. Since the potential of the second P-type doped layer 32 is higher than the potential of other P-type doped layers adjacent to the N region 42 of the photodiode, the electrons will overflow into the PN diode before the transfer transistor transfers the electrons to the floating diffusion area, thereby replacing the method of transmitting the overflowed electrons through the transfer transistor. It can not only store the electrons that naturally overflow when the photodiode is about to be full, but also avoid the dark current caused by the electrons generated by the insufficient negative bias of the transmission gate diffusing into the photodiode, thereby improving the dynamic range of the CMOS image sensor; and the PN diode as an overflow device does not require additional control, and the control is relatively simple.

[0055] Another pixel unit of a CMOS image sensor provided in an embodiment of the present application may include: a substrate on which a photodiode, an overflow device, and a reset transistor are disposed;

[0056] The overflow device includes a PN diode and a capacitor; the capacitor is connected in parallel with the PN diode;

[0057] The N region of the PN diode includes an N-type heavily doped layer 44 and an N-type medium doped layer 43; the P region of the PN diode includes a first P-type doped layer 31 and a second P-type doped layer 32; the doping concentration of the second P-type doped layer 32 is lower than the doping concentration of the first P-type doped layer 31; the first P-type doped layer 31 surrounds the N region of the PN diode; the second P-type doped layer 32 is located at the bottom of the N-type medium doped layer 43, so that the N-type medium doped layer 43 is connected to the N region 42 of the photodiode through the second P-type doped layer 32;

[0058] Among all the P-type doped layers adjacent to the N region 42 of the photodiode, the second P-type doped layer 32 has the highest potential, so that the electrons overflowing from the N region 42 of the photodiode are transferred into the PN diode through the second P-type doped layer 32;

[0059] The PN diode and the capacitor are connected to the reset transistor through metal lines.

[0060] Based on the above embodiment, the present application adds a PN diode and a capacitor in parallel as an overflow device, and uses a reset transistor to achieve simultaneous resetting of the PN diode and the capacitor. It can not only store the electrons that naturally overflow when the photodiode is about to be full, but also avoid the dark current caused by the electrons generated by the insufficient negative bias of the transmission gate diffusing into the photodiode, thereby improving the dynamic range of the CMOS image sensor. In addition, by storing the electrons that naturally overflow when the photodiode is about to be full through the parallel PN diode and capacitor, the storage capacity of the overflow device is improved; at the same time, the PN diode adopts an N+NP type diode, and the N region adds an N-type medium doping layer 43 as an extension area of ​​the N-type heavily doped layer 44, which can prevent the doping concentration fluctuation caused by the single-layer N-type heavily doped layer 44, resulting in fluctuations in the potential barrier between the PN diode and the photodiode, thereby improving the uniformity of the potential barrier within the chip.

[0061] An embodiment of the present application further provides a CMOS image sensor, comprising: a plurality of pixel units; the pixel units are the pixel units described above.

[0062] Based on the above embodiments, compared with conventional CMOS image sensors, the CMOS image sensor of the present application can achieve a higher dynamic range due to the use of the above-mentioned pixel units.

[0063] The working principle of the pixel unit of the above CMOS image sensor is explained below with reference to specific examples.

[0064] Please refer to Figure 2, which is a circuit schematic diagram of a pixel unit provided in an embodiment of the present application. The pixel unit is composed of a photodiode PD, a transfer transistor TG, and five other peripheral transistors (including a first reset transistor RST1, a second reset transistor RST2, a source follower SF, a row select transistor ROS, a dual conversion gain control unit DCG), a PN diode CPN, a capacitor C1 controlled by the dual conversion gain control unit DCG, and a large-capacity MIM capacitor C2.

[0065] Among them, the source of the transfer transistor TG is the N region of the photodiode PD; the drain of the transfer transistor TG is the first floating diffusion area FD1 connected to the gate of the source follower SF, and the drain of the transfer transistor TG and the gate of the source follower SF are both connected to the source of the first reset transistor RST1; the source of the source follower SF is connected to the drain of the row selection transistor ROS.

[0066] The second reset transistor RST2 is an NMOS transistor. The N region of the PN diode CPN and the source of the NMOS transistor are not in the same area, and are connected to the positive electrode of the MIM capacitor C2 and the source of the NMOS transistor through a metal wire. Both are reset by the NMOS transistor.

[0067] In addition, the dual conversion gain control unit DCG is an NMOS transistor, a drain of which is the first floating diffusion region FD1 , and a source of which is the second floating diffusion region FD2 and the capacitor C1 .

[0068] The N region of the PN diode CPN is connected to the N region of the photodiode PD via a P-type doped layer. The N-type heavily doped layer 44 of the PN diode CPN serves as the third floating diffusion region FD3.

[0069] Please refer to FIG1 , which is a cross-sectional schematic diagram of a pixel unit provided in an embodiment of the present application.

[0070] The transfer transistor TG is disposed in the silicon surface dielectric layer 21. The drain of the transfer transistor TG is a heavily doped N-type polysilicon layer 11, the gate is an oxide layer 12, and the source is a photodiode PD. An N-type heavily doped silicon single crystal layer 41 is disposed beneath the transfer transistor TG. The N-type heavily doped silicon single crystal layer 41 serves as the first floating diffusion region FD1 and is also the drain of the transfer transistor TG. The N region of the photodiode PD serves as the source terminal of the transfer transistor TG and is formed on a P-type epitaxial substrate 23. A silicon-oxygen interface P-type heavily doped passivation layer 18 is disposed between the photodiode PD and the silicon surface dielectric layer 21. A P-type isolation layer 13 is disposed between adjacent pixel units.

[0071] A layer of P-type medium-doped layer (including a first P-type medium-doped layer 31 and a second P-type medium-doped layer 32) is implanted into the upper half of the photodiode PD before gate oxidation, with a depth of between 0.15μm and 0.4μm. In the middle of the P-type medium-doped layer, after the sidewall process is completed, a layer of N-type medium-doped layer 43 and an N-type heavily-doped layer 44 are implanted successively to form the N region of the PN diode CPN. The N-type medium-doped layer 43 can partially overlap with the second P-type medium-doped layer 32 to form a P-type thin layer. The effective thickness of the second P-type medium-doped layer 32 below the N region of the PN diode CPN is thinner than the first P-type medium-doped layer 31 outside the N region of the PN diode CPN, and the doping is also lower due to compensation by the N-type medium-doped layer 43. The electric potential of the P-type thin layer is modulated by the N-type medium-doped layer 43 and the N-type heavily-doped layer 44 of the PN diode CPN and the N region of the photodiode PD at the same time, mainly by the injection doping of the N-type medium-doped layer 43 and the bias modulation on the N-type heavily-doped layer 44. It is a few tenths of a volt higher than the surrounding first P-type medium-doped region, forming a unique and controllable electron channel from the N region of the photodiode PD to the N region of the PN diode CPN.

[0072] In addition, since the doping concentrations of the P-type isolation layer 13 and the first P-type medium doping layer 31 are similar, the P-type isolation layer 13 between adjacent pixel units can be used as part of the first P-type medium doping layer 31. In this way, the additional first P-type medium doping layer 31 can be made into 0.3μm. 2 Below that, the depth is less than 0.4μm, so even if it is used on a small pixel unit, it has little impact on the total quantum efficiency.

[0073] To save area, the PN diode CPN is a very small capacitor. The N region of the PN diode CPN consists of an N-type heavily doped layer 44 and an N-type moderately doped layer 43 at the bottom of the N-type heavily doped layer 44. The N-type heavily doped layer 44 and the N-type moderately doped layer 43 are surrounded by a first P-type moderately doped layer 31, and the bottom is surrounded by a second P-type moderately doped layer 32. The N-type heavily doped layer 44 serves as an ohmic contact and is connected to the source of the NMOS transistor via a metal wire. The first P-type moderately doped layer 31 separates the N-type heavily doped layer 44 from the silicon-oxygen interface P-type heavily doped passivation layer 18 at the edge of the shallow trench isolation (STI). This prevents the formation of a high electric field between the N-type heavily doped layer 44 and the silicon-oxygen interface P-type heavily doped passivation layer 18, which could cause tunneling and introduce dark current into the PN diode CPN and MIM capacitor C2. The N-type moderately doped layer 43 also prevents doping fluctuations caused by the N-type heavily doped layer 44, which could lead to fluctuations in the potential barrier between the PN diode CPN and the photodiode PD, thereby improving the uniformity of the potential barrier within the chip.

[0074] In addition, the N region of the PN diode CPN newly added on the silicon wafer and the source of the second reset transistor RST2 are not in the same area and are isolated from each other by a P-type isolation layer 13 .

[0075] The N region of the PN diode CPN is different from the floating diffusion region of a traditional CMOS image sensor. It is far away from the shallow trench isolation, and a silicon-oxygen interface P-type heavily doped passivation layer 18 is provided at the edge of the shallow trench isolation, which is very beneficial for reducing dark current.

[0076] The manufacturing steps of the pixel unit of the CMOS image sensor provided in the embodiment of the present application may be as follows:

[0077] 1. Well injection module that performs standard CMOS process;

[0078] 2. Implanting a P-type isolation layer 13;

[0079] 3. Injection into the N region 42 of the photodiode PD;

[0080] 4. Implanting the first P-type medium doped layer 31;

[0081] Two masks are added to the CMOS image sensor process flow: one is used to implant the first P-type medium-doped layer 31 after shallow trench isolation and before gate oxidation; the other is used to implant the N-type medium-doped layer 43 and the N-type heavily-doped layer 44 in sequence after the sidewall process and before the source and drain implantation. Part of the implant dose of the N-type medium-doped layer 43 enters the first P-type medium-doped layer 31 at the bottom of the N-type medium-doped layer 43, causing it to naturally form the second P-type medium-doped layer 32.

[0082] 5. Gate formation module that performs standard CMOS process;

[0083] 6. Sidewall module that implements standard CMOS process;

[0084] 7. Implant a P-type heavily doped passivation layer to form shallow trench isolation;

[0085] 8. Implanting a heavily doped P-type passivation layer 18 at the silicon-oxygen interface;

[0086] 9. Injecting the N-type medium doped layer 43 and the N-type heavily doped layer 44 of the PN diode CPN;

[0087] 10. Perform source and drain implantation annealing of standard CMOS process;

[0088] 11. Perform metallization of standard CMOS process.

[0089] Please refer to FIG. 3 , which is a schematic diagram of a cross-sectional potential barrier of a pixel unit provided in an embodiment of the present application.

[0090] After the photodiode PD is reset, the potential of the N region of the photodiode PD is much higher than that of the above-mentioned P-type thin layer, and there is a very high potential barrier difference between the two; but the potential barrier difference between the photodiode PD and the surrounding P-type isolation layer 13 and the channel under the gate of the transfer transistor TG is even greater; as the photogenerated electrons accumulate in the photodiode PD, the potential of the photodiode PD also decreases, and the potential barrier difference with the above-mentioned P-type thin layer gradually decreases. When the potential barrier difference is lower than a few tenths of a volt, before the photogenerated electrons overflow into the floating diffusion area and the adjacent photodiode PD, the subsequently regenerated photogenerated electrons naturally overflow into the PN diode CPN and the MIM capacitor C2 in parallel therewith, so as to be subsequently utilized by circuits and algorithms.

[0091] The principles and implementation methods of the present application are described herein using specific examples, and the various embodiments are in a progressive relationship. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. The description of the above embodiments is only used to help understand the method and core ideas of the present application. For those of ordinary skill in the art, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0092] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

Claims

1. A pixel unit of a CMOS image sensor, characterized in that: The method comprises: a substrate on which a photodiode, an overflow device and a reset transistor are arranged; The overflow device includes a PN diode; The P region of the PN diode includes a first P-type doping layer and a second P-type doping layer; the doping concentration of the second P-type doping layer is less than the doping concentration of the first P-type doping layer; the first P-type doping layer surrounds the N region of the PN diode; the second P-type doping layer is located at the bottom of the N region of the PN diode, so that the N region of the PN diode is connected to the N region of the photodiode through the second P-type doping layer; Among all the P-type doped layers adjacent to the N region of the photodiode, the second P-type doped layer has the highest potential, so that the electrons overflowing from the N region of the photodiode are transmitted into the PN diode through the second P-type doped layer; The PN diode is connected to the reset transistor through a metal line.

2. The pixel unit of the CMOS image sensor according to claim 1, characterized in that: The overflow device further includes a capacitor; the capacitor is connected in parallel with the PN diode; and the capacitor is connected to the reset transistor through the metal line.

3. The pixel unit of the CMOS image sensor according to claim 2, characterized in that: The capacitor is a MIM capacitor; the positive electrode of the MIM capacitor is connected to the N region of the PN diode through a contact hole and the metal wire; the capacity of the MIM capacitor is greater than 100 times the capacity of the photodiode.

4. The pixel unit of the CMOS image sensor according to claim 1, characterized in that: The first P-type doped layer is a first P-type medium doped layer; The second P-type doped layer is a P-type lightly doped layer with a preset thickness, and the doping concentration of the P-type lightly doped layer is lower than 1×1013 / cm3; or, the second P-type doped layer is a second P-type medium-doped layer; the second P-type medium-doped layer overlaps with the N region of the PN diode on one side close to the N region of the PN diode.

5. The pixel unit of the CMOS image sensor according to claim 1, characterized in that: The doping concentration of the second P-type doping layer is lower than 3×10 17 / cm 3 .

6. The pixel unit of the CMOS image sensor according to claim 1, characterized in that: The reset transistor is an NMOS tube; The N region of the PN diode is connected to the source of the NMOS tube through the metal wire.

7. The pixel unit of the CMOS image sensor according to claim 1, characterized in that: The second P-type doping layer is parallel to the surface of the substrate, so that the electrons overflowing from the N region of the photodiode are transmitted into the PN diode through the second P-type doping layer in a direction perpendicular to the surface of the substrate.

8. The pixel unit of the CMOS image sensor according to claim 1, characterized in that: The PN diode is located in the N region of the photodiode away from the end connected to the transfer transistor; Alternatively, the PN diode is located in an upper center region of the photodiode.

9. The pixel unit of the CMOS image sensor according to claim 1, characterized in that: The distance between the N region of the PN diode and the shallow trench isolation is greater than 0.15 μm; the shallow trench isolation is used to isolate the active regions of adjacent pixel units.

10. The pixel unit of a CMOS image sensor according to any one of claims 1 to 9, characterized in that: The N region of the PN diode includes an N-type heavily doped layer and an N-type medium doped layer; The second P-type doping layer is located at the bottom of the N-type medium doping layer, so that the N-type medium doping layer is connected to the N region of the photodiode through the second P-type doping layer.

11. A CMOS image sensor, characterized in that: include: A plurality of pixel units; The pixel unit is the pixel unit according to any one of claims 1 to 10.

Images