Indium phosphide substrate and semiconductor epitaxial wafer

Abstract

This indium phosphide substrate has a diameter of at least 50 mm; the waviness Wz of the entire substrate surface excluding the edge region is not more than 800 nm; and the waviness Wz of the entire substrate surface excluding the edge region is measured by the following procedures (1) and (2).　(1) The region within 5 mm from the outer periphery toward the center is defined as the "edge region", and the entire surface of the wafer, excluding the region within 5 mm from the outer periphery of the wafer toward the center thereof, is defined as the "entire substrate surface excluding the edge region".　(2) The waviness Wz is measured using the white light interferometry function of a laser microscope. Defining the center in the short direction on the substrate surface in a 1 mm × 40 mm range as a reference line and defining 20 line portions on a 4.5 μm interval as one measurement interval, the waviness is determined over 40 mm in the long direction for a total of 11 lines, i.e., the reference line and 10 surrounding lines displaced in parallel with respect to the short direction, and the average value thereof is taken to be the waviness Wz.

Description

Indium phosphide substrates and semiconductor epitaxial wafers

[0001] The present invention relates to indium phosphide substrates and semiconductor epitaxial wafers.

[0002] Indium phosphide (InP) is a III-V compound semiconductor material consisting of indium (In) of group III and phosphorus (P) of group V. Its semiconductor properties are a band gap of 1.35 eV and an electron mobility of up to 5400 cm 2 / V·s, and has the property that its electron mobility under a high electric field is higher than that of other common semiconductor materials such as silicon and gallium arsenide. In addition, its stable crystal structure at room temperature and pressure is a cubic zinc blende structure, and its lattice constant is characterized by being larger than that of compound semiconductors such as gallium arsenide (GaAs) and gallium phosphide (GaP).

[0003] In silicon photonics, a device is created by epitaxially growing an InP substrate and then bonding it to a Si substrate using bonding or other methods. In this bonding process, adhesion between the InP epitaxial growth layer and the Si device is extremely important for device performance. However, waviness on the substrate surface propagates to the film surface after epitaxial growth, which is thought to affect the accuracy of bonding. Thus, controlling the waviness of the InP epitaxial growth layer surface when bonding it to the Si device is extremely important.

[0004] Patent Document 1 discloses a technique for suppressing surface waviness of an InP wafer by performing mirror polishing on a rotary polishing table with a polishing cloth using a predetermined InP wafer mirror polishing liquid.

[0005] Patent Document 2 discloses a method for grinding semiconductor wafers, in which semiconductor wafers are attached to the surfaces of multiple disk-shaped chucks rotatably arranged on a circle, a disk-shaped grinding wheel at least the size of the circumference is rotated in the direction opposite to the rotation of the chucks, and water and then drying gas are sprayed from a nozzle provided at the center of the grinding wheel, in which the chuck and the grinding wheel are brought relatively close to each other in the direction of the rotation axis to maintain a constant contact area between the wafer and the grinding wheel, and multiple wafers are ground together to a predetermined thickness. In this method, the chuck and the grinding wheel are brought relatively close to each other in the direction of the rotation axis to bring them into contact with each other, water and then drying gas are sprayed from the nozzle, and the grinding wheel grinds the surfaces of multiple wafers together to a predetermined thickness, thereby suppressing waviness of the substrate.

[0006] Patent Document 3 discloses a method for polishing indium phosphide, characterized by using a mixed solution of a solution of bromine dissolved in methyl alcohol and an aqueous solution of silica colloid. By polishing the substrate by adjusting the mixed solution in this way, waviness of the substrate due to etch pits is suppressed.

[0007] Japanese Patent Publication No. 07-027881 Publication of Patent No. 3316939 Publication of Japanese Unexamined Patent Publication No. 58-145604

[0008] As mentioned above, when epitaxial growth is performed on an InP substrate and then bonded to a Si substrate to form a device, adhesion between the InP epitaxial growth layer and the Si device is extremely important for the device characteristics, but waviness on the substrate surface propagates to the film surface after epitaxial growth and is thought to affect the accuracy of bonding. For this reason, if epitaxial growth is performed using an InP substrate with large waviness over the entire surface, there is a problem of poor bonding.

[0009] The techniques disclosed in Patent Documents 1 and 2 are intended to suppress waviness of the substrate, but there is no disclosure as to the extent to which waviness is suppressed over the entire substrate.

[0010] Furthermore, the technology disclosed in Patent Document 3 is for suppressing undulations of a substrate caused by etch pits, and focuses on local undulations of the substrate and relates to a technology for suppressing the local undulations. Thus, Patent Document 3 does not disclose a technology for suppressing undulations over the entire substrate.

[0011] The present invention has been made to solve the above-mentioned problems, and has an object to provide an indium phosphide substrate and a semiconductor epitaxial wafer with reduced surface waviness.

[0012] The above problems are solved by the embodiments of the present invention specified as follows: (1) An indium phosphide substrate having a diameter of 50 mm or more, and having a waviness Wz of 800 nm or less across the entire substrate surface excluding the edge portions. (2) The indium phosphide substrate according to (1), having a waviness Wz of 500 to 800 nm across the entire substrate surface excluding the edge portions. (3) The indium phosphide substrate according to (1) or (2), having a diameter of 50 to 150 mm. (4) A semiconductor epitaxial wafer comprising the indium phosphide substrate according to any one of (1) to (3) and an epitaxial crystal layer provided on a primary surface of the indium phosphide substrate.

[0013] According to the embodiments of the present invention, it is possible to provide an indium phosphide substrate and a semiconductor epitaxial wafer with reduced surface waviness.

[0014] 1 is a schematic diagram of the surface of an indium phosphide substrate according to an embodiment of the present invention, and FIG. 2 is a schematic diagram of the wafer surface for explaining a method of calculating waviness Wz.

[0015] Next, embodiments of the present invention will be described in detail with reference to the drawings. It should be understood that the present invention is not limited to the following embodiments, and that appropriate design changes and improvements may be made based on the ordinary knowledge of those skilled in the art without departing from the spirit of the present invention.

[0016] [Indium Phosphide Substrate] The configuration of the indium phosphide substrate of this embodiment will be described below. The indium phosphide (InP) substrate of this embodiment includes a substrate front surface (main surface), a substrate back surface, and an edge portion. The edge portion may have an orientation flat (OF) indicating the crystal orientation and an index flat (IF) for distinguishing the main surface from the back surface of the substrate.

[0017] The primary surface of the indium phosphide substrate can be a surface for forming an epitaxial crystal layer. The surface for forming an epitaxial crystal layer is the surface on which epitaxial growth is actually performed when the indium phosphide substrate of this embodiment is used as a substrate for epitaxial growth to form a semiconductor device structure.

[0018] The main surface of the indium phosphide substrate is formed to have a diameter of 50 mm or more. The diameter of the main surface of the indium phosphide substrate may be 50 to 150 mm. The planar shape of the indium phosphide substrate may be circular or rectangular, such as square.

[0019] The thickness of the indium phosphide substrate is not particularly limited, but is preferably 300 to 900 μm, and more preferably 300 to 700 μm, for example. In particular, when the diameter (caliber) of the indium phosphide substrate is large, if the thickness of the indium phosphide substrate is less than 300 μm, there is a risk of cracking, and if it exceeds 900 μm, there may be a problem in that the base crystal is wasted.

[0020] The indium phosphide substrate of this embodiment contains Zn (zinc) as a dopant (impurity) with a carrier concentration of 1×10 16 cm -3 1x10 or more 19 cm -3 or less, and S (sulfur) may be contained so that the carrier concentration is 1×10 16 cm -3 1x10 or more 19 cm -3 Sn (tin) may be contained so that the carrier concentration is 1×10 16 cm -3 1x10 or more 19 cm -3or less, and Fe (iron) may be contained so that the resistivity is 1×10 5 Ωcm or more 1×10 8 It may be contained so as to be Ωcm or less.

[0021] Fig. 1 shows a schematic diagram of the surface of an indium phosphide substrate according to an embodiment of the present invention. The indium phosphide substrate is formed in a substantially disk shape and has an OF and an IF. Note that Fig. 1 is a diagram for understanding the edge portion of the indium phosphide substrate according to an embodiment of the present invention, and the indium phosphide substrate according to an embodiment of the present invention is not limited to such a shape. In particular, it is not necessary for the indium phosphide substrate to have an OF and an IF.

[0022] In the indium phosphide substrate according to the embodiment of the present invention, the waviness Wz of the entire substrate surface excluding the edge portion is controlled to 800 nm or less. Here, in the present invention, the region within approximately 5 mm from the outer periphery of the wafer to the center, excluding the influence of roll-off, is defined as the "edge portion," and the entire wafer surface excluding the region within 5 mm from the outer periphery of the wafer to the center, excluding the influence of roll-off, is defined as the "entire substrate surface excluding the edge portion." That is, in the present invention, the "entire substrate surface excluding the edge portion" refers to the central circular region shown as the "waviness measurement area" in FIG. 1.

[0023] Since the entire surface of the wafer is ground simultaneously, the measurement of the center portion represents the waviness of the entire wafer, excluding the edge portion (the area within approximately 5 mm from the outer periphery to the center) where roll-off occurs due to the effects of polishing. In addition, since waviness is periodic, it is thought to be constant regardless of diameter.

[0024] In the present invention, the "waviness Wz" of the entire substrate surface excluding the edge portions is the "maximum waviness height" defined in JIS B 0601: 2013. By measuring the waviness Wz, it is possible to quantify the average value of the waviness of the entire substrate surface excluding the edge portions.

[0025] The waviness Wz of the entire substrate surface excluding the edge portions of the indium phosphide substrate can be measured using the white light interferometry function of a laser microscope VKX-3000 manufactured by Keyence Corp. When measuring the waviness Wz of the entire substrate surface excluding the edge portions of the indium phosphide substrate, a 10x interferometric lens is used to measure the waviness (Wz: maximum height waviness) curve as a profile curve in an area of ​​approximately 1 mm x 40 mm, with the center of the wafer being the center of the measurement range, and the waviness is determined with a cutoff wavelength λc of 25 mm. To calculate the waviness Wz, as shown in Figure 2, the center of the short side of the substrate surface within an area of ​​approximately 1 mm x 40 mm is used as a reference line, and 20 lines spaced approximately 4.5 μm apart (the basic interval specified for the VKX-3000 laser microscope) are used as one measurement interval (approximately 4.5 μm x 20 lines = approximately 90 μm intervals). The waviness is calculated over a 40 mm longitudinal direction, including 10 surrounding lines moved parallel to the short side and 11 reference lines, and the average value is taken as Wz. This average value is automatically measured using the white light interferometry function of the VKX-3000 laser microscope manufactured by Keyence Corporation. Measurements are performed in a clean room maintained at a room temperature of 22 ± 5°C to ignore the effects of thermal expansion and other factors. The various settings for the white light interferometry function of the VKX-3000 laser microscope are as follows:・Tilt correction: Automatic ・DCL / BCL: None ・Measurement type: Waviness ・Cutoff wavelength: λs and λf are not set. λc is 25 mm. ・End effect correction: Enabled ・Double Gaussian: OFF ・Stylus mode: OFF ・Number of reference wavelengths: 1 ・Number of profiles: 11 Because the entire surface of the wafer is ground simultaneously, there is no position dependency within the surface, and evaluating the waviness curve of the above part will result in a representative measurement of the waviness of the entire wafer, which is necessary for the bonding process. Furthermore, because the waviness is periodic, it is thought to be constant regardless of the diameter.

[0026] When the waviness Wz of the entire substrate surface excluding the edge portions of the indium phosphide substrate is 800 nm or less, the surface waviness after epitaxial growth is reduced, and even when bonded to a Si substrate including a Si device, an indium phosphide substrate can be provided in which poor adhesion due to the influence of waviness is effectively suppressed. The waviness Wz of the entire substrate surface excluding the edge portions of the indium phosphide substrate is preferably 700 nm or less, and more preferably 680 nm or less. Furthermore, the lower limit of the waviness Wz is not particularly limited, but Wz may be 500 to 800 nm.

[0027] [Method of Manufacturing Indium Phosphide Substrate] Next, a method of manufacturing an indium phosphide substrate according to an embodiment of the present invention will be described. In the method of manufacturing an indium phosphide substrate, first, an indium phosphide ingot is produced by a known method. Next, the indium phosphide ingot is ground to form a cylinder. At this time, an orientation flat (OF) and an index flat (IF) may be formed at predetermined positions on the outer periphery of the wafer. Next, wafers having a main surface and a back surface are cut out from the ground indium phosphide ingot. At this time, both ends of the crystal of the indium phosphide ingot are cut along predetermined crystal planes using a wire saw or the like, and multiple wafers with a thickness of 750 to 850 μm are cut out.

[0028] In the process of cutting out the wafers, it is preferable to constantly feed new wire while reciprocating the wire horizontally, and to move the stage carrying the indium phosphide ingot vertically toward the wire.

[0029] The conditions for cutting the ingot with a wire saw are as follows: - New wire feed speed: 10 to 60 m / min - Wire reciprocating speed: 300 to 350 m / min - Vertical movement speed of the stage carrying the indium phosphide ingot: 200 to 400 μm / min - Wire saw abrasive grain management: Abrasive grain GC #1200 and cutting oil PS-LP-500D are used, and the abrasive grain is managed so that the viscosity is 300 to 400 mPa s when the rotor shaft of the viscometer rotates at a speed of 60 rpm. The viscosity can be measured using a TVB-10 viscometer manufactured by Toki Sangyo Co., Ltd.

[0030] Next, in order to remove the process-affected layer generated in the cutting process using the wire saw, the cut wafer is etched on both sides with a predetermined etching solution (primary etching). The wafer can be etched by immersing the entire wafer in the etching solution. For example, the etching solution is a mixed solution of 85% by mass of phosphoric acid aqueous solution and 30% by mass of hydrogen peroxide solution, and it is preferable to etch a total of 5 to 15 μm from both sides.

[0031] Next, the outer periphery of the wafer is chamfered to a diameter of 50 mm or more. After chamfering, both sides of the wafer are roughly polished. This rough polishing process is also called a lapping process, and involves polishing with a specified abrasive to remove irregularities on the wafer surface while maintaining the wafer's flatness. Here, when cutting with the above-mentioned wire saw, undulations occur across the entire wafer due to wire vibration. The inventors have found that in order to remove this, it is necessary to remove the undulations by lapping after slicing (the process of cutting wafers from an ingot). Specifically, a lapping process is performed at a pressure of 100 g / cm. 2 While applying the above pressure, it is necessary to remove a total thickness of 100 μm or more from the front and back surfaces of the wafer by lapping. In order to obtain a large amount of lapping, it is preferable to increase the thickness of the wafer during slicing as necessary.

[0032] Next, the wafer is etched on both sides with a predetermined etching solution (secondary etching). The wafer can be etched by immersing the entire wafer in the etching solution. The etching solution is, for example, a mixed solution of 85% by mass of phosphoric acid aqueous solution, 30% by mass of hydrogen peroxide solution, and ultrapure water, and it is preferable to etch a total of 7 to 15 μm from both sides with the mixed solution.

[0033] Next, both sides of the wafer are polished. This step is for removing waviness that cannot be completely removed by the lapping step described above, and from the viewpoint of productivity, it is preferable to simultaneously polish multiple wafers on both sides. In order to uniformly remove waviness across the surface of all wafers polished simultaneously, when polishing both sides of the wafer with the upper and lower surface plates, it is necessary to supply a sufficient amount of polishing liquid to the wafer from multiple polishing liquid supply ports so that the polishing liquid fully penetrates the entire polishing pads provided on the upper and lower surface plates. Specifically, a flow rate of 0.07 mL / min cm per area of ​​the upper or lower surface plate is required. 2 By supplying the polishing liquid at this flow rate, uniform polishing of both sides of the wafer becomes possible. As a result, it becomes possible to remove waviness that cannot be completely eliminated in the lapping process. In this way, the waviness Wz of the entire substrate surface, excluding the edge portion, can be controlled to 800 nm or less.

[0034] Next, the main surface of the wafer is polished with a polishing material for mirror polishing to a mirror finish. Next, cleaning is performed to produce an indium phosphide substrate according to an embodiment of the present invention. Alternatively, after the mirror finish, etching, mirror polishing, cleaning, etc. may be performed to produce an indium phosphide substrate.

[0035] [Semiconductor Epitaxial Wafer] By epitaxially growing a semiconductor thin film on the main surface of an indium phosphide substrate according to an embodiment of the present invention using a known method, an epitaxial crystal layer can be formed, thereby producing a semiconductor epitaxial wafer. As an example of the epitaxial growth, a HEMT structure can be formed by epitaxially growing an InAlAs buffer layer, an InGaAs channel layer, an InAlAs spacer layer, and an InP electron supply layer on the main surface of the indium phosphide substrate. When producing a semiconductor epitaxial wafer having such a HEMT structure, a mirror-finished indium phosphide substrate is typically etched with an etchant such as sulfuric acid / hydrogen peroxide to remove impurities such as silicon (Si) adhering to the substrate surface. After this etching process, the back surface of the indium phosphide substrate is supported by contacting it with a susceptor, and an epitaxial crystal layer is formed on the main surface of the indium phosphide substrate by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD).

[0036] The semiconductor epitaxial wafer according to the embodiment of the present invention is fabricated using the indium phosphide substrate according to the embodiment of the present invention in which waviness of the entire substrate surface is suppressed as described above. Therefore, the surface waviness after epitaxial growth is reduced, and even when the wafer is bonded onto a Si substrate including a Si device, poor adhesion due to the influence of waviness is effectively suppressed.

[0037] The following examples are provided to provide a better understanding of the present invention and its advantages, but the present invention is not limited to these examples.

[0038] Examples 1 and 2 Examples 1 and 2 were fabricated as follows. First, an indium phosphide ingot was prepared. Next, the indium phosphide ingot was ground into a cylindrical shape. At this time, an orientation flat (OF) and an index flat (IF) were formed at predetermined positions on the outer periphery of the wafer. Next, wafers having a main surface and a back surface were cut out from the ground indium phosphide ingot. At this time, both ends of the crystal of the indium phosphide ingot were cut along predetermined crystal planes using a wire saw or the like, and multiple wafers with a thickness of 0.84 mm were cut out.

[0039] In the process of cutting out the wafers, the wire was moved back and forth horizontally while new wire was constantly being fed, and the stage carrying the indium phosphide ingot was moved vertically toward the wire.

[0040] The conditions for cutting the ingot with a wire saw are as follows: - New wire feed speed: 10 to 60 m / min - Wire reciprocating speed: 320 m / min - Vertical movement speed of the stage carrying the indium phosphide ingot: 330 μm / min - Wire saw abrasive grain management: Abrasive grain GC #1200 and cutting oil PS-LP-500D were used, and the abrasive grain was managed so that the viscosity was 300 to 400 mPa s when the rotor shaft of the viscometer rotated at a speed of 60 rpm. The viscosity can be measured using a TVB-10 viscometer manufactured by Toki Sangyo Co., Ltd.

[0041] Next, in order to remove the damaged layer generated during the cutting process using the wire saw, the cut wafer was etched from both sides to a total depth of 15 μm using a mixed solution of 85% by mass of phosphoric acid aqueous solution and 30% by mass of hydrogen peroxide solution (primary etching). The wafer was etched by immersing the entire wafer in the etching solution.

[0042] Next, the outer periphery of the wafer was chamfered to a diameter of 50 mm or more. After chamfering, both sides of the wafer were roughly polished (lapped). Specifically, the wafer was polished at a pressure of 150 g / cm 2 While applying a pressure of 120 μm, a total thickness of 120 μm was removed from the front and back surfaces of the wafer by lapping.

[0043] Next, the wafer was etched from both sides to a total depth of 7 μm using a mixed solution of 85% by mass of phosphoric acid aqueous solution, 30% by mass of hydrogen peroxide solution, and ultrapure water (secondary etching). The wafer was etched by immersing the entire wafer in the etching solution.

[0044] Next, both sides of the wafer were polished. This process was intended to remove any waviness that could not be completely removed by the lapping process described above. In this double-side polishing process, when both sides of the wafer were polished using the upper and lower surface plates, a sufficient amount of polishing liquid was supplied to the wafer from multiple polishing liquid supply ports so that the polishing liquid would fully penetrate the entire polishing pads provided on the upper and lower surface plates. Specifically, the polishing liquid was supplied at a rate of 0.072 mL / min cm per area of ​​the upper or lower surface plate. 2 The polishing solution was supplied at a flow rate of 5608 cm2 (total amount of polishing solution). 2 It was.

[0045] Next, the main surface of the wafer was polished with a polishing material for mirror polishing to a mirror finish, and then washed to prepare an indium phosphide substrate sample having a diameter of 76.2 mm and the shape shown in FIG.

[0046] (Comparative Examples 1 to 5) In each of Comparative Examples 1 to 5, a total thickness of 40 μm was removed by lapping on the front and back surfaces of the wafer in the lapping step, and the total amount of the polishing liquid was 0.065 mL / min cm in the double-side polishing step after the secondary etching. 2 A sample of an indium phosphide substrate having a diameter of 76.2 mm and a shape as shown in FIG. 1 was produced under the same conditions as in Examples 1 and 2, except that:

[0047] (Evaluation of Waviness Wz) For the indium phosphide substrate samples of Examples 1 and 2 and Comparative Examples 1 to 5, the waviness Wz of the entire substrate surface excluding the edge portion was measured using the following method. That is, for each sample of the indium phosphide substrate having a diameter of 76.2 mm and having IF and OF as shown in FIG. 1 in Examples 1 and 2 and Comparative Examples 1 to 5, the region within approximately 5 mm from the outer periphery to the center was defined as the "edge portion," and the entire wafer surface excluding the region within 5 mm from the outer periphery to the center of the wafer, excluding the influence of roll-off, was defined as the "entire substrate surface excluding the edge portion." Next, the waviness Wz of the waviness measurement area was measured using the white light interferometry function of a laser microscope VKX-3000 manufactured by Keyence Corporation. For this measurement, a 10x magnification lens for interference measurement was used to measure the waviness curve in an area of ​​approximately 1 mm x 40 mm, with the center of the wafer being the center of the measurement range, and the waviness was determined with a cutoff wavelength λc of 25 mm. To calculate the waviness Wz, as shown in Figure 2, the center of the short side of the substrate surface within an area of ​​approximately 1 mm x 40 mm was used as a reference line, and 20 lines spaced approximately 4.5 μm apart (the basic interval specified for the VKX-3000 laser microscope) were used as one measurement interval (approximately 4.5 μm x 20 lines = approximately 90 μm intervals). The waviness was measured over a 40 mm longitudinal direction, including 10 surrounding lines moved parallel to the short side and 11 reference lines, and the average value was taken as Wz. This average value was automatically measured using the white light interferometry function of a VKX-3000 laser microscope manufactured by Keyence Corporation. The measurement was performed in a clean room maintained at a room temperature of 22 ± 5°C to ignore the effects of thermal expansion and other factors. The various settings for the white light interferometry function of the VKX-3000 laser microscope were as follows: Tilt correction: Automatic DCL / BCL: None Measurement type: Waviness Cutoff wavelength: λs and λf not set. λc is 25 mm End effect correction: Enabled Double Gaussian: OFF Stylus mode: OFF Number of reference wavelengths: 1 Number of profiles: 11 The above manufacturing conditions and evaluation results are shown in Table 1.

[0048]

[0049] (Discussion) In both Examples 1 and 2, the waviness Wz of the entire substrate surface excluding the edge portion was 800 nm or less, and the surface waviness was well suppressed. In contrast, in all of Comparative Examples 1 to 5, the waviness Wz of the entire substrate surface excluding the edge portion exceeded 800 nm. Note that in Examples 1 and 2, the total lapping amount on the front and back surfaces of the wafer was the same, 120 μm, and the total amount of polishing liquid on the front and back surfaces of the wafer was also 0.072 mL / min cm 2 However, the waviness Wz of the entire substrate surface excluding the edge portion was 572.7 nm and 668.8 nm, which were different values. Similarly, in Comparative Examples 1 to 5, the total lapping amount of the front and back surfaces of the wafer was the same as 40 μm, and the total amount of polishing liquid on the front and back surfaces of the wafer was also 0.065 mL / min cm 2 However, the waviness Wz of the entire substrate surface excluding the edge portion varied between 895.4 and 1097.2 nm. This is thought to be because the waviness after cutting differs due to variations in temperature during wire saw cutting.

Claims

1. An indium phosphide substrate having a diameter of 50 mm or more, a waviness Wz of the entire substrate surface excluding the edge portion of 800 nm or less, and the waviness Wz of the entire substrate surface excluding the edge portion being measured by the following steps (1) to (2). (1) For an indium phosphide substrate, the area within 5 mm from the periphery to the center is defined as the "edge portion," and the entire wafer surface excluding the area within 5 mm from the periphery to the center of the wafer is defined as the "entire substrate surface excluding the edge portion." (2) Next, the waviness Wz is measured using the white light interference measurement function of a laser microscope. In the above measurement, a 10x lens for interference measurement is used to measure the waviness curve in a 1 mm x 40 mm range with the center of the wafer being the center of the measurement range, and the waviness is determined with a cutoff wavelength λc = 25 mm. When calculating the waviness Wz, the center of the short side of the substrate surface in an area of ​​1 mm x 40 mm is used as a reference line, and 20 lines spaced 4.5 μm apart are used as one measurement interval. The waviness over a longitudinal direction of 40 mm is calculated for a total of 11 lines, including 10 surrounding lines moved parallel to the short side direction and the reference line, and the average value is used as the waviness Wz.

2. The indium phosphide substrate according to claim 1, wherein the waviness Wz of the entire substrate surface excluding the edges is 500 to 800 nm.

3. The indium phosphide substrate according to claim 1 or 2, wherein the diameter is 50 to 150 mm.

4. A semiconductor epitaxial wafer comprising the indium phosphide substrate according to claim 1 or 2, and an epitaxial crystal layer provided on a primary surface of the indium phosphide substrate.

5. A semiconductor epitaxial wafer comprising the indium phosphide substrate according to claim 3 and an epitaxial crystal layer provided on a principal surface of said indium phosphide substrate.

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