Chip packaging method, chip packaging structure, and terminal device

Abstract

A chip packaging method, which uses the principle of thermal expansion and cold contraction. The method comprises: firstly, putting a chip assembly at a first temperature, such that a deformation sheet in the chip assembly contracts; then putting the chip assembly in a circuit board provided with a groove, and adjusting the position of the chip assembly in the groove at a second temperature, such that solder pins of a chip correspond to a circuit layer of the circuit board, and the position of the chip assembly in the groove is relatively fixed; and performing reflow soldering at a third temperature, such that a conductive paste is connected to the circuit board and the chip, and the deformation sheet expands in a high-temperature environment and thus presses the chip, thereby improving the connection reliability of the chip and the circuit board. Further provided are a chip packaging structure and a terminal device.

Description

Chip packaging method, chip packaging structure and terminal device Technical Field

[0001] The present application relates to the field of chip packaging, and in particular to a chip packaging method, a chip packaging structure, and a terminal device. Background Art

[0002] Chips are typically embedded within circuit boards to minimize the size of the chip package. The thickness of the chip typically aligns with the direction of the circuit board stacking. During the chip packaging process, vias are drilled into the circuit board to electrically connect the chip and board. If the chip has dense solder pins, high precision is required in both drilling and plating the vias, otherwise poor soldering can occur.

[0003] Summary of the Invention

[0004] In view of this, it is necessary to provide a chip packaging method with good welding to solve the above problems.

[0005] A chip packaging method includes the following steps: forming a groove on a circuit board, the groove including a first side wall and a second side wall arranged opposite to each other, the circuit board including a circuit layer, the circuit layer being exposed to the first side wall; providing a chip assembly, the chip assembly including a chip, a conductive paste and a deformable sheet, the deformable sheet and the conductive paste being located on two opposite surfaces of the chip, exposing the chip assembly to a first temperature to shrink the deformable sheet; placing the chip assembly after the shrinkage of the deformable sheet in the groove, the deformable sheet being spaced apart from the second side wall; at a second temperature, the conductive paste contacts the circuit layer, and the deformable sheet contacts the second side wall; exposing the circuit board and the chip assembly to a third temperature for reflow soldering to electrically connect the conductive paste and the circuit layer, wherein the third temperature is greater than the second temperature, and the second temperature is greater than the first temperature.

[0006] In some embodiments of the present application, the chip packaging method further includes: filling the packaging layer in the groove; forming a through hole on the circuit board and removing the deformed sheet, exposing the surface of the chip facing away from the conductive paste to the through hole; and forming a conductive layer in the through hole.

[0007] In some embodiments of the present application, the thermal expansion coefficient of the deformable sheet is greater than the thermal expansion coefficient of the circuit board.

[0008] In some embodiments of the present application, the material of the deformable sheet is selected from one of zinc, copper, lead and aluminum.

[0009] In some embodiments of the present application, the groove is recessed along a first direction, the conductive paste, the chip, and the deformable sheet are stacked along a second direction, and the first direction and the second direction are perpendicular to each other.

[0010] In some embodiments of the present application, after the chip assembly with the deformable sheet shrunk is placed in the groove, the distance between the deformable sheet and the second side wall is greater than or equal to 0.56 μm.

[0011] In some embodiments of the present application, the first temperature is less than or equal to 0°C, and / or the third temperature is greater than or equal to 220°C.

[0012] A chip packaging structure includes a circuit board, a chip, a conductive paste, and a conductive layer. The circuit board includes a circuit layer and a dielectric layer stacked along a first direction; the chip includes a body and solder pins, with the solder pins disposed on the surface of the body along a second direction; the conductive paste is disposed between the circuit layer and the solder pins along the second direction to electrically connect the solder pins and the circuit layer; and the conductive layer extends through the circuit board along the first direction and is connected to the surface of the body facing away from the solder pins.

[0013] In some embodiments of the present application, the first direction and the second direction are perpendicular to each other.

[0014] A terminal device includes a chip packaging structure.

[0015] A chip packaging method utilizes the principle of thermal expansion and contraction. A chip assembly is first placed in a low-temperature environment (i.e., a first temperature) to cause a deformable sheet in the chip assembly to contract. The chip assembly is then placed in a circuit board with a groove. The position of the chip assembly in the groove is adjusted in a normal temperature environment (i.e., a second temperature) so that the solder pins of the chip correspond to the circuit layer of the circuit board and the position of the chip assembly in the groove is relatively fixed. Reflow soldering is performed in a high-temperature environment (i.e., a third temperature) so that the conductive paste connects the circuit board and the chip. The deformable sheet expands and squeezes the chip in the high-temperature environment to increase the connection reliability between the chip and the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG1 is a schematic cross-sectional view of a circuit board after a groove is formed according to an embodiment of the present application.

[0017] FIG. 2 is a schematic diagram of a process of placing the chip assembly at a first temperature to shrink the deformable sheet in an embodiment of the present application.

[0018] FIG. 3 is a cross-sectional view of the chip assembly after shrinkage shown in FIG. 2 being placed in the groove of FIG. 1 .

[0019] FIG4 is a cross-sectional view of the circuit board and chip assembly shown in FIG3 after being placed in a second temperature to allow the deformed piece to recover its size.

[0020] FIG5 is a cross-sectional view of the circuit board and chip assembly shown in FIG4 after being subjected to reflow soldering at a third temperature.

[0021] FIG. 6 is a cross-sectional view of the circuit board and chip assembly after being subjected to reflow soldering shown in FIG. 5 and placed at a second temperature.

[0022] FIG. 7 is a cross-sectional schematic diagram showing the groove shown in FIG. 6 and the surface of the circuit board after a packaging layer is formed.

[0023] FIG8 is a cross-sectional schematic diagram showing a copper clad laminate provided on the surface of the packaging layer and the circuit board shown in FIG7 .

[0024] FIG9 is a schematic cross-sectional view of the circuit board shown in FIG8 after a through hole is formed.

[0025] FIG10 is a schematic cross-sectional view of a chip packaging structure obtained after forming a conductive layer in the through hole of FIG9 and performing circuit fabrication on the copper clad laminate.

[0026] FIG11 is a schematic structural diagram of a partial area of ​​the chip packaging structure of FIG10.

[0027] FIG12 is a schematic diagram of the structure of a terminal device provided in an embodiment of the present application.

[0028] Description of main component symbols DETAILED DESCRIPTION

[0029] In order to be able to more clearly understand the above-mentioned purposes, features and advantages of the present application, the present application is described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other. In the following description, many specific details are set forth in order to fully understand the present application. The embodiments described are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes all and any combinations of one or more of the relevant listed items.

[0031] In the various embodiments of the present application, for the sake of convenience of description and not limitation of the present application, the term "connection" used in the patent application specification and claims of the present application is not limited to physical or mechanical connection, whether direct or indirect. "Up", "down", "above", "below", "left", "right", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship also changes accordingly.

[0032] Referring to FIG. 1 to FIG. 11 , an embodiment of the present application provides a chip packaging method, which may include the following steps:

[0033] Step S1 : Referring to FIG. 1 , a groove 15 is formed on a circuit board 10 . The groove 15 includes a first sidewall 152 and a second sidewall 154 oppositely disposed. The circuit board 10 includes a circuit layer 13 , and the circuit layer 13 is exposed on the first sidewall 152 .

[0034] The circuit board 10 may be a flexible board, a rigid board, or a rigid-flex board. The circuit board 10 may further include a dielectric layer 11. A circuit layer 13 and the dielectric layer 11 are stacked along a first direction L1. The circuit layer 13 and the dielectric layer 11 may have one or more layers. In this embodiment, the circuit layer 13 has multiple layers.

[0035] The groove 15 is recessed along the first direction L1 and further includes a bottom wall 156. The bottom wall 156 connects the first side wall 152 and the second side wall 154. The first side wall 152, the second side wall 154, and the bottom wall 156 enclose the groove 15. In this embodiment, the first side wall 152 and the second direction L2 are both parallel to the first direction L1, and the bottom wall 156 is parallel to the second direction L2. The second direction L2 may be perpendicular to the first direction L1.

[0036] The groove 15 can be formed by laser cutting or mechanical drilling.

[0037] Step S2: Referring to FIG. 2 , a chip assembly 20 is provided. The chip assembly 20 includes a chip 21 , a conductive paste 25 , and a deformable sheet 23 . The deformable sheet 23 and the conductive paste 25 are located on opposite surfaces of the chip 21 . The chip assembly 20 is placed at a first temperature T1 to cause the deformable sheet 23 to shrink.

[0038] Chip 21 includes a body 212 and multiple solder pins 214. Solder pins 214 are located on the surface of body 212. Deformable sheet 23 is located on the surface of body 212 facing away from solder pins 214. Conductive paste 25 is located on the surface of each solder pin 214. The position of circuit layer 13 exposed in groove 15 corresponds to the position of the multiple conductive pastes 25. This is equivalent to groove 15 being recessed along first direction L1. Conductive paste 25, chip 21, and deformable sheet 23 are stacked along second direction L2, with first direction L1 and second direction L2 being perpendicular to each other.

[0039] The conductive paste 25 may be made of tin paste, silver paste, etc.

[0040] The thermal expansion coefficient of the deformable sheet 23 is greater than that of the circuit board 10, so as to ensure that in a subsequent high temperature environment, the expansion amplitude of the deformable sheet 23 is greater than that of the circuit board 10. The material of the deformable sheet 23 can be selected from zinc, copper, lead, aluminum, etc. In this embodiment, the material of the deformable sheet 23 is zinc, and the thermal expansion coefficient of zinc is 3.6×10 -5 K -1 .

[0041] In this embodiment, the chip assembly 20 is cooled from the second temperature T2 to the first temperature T1, and the second temperature T2 is greater than the first temperature T1. The second temperature T2 can be room temperature, such as 15°C-35°C, that is, a temperature that does not change with the help of external factors. When the chip assembly 20 is at the first temperature T1, the deformation piece 23 shrinks relative to the state at the second temperature T2, and the volume of the deformation piece 23 decreases. The first temperature T1 can be less than or equal to 0°C, such as -25°C, -40°C, -50°C, etc. In this embodiment, the chip assembly 20 is placed in a low temperature environment of -50°C to shrink the deformation piece 23. Among them, the material of the chip 21 is usually silicon, and the thermal expansion coefficient of silicon is 2.4×10 -6 K -1 , the thermal expansion coefficient of the deformable piece 23 is relatively small, and the shrinkage of the chip 21 at the first temperature T1 can be ignored.

[0042] Step S3 : Referring to FIG. 3 , the chip assembly 20 with the deformable sheet 23 contracted is placed in the groove 15 . The deformable sheet 23 can be spaced apart from the second sidewall 154 , that is, a first gap 252 is defined between the deformable sheet 23 and the second sidewall 154 .

[0043] After the chip assembly 20 has been at the first temperature T1 for a period of time, the chip assembly 20 is placed in the groove 15, with the conductive paste 25 facing the first sidewall 152 and the deformable sheet 23 facing the second sidewall 154. Along the second direction L2, the width of the chip assembly 20 is smaller than the width of the groove 15. Therefore, after the chip assembly 20 is placed in the groove 15 with the deformable sheet 23 contracted, a certain distance can be maintained between the deformable sheet 23 and the second sidewall 154. The chip assembly 20 can be adjusted in the groove 15 so that the conductive paste 25 aligns with the circuit layer 13.

[0044] In some embodiments, the distance between the deformable piece 23 and the second sidewall 154 is greater than or equal to 0.56 μm, so that the position of the chip component 20 in the groove 15 can be adjusted.

[0045] Step S4 : Please refer to FIG. 4 . At the second temperature T2 , the conductive paste 25 contacts the circuit layer 13 , and the deformable sheet 23 contacts the second sidewall 154 .

[0046] In this embodiment, after the chip assembly 20 is placed in the groove 15, the chip assembly 20 and the circuit board 10 are placed in an environment with a second temperature T2 of 24°C, and the deformable sheet 23 returns to its initial size. At this time, both sides of the chip assembly 20 are connected to the circuit board 10, that is, the conductive paste 25 is in contact with the circuit layer 13, and the deformable sheet 23 is in contact with the second side wall 154, which is conducive to reducing or avoiding the displacement of the chip assembly 20 in the groove 15 after the position of the conductive paste 25 and the circuit layer 13 correspond.

[0047] If the chip assembly 20 is not placed at the first temperature T1 but is directly placed in the groove 15, it is difficult to adjust the position of the chip assembly 20 in the groove 15, and it is difficult to ensure that the position of the conductive paste 25 corresponds to the position of the circuit layer 13. In the subsequent welding process, poor welding phenomena such as bridging and cracks are likely to occur; if the width of the groove 15 along the second direction L2 is increased, the chip assembly 20 is likely to be displaced in the groove 15. Even if the conductive paste 25 is matched with the position of the circuit layer 13 in advance, in the subsequent process, the chip assembly 20 is likely to be displaced in the groove 15, and the position of the conductive paste 25 and the circuit layer 13 will deviate, resulting in poor welding.

[0048] Step S5: Referring to FIG. 5 , the circuit board 10 and the chip assembly 20 are placed in a third temperature T3 for reflow soldering to electrically connect the conductive paste 25 and the circuit layer 13 . The third temperature T3 is greater than the second temperature T2 .

[0049] The third temperature T3 may be adjusted according to the type of the conductive paste 25 . For example, in some embodiments, the third temperature T3 may be greater than 220° C. For example, in this embodiment, the third temperature T3 is 250° C.

[0050] At the third temperature T3, the deformable sheet 23 and the circuit board 10 expand due to heat. Because the thermal expansion coefficient of the deformable sheet 23 is greater than that of the circuit board 10, the deformable sheet 23 expands more rapidly than the circuit board 10. This means that along the second direction L2, the width of the groove 15 is smaller than the width of the chip assembly 20. The expansion of the deformable sheet 23 exerts a force that compresses the components located on both sides of the deformable sheet 23. In other words, the deformable sheet 23 exerts a force that compresses the chip 21, causing it to move toward the first sidewall 152. Simultaneously, the conductive paste 25 becomes molten at the third temperature T3 and connects to the circuit layer 13. The deformable sheet 23 exerts a force that compresses the chip 21, further tightening the connection between the conductive paste 25 and the circuit layer 13. Using the conductive paste 25 to directly connect the solder fillet 214 to the circuit layer 13 eliminates the drilling and electroplating required to achieve conductivity in the related art.

[0051] Referring again to Figures 4 and 5 , when the chip assembly 20 is in an environment at the second temperature T2, the width of the deformable sheet 23 along the first direction L1 is smaller than the width of the body 212, and the projection of the deformable sheet 23 is located within the projection of the body 212. This allows the deformable sheet 23 to expand when the chip assembly 20 is in an environment at the third temperature T3. This prevents the deformable sheet 23 from deforming excessively in the first direction L1, which could cause the chip assembly 20 to move in the first direction L1 and thereby misalign the conductive paste 25 with the circuit layer 13.

[0052] Referring to FIG. 6 , when the temperature decreases, for example, to the second temperature T2, the conductive paste 25 solidifies and electrically connects the chip 21 and the circuit board 10. The chip assembly 20 moves a certain distance toward the first sidewall 152 relative to its position before reflow. The deformable piece 23 contracts and is spaced apart from the second sidewall 154, thereby defining a second gap 254 between the deformable piece 23 and the second sidewall 154. Since the chip assembly 20 moves a certain distance toward the first sidewall 152 after the reflow process, the width of the second gap 254 is greater than the width of the first gap 253 along the second direction L2.

[0053] Step S6 : Please refer to FIG. 7 , filling the groove 15 with a packaging layer 30 .

[0054] The packaging layer 30 may be filled between the conductive paste 25 and the first side wall 152 and between the deformable sheet 23 and the second side wall 154. The packaging layer 30 may also be located on the surface of the circuit board 10 where the groove 15 is formed.

[0055] Step S7 : Referring to FIG. 8 , a copper clad plate 40 is disposed on the surface of the packaging layer 30 facing away from the circuit board 10 .

[0056] In some embodiments, a build-up step can be added based on the number of layers required for the circuit layer 13. The copper clad laminate 40 is subsequently used to form the circuit substrate 41 to achieve the build-up of the circuit layer 13. In some implementations, step S7 can also be omitted.

[0057] Step S8: Please refer to Figures 9, 10 and 11, a through hole 50 is formed through the copper clad laminate 40 and the circuit board 10, and the deformed sheet 23 is removed. The surface of the chip 21 facing away from the conductive paste 25 is exposed to the through hole 50, and a conductive layer 51 is formed in the through hole 50.

[0058] A conductive layer 51 can be formed in the through-hole 50 by electroplating to obtain the chip package structure 100. The conductive layer 51 is connected to the surface of the chip 21 to achieve heat dissipation. The conductive layer 51 can also be connected to the circuit board 10 and the circuit layer 13 of the circuit substrate 41 to achieve electrical conduction.

[0059] The entire surface of the body 212 away from the solder pins 214 can be connected to the conductive layer 51 , thereby increasing the heat dissipation area and thus improving the heat dissipation effect.

[0060] By packaging the chip 21 in the circuit board 10 with the solder legs 214 facing the second direction L2 , the width of the chip package structure 100 along the second direction L2 can be reduced, so that the chip package structure 100 is suitable for an environment with a smaller installation space along the second direction L2 .

[0061] During the process of forming the conductive layer 51 , circuits are also fabricated on the copper clad laminate 40 to form a circuit substrate 41 .

[0062] Referring to FIG10 , an embodiment of the present application further provides a chip package structure 100, which may include a circuit board 10, a chip 21, a conductive paste 25, and an encapsulation layer 30. The conductive paste 25 connects the chip 21 and the circuit board 10, and the encapsulation layer 30 encapsulates the chip 21 in the circuit board 10.

[0063] The circuit board 10 includes a dielectric layer 11 and a circuit layer 13, which are stacked along a first direction L1. The chip 21 includes a body 212 and solder pins 214, which are disposed on the surface of the body 212 along a second direction L2. Conductive paste 25 is disposed along the second direction L2 between the circuit layer 13 and the solder pins 214 to electrically connect the solder pins 214 and the circuit layer 13. The first direction L1 and the second direction L2 may be perpendicular to each other. An encapsulation layer 30 is placed between the chip 21 and the circuit board 10.

[0064] The circuit board 10 further includes a conductive layer 51 , and the through hole 50 penetrates the circuit board 10 along the first direction L1 . The conductive layer 51 is connected to the surface of the body 212 away from the solder foot 214 . The conductive layer 51 can be used to quickly transfer the heat generated by the chip 21 during operation.

[0065] 12 , an embodiment of the present application further provides a terminal device 200 , which includes a chip package structure 100 . The terminal device 200 may be a mobile phone, a camera, a drone, a computer, a webcam, etc. In this embodiment, the terminal device 200 is a mobile phone.

[0066] The chip packaging method provided in the embodiment of the present application adopts the principle of thermal expansion and contraction. The chip assembly 20 is first placed in a low-temperature environment (i.e., a first temperature T1) to shrink the deformable sheet 23 in the chip assembly 20. The chip assembly 20 is then placed in a circuit board 10 having a groove 15. The position of the chip assembly 20 in the groove 15 is adjusted in a normal temperature environment (i.e., a second temperature T2) so that the solder pins 214 of the chip 21 correspond to the circuit layer 13 of the circuit board 10 and the position of the chip assembly 20 in the groove 15 is relatively fixed. Reflow soldering is performed in a high-temperature environment (i.e., a third temperature T3) so that the conductive paste 25 connects the circuit board 10 and the chip 21. The deformable sheet 23 expands and squeezes the chip 21 in the high-temperature environment to increase the connection reliability between the chip 21 and the circuit board 10.

[0067] The above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit the present application. Although the present application has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that modifications or equivalent replacements of the technical solutions of the present application should not depart from the spirit and scope of the technical solutions of the present application.

Claims

1. A chip packaging method, characterized in that, it includes: forming a groove on a circuit board, the groove includes a first side wall and a second side wall arranged oppositely, the circuit board includes a circuit layer, and the circuit layer is exposed on the first side wall; providing a chip component, the chip component includes a chip, a conductive paste and a deformation sheet, the deformation sheet and the conductive paste are located on two opposite surfaces of the chip, and placing the chip component in a first temperature to make the deformation sheet shrink; placing the chip component after the deformation sheet shrinks into the groove, and the deformation sheet is arranged at an interval from the second side wall; at a second temperature, the conductive paste contacts the circuit layer, and the deformation sheet contacts the second side wall; and placing the circuit board and the chip component in a third temperature for reflow soldering to electrically connect the conductive paste and the circuit layer, wherein the third temperature is greater than the second temperature, and the second temperature is greater than the first temperature.

2. The chip packaging method according to claim 1, characterized in that, the chip packaging method further includes: filling a packaging layer in the groove; forming a through hole on the circuit board and removing the deformation sheet, and the surface of the chip facing away from the conductive paste is exposed in the through hole; and forming a conduction layer in the through hole.

3. The chip packaging method according to claim 1 or 2, characterized in that, the coefficient of thermal expansion of the deformation sheet is greater than the coefficient of thermal expansion of the circuit board.

4. The chip packaging method according to claim 3, characterized in that, the material of the deformation sheet is selected from one of zinc, copper, lead and aluminum.

5. The chip packaging method according to claim 1 or 2, characterized in that, the groove is recessed along a first direction, the conductive paste, the chip and the deformation sheet are stacked along a second direction, and the first direction is perpendicular to the second direction.

6. The chip packaging method according to claim 1 or 2, characterized in that, after the chip component with the deformed sheet shrinks is placed in the groove, the distance between the deformed sheet and the second side wall is greater than or equal to 0.56 μm.

7. The chip packaging method according to claim 1 or 2, characterized in that, the first temperature is less than or equal to 0 °C, and / or the third temperature is greater than or equal to 220 °C.

8. A chip packaging structure, characterized in that, it includes: a circuit board, including a circuit layer and a dielectric layer stacked along a first direction; a chip, including a body and welding feet, the welding feet are arranged on the surface of the body along a second direction; a conductive paste, arranged between the circuit layer and the welding feet along the second direction to electrically connect the welding feet and the circuit layer; and a conduction layer, penetrating the circuit board along the first direction and connecting to the surface of the body facing away from the welding feet.

9. The chip packaging structure according to claim 8, characterized in that, the first direction is perpendicular to the second direction.

10. A terminal device, characterized in that, the terminal device includes the chip packaging structure according to any one of claims 8-9.

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