Driving control circuit, driving system, and display apparatus

Abstract

The present application relates to the technical field of displays, and discloses a driving control circuit, a driving system, and a display apparatus. The driving control circuit comprises: a voltage conversion sub-circuit, a first shunting sub-circuit, a conduction control sub-circuit and a second shunting sub-circuit. The voltage conversion sub-circuit outputs power supply voltage to a power supply end; the first shunting sub-circuit, on the basis of the power supply voltage of the power supply end, enables a current limiting node to generate a first voltage; in response to the first voltage of the current limiting node and the power supply voltage of the power supply end, the conduction control sub-circuit causes a control node to generate a control voltage, and generate a current flowing through the power supply end to the grounding end; in response to the voltage of the control node being higher than a first conduction threshold value, the second shunting sub-circuit connects the current limiting node and the grounding end, so that the current generated by the conduction control sub-circuit is shunted. The described configuration achieves the purpose of limiting the current of a power supply end, so that current flowing through the power supply end is effectively reduced, and the reliability of the power supply voltage is improved.

Description

Drive control circuit, drive system and display device Technical Field

[0001] The present application relates to the field of display technology and provides a drive control circuit, a drive system and a display device. Background Art

[0002] Currently, during the power-up process of Mini LED-related display devices, high current false triggering or parasitic oscillation of the power supply by the chip's internal power filter capacitors and other internal components can occur. Both of these situations can lead to the generation of high currents such as surges. Typically, the capacitors within the chip used to control Mini LED-related display devices can absorb a maximum current of 120mA. If this high current is even higher, it can damage the load resistors within the chip that handle logic functions, and in severe cases, cause the Mini LED-related display device to display poorly.

[0003] Summary of the Invention

[0004] The embodiments of the present application provide a drive control circuit, a drive system, and a display device for limiting the magnitude of the current at the power supply end, thereby effectively reducing the current flowing through the power supply end and improving the reliability of the power supply voltage.

[0005] The specific technical solutions provided in this application are as follows:

[0006] In a first aspect, an embodiment of the present application provides a drive control circuit, comprising: a voltage conversion subcircuit, a first shunt subcircuit, a conduction control subcircuit, and a second shunt subcircuit;

[0007] a voltage conversion subcircuit, configured to output the supply voltage to the power supply terminal;

[0008] The first shunt sub-circuit is coupled to the power supply terminal and the current limiting node, and is configured to generate a first voltage at the current limiting node according to the power supply voltage of the power supply terminal;

[0009] The conduction control subcircuit is coupled to the power supply terminal, the current limiting node, and the ground terminal, and is configured to generate a control voltage at the control node and a current flowing through the power supply terminal to the ground terminal in response to a first voltage at the current limiting node and a supply voltage at the power supply terminal;

[0010] The second shunt subcircuit is coupled to the control node, the current limiting node and the ground terminal, and is configured to conduct the current limiting node and the ground terminal in response to the voltage of the control node being greater than the first conduction threshold to shunt the current generated by the conduction control subcircuit.

[0011] Optionally, the first shunt sub-circuit includes: a first resistor;

[0012] A first end of the first resistor is coupled to the power supply end, and a second end of the first resistor is coupled to the current limiting node.

[0013] Optionally, the conduction control subcircuit includes: a load resistor, a first transistor, and a current limiting resistor;

[0014] A first end of the load resistor is coupled to the power supply end, and a second end of the load resistor is coupled to the first end of the first transistor;

[0015] The control terminal of the first transistor is coupled to the current limiting node, and the second terminal of the first transistor is coupled to the control node;

[0016] A first terminal of the current limiting resistor is coupled to the control node, and a second terminal of the current limiting resistor is coupled to the ground.

[0017] Optionally, the resistance of the first resistor is smaller than the resistance of the load resistor, and the resistance of the first resistor is smaller than the resistance of the current-limiting resistor.

[0018] Optionally, the second shunt sub-circuit includes: a shunt control unit and a second resistor;

[0019] a current shunting control unit configured to connect the current limiting node to the second resistor in response to a current value in the control node being greater than a first conduction threshold, so as to shunt the current generated by the conduction control subcircuit;

[0020] The second resistor is configured to divert the current generated by the conduction control subcircuit to the ground.

[0021] Optionally, the shunt control unit includes a first MOS transistor;

[0022] The control end of the first MOS transistor is coupled to the control node, the first end of the first MOS transistor is coupled to the current limiting node, and the second end of the first MOS transistor is coupled to the first end of the second resistor.

[0023] Optionally, the diversion control unit includes: a first diversion control subunit and a second diversion control subunit;

[0024] a first shunt control sub-unit configured to connect the current limiting node to the second resistor in response to the voltage of the AC component in the control node being greater than a first conduction threshold, so as to shunt the current generated by the conduction control sub-circuit;

[0025] The second shunt control sub-unit is configured to connect the current limiting node with the second resistor in response to the voltage of the DC component in the control node being greater than the first conduction threshold, so as to shunt the current generated by the conduction control sub-circuit.

[0026] Optionally, the first shunt control subunit includes: a capacitor and a second MOS transistor;

[0027] The first end of the capacitor is coupled to the control node, and the second end of the capacitor is coupled to the control end of the second MOS transistor;

[0028] The first end of the second MOS transistor is coupled to the current limiting node, and the second end of the second MOS transistor is coupled to the first end of the second resistor.

[0029] Optionally, the second shunt control subunit includes: an inductor and a third MOS tube;

[0030] The first end of the inductor is coupled to the control node, and the second end of the inductor is coupled to the control end of the third MOS transistor;

[0031] A first end of the third MOS transistor is coupled to the current limiting node, and a second end of the third MOS transistor is coupled to the first end of the second resistor.

[0032] Optionally, it further includes: a first voltage follower;

[0033] The positive input terminal of the first voltage follower is coupled to the control node, and the negative input terminal and the output terminal of the first voltage follower are coupled to the control terminal of the first MOS transistor.

[0034] Optionally, the first current shunt control subunit further includes: a second voltage follower;

[0035] The positive input terminal of the second voltage follower is coupled to the control node, and the negative input terminal and the output terminal of the second voltage follower are coupled to the control terminal of the second MOS transistor.

[0036] Optionally, the second current shunt control subunit further includes: a third voltage follower;

[0037] The positive input terminal of the third voltage follower is coupled to the control node, and the negative input terminal and the output terminal of the third voltage follower are coupled to the control terminal of the third MOS transistor.

[0038] Optionally, it further includes: a driver chip;

[0039] The voltage conversion sub-circuit, the first shunt sub-circuit, the conduction control sub-circuit and the second shunt sub-circuit are arranged inside the driving chip.

[0040] Optionally, it further includes: a driver chip;

[0041] The voltage conversion sub-circuit, the first shunt sub-circuit, the conduction control sub-circuit and the second shunt sub-circuit are arranged outside the driver chip, and the voltage conversion sub-circuit is coupled to the power pin of the chip.

[0042] Optionally, the current of the conduction control subcircuit does not exceed a current threshold, where the current threshold is a ratio of a threshold voltage of the first transistor to a current limiting resistor.

[0043] In a second aspect, an embodiment of the present application further provides a driving system, comprising: a first voltage conversion module, a second voltage conversion module, a driving interface module, and the above-mentioned driving control circuit;

[0044] a first voltage conversion module, configured to convert the power supply voltage into a supply voltage in response to a power-on enable trigger, and provide the supply voltage to the drive control circuit;

[0045] The second voltage conversion module is configured to receive an external power supply voltage in response to a power-on enable trigger, and provide the external power supply voltage to the Mini LED backlight panel via the driving interface module.

[0046] Optionally, a logic opening control module is further included;

[0047] The logic start control module is configured to send a start signal to the driver chip in response to a power-on enable trigger, so as to enable the driver chip to start the logic control function.

[0048] In a third aspect, an embodiment of the present application further provides a display device, comprising: the driving system and the Mini LED backlight panel as described above;

[0049] The driving system is coupled to the Mini LED backlight panel and is configured to provide a driving signal to the Mini LED backlight panel through the driving interface module.

[0050] In a fourth aspect, an embodiment of the present application further provides a drive control method, including:

[0051] The voltage conversion subcircuit outputs the supply voltage to the power supply terminal;

[0052] The first shunt sub-circuit causes the current limiting node to generate a first voltage according to the supply voltage of the power supply end;

[0053] The conduction control subcircuit responds to the first voltage of the current limiting node and the supply voltage of the power supply terminal, causing the control node to generate a control voltage and generate a current flowing through the power supply terminal to the ground terminal;

[0054] In response to the control node being greater than the first conduction threshold, the second shunting sub-circuit conducts the current limiting node and the ground terminal to shunt the current generated by the conduction control sub-circuit.

[0055] Optionally, when the first shunt sub-circuit is turned on and the second shunt sub-circuit is not turned on, the current generated by the conduction control sub-circuit is a ratio of the voltage of the control node to the current limiting resistor.

[0056] Optionally, when the first shunt sub-circuit is turned on and the second shunt sub-circuit is turned on, the current generated by the conduction control sub-circuit is a ratio of the threshold voltage of the first transistor to the current limiting resistor.

[0057] The beneficial effects of this application are as follows:

[0058] In summary, an embodiment of the present application provides a drive control circuit, a drive system, and a display device. The drive control circuit includes: a voltage conversion subcircuit, a first shunt subcircuit, a conduction control subcircuit, and a second shunt subcircuit. The voltage conversion subcircuit is configured to output the supply voltage to the power supply end. The first shunt subcircuit is coupled to the power supply end and the current limiting node, and is configured to cause the current limiting node to generate a first voltage according to the power supply voltage of the power supply end. The conduction control subcircuit is coupled to the power supply end, the current limiting node, and the ground end. It is configured to respond to the first voltage of the current limiting node and the power supply voltage of the power supply end, so that the control node generates a control voltage and generates a current flowing through the power supply end to the ground end. The second shunt subcircuit is coupled to the control node, the current limiting node, and the ground end. It is configured to conduct the current limiting node and the ground end in response to the voltage of the control node being greater than the first conduction threshold, so as to shunt the current generated by the conduction control subcircuit. The above-mentioned first shunt subcircuit and the second shunt subcircuit achieve the purpose of limiting the current of the power supply end, thereby effectively reducing the current flowing through the power supply end and improving the reliability of the power supply voltage.

[0059] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0061] FIG1 is a schematic diagram of a driving system in the related art;

[0062] FIG2 is a schematic diagram of a drive control circuit in the related art;

[0063] FIG3 is a schematic diagram of a waveform of a power supply voltage during a power-on process in the related art;

[0064] FIG4 is a connection diagram of a first drive control circuit according to an embodiment of the present application;

[0065] FIG5 is a circuit connection diagram of a first drive control circuit in an embodiment of the present application;

[0066] FIG6 is a schematic diagram showing the connection between the first drive control circuit and the power supply voltage in an embodiment of the present application;

[0067] FIG7 is a circuit connection diagram of a second drive control circuit in an embodiment of the present application;

[0068] FIG8 is a circuit connection diagram of a third drive control circuit in an embodiment of the present application;

[0069] FIG9 is a circuit connection diagram of a driving system according to an embodiment of the present application;

[0070] FIG10 is a circuit connection diagram of another driving system in the related art;

[0071] FIG11 is a simulation waveform diagram of the first drive control circuit in an embodiment of the present application;

[0072] FIG12 is a simulation waveform diagram of the second drive control circuit in an embodiment of the present application;

[0073] FIG13 is a simulation waveform diagram of a third drive control circuit in the related art;

[0074] FIG14 is a simulation waveform diagram of the fourth drive control circuit in an embodiment of the present application;

[0075] FIG15 is a simulation waveform diagram of the fifth drive control circuit in an embodiment of the present application;

[0076] FIG16 is a simulation waveform diagram of a sixth drive control circuit in the related art;

[0077] FIG17 is a flow chart of a driving control method in an embodiment of the present application. DETAILED DESCRIPTION

[0078] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of the technical solutions of this application, but not all of them. Based on the embodiments described in this application document, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the technical solutions of this application.

[0079] The terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be practiced using orders other than those illustrated or described herein.

[0080] In the prior art, during the power-up process of Mini LED-related display devices, high current false triggering or parasitic oscillation of the power supply by the chip's internal power filter capacitors and other internal components can occur. Both of these situations can lead to the generation of high currents such as surges. Typically, the capacitors within the chip used to control Mini LED-related display devices can absorb a maximum current of 120mA. When this high current is even higher, it can damage the load resistors within the chip that handle logic functions, and in severe cases, cause the Mini LED-related display device to display poorly.

[0081] Referring to Figures 1, 2 and 3, the power filter capacitor inside the chip and other devices inside the chip generate parasitic oscillations on the power supply to illustrate the situation. When the power-on enable signal EN rises to about 80%, that is, when the power supply voltage AVDD is approximately equal to the power supply voltage DVDD, the internal circuit of the chip starts to work. Taking the capacitor inside the chip that can absorb a maximum current of 120mA as an example, the large overshoot current (140mA-120mA) in Figure 3 will cause a current of about 20mA to enter the load branch (that is, the branch composed of RL and Rcs). In addition, the same Mini Led display device will generate large currents of different values ​​as the power-on time and power-on speed change. When the maximum absorbable value of the capacitor inside the chip is exceeded, there is a risk of abnormal logic function in the chip and burning of certain devices.

[0082] The preferred embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0083] 4 , a driving control circuit provided in an embodiment of the present application includes: a voltage conversion sub-circuit 10 , a first shunt sub-circuit 20 , a conduction control sub-circuit 30 , and a second shunt sub-circuit 40 .

[0084] During implementation, the voltage conversion sub-circuit 10 is configured to convert the power supply voltage AVDD into the supply voltage DVDD, and output the supply voltage DVDD to the power supply terminal Va.

[0085] Typically, the voltage conversion sub-circuit 10 includes a switching transistor. When the Mini LED display device is powered on, i.e., in response to a power-on enable trigger EN, the switching transistor turns on, receives a supply voltage DVDD, and then provides the supply voltage DVDD to the power supply terminal Va. It should be noted that the degree of conduction of the switching transistor is related to the activation rate of the power-on enable trigger EN. When the power supply voltage AVDD provided by the power-on enable trigger EN gradually increases and exceeds the conduction threshold voltage of the switching transistor, the switching transistor turns on.

[0086] The first shunt sub-circuit 20 is coupled to the power supply terminal Va and the current limiting node Vb, and is configured to generate a first voltage at the current limiting node Vb according to the power supply voltage DVDD of the power supply terminal Va.

[0087] During implementation, when the supply voltage DVDD at the power supply terminal Va gradually increases during the power-on process, the first shunt sub-circuit 20 enables the current limiting node Vb to generate a first voltage according to the supply voltage DVDD at the power supply terminal Va.

[0088] 5 and 6 , the first shunt sub-circuit 20 includes a first resistor R1 .

[0089] A first end of the first resistor R1 is coupled to the power supply terminal Va, and a second end of the first resistor R1 is coupled to the current limiting node Vb.

[0090] The first resistor R1 is a new branch (assuming it is branch 1 ) that shares the supply voltage DVDD of the power supply terminal Va, and generates a first voltage at the current limiting node Vb of the branch.

[0091] In order to ensure the normal operation of the first transistor M1 , the resistance of the first resistor R1 is smaller than the resistance of the load resistor RL, and the resistance of the first resistor R1 is smaller than the resistance of the current-limiting resistor Rcs.

[0092] The resistance of the first resistor R1 is relatively small. Typically, the resistance of the first resistor R1 is smaller than the resistances of the load resistor RL and the current-limiting resistor Rcs in the conduction control subcircuit 30. Thus, when the first resistor R1 is connected to the circuit, due to the relatively small resistance of the first resistor R1, the first voltage generated at the current-limiting node Vb is approximately equal to the supply voltage DVDD of the power supply terminal Va, and the first transistor M1 is in a saturated state.

[0093] The conduction control subcircuit 30 is coupled to the power supply terminal Va, the current limiting node Vb, and the ground terminal, and is configured to generate a control voltage at the control node Ve and a current flowing through the power supply terminal Va to the ground terminal in response to a first voltage at the current limiting node Vb and a supply voltage DVDD at the power supply terminal Va.

[0094] During implementation, the conduction control subcircuit 30 is another branch (assuming it is branch 2) that shares the power supply voltage DVDD of the power supply terminal Va. When the first voltage of the current-limiting node Vb is greater than the power supply voltage DVDD of the power supply terminal Va, the conduction control subcircuit 30 is turned on, and the control node Ve generates a control voltage accordingly. The control voltage then causes the conduction control subcircuit 30 to generate a current flowing through the power supply terminal Va to the ground terminal.

[0095] 6 , the conduction control sub-circuit 30 includes a load resistor RL, a first transistor M1 , and a current limiting resistor Rcs.

[0096] In FIG6 , a first end of the load resistor RL is coupled to the power supply terminal Va, and a second end of the load resistor RL is coupled to the first end of the first transistor M1 .

[0097] A control terminal of the first transistor M1 is coupled to the current limiting node Vb, and a second terminal of the first transistor M1 is coupled to the control node Ve.

[0098] A first terminal of the current limiting resistor Rcs is coupled to the control node Ve, and a second terminal of the current limiting resistor Rcs is coupled to the ground.

[0099] During implementation, when the voltage of the current limiting node Vb is greater than the threshold voltage of the first transistor M1, the first transistor M1 is turned on, and the supply voltage DVDD of the power supply terminal Va generates corresponding current in the load resistor RL and the current limiting resistor Rcs.

[0100] It should be noted that when the conduction control subcircuit 30 is in the on state, the first transistor M1 is in a saturation state, and the current generated on the load resistor RL is equal to the current generated on the current limiting resistor Rcs.

[0101] The above-mentioned second shunt sub-circuit 40 is coupled to the control node Ve, the current limiting node Vb and the ground terminal, and is configured to conduct the current limiting node Vb and the ground terminal in response to the voltage of the control node Ve being greater than the first conduction threshold, so as to shunt the current generated by the conduction control sub-circuit 30.

[0102] During implementation, the second shunt sub-circuit 40 is the third branch (assuming it is branch 3) that shares the supply voltage DVDD from the power supply terminal Va. The second shunt sub-circuit 40 is coupled to the first shunt sub-circuit 20, the conduction control sub-circuit 30, and the like via the control node Ve and the current-limiting node Vb. When the voltage at the control node Ve is greater than a first conduction threshold, the branch containing the second shunt sub-circuit 40 is turned on. That is, the current-limiting node Vb is connected to the ground terminal via the second shunt sub-circuit 40, thereby shunting the current generated by the conduction control sub-circuit 30.

[0103] 6 , the second shunt sub-circuit 40 includes a shunt control unit and a second resistor R2 .

[0104] In FIG6 , the shunt control unit is configured to connect the current limiting node Vb and the second resistor R2 in response to the current value in the control node Ve being greater than the first conduction threshold, so as to shunt the current generated by the conduction control subcircuit 30 .

[0105] The second resistor R2 is configured to divert the current generated by the conduction control sub-circuit 30 to the ground.

[0106] During the implementation process, when the current value in the control node Ve is greater than the first conduction threshold, the shunt node is connected to the second resistor R2 through the shunt control unit, and then the second resistor R2 shunts the current generated by the conduction control subcircuit 30 and conducts the shunt current to the ground. In this way, the magnitude of the current generated by the conduction control subcircuit 30 is further limited, thereby reducing the risk of burning the load resistor RL and the current limiting resistor Rcs.

[0107] The following describes the shunt control unit according to different situations:

[0108] The first case: the above-mentioned shunt control unit includes a first MOS tube M2.

[0109] A control terminal of the first MOS transistor M2 is coupled to the control node Ve, a first terminal of the first MOS transistor M2 is coupled to the current limiting node Vb, and a second terminal of the first MOS transistor M2 is coupled to the first terminal of the second resistor R2.

[0110] During implementation, when the voltage at the control node Ve is greater than the first conduction threshold of the first MOS transistor M2, the first MOS transistor M2 is turned on, and the current-limiting node Vb is coupled to the second resistor R2 via the first MOS transistor M2. In this case, the second shunt sub-circuit 40 specifically includes the first MOS transistor M2 and the second resistor R2. The first MOS transistor M2 controls whether the second shunt sub-circuit 40 is turned on or off. When the first MOS transistor M2 is turned on, the second shunt sub-circuit 40 shunts the current in the conduction control sub-circuit 30. When the first MOS transistor M2 is turned off, the second shunt sub-circuit 40 does not shunt the current in the conduction control sub-circuit 30.

[0111] It should be supplemented that the current of the conduction control subcircuit does not exceed the current threshold, where the current threshold is the ratio of the threshold voltage Vth of the first transistor M1 to the current limiting resistor Rcs.

[0112] During implementation, when the second shunt sub-circuit 40 does not shunt the current in the conduction control sub-circuit 30, that is, when the second shunt sub-circuit 40 is not turned on, the first transistor M1 is in a saturation state. In this case, the current flowing through the load resistor is equal to the current flowing through the current limiting resistor, that is, the current value of the conduction control sub-circuit is the voltage of the control node Ve divided by the resistance of the current limiting resistor, and the voltage of the above-mentioned control node Ve is less than the threshold voltage Vth of the first transistor M1; when the second shunt sub-circuit 40 shunts the current in the conduction control sub-circuit 30, that is, after the second shunt sub-circuit 40 is turned on, in this case, the first transistor M1 is in a critical saturation state, and the current value of the conduction control sub-circuit is the ratio of the threshold voltage Vth of the first transistor M1 to the current limiting resistor Rcs.

[0113] In addition, referring to FIG. 7 , in order to limit the current generated by the shunt control unit from flowing in reverse into the conduction control sub-circuit 30 , the drive control circuit further includes a first voltage follower U1 .

[0114] A positive input terminal of the first voltage follower U1 is coupled to the control node Ve, and a negative input terminal and an output terminal of the first voltage follower U1 are coupled to the control terminal of the first MOS transistor M2.

[0115] The configuration of the first voltage follower U1 limits the current to flow only from the conduction control subcircuit 30 to the shunt control unit, and not from the shunt control unit to the conduction control subcircuit 30. It should be noted that the current is usually the reverse flow of the parasitic capacitance C of the first MOS transistor M2, which can affect the voltage of the control node Ve and further generate current or voltage noise oscillation.

[0116] Considering that false triggering or high currents triggered by power-on current are usually AC, during implementation, the second shunt sub-circuit 40 is further divided into two parts: one for shunting AC components and the other for shunting DC components. That is, the shunt control unit includes a first shunt control sub-unit and a second shunt control sub-unit.

[0117] The second case: the first shunt control sub-unit is configured to connect the current limiting node Vb and the second resistor R2 in response to the voltage of the AC component in the control node Ve being greater than the first conduction threshold, so as to shunt the current generated by the conduction control sub-circuit 30.

[0118] During implementation, when the voltage of the AC component in the control node Ve is greater than the first conduction threshold, the first shunt control sub-unit is turned on, and the current limiting node Vb is turned on through the first shunt control sub-unit and the second resistor R2, thereby shunting the current generated by the conduction control sub-circuit 30.

[0119] 6 , the first current shunt control sub-unit includes a capacitor C and a second MOS transistor M3 .

[0120] A first terminal of the capacitor C is coupled to the control node Ve, and a second terminal of the capacitor C is coupled to the control terminal of the second MOS transistor M3.

[0121] A first terminal of the second MOS transistor M3 is coupled to the current limiting node Vb, and a second terminal of the second MOS transistor M3 is coupled to a first terminal of the second resistor R2.

[0122] During implementation, the characteristic of capacitor C of blocking DC and passing AC is utilized. After the AC component generated at the control node Ve by the conduction control sub-circuit 30 flows through capacitor C, if the voltage of the AC component is greater than the first conduction threshold, the second MOS transistor M3 is turned on. The second MOS transistor M3 further introduces the above-mentioned AC component into the second resistor R2 and the ground terminal, thereby shunting the AC component generated by the conduction control sub-circuit 30.

[0123] Similarly, referring to FIG8 , in order to limit the current generated by the first shunt control sub-unit from flowing back into the conduction control sub-circuit 30 , the first shunt control sub-unit further includes a second voltage follower U2 .

[0124] A positive input terminal of the second voltage follower U2 is coupled to the control node Ve, and a negative input terminal and an output terminal of the second voltage follower U2 are coupled to the control terminal of the second MOS transistor M3.

[0125] The configuration of the second voltage follower U2 restricts current flow from the conduction control subcircuit 30 to the first shunt control subunit, and prevents current from flowing from the first shunt control subunit to the conduction control subcircuit 30. Similarly, the configuration of the second voltage follower U2 is also to prevent backflow of the parasitic capacitance C of the second MOS transistor M3, thereby preventing current or voltage noise oscillation at the control node Ve.

[0126] The third case: the second shunt control sub-unit is configured to connect the current limiting node Vb and the second resistor R2 in response to the voltage of the DC component in the control node Ve being greater than the first conduction threshold, so as to shunt the current generated by the conduction control sub-circuit 30.

[0127] During implementation, when the voltage of the DC component in the control node Ve is greater than the first conduction threshold, the second shunt control subunit is turned on, and the current limiting node Vb is turned on through the second shunt control subunit and the second resistor R2, thereby shunting the current generated by the conduction control subcircuit 30.

[0128] 6 , the second current shunt control sub-unit includes an inductor L and a third MOS transistor M4 .

[0129] A first end of the inductor L is coupled to the control node Ve, and a second end of the inductor L is coupled to the control end of the third MOS transistor M4.

[0130] A first terminal of the third MOS transistor M4 is coupled to the current limiting node Vb, and a second terminal of the third MOS transistor M4 is coupled to the first terminal of the second resistor R2.

[0131] During implementation, the characteristic of the inductor L that it passes DC and blocks AC is utilized. After the DC component generated by the conduction control sub-circuit 30 at the control node Ve flows through the inductor L, if the voltage of the DC component is greater than the first conduction threshold, the third MOS transistor M4 is turned on. The third MOS transistor M4 further introduces the above-mentioned DC component into the second resistor R2 and the ground terminal, thereby shunting the DC component generated by the conduction control sub-circuit 30.

[0132] Similarly, referring to FIG8 , in order to limit the current generated by the second shunt control sub-unit from flowing back into the conduction control sub-circuit 30 , the second shunt control sub-unit further includes: a third voltage follower U3 .

[0133] A positive input terminal of the third voltage follower U3 is coupled to the control node Ve, and a negative input terminal and an output terminal of the third voltage follower U3 are coupled to the control terminal of the third MOS transistor M4.

[0134] The configuration of the third voltage follower U3 restricts current flow from the conduction control subcircuit 30 to the second shunt control subunit, and prevents current from flowing from the second shunt control subunit to the conduction control subcircuit 30. Similarly, the configuration of the third voltage follower U3 is also to prevent backflow of the parasitic capacitance C of the third MOS transistor M4, thereby preventing current or voltage noise oscillation at the control node Ve.

[0135] In addition, referring to FIG9 and FIG10 , the driving control circuit further includes a driving chip.

[0136] In one embodiment, referring to FIG. 9 , the voltage conversion sub-circuit 10 , the first shunt sub-circuit 20 , the conduction control sub-circuit 30 , and the second shunt sub-circuit 40 are disposed inside the driver chip.

[0137] Since the voltage conversion sub-circuit 10, the first shunt sub-circuit 20, the conduction control sub-circuit 30 and the second shunt sub-circuit 40 are all used to limit the current generated by the chip-level power supply voltage DVDD, the voltage conversion sub-circuit 10, the first shunt sub-circuit 20, the conduction control sub-circuit 30 and the second shunt sub-circuit 40 can all be set inside the driver chip.

[0138] When the driver chip is powered on, that is, when a gradually increasing power supply voltage AVDD is provided to the driver chip, the voltage conversion sub-circuit 10 converts the power supply voltage AVDD into the power supply voltage DVDD, and then the first shunt sub-circuit 20, the conduction control sub-circuit 30 and the second shunt sub-circuit 40 limit the current generated by the power supply voltage DVDD.

[0139] In another embodiment, as shown in FIG10 , the voltage conversion sub-circuit 10, the first shunt sub-circuit 20, the conduction control sub-circuit 30 and the second shunt sub-circuit 40 are arranged outside the driver chip, and the voltage conversion sub-circuit 10 is coupled to the power pin of the chip.

[0140] Although the voltage conversion sub-circuit 10, the first shunt sub-circuit 20, the conduction control sub-circuit 30, and the second shunt sub-circuit 40 are all used to limit the current generated by the chip-level power supply voltage DVDD, the voltage conversion sub-circuit 10, the first shunt sub-circuit 20, the conduction control sub-circuit 30, and the second shunt sub-circuit 40 can all be disposed outside the driver chip, and the voltage conversion sub-circuit 10 can be coupled to the power pin of the chip. In some embodiments, the drive control circuit can also be disposed on a driver board.

[0141] When the driver chip is powered on, that is, when a gradually increasing power supply voltage AVDD is provided to the driver chip, the voltage conversion sub-circuit 10 obtains the power supply voltage AVDD through the power pin of the driver chip, and further converts the power supply voltage AVDD into the power supply voltage DVDD. Then, the first shunt sub-circuit 20, the conduction control sub-circuit 30, and the second shunt sub-circuit 40 limit the current generated by the power supply voltage DVDD. The limited current is then provided to the driver chip to enable the driver chip to implement the corresponding logical function.

[0142] The following describes in detail the specific working process of the drive control circuit:

[0143] Initial power-up phase: When the power-on enable signal EN is triggered, the voltage conversion sub-circuit 10 converts the power supply voltage AVDD, which increases from 0, into the supply voltage DVDD and supplies this supply voltage DVDD to the power supply terminal Va. During this phase, the current generated by the supply voltage DVDD is less than the absorption limit of the capacitor C. That is, the current is completely absorbed by the capacitor CC, thereby ensuring that the voltage difference across the load resistor RL remains unchanged, and the load current remains unchanged.

[0144] During the power-on overshoot phase, as the power-on process progresses, the supply voltage DVDD provided to the power supply terminal Va also increases. Consequently, the current generated by the supply voltage DVDD exceeds the absorption limit of the capacitor C. After the capacitor C has absorbed the current at its absorption limit, some unnecessary current will still flow through the load resistor RL. To ensure the normal operation of the load resistor RL, the second shunt sub-circuit 40 is activated to ensure that the voltage difference across the load resistor RL remains constant, and the load current remains constant. This process is further described below in the following subdivisions:

[0145] (1) In the event of a high current false trigger during the power-on process, when the power-on enable trigger EN rise time reaches 80% but not 100%, and the current generated by the power supply voltage DVDD does not exceed the absorption limit of the capacitor C and the normal current that the load resistor RL can withstand, no large current is generated on the load resistor RL. Because the resistance of the first resistor R1 is small, the voltage of the current limiting node Vb is large (approximately equal to the power supply voltage DVDD of the power supply terminal Va), the first transistor M1 enters a saturation state, at which time Ic≈Ie=Ve / Rcs. In this case, the second shunt sub-circuit 40 does not turn on. It should be noted that after the first transistor M1 is saturated, the voltage difference of Vbe is extremely small, Vb≈Ve.

[0146] As the supply voltage DVDD at the power supply terminal Va slowly increases, if the control voltage at the control node Ve exceeds the first conduction threshold of the first MOS transistor M2, the second current shunt sub-circuit 40 is activated. At this point, the first MOS transistor M2 is turned on, shunting the current through the load resistor RL. This causes the voltage at the current-limiting node Vb to drop, and the first transistor M1 enters an unsaturated state. Since the transistor's current in the unsaturated state is Ie=Ic+Ib, this drop in current at the current-limiting node Vb causes the current through the current-limiting resistor Rcs to drop, further reducing the voltage across the current-limiting resistor Rcs (Ve=Ie*Rcs). This repeated adjustment continues until Ve≈Vth, bringing the first transistor M1 into a critical saturation state. At this point, the current through the current-limiting resistor Rcs ≈ the current through the load resistor RL, which equals Ve / Rcs≈Vth / Rcs. For detailed simulation waveforms, see Figures 11 and 12.

[0147] (2) In the event of a high current false trigger during power-on, the power-on enable trigger EN rise time reaches 100%, and the current generated by the supply voltage DVDD does not exceed the absorption limit of the capacitor C and the normal current that the load resistor RL can withstand. There is no large current on the load resistor RL. If the voltage at the control node Ve is less than the threshold voltage of the first transistor M1, the first transistor M1 is saturated, and the current on the current-limiting resistor Rcs ≈ the current on the load resistor RL ≈ Ve / Rcs. If the voltage at the control node Ve is greater than the first conduction threshold of the first MOS transistor M2, the second shunt sub-circuit 40 is turned on, the first transistor M1 is in a critical saturation state, and the current on the current-limiting resistor Rcs ≈ the current on the load resistor RL = Ve / Rcs ≈ Vth / Rcs. For specific simulation waveforms, please refer to Figures 13 and 14.

[0148] The above (1) and (2) effectively avoid the situation where the chip is burned due to abnormal power supply voltage AVDD (for example, debugging personnel error).

[0149] (3) When the power filter capacitor C and other components inside the chip generate parasitic oscillations on the power supply, the rise time of the power-on enable trigger EN reaches 80%, and the current generated by the supply voltage DVDD exceeds the absorption limit of the capacitor C and the normal current that the load resistor RL can withstand. Due to the sudden increase in the current of the load resistor RL, the voltage of the control node Ve is Ve=Ie*Rcs, and the voltage of the control node Ve suddenly increases. When the voltage of the control node Ve is greater than the first conduction threshold of the first MOS transistor M2, the second shunt sub-circuit 40 is turned on, reducing the voltage of the control node Ve to Ve≈Vth. At this time, the first transistor M1 is in a critical saturation state, and the current on the current limiting resistor Rcs ≈ the current on the load resistor RL = Ve / Rcs≈Vth / Rcs. For specific simulation waveforms, please refer to Figures 15 and 16.

[0150] The above (3) effectively avoids the situation where the chip logic function may be abnormal due to large current overshoot noise caused by internal coupling or other factors.

[0151] Based on the same inventive concept, referring to FIG. 9 and FIG. 10 , an embodiment of the present application provides a driving system, including: a first voltage conversion module, a second voltage conversion module, a driving interface module and the above-mentioned driving control circuit.

[0152] In order to be able to be used in conjunction with the rear-end Mini LED backlight panel, the driving system in the embodiment of the present application also includes a first voltage conversion module, a second voltage conversion module and a driving interface module used in conjunction with the above-mentioned driving control circuit.

[0153] The first voltage conversion module converts the external input power voltage into a supply voltage in response to the power-on enable trigger EN, and further provides the supply voltage to the drive control circuit.

[0154] During the implementation process, when the power-on enable trigger EN is valid, the first voltage conversion module receives the power supply voltage AVDD, and then converts the power supply voltage AVDD into the power supply voltage DVDD, and then provides the power supply voltage DVDD to the drive control circuit. It should be noted that the common first voltage conversion module is used for DC voltage conversion, for example, DC 5V is converted to DC 3.3V.

[0155] During implementation, the second voltage conversion module is configured to receive the external power supply voltage PVDD in response to a power-on enable trigger and provide the external power supply voltage PVDD to the Mini LED backlight panel via the driver interface module. Typically, the second voltage conversion module is used to boost the external power supply voltage PVDD to increase its driving capability. This voltage is then further provided to the Mini LED backlight panel via the driver interface module. Specifically, the driver interface module divides the external power supply voltage PVDD into multiple paths and provides them to the Mini LED backlight panel. Typically, to ensure the stability of the Mini LED backlight panel's power supply, a feedback signal DFB is provided to provide feedback and adjust the external power supply voltage PVDD.

[0156] In addition, the above-mentioned driving system also includes a logic opening control module.

[0157] The logic start control module is configured to send a start signal to the driver chip in response to a power-on enable trigger, so as to enable the driver chip to start the logic control function.

[0158] During the implementation process, the above-mentioned driving system also includes a logic start control module, usually referred to as the AP end or MCU. When responding to the power-on enable trigger of the external input, the logic start control module is used to send a start signal to the driving chip, such as an SPI signal, thereby controlling the start of the control logic function of the driving chip.

[0159] Based on the same inventive concept, an embodiment of the present application provides a display device, including: a driving system and a Mini LED backlight panel as described above.

[0160] The driving system is coupled to the Mini LED backlight panel and is configured to provide a driving signal to the Mini LED backlight panel through the driving interface module.

[0161] During the implementation process, the above-mentioned driving system is electrically connected to the Mini LED backlight panel through the driving interface module. After the driving current is limited in the driving system, the above-mentioned limited current is converted into a driving signal compatible with the Mini LED backlight panel through the driving interface module, and the above-mentioned driving signal is provided to the Mini LED backlight panel.

[0162] The display device provided in the embodiments of the present application can be any product or component with a display function, such as a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, etc. Other essential components of the display device are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present application.

[0163] Based on the same inventive concept, an embodiment of the present application provides a drive control method, as shown in FIG17 , including:

[0164] Step 201 : The voltage conversion sub-circuit 10 outputs the supply voltage DVDD to the power supply terminal Va.

[0165] During the implementation process, under the action of the power-on enable trigger EN, the power supply voltage AVDD is provided to the voltage conversion sub-circuit 10 by a small increase, and then the voltage conversion sub-circuit 10 converts the obtained power supply voltage AVDD into the power supply voltage DVDD. Usually, the voltage conversion sub-circuit 10 is a switching transistor, and then the voltage conversion sub-circuit 10 outputs the power supply voltage DVDD to the power supply terminal Va, that is, the voltage value DVDD of the Va node is equal to the value AVDD of the power supply voltage AVDD.

[0166] Step 202 : The first current dividing sub-circuit 20 causes the current limiting node Vb to generate a first voltage according to the supply voltage DVDD of the power supply terminal Va.

[0167] Under the action of the power supply voltage DVDD of the power supply terminal Va, the first shunt sub-circuit 20 causes the current limiting node Vb to generate a first voltage according to the power supply voltage DVDD. That is, the voltage value of the Vb node is the first voltage.

[0168] Step 203 : Turn on the control sub-circuit 30 in response to the first voltage of the current limiting node Vb and the supply voltage DVDD of the power supply terminal Va, so that the control node Ve generates a control voltage and generates a current flowing through the power supply terminal Va to the ground terminal.

[0169] During implementation, whether the conduction control subcircuit 30 is conducted or not mainly depends on whether the first transistor M1 is conducted. When the first voltage of the current limiting node Vb is greater than the supply voltage DVDD of the power supply terminal Va, that is, when the first voltage of the current limiting node Vb is greater than the threshold voltage of the first transistor M1, the first transistor M1 is conducted, and the control node Ve of the conduction control subcircuit 30 composed of the load resistor RL, the first transistor M1 and the current limiting resistor Rcs generates a control voltage, and generates a current flowing through the power supply terminal Va to the ground terminal.

[0170] It should be noted that, since the first transistor M1 is in a saturated conduction state, the current of the load resistor RL is equal to the current Ib of the current-limiting resistor Rcs.

[0171] That is, in this embodiment, when the first shunt sub-circuit is turned on and the second shunt sub-circuit is not turned on, the current generated by the conduction control sub-circuit is the ratio of the voltage of the control node Ve to the current limiting resistor Rcs.

[0172] During implementation, when the loop including the first resistor R1 connected to the power supply end and the loop including the load resistor RL, the first transistor M1 and the current-limiting resistor Rcs connected to the power supply end are turned on, that is, when the above-mentioned conduction control subcircuit only shunts current through the first shunt subcircuit, the first transistor M1 is in a saturated state, and the current generated by the conduction control subcircuit is the ratio of the voltage of the control node Ve to the current-limiting resistor Rcs.

[0173] Step 204 : In response to the control node Ve being greater than the first conduction threshold, the second shunt sub-circuit 40 conducts the current limiting node Vb and the ground terminal to shunt the current generated by the conduction control sub-circuit 30 .

[0174] To protect the load resistor RL from being burned by excessive current, when the current in the conduction control sub-circuit 30 is too large, the current at the control node Ve will be greater than the first conduction threshold of the first MOS transistor M2, the second MOS transistor M3, or the third MOS transistor M4 in the shunt control unit. In this case, the second shunt sub-circuit 40 is turned on, that is, the shunt control unit and the second circuit form a new current limiting branch to shunt the current generated by the conduction control sub-circuit 30, thereby further reducing the current of the conduction control sub-circuit 30.

[0175] In another embodiment, when the first shunt sub-circuit is turned on and the second shunt sub-circuit is turned on, the current generated by the conduction control sub-circuit is a ratio of the threshold voltage of the first transistor to the current limiting resistor.

[0176] During implementation, when the loop where the first resistor R1 connected to the power supply end is connected, the loop where the load resistor RL, the first transistor M1 and the current-limiting resistor Rcs connected to the power supply end are connected, and the loop where the second resistor R2 and the shunt control unit are connected is also connected, that is, when the above-mentioned conduction control subcircuit simultaneously shunts current through the first shunt subcircuit and the second shunt subcircuit, the first transistor M1 is in a critical saturation state, and the current generated by the conduction control subcircuit is the ratio of the threshold voltage Vth of the first transistor M1 to the current-limiting resistor Rcs.

[0177] In summary, a drive control circuit, a drive system, and a display device are provided in an embodiment of the present application. The drive control circuit includes: a voltage conversion subcircuit, a first shunt subcircuit, a conduction control subcircuit, and a second shunt subcircuit. The voltage conversion subcircuit is configured to output a supply voltage to a power supply terminal. The first shunt subcircuit is coupled to the power supply terminal and the current limiting node, and is configured to cause the current limiting node to generate a first voltage according to the power supply voltage of the power supply terminal. The conduction control subcircuit is coupled to the power supply terminal, the current limiting node, and the ground terminal, and is configured to cause the control node to generate a control voltage in response to the first voltage of the current limiting node and the power supply voltage of the power supply terminal, and to generate a current flowing through the power supply terminal to the ground terminal. The second shunt subcircuit is coupled to the control node, the current limiting node, and the ground terminal, and is configured to conduct the current limiting node and the ground terminal in response to the voltage of the control node being greater than a first conduction threshold, so as to shunt the current generated by the conduction control subcircuit. The above-mentioned first shunt subcircuit and the second shunt subcircuit achieve the purpose of limiting the current of the power supply terminal, thereby effectively reducing the current flowing through the power supply terminal and improving the reliability of the power supply voltage.

[0178] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program product systems. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0179] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program product systems according to the present application. It should be understood that each flow and / or box in the flow chart and / or block diagram, as well as the combination of the flow chart and / or box in the flow chart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more flow charts and / or one or more boxes in the block diagram.

[0180] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0181] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0182] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A drive control circuit, wherein, Comprising: A voltage conversion sub - circuit, a first shunt sub - circuit, a conduction control sub - circuit, and a second shunt sub - circuit; The voltage conversion sub - circuit is configured to output a supply voltage to a supply terminal; The first shunt sub - circuit is coupled to the supply terminal and a current - limiting node, and is configured to generate a first voltage at the current - limiting node according to the supply voltage at the supply terminal; The conduction control sub - circuit is coupled to the supply terminal, the current - limiting node, and a ground terminal, and is configured to generate a control voltage at a control node and generate a current flowing from the supply terminal to the ground terminal in response to the first voltage at the current - limiting node and the supply voltage at the supply terminal; The second shunt sub - circuit is coupled to the control node, the current - limiting node, and the ground terminal, and is configured to conduct the current - limiting node and the ground terminal in response to the voltage at the control node being greater than a first conduction threshold to shunt the current generated by the conduction control sub - circuit.

2. The circuit according to claim 1, wherein, The first shunt sub - circuit includes: a first resistor; A first end of the first resistor is coupled to the supply terminal, and a second end of the first resistor is coupled to the current - limiting node.

3. The circuit according to claim 2, wherein, The conduction control sub - circuit includes: a load resistor, a first transistor, and a current - limiting resistor; A first end of the load resistor is coupled to the supply terminal, and a second end of the load resistor is coupled to a first end of the first transistor; A control end of the first transistor is coupled to the current - limiting node, and a second end of the first transistor is coupled to the control node; A first end of the current - limiting resistor is coupled to the control node, and a second end of the current - limiting resistor is coupled to the ground terminal.

4. The circuit according to claim 3, wherein The resistance value of the first resistor is less than the resistance value of the load resistor, and the resistance value of the first resistor is less than the resistance value of the current - limiting resistor.

5. The circuit according to claim 1, wherein, The second shunt sub - circuit includes: a shunt control unit and a second resistor; The shunt control unit is configured to conduct the current - limiting node and the second resistor in response to a current value in the control node being greater than the first conduction threshold to shunt the current generated by the conduction control sub - circuit; The second resistor is configured to conduct the shunt current after shunting the current generated by the conduction control sub - circuit to the ground.

6. The circuit according to claim 5, wherein, The shunt control unit includes a first MOS transistor; A control end of the first MOS transistor is coupled to the control node, a first end of the first MOS transistor is coupled to the current - limiting node, and a second end of the first MOS transistor is coupled to a first end of the second resistor.

7. The circuit according to claim 5, wherein, The shunt control unit includes: a first shunt control sub - unit and a second shunt control sub - unit; The first shunt control sub - unit is configured to conduct the current - limiting node and the second resistor in response to a voltage of an AC component in the control node being greater than the first conduction threshold to shunt the current generated by the conduction control sub - circuit; The second shunt control sub - unit is configured to conduct the current - limiting node and the second resistor in response to a voltage of a DC component in the control node being greater than the first conduction threshold to shunt the current generated by the conduction control sub - circuit.

8. The circuit according to claim 7, wherein, The first shunt control sub - unit includes: a capacitor and a second MOS transistor; The first end of the capacitor is coupled to the control node, and the second end of the capacitor is coupled to the control end of the second MOS transistor; The first end of the second MOS transistor is coupled to the current limiting node, and the second end of the second MOS transistor is coupled to the first end of the second resistor.

9. The circuit according to claim 7, wherein The second shunt control sub-unit includes: the inductor and the third MOS transistor; The first end of the inductor is coupled to the control node, and the second end of the inductor is coupled to the control end of the third MOS transistor; The first end of the third MOS transistor is coupled to the current limiting node, and the second end of the third MOS transistor is coupled to the first end of the second resistor.

10. The circuit according to claim 6, wherein, It further includes: a first voltage follower; The positive input terminal of the first voltage follower is coupled to the control node, and the negative input terminal and the output terminal of the first voltage follower are coupled to the control end of the first MOS transistor.

11. The circuit according to claim 8, wherein, The first shunt control sub-unit further includes: a second voltage follower; The positive input terminal of the second voltage follower is coupled to the control node, and the negative input terminal and the output terminal of the second voltage follower are coupled to the control end of the second MOS transistor.

12. The circuit according to claim 9, wherein, The second shunt control sub-unit further includes: a third voltage follower; The positive input terminal of the third voltage follower is coupled to the control node, and the negative input terminal and the output terminal of the third voltage follower are coupled to the control end of the third MOS transistor.

13. The circuit according to any one of claims 1 to 12, wherein, It further includes: a driving chip; The voltage conversion sub-circuit, the first shunt sub-circuit, the conduction control sub-circuit and the second shunt sub-circuit are arranged inside the driving chip.

14. The circuit according to any one of claims 1 to 12, wherein, It further includes: a driving chip; The voltage conversion sub-circuit, the first shunt sub-circuit, the conduction control sub-circuit and the second shunt sub-circuit are arranged outside the driving chip, and the voltage conversion sub-circuit is coupled to the power supply pin of the chip.

15. The circuit according to claim 3, wherein The current of the conduction control sub-circuit does not exceed the current threshold, where the current threshold is the ratio of the threshold voltage of the first transistor to the current limiting resistor.

16. A drive system, wherein, It includes: A first voltage conversion module, a second voltage conversion module, a driving interface module and the driving control circuit according to any one of claims 1 to 15; The first voltage conversion module is configured to convert the power supply voltage into a supply voltage in response to a power-on enable trigger, and provide the supply voltage to the driving control circuit; The second voltage conversion module is configured to receive an external supply voltage in response to a power-on enable trigger, and provide the external supply voltage to the Mini LED backlight panel through the driving interface module.

17. The drive system according to claim 16, wherein, It further includes a logic turn-on control module; The logic turn-on control module is configured to send a start signal to the driving chip in response to a power-on enable trigger, so that the driving chip enables the logic control function.

18. A display device, wherein, It includes: The driving system and the Mini LED backlight panel according to claim 16 or 17; The driving system is coupled to the Mini LED backlight panel and is configured to provide a driving signal to the Mini LED backlight panel through the driving interface module.

19. A drive control method, wherein, It includes: The voltage conversion sub-circuit outputs the supply voltage to the power supply terminal; The first shunt sub-circuit generates a first voltage at the current-limiting node according to the supply voltage of the supply terminal; The conduction control sub-circuit generates a control voltage at the control node and generates a current flowing from the supply terminal to the ground terminal in response to the first voltage at the current-limiting node and the supply voltage of the supply terminal; The second shunt sub-circuit conducts the current-limiting node and the ground terminal in response to the control node being greater than a first conduction threshold to shunt the current generated by the conduction control sub-circuit.

20. The method according to claim 19, wherein, When the first shunt sub-circuit is turned on and the second shunt sub-circuit is not turned on, the current generated by the conduction control sub-circuit is the ratio of the voltage of the control node to the current-limiting resistor.

21. The method according to claim 19, wherein When the first shunt sub-circuit is turned on and the second shunt sub-circuit is turned on, the current generated by the conduction control sub-circuit is the ratio of the threshold voltage of the first transistor to the current-limiting resistor.

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