Drive circuit, chip, and display apparatus

Abstract

The present application discloses a drive circuit, a chip, and a display apparatus. The drive circuit, by means of multiple data lines, drives multiple pixel units in the display apparatus. Each pixel unit, on the basis of a source electrode driving voltage, emits light having a corresponding brightness. The drive circuit comprises: a data driver, used to provide a data voltage corresponding to each pixel unit; and multiple first capacitors. When each first capacitor is coupled with a corresponding pixel unit by means of a corresponding data line, each first capacitor, on the basis of the corresponding data voltage, adjusts the source electrode driving voltage of each pixel unit, so that the corresponding source electrode driving voltage is related to the capacitance value of the corresponding first capacitor and the corresponding data voltage. Thus, the range of data voltages can be expanded, facilitating accurate control of light-emitting current, and improving display quality of the display apparatus. Additionally, the design difficulty of the data driver is reduced, helping to further improve display quality.

Description

Driving circuit, chip and display device

[0001] This application claims priority to a Chinese invention application filed on November 22, 2023, with application number 2023115687167 and titled “Driving circuit, chip and display device,” and incorporates the entire specification, claims, drawings and abstract of the above-mentioned Chinese invention application into this application by reference. Technical Field

[0002] The present invention relates to the field of display technology, and in particular to a driving circuit, a chip and a display device. Background Art

[0003] OLED (Organic Light-Emitting Diode) is an emerging flat-panel display device with broad application prospects due to its advantages such as self-luminescence, high contrast, wide color gamut, simple preparation process, low cost, low power consumption, and easy realization of flexible display.

[0004] MicroOLED (also known as silicon-based OLED, OLEDoS) is a key branch of OLED technology. It utilizes a CMOS process to fabricate pixel units on a single-crystal silicon substrate, offering advantages such as thinner, lighter, and smaller display panels, while consuming less power. In OLEDoS, current is typically used to drive the OLED, adjusting the OLED's brightness by varying the current flowing through it. However, the current requirement of each pixel is very small (e.g., 1pA to 10nA). This small current range corresponds to a narrow data voltage range, making precise control of the current difficult. This results in suboptimal grayscale gradation performance. Furthermore, the narrow data voltage range complicates data driver design, increasing development time and complexity. Summary of the Invention

[0005] In view of the above problems, the purpose of this application is to provide a driving circuit, a chip and a display device that can expand the data voltage range.

[0006] According to one aspect of the present application, a driving circuit is provided for driving a plurality of pixel units in a display device via a plurality of data lines, wherein each of the pixel units emits light of corresponding brightness according to a source driving voltage, wherein the driving circuit comprises: a data driver for providing a data voltage corresponding to each pixel unit; and a plurality of first capacitors, wherein when each of the first capacitors is coupled to a corresponding pixel unit via a corresponding data line, each of the first capacitors adjusts the source driving voltage of each of the pixel units according to the corresponding data voltage, so that the corresponding source driving voltage is correlated with the capacitance value of the corresponding first capacitor and the corresponding data voltage.

[0007] Optionally, the driving circuit also includes a first power supply end, which provides a pre-processing voltage. Each row scanning stage of at least one frame of the display device includes a first sub-stage and a second sub-stage: in the first sub-stage, the first capacitor and / or the data line receives the pre-processing voltage; in the second sub-stage, the first capacitor is coupled to the data line and disconnected from the pre-processing voltage.

[0008] Optionally, the driving circuit further includes a switching element corresponding to each of the data lines, and the switching element is used to switch between the first sub-phase and the second sub-phase.

[0009] Optionally, the first capacitor is connected in series to the data line, one end of the first capacitor is connected to the data driver, and the other end is connected to the corresponding pixel units; the first power supply end is respectively connected to both ends of the first capacitor.

[0010] Optionally, the switching element includes a first switching element, a second switching element and a third switching element. For each data line, the first switching element corresponding to the data line is connected in series between the data driver and the first capacitor; one end of the second switching element is connected to the intermediate node between the first switching element and the first capacitor, and the other end is connected to the first power supply end; one end of the third switching element is connected to the intermediate node between the first capacitor and each pixel unit, and the other end is connected to the first power supply end. The driving circuit is configured to: in the first sub-stage, close the second switching element and the third switching element and disconnect the first switching element; and in the second sub-stage, disconnect the second switching element and the third switching element and close the first switching element.

[0011] Optionally, the first end of the data line is connected to the data driver, and the second end is connected to the first power supply end; one end of the first capacitor is grounded, and the other end is connected to the data line, and the corresponding pixel units are all located between the first capacitor and the data driver; or the corresponding pixel units are all located between the first capacitor and the first power supply end.

[0012] Optionally, the switching element includes a first switching element, a second switching element and a third switching element. For each data line, the first switching element, the second switching element and the third switching element corresponding to the data line are connected in series between the first end and the second end of the data line in sequence, each pixel unit is connected between the second switching element and the third switching element, one end of the first capacitor is connected between the first switching element and the second switching element, and the other end is grounded. The driving circuit is configured to: in the first sub-stage, close the first switching element and the third switching element and disconnect the second switching element; in the second sub-stage, disconnect the first switching element and the third switching element and close the second switching element.

[0013] Optionally, the switching element includes a first switching element, a second switching element and a third switching element. For each data line, the first switching element, the second switching element and the third switching element corresponding to the data line are connected in series between the first end and the second end of the data line in sequence, each pixel unit is connected between the first switching element and the second switching element, one end of the first capacitor is connected between the second switching element and the third switching element, and the other end is grounded. The driving circuit is configured to: in the first sub-stage, close the first switching element and the third switching element and disconnect the second switching element; in the second sub-stage, disconnect the first switching element and the third switching element and close the second switching element.

[0014] Optionally, the driving circuit further includes a plurality of operational amplifiers, each of the operational amplifiers being connected between the data driver and the corresponding data line, the inverting input and output of the operational amplifier being connected and connected to the corresponding data line, and the non-inverting input of the operational amplifier being connected to the data driver.

[0015] According to another aspect of the present application, a chip is provided, wherein the chip includes the driving circuit as described in any one of the above items.

[0016] According to a third aspect of the present application, a display device is provided, wherein the display device includes: a driving circuit as described in any one of the above items; and a plurality of the pixel units.

[0017] According to the driver circuit, chip, and display device provided herein, the source drive voltage of a pixel unit is adjusted via the first capacitor. This allows a larger data voltage to be required while maintaining a constant source drive voltage for a single pixel unit (i.e., maintaining constant luminous brightness). This expands the data voltage range, facilitates precise control of the luminous current, and enhances the display quality of the display device. This also reduces the design complexity of the data driver, further improving display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0019] FIG1 shows a schematic circuit structure diagram of a pixel unit capable of widening data voltage;

[0020] FIG2 shows a schematic structural diagram of a display device according to a first embodiment of the present application;

[0021] FIG3A shows a circuit state of the driving circuit in the first sub-phase according to the first embodiment of the present application;

[0022] FIG3B shows the circuit state of the driving circuit in the second sub-phase according to the first embodiment of the present application;

[0023] FIG4 outputs the switching timing of each switching element of the driving circuit of the first embodiment of the present application;

[0024] FIG5 shows a schematic structural diagram of a driving circuit according to a second embodiment of the present application;

[0025] FIG6 shows a schematic structural diagram of a driving circuit according to a third embodiment of the present application;

[0026] FIG7 outputs the switching timing of each switching element of the driving circuit of the third embodiment of the present application. DETAILED DESCRIPTION

[0027] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0028] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Persons skilled in the art will appreciate that manufacturers may use different terms to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in their functionality.

[0029] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected" between two nodes, it can be directly coupled or connected to the other element or there can be intermediate elements. The connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0030] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0031] In OLEDoS, current-driven OLEDs are typically used, varying the current flowing through them to adjust their brightness. However, the current requirement of each pixel is very small (e.g., 1pA to 10nA). This small current range corresponds to a narrow data voltage range, making precise control of the current difficult. This results in suboptimal grayscale gradation performance. Furthermore, the narrow data voltage range complicates data driver design, increasing development time and complexity.

[0032] In some embodiments, the data voltage range is expanded by changing the circuit structure of a single pixel unit. Figure 1 shows a schematic circuit structure diagram of a pixel unit that can widen the data voltage. In the pixel unit structure shown in Figure 1, the data voltage is redistributed inside the pixel unit through coupling capacitors C1 and C2. Therefore, if you want to achieve the same luminous brightness, you need to provide a larger data voltage to the pixel unit, which is more convenient for the design of the data driver. However, changes to the internal structure of the pixel unit may make it impossible for the original pixel unit to take into account both display quality and occupied area, which is not conducive to the development of thinner and lighter display devices and higher display quality.

[0033] This application provides a driver circuit that adjusts the source drive voltage of a pixel unit via a first capacitor. This allows a larger data voltage to be required while maintaining the source drive voltage of a single pixel unit (i.e., maintaining constant luminous brightness). This expands the data voltage range, facilitates precise control of the luminous current, and enhances the display quality of the display device. Furthermore, this reduces the design complexity of the data driver and further improves display quality.

[0034] Figure 2 shows a schematic structural diagram of a display device according to a first embodiment of the present application. As shown in Figure 2 , the display device 1 includes a driving circuit 10 (including a data driver 100 ), a scan driver 200 , and a plurality of pixel units 300 arranged in an array.

[0035] 2 , which illustrates an example of n rows × m columns of pixel cells 300 (n and m are both integers greater than or equal to 1). FIG2 takes n = 2 and m = 3 as an example. Each pixel cell is identified by coordinates (i, j), where i represents the row address of each pixel cell (in FIG2 , i = 1 or 2), and j represents the column address of each pixel cell (in FIG2 , i = 1, 2, or 3). Both i and j are integers greater than or equal to 1, and i ≤ n and j ≤ m.

[0036] The data driver 100 and the scan driver 200 are used to drive each pixel unit 300. In some embodiments, multiple scan drivers 200 can be provided as required. In the embodiment shown in FIG2 , a single scan driver 200 is used as an example. Each scan driver 200 includes a drive scan unit 210 and a write scan unit 220.

[0037] Furthermore, the display device 1 includes a plurality of data lines DL, a plurality of first scan lines GL1, and a plurality of second scan lines GL2. Each pixel unit 300(i, j) is connected to the data driver 100 and the drive scanning unit 210 and write scanning unit 220 of the scan driver 200 via the corresponding data lines DL, first scan lines GL1, and second scan lines GL2 to receive the corresponding data voltage Vdata, drive scan voltage Vscan1, and write scan voltage Vscan2.

[0038] In the embodiment shown in FIG2 , the pixel units 300 in the same row share a first scan line GL1 and a second scan line GL2. The drive scan voltage Vscan1 (1) is applied from the drive scan unit 210 to the pixel units 300 (1, 1), 300 (1, 2), and 300 (1, 3) in the first row via the first scan line GL1 (1), and the write scan voltage Vsacn2 (1) is applied from the write scan unit 220 to the pixel units 300 (1, 1), 300 (1, 2), and 300 (1, 3) in the first row via the second scan line GL2 (1). Similarly, the drive scan voltage Vscan1 (2) is applied from the drive scan unit 210 to the pixel units 300 (2, 1), 300 (2, 2) and 300 (2, 3) in the second row via the first scan line GL1 (2), and the write scan voltage Vsacn2 (2) is applied from the write scan unit 220 to the pixel units 300 (2, 1), 300 (2, 2) and 300 (2, 3) in the second row via the second scan line GL2 (2).

[0039] The pixel units 300 in the same column share one data line DL. For example, the pixel units 300 (1, 1) and 300 (2, 1) are connected to the data line DL (1), the pixel units 300 (1, 2) and 300 (2, 2) are connected to the data line DL (2), and the pixel units 300 (1, 3) and 300 (2, 3) are connected to the data line DL (3).

[0040] The driving circuit 10 further includes a first capacitor Cgain coupled to the data line, a first power supply terminal (providing a pre-processed voltage Vgain), and a switching element corresponding to each data line (for example, the switching element includes a first switching element S1, a second switching element S2, and a third switching element S3 corresponding to each data line).

[0041] Specifically, the first end of each data line DL is connected to the data driver 100 to receive the data voltage Vdata, and the second end is connected to the first power supply terminal to receive the pre-processing voltage Vgain. A first switching element S1, a second switching element S2, and a third switching element S3 are sequentially connected in series between the first and second ends of the data line, and each row of pixel units 300 is connected to the data line DL between the first switching element S1 and the second switching element S2. One end of the first capacitor Cgain is connected to the middle node between the second switching element S2 and the third switching element S3, and the other end of the first capacitor Cgain is grounded. During the row scanning phase corresponding to each pixel unit, by changing the switching states of the first switching element S1, the second switching element S2, and the third switching element S3, the pixel unit can be operated in the first sub-phase or the second sub-phase.

[0042] Figure 3A illustrates the circuit state of the driving circuit of the first embodiment of the present application during the first sub-phase; Figure 3B illustrates the circuit state of the driving circuit of the first embodiment of the present application during the second sub-phase; and Figure 4 outputs the switching timing of each switching element of the driving circuit of the first embodiment of the present application. In Figures 3A and 3B , a single data line driving a single pixel unit is used as an example. The driving circuit of the first embodiment of the present application will be further described below in conjunction with Figures 3A , 3B , and 4 .

[0043] 3A and 3B , a pixel unit 300 includes a pixel circuit and an organic light-emitting diode (OLED) driven by the pixel unit. The pixel circuit is exemplified by a basic 2T1C structure, i.e., the pixel circuit includes a driving transistor Td, a sampling transistor Ts, and a holding capacitor Cs. For example, the driving transistor Td and the sampling transistor Ts are PMOS TFTs.

[0044] Specifically, the gate of the sampling transistor Ts is connected to the second scan line GL2; one of its source and drain is connected to the gate of the driving transistor Td, and the other is connected to the data line DL. The source of the driving transistor is connected to a high-potential power supply terminal VDD, and the drain is connected to the anode of the organic light-emitting diode OLED. The cathode of the organic light-emitting diode OLED is connected to, for example, a ground voltage Vcath. A holding capacitor is connected between the high-potential power supply terminal VDD and the gate of the driving transistor Td.

[0045] The display device sequentially displays multiple frames of display images (only two frames of display images are shown as an example in FIG4 ). In each frame of display image, each pixel unit of the display device is turned on row by row (in FIG4 , the display device includes two rows of pixel units as an example).

[0046] In the row scanning phase corresponding to any pixel unit 300, when the second scanning voltage Vscan2 provided by the second scanning line GL2 is low, the sampling transistor Ts is turned on. The pixel unit operates in the first sub-phase or the second sub-phase according to the on / off state of the switch element.

[0047] In the first sub-stage, referring to FIG3A , the first switch element S1 and the third switch element S3 on the data line DL are closed, and the second switch element S2 is open. At this point, the first capacitor Cgain is connected to the first power supply terminal and charged to the preprocessing voltage Vgain. The total charge of the first capacitor Cgain is Cgain×Vgain. Furthermore, the data driver 100 provides the data voltage Vdata to the pixel unit 300 via the data line DL. If the equivalent total capacitance on the data line DL is calculated as Cdata (Cdata = M×CC, where CC is the parasitic capacitance per unit length and M is the total length of the data line), then the total charge on the data line DL is Cdata×Vdata.

[0048] In the second sub-phase, referring to FIG3B , the first switch element S1 and the third switch element S3 on the data line DL are turned off, and the second switch element S2 is turned on. At this point, the first capacitor Cgain, the parasitic capacitance on the data line DL, and the holding capacitor Cs within the pixel unit 300 are connected in parallel. Due to the characteristics of parallel capacitance, the charge of the data line DL and the first capacitor Cgain is redistributed.

[0049] After the charge is redistributed, the voltage stored in the holding capacitor Cs can be expressed as follows:

[0050] Among them, Vcs represents the voltage of the holding capacitor (that is, the source driving voltage of the pixel unit), Cdata represents the equivalent capacitance on the data line, Vdata represents the data voltage output by the data driver, Cgain represents the capacitance of the first capacitor, and Vgain represents the pre-processing voltage provided by the first power supply end.

[0051] When the row scan phase corresponding to the pixel ends, the second scanning voltage Vscan2 reaches a high level, the sampling transistor Ts is turned off, and the storage capacitor Cs, lacking a discharge path, maintains the stored drive voltage Vcs. It remains unchanged until the next time the sampling transistor Ts is turned on, when it is updated. The drive voltage stored in the storage capacitor Cs, which is the voltage applied to the gate-source of the drive transistor Td, determines the current flowing through the source and drain of the drive transistor Td. This current drives the OLED to emit light of a corresponding brightness.

[0052] According to the above formula (1), the data voltage Vdata can be expressed as follows:

[0053] Among them, Vcs represents the voltage of the holding capacitor (that is, the source driving voltage of the pixel unit), Cdata represents the equivalent capacitance on the data line, Vdata represents the data voltage output by the data driver, Cgain represents the capacitance of the first capacitor, and Vgain represents the pre-processing voltage provided by the first power supply end.

[0054] According to equation (2), Vcs is related to Cgain and Vdata. Therefore, while maintaining the OLED's luminance (i.e., maintaining Vcs), Vdata can be adjusted by adjusting Cgain. This expands the Vdata range, facilitates precise control of the luminous current, and improves the display quality of the display device. This also reduces the design complexity of the data driver and further improves display quality.

[0055] It should be noted that the pixel circuits of Figures 3A and 3B also include a structure for driving scanning controlled by the scan driver unit 210. However, since this structure is not unique, for example, in some embodiments, this structure is another transistor connected between the high potential VDD and the drive transistor Md. In other embodiments, it can also be other structures suitable for repeatedly applying the high potential VDD at a certain period. Therefore, these components are omitted in Figures 3A and 3B. Of course, it should also be understood that in some embodiments, based on actual display requirements, these structures may not be included in the pixel unit. In this case, the corresponding display device does not need to include the scan driver unit 210 and the second scan line GL2 in the scan driver 200.

[0056] It should also be noted that the pixel unit shown in FIG3A and FIG3B uses a basic 2T1C structure as an example of a pixel circuit structure. However, the present application does not limit the specific pixel circuit structure of the pixel unit. In some other embodiments, in addition to the 2T1C structure shown in FIG3A and FIG3B as the basic structure, additional transistors and / or capacitors may be included. For example, other structures may include 4T1C (i.e., including four transistors and one capacitor. For example, in some embodiments, the 4T1C structure differs from the 2T1C structure in that the 4T1C structure also includes two reset transistors to discharge the pixel unit), 4T2C (i.e., including four transistors and two capacitors. For example, in some embodiments, the 4T2C structure adds a capacitor to the 4T1C structure to improve charge storage stability), and 5T1C (i.e., including five transistors and one capacitor. In some embodiments, the 5T1C structure adds a transistor to the 4T1C structure to improve display quality). Since the specific structures and operating principles of each type of pixel circuit are substantially or completely consistent with those in the prior art, they are not further described here. Furthermore, in the timing sequence shown in FIG4 , the duration t1 of the first sub-phase and the duration t2 of the second sub-phase are only used as examples and do not represent the actual time ratio.

[0057] Furthermore, in a preferred embodiment, the driving circuit 10 further includes an operational amplifier OP corresponding to each data line DL. The operational amplifier OP is connected between the data driver 100 and the corresponding data line. Specifically, the non-inverting input terminal of the operational amplifier OP is connected to the data driver 100, and the inverting input terminal and output terminal are both connected to the first end of the corresponding data line DL. This allows the operational amplifier OP to function as a voltage follower to ensure complete transmission of the data voltage Vdata.

[0058] Figure 5 shows a schematic structural diagram of a display device according to a second embodiment of the present application. As shown in Figure 5 , the display device 2 includes a driving circuit 20 (including a data driver 100 ), a scan driver 200 , and a plurality of pixel units 300 arranged in an array.

[0059] 5 , which illustrates an example of n rows × m columns of pixel cells 300 (n and m are both integers greater than or equal to 1). FIG5 takes n = 2 and m = 3 as an example. Each pixel cell is identified by coordinates (i, j), where i represents the row address of each pixel cell (in FIG5 , i = 1 or 2), and j represents the column address of each pixel cell (in FIG5 , i = 1, 2, or 3). Both i and j are integers greater than or equal to 1, and i ≤ n and j ≤ m.

[0060] The data driver 100 and the scan driver 200 are used to drive each pixel unit 300. In some embodiments, multiple scan drivers 200 can be provided as required. In the embodiment shown in FIG5 , a single scan driver 200 is used as an example. Each scan driver 200 includes a drive scan unit 210 and a write scan unit 220.

[0061] Furthermore, the display device 2 includes a plurality of data lines DL, a plurality of first scan lines GL1, and a plurality of second scan lines GL2. Each pixel unit 300(i, j) is connected to the drive scanning unit 210 and the write scanning unit 220 of the data driver 100 or the scan driver 200 via the corresponding data lines DL, the first scan lines GL1, and the second scan lines GL2 to receive the corresponding data voltage Vdata, the drive scan voltage Vscan1, and the write scan voltage Vscan2.

[0062] In addition, in a second embodiment of the present application, as shown in FIG5 , the driving circuit 20 further includes a first capacitor Cgain coupled to the data line, a first power supply terminal (providing a pre-processing voltage Vgain), and a switching element corresponding to each data line (including a first switching element S1, a second switching element S2, and a third switching element S3 corresponding to each data line).

[0063] Specifically, a first end of each data line DL is connected to the data driver 100 to receive a data voltage Vdata, and a second end is connected to a first power supply terminal to receive a pre-processing voltage Vgain. A first switching element S1, a second switching element S2, and a third switching element S3 are sequentially connected in series between the first and second ends of the data line.

[0064] The difference from the first embodiment of the present application is that in the second embodiment of the present application, the first capacitor Cgain is connected to one end of the corresponding data line DL near the data driver 100. Specifically, each row of pixel units 300 is connected to the data line DL between the second switching element S2 and the third switching element S3. One end of the first capacitor Cgain is connected to the middle node between the first switching element S1 and the second switching element S2, and the other end of the first capacitor Cgain is grounded. During the row scanning phase corresponding to each pixel unit, by changing the switching state of the first switching element S1, the second switching element S2, and the third switching element S3, the pixel unit can be operated in the first sub-phase or the second sub-phase.

[0065] The timing logic of each switching element under the second embodiment of the present application is consistent with the timing logic of each switching element under the first embodiment of the present application. Specifically, in the first sub-stage, the first switching element S1 and the third switching element S3 on the data line DL are closed, and the second switching element S2 is disconnected. At this time, the first capacitor Cgain is connected to the data driver 100 and is charged to the data voltage Vdata. The total charge of the first capacitor Cgain is Cgain×Vdata. In addition, the first power supply end provides the pre-processing voltage Vgain to the pixel unit 300 through the data line DL. If the equivalent total capacitance on the data line DL is counted as Cdata, then the total charge on the data line DL at this time is Cdata×Vgain.

[0066] In the second sub-phase, the first switch element S1 and the third switch element S3 on the data line DL are turned off, and the second switch element S2 is turned on. At this point, the first capacitor Cgain, the parasitic capacitance on the data line DL, and the holding capacitor Cs within the pixel unit 300 are connected in parallel. Due to the characteristics of parallel capacitance, the charge of the data line DL and the first capacitor Cgain is redistributed.

[0067] After the charge is redistributed, the voltage stored in the holding capacitor Cs can be expressed as follows:

[0068] Among them, Vcs represents the voltage of the holding capacitor (that is, the source driving voltage of the pixel unit), Cdata represents the equivalent capacitance on the data line, Vdata represents the data voltage output by the data driver, Cgain represents the capacitance of the first capacitor, and Vgain represents the pre-processing voltage provided by the first power supply end.

[0069] According to the above formula (3), the data voltage Vdata can be expressed as follows:

[0070] Among them, Vcs represents the voltage of the holding capacitor (that is, the source driving voltage of the pixel unit), Cdata represents the equivalent capacitance on the data line, Vdata represents the data voltage output by the data driver, Cgain represents the capacitance of the first capacitor, and Vgain represents the pre-processing voltage provided by the first power supply end.

[0071] According to the above formula (4), since Vcs is related to Cgain and Vdata, when the OLED luminance remains unchanged (that is, when Vcs remains unchanged), the corresponding Vdata can be adjusted by adjusting Cgain, thereby achieving the purpose of expanding the Vdata range.

[0072] Figure 6 shows a schematic structural diagram of a display device according to a third embodiment of the present application. As shown in Figure 6 , the display device 3 includes a driving circuit 30 (including a data driver 100 ), a scan driver 200 , and a plurality of pixel units 300 arranged in an array.

[0073] 6 , which illustrates an example of n rows × m columns of pixel cells 300 (n and m are both integers greater than or equal to 1). FIG6 takes n = 2 and m = 3 as an example. Each pixel cell is identified by a coordinate (i, j), where i represents the row address of each pixel cell (in FIG6 , i = 1 or 2), and j represents the column address of each pixel cell (in FIG6 , i = 1, 2, or 3). Both i and j are integers greater than or equal to 1, and i ≤ n and j ≤ m.

[0074] The data driver 100 and the scan driver 200 are used to drive each pixel unit 300. In some embodiments, multiple scan drivers 200 can be provided as required. In the embodiment shown in FIG6 , a single scan driver 200 is used as an example. Each scan driver 200 includes a drive scan unit 210 and a write scan unit 220.

[0075] Furthermore, the display device 3 includes a plurality of data lines DL, a plurality of first scan lines GL1, and a plurality of second scan lines GL2. Each pixel unit 300(i, j) is connected to the drive scanning unit 210 and the write scanning unit 220 of the data driver 100 or the scan driver 200 via the corresponding data lines DL, first scan lines GL1, and second scan lines GL2 to receive the corresponding data voltage Vdata, drive scan voltage Vscan1, and write scan voltage Vscan2.

[0076] In addition, in a third embodiment of the present application, as shown in FIG6 , the driving circuit 30 further includes a first capacitor Cgain coupled to the data line, a first power supply terminal (providing a pre-processing voltage Vgain), and a switching element corresponding to each data line (including a first switching element S1, a second switching element S2, and a third switching element S3 corresponding to each data line).

[0077] The difference from the first or second embodiment of the present application is that in the third embodiment of the present application, the first switching element S1 and the first capacitor Cgain are connected in series on the data line DL, with the first switching element S1 located at one end of the first capacitor Cgain and each pixel unit 300 located at the other end of the first capacitor. One end of the second switching element S2 is connected to the middle node between the first switching element S1 and the first capacitor Cgain, and the other end is connected to the first power supply terminal. One end of the third switching element S3 is connected to the middle node between the first capacitor Cgain and each pixel unit 300, and the other end is connected to the first power supply terminal.

[0078] In the row scanning phase corresponding to the pixel unit 300, in the row scanning phase corresponding to each pixel unit, by changing the switching states of the first switching element S1, the second switching element S2 and the third switching element S3, the pixel unit can operate in the first sub-phase or the second sub-phase.

[0079] Figure 7 shows the switching timing of each switching element in the driving circuit of the third embodiment of the present application. In conjunction with Figure 7, for the third embodiment of the present application, in the first sub-phase, the first switching element S1 connected to the data line DL is disconnected, the second switching element S2 and the third switching element S3 are closed, and the first power supply terminal is connected to the two plates of the first capacitor Cgain (i.e., the first power supply terminal is connected to the first capacitor Cgain and the data line), clearing the capacitor charge. This allows for adjustment of the DC offset, thereby improving display quality.

[0080] In the second sub-phase, the first switch element S1 connected to the data line DL is closed, the second switch element S2 and the third switch element S3 are opened, and the data driver 100 provides the data voltage Vdata to the data line. At this time, the first capacitor Cgain and the parasitic capacitance on the data line DL are connected in series. Due to the characteristics of series capacitance, the first capacitor Cgain divides the data voltage Vdata. Based on the principle of linear superposition, the voltage stored in the holding capacitor Cs can be expressed as follows:

[0081] Among them, Vcs represents the voltage of the holding capacitor (that is, the source driving voltage of the pixel unit), Cdata represents the equivalent capacitance on the data line, Vdata represents the data voltage output by the data driver, Cgain represents the capacitance of the first capacitor, and Vgain represents the pre-processing voltage provided by the first power supply end.

[0082] According to the above formula (5), the data voltage Vdata can be expressed as follows:

[0083] Among them, Vcs represents the voltage of the holding capacitor (that is, the source driving voltage of the pixel unit), Cdata represents the equivalent capacitance on the data line, Vdata represents the data voltage output by the data driver, Cgain represents the capacitance of the first capacitor, and Vgain represents the pre-processing voltage provided by the first power supply end.

[0084] According to equation (6), Vcs is related to Cgain and Vdata. Therefore, while maintaining the OLED's luminance (i.e., maintaining Vcs), adjusting Cgain can adjust the corresponding Vdata. This expands the Vdata range, facilitates precise control of the luminous current, and improves the display quality of the display device. This also reduces the design difficulty of the data driver and further improves display quality.

[0085] It should be understood that, in the timing sequence shown in FIG. 7 , the duration t3 of the first sub-phase and the duration t4 of the second sub-phase are merely examples and do not represent actual time proportions.

[0086] Furthermore, in a preferred embodiment, the driving circuit 30 further includes an operational amplifier OP corresponding to each data line DL. The operational amplifier OP is connected between the data driver 100 and the corresponding data line. Specifically, the non-inverting input terminal of the operational amplifier OP is connected to the data driver 100, and the inverting input terminal and output terminal are both connected to the first end of the corresponding data line DL. This allows the operational amplifier OP to function as a voltage follower to ensure complete transmission of the data voltage Vdata.

[0087] In summary, according to the driver circuit and display device provided herein, the first capacitor is used to adjust the source drive voltage of the pixel unit. This allows a larger data voltage to be required while maintaining the source drive voltage of a single pixel unit (i.e., maintaining the same luminous brightness). This expands the data voltage range, facilitates more precise control of the luminous current, and improves the display quality of the display device. Furthermore, this reduces the design complexity of the data driver and further improves display quality.

[0088] In addition, the present application also provides a chip, including the driving circuit as described above, and thus also including the above-mentioned beneficial effects, which will not be repeated here.

[0089] The embodiments of the present invention are described above, but these embodiments do not describe all details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and modify and use it based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A driving circuit drives a plurality of pixel units in a display device via a plurality of data lines, and each of the pixel units emits light with a corresponding brightness according to a source driving voltage. Among them, The driving circuit includes: A data driver that provides data voltages corresponding to the pixel units; and A plurality of first capacitors. When each of the first capacitors is coupled to a corresponding pixel unit via a corresponding data line, each of the first capacitors adjusts the source driving voltage of each of the pixel units according to the corresponding data voltage, so that the corresponding source driving voltage is related to the capacitance value of the corresponding first capacitor and the corresponding data voltage.

2. The driving circuit according to claim 1, Among them, The driving circuit further includes a first power supply terminal that provides a preprocessing voltage. Each line scanning stage of at least one frame of the display device includes a first sub-stage and a second sub-stage: In the first sub-stage, the first capacitor and / or the data line receive the preprocessing voltage. In the second sub-stage, the first capacitor is coupled to the data line and disconnected from the preprocessing voltage.

3. The driving circuit according to claim 2, Among them, The driving circuit further includes a switching element corresponding to each data line, and the switching element is used to switch between the first sub-stage and the second sub-stage.

4. The driving circuit according to claim 3, Among them, The first capacitor is connected in series on the data line, one end of the first capacitor is connected to the data driver, and the other end is connected to the corresponding pixel units. The first power supply terminal is connected to both ends of the first capacitor respectively.

5. The driving circuit according to claim 4, Among them, The switching element includes a first switching element, a second switching element, and a third switching element. For each data line, the first switching element corresponding to the data line is connected in series between the data driver and the first capacitor; one end of the second switching element is connected to the intermediate node between the first switching element and the first capacitor, and the other end is connected to the first power supply terminal; one end of the third switching element is connected to the intermediate node between the first capacitor and the pixel units, and the other end is connected to the first power supply terminal. The driving circuit is configured to: In the first sub-stage, close the second switching element and the third switching element and open the first switching element. And In the second sub-stage, open the second switching element and the third switching element and close the first switching element.

6. The driving circuit according to claim 3, Among them, The first end of the data line is connected to the data driver, and the second end is connected to the first power supply terminal. One end of the first capacitor is grounded, and the other end is connected to the data line, and the corresponding pixel units are all located between the first capacitor and the data driver; or the corresponding pixel units are all located between the first capacitor and the first power supply terminal.

7. The driving circuit according to claim 6, Among them, The switching element includes a first switching element, a second switching element, and a third switching element. For each of the data lines, the corresponding first switching element, second switching element, and third switching element are sequentially connected in series between the first end and the second end of the data line. Each of the pixel units is connected between the second switching element and the third switching element. One end of the first capacitor is connected between the first switching element and the second switching element, and the other end is grounded. The driving circuit is configured to: In the first sub-phase, close the first switching element and the third switching element and open the second switching element. In the second sub-phase, open the first switching element and the third switching element and close the second switching element.

8. The driving circuit according to claim 6, wherein, The switching element includes a first switching element, a second switching element, and a third switching element. For each of the data lines, the corresponding first switching element, second switching element, and third switching element are sequentially connected in series between the first end and the second end of the data line. Each of the pixel units is connected between the first switching element and the second switching element. One end of the first capacitor is connected between the second switching element and the third switching element, and the other end is grounded. The driving circuit is configured to: In the first sub-phase, close the first switching element and the third switching element and open the second switching element. In the second sub-phase, open the first switching element and the third switching element and close the second switching element.

9. The driving circuit according to claim 1, wherein, The driving circuit further includes a plurality of operational amplifiers. Each of the operational amplifiers is connected between the data driver and the corresponding data line. The inverting input terminal and the output terminal of the operational amplifier are connected and connected to the corresponding data line, and the non-inverting input terminal of the operational amplifier is connected to the data driver.

10. A chip, wherein, The chip includes the driving circuit according to any one of claims 1 to 9.

11. A display device, wherein, The display device includes: The driving circuit according to any one of claims 1 to 9; and A plurality of the pixel units.

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