Three-dimensional semiconductor structure, three-dimensional capacitor, and preparation method therefor

Abstract

Provided in the present invention are a three-dimensional semiconductor structure, a three-dimensional capacitor, and a preparation method therefor. The three-dimensional semiconductor structure comprises the following structures: a first conductive layer; a dielectric layer which is located on the surface of the first conductive layer and is at least partially in conformal contact with the first conductive layer; and a second conductive layer which is located on the surface of the dielectric layer and is at least partially in conformal contact with the dielectric layer. The first conductive layer comprises a metal patterning layer and a grid-shaped conductive layer which are in electrical contact with one another, and the first conductive layer has a plurality of protruding structures. As the three-dimensional capacitor of the present invention has very good conductive and heat dissipation performance, the three-dimensional capacitor is at an advantage in high-power and high-temperature application scenarios, and can achieve greater power tolerance and a wider working temperature range.

Description

A three-dimensional semiconductor structure, a three-dimensional capacitor and a method for manufacturing the same Technical Field

[0001] The present invention relates to a three-dimensional semiconductor structure, a three-dimensional capacitor and a preparation method thereof, belonging to the field of semiconductor capacitor device structures, and in particular to a three-dimensional semiconductor structure with good performance in high-temperature and high-power application scenarios. Background Art

[0002] As one of the three major passive components (capacitors, resistors, and inductors), capacitors have long been a crucial component of various circuits. However, as demand for electronic products shifts toward miniaturization, multi-functions, and environmental friendliness, efforts are underway to make electronic systems smaller, more integrated, and more powerful.

[0003] In this context, traditional two-dimensional capacitors have shown limitations when faced with requirements such as multi-layer interconnection and high-frequency performance. Due to the constraints of the two-dimensional capacitor structure, the capacitance density of two-dimensional capacitors is greatly limited, making it difficult to meet the current electronic devices' requirements for high performance and high integration. At the same time, under high-frequency conditions, two-dimensional capacitors often have large losses, which also restricts their application in the radio frequency field. Therefore, in order to meet the needs of modern electronic devices for high-performance capacitors, researchers have begun to explore new capacitor structures and manufacturing processes, hoping to break through the limitations of traditional two-dimensional capacitors and explore new capacitor structures to improve integration and performance.

[0004] Conventionally, the stored charge in a cell is increased by reducing the thickness of the dielectric and / or increasing the capacitor area. The capacitor area has been increased by using complex three-dimensional semiconductor structures such as deep cylinders, pillars, and crowns. Three-dimensional semiconductor structures use high aspect ratios to increase capacitor area.

[0005] With the continuous development of micro-nano processing technology, people can prepare more complex micro-nano structures and achieve more precise control at the nanoscale, which provides more possibilities for the development of new three-dimensional capacitors. For example, higher capacitance density can be achieved through multi-layer stacking, and better frequency response characteristics can be achieved through precise control of the structure. At the same time, progress in materials science has also provided more material options for new capacitors, such as dielectric materials with high dielectric constant and low loss, and electrode materials with excellent conductive properties. The development of these materials provides the basis for the realization of three-dimensional capacitors.

[0006] Currently, most existing three-dimensional capacitors use low-resistance silicon as the conductive layer material, and use a steep etching process to create a three-dimensional structure, ultimately forming a three-dimensional semiconductor structure. These capacitors often face problems such as high parasitic resistance, susceptibility to ambient temperature, and slow heat dissipation. Furthermore, steep etching of metal or semiconductor materials is difficult with existing technology, making it difficult to obtain a structure with precise dimensions and high uniformity. This limits the application of three-dimensional capacitors in high-temperature and high-power scenarios. Summary of the Invention

[0007] In view of this, the present invention provides a three-dimensional semiconductor structure with good performance in high-temperature and high-power application scenarios. The bottom of the three-dimensional semiconductor structure has multiple three-dimensional structures protruding toward the dielectric layer. The protruding three-dimensional structures are not formed by etching. Avoiding the etching process can prevent the occurrence of defects such as rough and uneven side walls of the protrusions. The first electrode layer below is a double-layer structure of a metal patterned layer and a grid-shaped conductive layer. The double-layer structure is made of metal or carbon nanotubes with excellent heat dissipation and conductivity, which improves the heat dissipation capacity and can quickly dissipate heat in high-temperature and high-power environments.

[0008] In order to solve the technical problems mentioned in the above-mentioned prior art and achieve corresponding technical effects, the present invention provides a three-dimensional semiconductor structure, a three-dimensional capacitor, a method for preparing a three-dimensional capacitor, and an electronic device having a three-dimensional capacitor.

[0009] The three-dimensional semiconductor structure of the present invention includes the following structure:

[0010] a first conductive layer;

[0011] a dielectric layer located on a surface of the first conductive layer and in conformal contact with at least a portion of the first conductive layer;

[0012] a second conductive layer located on the surface of the dielectric layer and in conformal contact with at least a portion of the dielectric layer;

[0013] It is characterized in that the first conductive layer includes a metal patterned layer and a grid-shaped conductive layer that are electrically in contact with each other, and the first conductive layer has a plurality of protruding structures.

[0014] Furthermore, the grid-shaped conductive layer is copper and / or carbon nanotubes.

[0015] Furthermore, the grid-shaped conductive layer may also be other metals and / or carbon nanotubes, and the other metals include but are not limited to Al, Pt, and Au.

[0016] Furthermore, the width of the protruding structure is a, the height of the protruding structure is h, and the aspect ratio h / a of the protruding structure is greater than 1.

[0017] The present invention also discloses a three-dimensional capacitor, characterized in that it comprises the three-dimensional semiconductor structure as described above, and a first electrode and a second electrode, wherein the first electrode is electrically connected to the first conductive layer, and the second electrode is electrically connected to the second conductive layer.

[0018] Furthermore, the sum of the thickness of the first conductive layer excluding the protruding structure and the thickness of the first electrode is t1, and the sum of the thickness of the second conductive layer excluding the thickness of the inwardly protruding part and the thickness of the second electrode is t2, where the ratio of t1 to t2 is 0.5-2.

[0019] The present invention also discloses a method for preparing a three-dimensional capacitor, which is characterized by comprising the following steps:

[0020] Step S01: providing a semiconductor substrate;

[0021] Step S02: fabricating a metal patterned structure on the semiconductor substrate;

[0022] Step S03: forming a grid-shaped conductive layer on the metal patterned structure, wherein the metal patterned structure and the grid-shaped conductive layer together constitute a first conductive layer of the three-dimensional semiconductor structure, and the first conductive layer has a plurality of protruding structures;

[0023] Step S04: forming a dielectric layer on the first conductive layer, wherein the dielectric layer is in conformal contact with the first conductive layer at least partially;

[0024] Step S05: forming a second conductive layer on the surface of the dielectric layer, wherein the second conductive layer is in conformal contact with at least part of the dielectric layer.

[0025] Furthermore, after step S05, the method further includes:

[0026] Step S06: peeling off the semiconductor substrate to expose the first conductive layer.

[0027] Furthermore, after step S06, the method further includes:

[0028] Step S07: forming a first electrode and a second electrode on the first conductive layer and the second conductive layer respectively, wherein the first electrode is electrically connected to the first conductive layer, and the second electrode is electrically connected to the second conductive layer.

[0029] Furthermore, the semiconductor substrate includes but is not limited to a silicon substrate, a germanium substrate or an SOI substrate.

[0030] Furthermore, the grid-shaped conductive layer is copper and / or carbon nanotubes.

[0031] Furthermore, the grid-shaped conductive layer may also be other metals and / or carbon nanotubes, and the other metals include but are not limited to Al, Pt, and Au.

[0032] Furthermore, the width of the protruding structure is a, the height of the protruding structure is h, and the aspect ratio h / a of the protruding structure is greater than 1.

[0033] Furthermore, the dielectric layer is an insulating material, and the dielectric layer is formed by an atomic layer deposition process.

[0034] Furthermore, the fabrication of the metal patterned structure includes depositing a metal layer on a substrate, and forming the metal patterned structure using methods including but not limited to electroplating or 3D printing.

[0035] Furthermore, the process of forming the grid-shaped conductive layer on the metal patterned structure includes but is not limited to one or a combination of electroplating, 3D printing and selective growth.

[0036] Furthermore, the second conductive layer is formed by a two-step process, firstly using atomic layer deposition technology to form a conductive thin layer, and then using electroplating and / or chemical plating methods.

[0037] Furthermore, the sum of the thickness of the first conductive layer excluding the protruding structure and the thickness of the first electrode is t1, and the sum of the thickness of the second conductive layer excluding the thickness of the inwardly protruding part and the thickness of the second electrode is t2, where the ratio of t1 to t2 is 0.5-2.

[0038] The present invention also discloses an electronic device, which is characterized by comprising a control circuit and the three-dimensional capacitor as described above.

[0039] Furthermore, the second electrode extends through the hole to the plane where the first electrode is located.

[0040] From the above description of the three-dimensional semiconductor structure, three-dimensional capacitor and preparation method of the present invention, it can be seen that the raised structure of the first conductive layer below the three-dimensional semiconductor structure of the present invention is not formed by an etching process, which prevents side wall damage and the formation of rough surfaces during the etching process. It is formed using metals and carbon nanotubes whose conductivity and heat dissipation are better than low-resistance silicon. The grid shape also increases the heat dissipation area, which can quickly dissipate heat in high temperature and high power environments, thereby improving the performance of the three-dimensional capacitor.

[0041] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without making any creative efforts.

[0043] FIG1 is a schematic diagram of a three-dimensional semiconductor structure of the present invention.

[0044] FIG2 is a schematic diagram of a grid structure of a first conductive layer of the present invention;

[0045] FIG3 is a schematic diagram of the carbon nanotube structure on the first conductive layer of the present invention;

[0046] FIG4 is a schematic diagram of a three-dimensional capacitor according to the present invention;

[0047] 5a and 5b are schematic diagrams of the width and height of the protrusions in the first conductive layer of the three-dimensional semiconductor structure and the three-dimensional capacitor, respectively, according to the present invention;

[0048] FIG6 is a flow chart of the process for preparing a three-dimensional capacitor according to the present invention;

[0049] 7a-7f are schematic structural diagrams of various stages in the preparation process of the three-dimensional capacitor of the present invention.

[0050] FIG8 is a comparison of the parasitic resistance of the copper conductive layer and the low-resistance silicon conductive layer.

[0051] FIG9 is a comparison of the parasitic resistance of the carbon nanotube + copper conductive layer and the low-resistance silicon conductive layer.

[0052] Reference numerals: 1 - dielectric layer; 2 - first conductive layer; 3 - second conductive layer; 4 - first electrode; 5 - second electrode; a - width of the protruding structure; h - height of the protruding structure; 100 - semiconductor substrate; 200 - metal patterned structure. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0054] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are used only to distinguish the description and should not be understood as indicating or implying relative importance.

[0055] The prior art already has technical solutions for increasing the area of ​​3D capacitors by etching columnar or crown-shaped protrusions. However, since columnar or crown-shaped protrusions are formed using either dry or wet etching processes, dry etching easily forms uneven, rough surfaces on the protrusion sidewalls, while wet etching processes take a long time and, because wet etching is isotropic, easily forms inwardly concave "big-bellied" groove structures on the protrusion sidewalls, which is not conducive to the further adhesion and formation of the dielectric layer and the conductive layer. While the underlying conductive layer in the prior art typically uses low-resistance silicon, this is because low-resistance silicon has better process compatibility in integrated circuits, but it also has the disadvantages of etching defects, high resistance, and slow heat dissipation, which are not conducive to the use of 3D capacitors in high-temperature and high-power application environments, thus limiting the use of 3D capacitors.

[0056] Therefore, the present invention proposes a new three-dimensional semiconductor structure and its preparation method, which can avoid the defect problem caused by etching the raised structure, and has the characteristics of low resistance and fast heat dissipation. The schematic diagram of the three-dimensional semiconductor structure of the present invention is shown in Figure 1: The three-dimensional semiconductor structure is a sandwich structure stacked up and down, specifically including a first conductive layer 2 located at the bottom, a dielectric layer 1 in the middle, and a second conductive layer 3 at the top, wherein the dielectric layer 1 in the middle is located on the surface of the first conductive layer 2 and is in at least partial conformal contact with the first conductive layer 2. Conformal contact here means that the dielectric layer is formed on the surface of the first conductive layer according to the undulating shape of the first conductive layer and is in contact with the first conductive layer. The second conductive layer 3 is located on the surface of the dielectric layer 1 and is in at least partial conformal contact with the dielectric layer 1. The three-layer stacked structure in contact with each other from top to bottom forms a three-dimensional semiconductor structure.

[0057] The first conductive layer 2 includes a metal patterned layer and a grid-shaped conductive layer that are in electrical contact with each other, and the first conductive layer has a plurality of protruding structures.

[0058] The metal of the metal patterned layer is Al or Cu. After forming a metal layer of the corresponding metal material, a metal patterned layer having a patterned structure is formed by electroplating or 3D printing.

[0059] The thermal conductivity of copper is about 400 W / (m·K) below 100℃, while the specific heat capacity of copper is 390J / (kg·℃) and the resistivity is 1.75 × 10 -6Ω·cm, and the temperature coefficient is 0.0039 / ℃. The thermal conductivity of aluminum is about 230W / (m·K) when it is below 100℃, the specific heat capacity of aluminum is 880J / (kg·℃), and the resistivity is 2.65 × 10 -6 Ω·cm, and the temperature coefficient is 0.0051 / ℃. The thermal conductivity of silicon material is about 200 W / (m·k), the specific heat capacity of silicon material is about 700 J / (kg·K), and the resistivity of low-resistance silicon is about 10 -3 Ω·cm or 10 -2 The thermal conductivity is on the order of Ω·cm, with a temperature coefficient between -0.05 / °C and -0.1 / °C. A comprehensive comparison of the electrical conductivity, heat absorption and heat dissipation, and thermal expansion properties of silicon, copper, and aluminum reveals that copper and aluminum have a lower thermal expansion coefficient, better heat absorption and heat dissipation, and excellent electrical conductivity, making them suitable for high-temperature environments (less susceptible to thermal deformation), with lower parasitic resistance and easier heat dissipation.

[0060] The metal patterned layer has a grid-like conductive layer (conductive grid), and the grid-like conductive layer and the metal patterned layer together constitute a first conductive layer 2. The grid-like conductive layer can be copper, carbon nanotubes, or a combination of copper and carbon nanotubes. The combination of copper and carbon nanotubes is copper grown on the outer surface of the carbon nanotubes or carbon nanotubes grown on the outer surface of copper. Since carbon nanotubes have good electrical and thermal conductivity, this is also beneficial for the three-dimensional semiconductor structure to reduce parasitic resistance and be able to work better in a high-temperature environment.

[0061] The mesh conductive layer can also select other suitable combinations of metals and carbon nanotubes. These suitable metals include but are not limited to combinations of metals such as Al, Pt, Au and carbon nanotubes, such as Al and / or carbon nanotubes, Pt and / or carbon nanotubes, Au and / or carbon nanotubes, etc.

[0062] The schematic diagram of the grid-like structure of the first conductive layer 2 is shown in FIG2 . It can be a grid-like structure with multiple evenly distributed protrusions and recesses spaced apart from each other. Because the dielectric layer 1 above the first conductive layer 2 is at least partially conformally attached to the surface of the first conductive layer, this can increase the area of ​​the formed capacitor structure and improve the capacitance. Protrusions with regular shapes and even distribution are easier to form, but non-uniform distribution of protrusions can also achieve the three-dimensional semiconductor structure of the present invention.

[0063] As shown in FIG3 , the first conductive layer is a grid-like conductive layer formed by carbon nanotubes of the present invention. The carbon nanotubes can be selectively grown in the corresponding areas of the metal patterned layer where protrusions need to be formed to form a grid-like conductive layer.

[0064] In the present invention, the dielectric layer can achieve the required capacitance by using an insulating layer. However, according to the capacitance calculation formula, the capacitance is proportional to the dielectric constant of the dielectric layer and the relative area of ​​the plates. In addition to forming a certain raised structure to increase the area, the present invention also uses a dielectric layer material with a high dielectric constant, which can achieve a higher capacitance density.

[0065] A second conductive layer 3 is formed on the surface in contact with the dielectric layer 1 and is in conformal contact with the dielectric layer 1 at least partially. The second conductive layer 3 can be made of a conductive material. Preferably, a metal, a conductive element or a compound with good conductive properties can be selected. More preferably, the material of the second conductive layer is selected from one or more materials with good conductive properties such as Al, Ir, Ru, Pt, Cu, Au, graphene, carbon nanotubes, and their alloys or compounds, which can reduce the loss of parasitic resistance.

[0066] Furthermore, the present invention also discloses a three-dimensional capacitor, as shown in Figure 4, which has the sandwich-stacked three-dimensional semiconductor structure described above, including a dielectric layer 1, a first conductive layer 2 and a second conductive layer 3, and further including a first electrode 4 and a second electrode 5, wherein the first electrode 4 is electrically connected to the first conductive layer 2, and the second electrode 5 is electrically connected to the second conductive layer 3.

[0067] The first electrode and the second electrode can be made of metals with excellent conductive properties. Preferably, metals with good conductive properties and anti-oxidation properties are selected as electrode materials to reduce impedance and prevent oxidation by external water, oxygen, etc., such as Cu, Au, Pt, Ru or one or more materials and alloys thereof.

[0068] Furthermore, as shown in FIG4 , the sum of the thickness of the first conductive layer excluding the protruding structure and the thickness of the first electrode is t1, and the sum of the thickness of the second conductive layer excluding the thickness of the inwardly protruding portion and the thickness of the second electrode is t2, wherein the ratio of t1 to t2 is 0.5-2. Within this range, the thickness of the electrodes and conductive layers, compared to the total thickness of the upper and lower conductive layers and electrodes in the existing capacitor structure, is such that when one side is thicker and the other is thinner, the thinner portion will break when the wire is broken during the electrical connection. At the same time, when the thickness of the upper and lower portions is uneven, the film quality, insulation of the dielectric sacrificial layer, and the current carrying capacity of the lower electrode cannot be guaranteed, resulting in a decrease in the power handling capability of the device. In this solution, the thickness of the first conductive layer and the first electrode excluding the protruding structure is basically similar to the thickness of the second conductive layer and the second electrode excluding the protruding structure, and the thickness is relatively uniform. This can improve the film quality of the formed insulating film and sacrificial layer, and prevent the occurrence of uneven force on both sides during wire bonding, thereby improving the power handling capability of the device.

[0069] When forming an electronic device (electronic apparatus) including the above-mentioned three-dimensional capacitor, the second electrode can also be connected to the plane where the first electrode is located through a hole in the insulating material surrounding the three-dimensional capacitor, so that the first electrode and the second electrode are on the same plane to facilitate surface mounting.

[0070] As shown in Figures 5a and 5b, the width of the protrusion structure of the first conductive layer 2 in the capacitor structure is a, and the height of the protrusion structure is h, then the aspect ratio of the protrusion structure h / a is greater than 1. The height of the protrusion is greater than the width. In this way, under the same vertical cross-sectional area and the same number of protrusions, the surface area of ​​the dielectric layer of the capacitor structure can be further increased, improving the ability of the capacitor to store charge. The increased surface area is also conducive to heat dissipation. The aspect ratio is preferably 3-100. When the ratio of height to width is greater than 100, the formed protrusions are easily deformed or collapsed under the action of gravity, which is not conducive to the formation of capacitance.

[0071] Furthermore, the process flow chart of the method for preparing the three-dimensional capacitor of the present invention is shown in FIG6 , and the structural schematic diagrams of each stage in the three-dimensional capacitor preparation process are shown in FIG7 a - 7 f .

[0072] Step S01: Providing a semiconductor substrate. As shown in Figure 7a, semiconductor substrate 100 is used to form and support subsequent devices and facilitate subsequent substrate removal. In the present invention, the semiconductor substrate can be a silicon substrate, a germanium substrate, or an SOI substrate. The semiconductor substrate can first undergo polishing, cleaning, and drying to remove surface impurities, contaminants, and surface oxide layers to prevent oxidation or contamination of subsequent metal layers.

[0073] Step S02: forming a metal graphic structure on the semiconductor substrate. As shown in FIG7b, the production of the metal graphic structure includes depositing a metal layer on the dried semiconductor substrate 100. The deposition method can be sputtering or ion beam deposition process. The deposited metal is Al or Cu. After the metal layer of a certain thickness is deposited, the metal graphic structure 200 is formed by electroplating or 3D printing. The formation of the metal graphic structure here facilitates the subsequent formation of a raised conductive grid structure on the graphic structure. When the metal graphic structure is formed by electroplating or 3D printing, the target position and spacing of the protrusions are first set, and then the metal graphic structure is formed according to the control process.

[0074] Step S03: forming a grid-shaped conductive layer on the metal patterned structure, wherein the grid-shaped conductive layer and the metal patterned structure together serve as the first conductive layer 2. As shown in FIG7c , the process for forming the grid-shaped conductive layer on the metal patterned structure includes one or a combination of electroplating, 3D printing, and selective growth. The grid-shaped conductive layer can be copper, carbon nanotubes, or a combination of copper and carbon nanotubes. The combination of copper and carbon nanotubes is to grow copper on the outer surface of carbon nanotubes or to grow carbon nanotubes on the outer surface of copper. Since carbon nanotubes have good electrical and thermal conductivity, this is also beneficial for the three-dimensional semiconductor structure to reduce parasitic resistance and to be able to work better in high-temperature environments.

[0075] When copper or other suitable metals are selected, electroplating or 3D printing can be used to form a raised grid-like conductive layer on the surface. The grid-like conductive layer can be formed on the specified area by setting a pattern and program. When the material forming the grid-like conductive layer is carbon nanotubes, a selective growth process can be used, such as depositing carbon nanotubes at specified raised positions. When the material forming the grid-like conductive layer is a combination of copper and carbon nanotubes, where the combination of copper and carbon nanotubes is copper grown on the outer surface of the carbon nanotubes or carbon nanotubes grown on the outer surface of copper, the specific formation process can be to first form carbon nanotubes at the corresponding raised positions, and then form a copper metal layer on the surface of the carbon nanotubes by electroplating or sputtering; or first form a copper metal layer at the corresponding raised positions by sputtering or electroplating, and then selectively deposit a carbon nanotube layer at the corresponding raised positions, so that a combination material layer of copper and carbon nanotubes can also be formed. In other words, the grid-like conductive layer can be copper and / or carbon nanotube materials. Other suitable metals with good conductivity can be used as materials for the grid-like conductive layer, and similar processes can be used to form a grid-like conductive layer of metal and / or carbon nanotube materials. Other suitable metals include, but are not limited to, combinations of metals such as Al, Pt, and Au with carbon nanotubes, such as Al and / or carbon nanotubes, Pt and / or carbon nanotubes, Au and / or carbon nanotubes, etc. These metals can be formed using processes similar to those used for copper and carbon nanotubes.

[0076] The width of the protrusion structure of the first conductive layer 2 is a, and the height of the protrusion structure is h, then the aspect ratio of the protrusion structure h / a is greater than 1. The height of the protrusion is greater than the width. This can further increase the surface area of ​​the dielectric layer of the capacitor structure and improve the capacitance under the same vertical cross-sectional area and the same number of protrusions. The aspect ratio is preferably 3-100. When the height to width ratio is greater than 100, the formed protrusions are prone to deformation or collapse under the action of gravity, which is not conducive to the formation of capacitance.

[0077] Step S04: Forming a dielectric layer 1 on the first conductive layer 2. As shown in FIG7c , a dielectric layer 1 is at least partially conformally deposited on the first conductive layer 2. Because the dielectric layer 1 above the first conductive layer 2 is at least partially conformally attached to the surface of the first conductive layer, the area of ​​the formed capacitor structure can be increased, thereby improving the capacitance. The process for depositing the dielectric layer can be carried out by atomic layer deposition. This process forms a dielectric layer with good density and few defects. By improving the quality of the film layer, the performance of the three-dimensional semiconductor structure is further improved.

[0078] The material of the dielectric layer 1 can achieve the requirements of the capacitor structure by using an insulating material. However, according to the capacitance calculation formula, the preferred solution of the present invention is to use a dielectric layer material with a high dielectric constant, so that a higher capacitance density can be achieved.

[0079] Step S05: forming a second conductive layer on the dielectric layer. As shown in FIG7d , the second conductive layer 3 is in at least partially conformal contact with the dielectric layer 1. In order to improve the quality of the film forming the second conductive layer, a two-step process is adopted to form the second conductive layer 3. First, the atomic layer deposition technology is used to form a conductive thin layer, and then the conductive thin layer is formed by electroplating and / or chemical plating. The atomic layer deposition technology forms a conductive film layer with a thickness of approximately one tenth to one fifth of the overall thickness. The conductive film layer formed by the atomic layer deposition technology has a good film density and can be well attached to the surface of the dielectric layer. However, since the film layer deposited by the atomic layer deposition technology is slow, the use of the atomic layer deposition technology will greatly prolong the deposition time. Therefore, after forming a conductive film layer with better quality at the bottom, the remaining thickness of the second conductive layer is formed by electroplating and / or chemical plating, which shortens the preparation time and can also meet the conductivity requirements of the three-dimensional capacitor.

[0080] The second conductive layer can be made of any conductive material. Preferably, it can be a conductive metal, a conductive element or a compound. Preferably, it can be one or more materials such as Al, Ir, Ru, Pt, Cu, Au, carbon nanotubes, graphene and their alloys or compounds with good conductive properties, which can reduce the loss of parasitic resistance.

[0081] Furthermore, in the three-dimensional capacitor structure of the present invention, the sum of the thickness of the first conductive layer excluding the protruding structure and the thickness of the first electrode is t1, and the sum of the thickness of the second conductive layer excluding the thickness of the inwardly protruding portion and the thickness of the second electrode is t2, wherein the ratio of t1 to t2 is 0.5-2. Within this range of electrode and conductive layer thicknesses, compared to the total thickness of the upper and lower conductive layers and electrodes in the existing capacitor structure, if one side is thicker and the other is thinner, the thinner portion will break when the electrical connection is broken through by wire bonding. At the same time, when the thickness of the upper and lower portions is uneven, the film formation quality, insulation of the dielectric sacrificial layer, and the current carrying capacity of the lower electrode cannot be guaranteed, resulting in a decrease in the power handling capability of the device. In this solution, the thickness of the first conductive layer and the first electrode excluding the protruding structure is basically similar to the thickness of the second conductive layer and the second electrode excluding the protruding structure, and the thickness is relatively uniform. This can improve the film formation quality of the formed insulating film and sacrificial layer, prevent uneven force on both sides during wire bonding, and improve the power handling capability of the device.

[0082] Step S06: Stripping the semiconductor substrate to expose the first conductive layer. As shown in FIG7e , the semiconductor substrate is stripped and removed. Laser stripping, chemical mechanical polishing, and etching can be used to remove the semiconductor substrate. After stripping and removing the semiconductor substrate 100, the first conductive layer 2 is exposed, facilitating the formation of an electrode structure on the outer surface of the first conductive layer 2. The substrate is stripped and removed, as shown in FIG7f .

[0083] Step S07: Form a first electrode and a second electrode on the first conductive layer and the second conductive layer, respectively, to form a structure as shown in FIG4 . The first electrode is electrically connected to the first conductive layer, and the second electrode is electrically connected to the second conductive layer. The first electrode and the second electrode can be conductive metals. Preferably, metals with excellent electrical conductivity and oxidation resistance are selected as electrode materials to reduce impedance and prevent oxidation by external water, oxygen, etc., such as Cu, Au, Pt, Ru, or one or more materials and alloys thereof. The first electrode and the second electrode can be formed by sputtering, deposition, or other processes, and then etched to form the desired electrode shape.

[0084] The present invention also discloses an electronic device using a three-dimensional capacitor, which includes the aforementioned three-dimensional capacitor and a control circuit (not shown). The control circuit may include a drive circuit, a control switch circuit, etc., and may be a collection of multiple CMOS. In the electronic device, in order to facilitate circuit derivation and subsequent surface mounting of the first electrode and the second electrode, the second electrode can also be connected to the plane where the first electrode is located through a hole in the insulating material surrounding the three-dimensional capacitor, so that the first electrode and the second electrode are on the same plane.

[0085] Figures 8 and 9 show the simulation results for the parasitic resistance of conductive layers measuring 0.3 mm × 0.3 mm × 50 μm, made of copper, carbon nanotubes + copper, and low-resistance silicon. As shown in the figures, at a frequency of 20 GHz, the parasitic resistance of the copper conductive layer is 1.32 mΩ, and the parasitic resistance of the carbon nanotube + copper conductive layer is 1.18 mΩ, both lower than the 55.59 mΩ of the low-resistance silicon conductive layer.

[0086] Through the above further description of the three-dimensional semiconductor structure and the preparation method thereof of the present invention, it can be seen that the three-dimensional semiconductor structure of the present invention has the following advantages: 1. Good heat dissipation performance. The first conductive layer of the lower layer of the capacitor structure is a double-layer structure of a metal patterned layer and a grid-shaped conductive layer. The double-layer structure is made of metal or carbon nanotubes with excellent heat dissipation and conductivity, which improves the heat dissipation capacity and can quickly dissipate heat in high temperature and high power environments; 2. The first conductive layer below the three-dimensional semiconductor structure is formed without an etching process to form a raised structure, thereby preventing the disadvantages caused by etching; 3. The second conductive layer above is formed by a two-step process, which improves the quality of the metal film layer and shortens the preparation time; 4. The dielectric layer adopts a material with a high dielectric constant, and It is formed by atomic layer deposition technology, which improves the quality of the film layer; 5. The first conductive layer below the three-dimensional capacitor has multiple protruding structures, and the ratio of the height to the width of the protruding structure is greater than 1, and the more preferred ratio is between 3-100, so that the area of ​​the capacitor can be increased as much as possible, the ability of the capacitor to store charge is improved, and it is beneficial to heat dissipation; and the sum of the thickness of the first conductive layer excluding the protruding structure and the thickness of the first electrode is t1, and the sum of the thickness of the second conductive layer excluding the thickness of the inwardly protruding part and the thickness of the second electrode is t2, wherein the ratio of t1 to t2 is 0.5-2, which can improve the film formation quality of the insulating layer and the sacrificial layer, and improve the power tolerance of the device.

[0087] In summary, the three-dimensional capacitor proposed in the present invention has advantages in high-power and high-temperature application scenarios. Using copper as a substitute for low-resistance silicon can obtain greater power tolerance and a wider operating temperature range, which has great advantages in scenarios such as fast charging of new energy vehicle power batteries.

[0088] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Various modifications and variations are readily apparent to those skilled in the art. Any modifications, equivalent substitutions, improvements, and the like made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention. It should be noted that similar reference numerals and letters denote similar items in the following figures. Therefore, once an item is defined in one figure, it need not be further defined or explained in subsequent figures.

[0089] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A three-dimensional semiconductor structure, comprising the following structure: a first conductive layer; a dielectric layer located on the surface of the first conductive layer and in conformal contact with at least part of the first conductive layer; A second conductive layer located on the surface of the dielectric layer and in conformal contact with at least part of the dielectric layer; It is characterized in that the first conductive layer includes a metal patterned layer and a grid-shaped conductive layer which are in electrical contact with each other, and the first conductive layer has a plurality of protruding structures.

2. The three-dimensional semiconductor structure according to claim 1, characterized in that: The grid-shaped conductive layer is copper and / or carbon nanotubes.

3. The three-dimensional semiconductor structure according to claim 2, characterized in that: The grid-shaped conductive layer may also be other metals and / or carbon nanotubes, and the other metals include but are not limited to Al, Pt, and Au.

4. The three-dimensional semiconductor structure according to claim 1, characterized in that: The width of the protruding structure is a, and the height of the protruding structure is h, and the aspect ratio h / a of the protruding structure is greater than 1.

5. A three-dimensional capacitor, characterized in that: It comprises the three-dimensional semiconductor structure as described in any one of claims 1 to 4, and a first electrode and a second electrode, wherein the first electrode is electrically connected to the first conductive layer, and the second electrode is electrically connected to the second conductive layer.

6. The three-dimensional capacitor according to claim 5, characterized in that: The sum of the thickness of the first conductive layer excluding the protruding structure and the thickness of the first electrode is t1, and the sum of the thickness of the second conductive layer excluding the thickness of the inwardly protruding portion and the thickness of the second electrode is t2, wherein the ratio of t1 to t2 is 0.5-2.

7. A method for preparing a three-dimensional capacitor, characterized in that: The following steps are involved: Step S01: providing a semiconductor substrate; Step S02: fabricating a metal patterned structure on the semiconductor substrate; Step S03: manufacturing a grid-shaped conductive layer on the metal patterned structure, wherein the metal patterned structure and the grid-shaped conductive layer together constitute a first conductive layer of the three-dimensional semiconductor structure, and the first conductive layer has a plurality of protruding structures; Step S04: forming a dielectric layer on the first conductive layer, wherein the dielectric layer is in conformal contact with the first conductive layer at least partially; Step S05: forming a second conductive layer on the surface of the dielectric layer, wherein the second conductive layer is in conformal contact with at least part of the dielectric layer.

8. The method for preparing a three-dimensional capacitor according to claim 7, characterized in that: After step S05, the method further includes: Step S06: stripping the semiconductor substrate to expose the first conductive layer.

9. The method for preparing a three-dimensional capacitor according to claim 7, characterized in that: After step S06, the method further includes: Step S07: forming a first electrode and a second electrode on the first conductive layer and the second conductive layer respectively, wherein the first electrode is electrically connected to the first conductive layer, and the second electrode is electrically connected to the second conductive layer.

10. The method for preparing a three-dimensional capacitor according to claim 7, characterized in that: The semiconductor substrate includes but is not limited to a silicon substrate, a germanium substrate or an SOI substrate.

11. The method for preparing a three-dimensional capacitor according to claim 7, characterized in that: The grid-shaped conductive layer is copper and / or carbon nanotubes.

12. The method for preparing a three-dimensional capacitor according to claim 11, characterized in that: The grid-shaped conductive layer may also be other metals and / or carbon nanotubes, and the other metals include but are not limited to Al, Pt, and Au.

13. The method for preparing a three-dimensional capacitor according to claim 7, characterized in that: The width of the protruding structure is a, and the height of the protruding structure is h, and the aspect ratio h / a of the protruding structure is greater than 1.

14. The method for preparing a three-dimensional capacitor according to claim 7, characterized in that: The dielectric layer is made of insulating material, and the dielectric layer is formed by an atomic layer deposition process.

15. The method for preparing a three-dimensional capacitor according to claim 7, characterized in that: The manufacturing of the metal patterned structure includes depositing a metal layer on a substrate, and forming the metal patterned structure using methods including but not limited to electroplating or 3D printing.

16. The method for preparing a three-dimensional capacitor according to claim 7, characterized in that: The process of forming the grid-shaped conductive layer on the metal patterned structure includes but is not limited to electroplating, 3D printing and selective growth, or a combination of these.

17. The method for preparing a three-dimensional capacitor according to claim 7, characterized in that: The second conductive layer is formed by a two-step process, firstly using an atomic layer deposition technique to form a conductive thin layer, and then using an electroplating and / or chemical plating method to form the second conductive layer.

18. The method for preparing a three-dimensional capacitor according to claim 7, characterized in that: The sum of the thickness of the first conductive layer excluding the protruding structure and the thickness of the first electrode is t1, and the sum of the thickness of the second conductive layer excluding the thickness of the inwardly protruding portion and the thickness of the second electrode is t2, wherein the ratio of t1 to t2 is 0.5-2.

19. An electronic device, characterized in that The device comprises a control circuit and the three-dimensional capacitor as claimed in claim 5.

20. The electronic device according to claim 19, characterized in that The second electrode extends through the hole to the plane where the first electrode is located.

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