Static random access memory, processing circuit chip, and electronic device

Abstract

The present application discloses a static random access memory, a processing circuit chip, and an electronic device. Memory cells are arranged in an array on a first side of a substrate, and a plurality of trenches extend, in a third direction, into the substrate from the surface of the substrate on a second side thereof, so that the trenches are prevented from being limited by channels in a first direction, and the line width of the trenches in the first direction can be released. A power wire is arranged on the second side of the substrate and the power wire is connected to power adapter wires in the trenches, and a connecting part is further connected to the power adapter wires in the trenches by means of contact holes, so as to supply power to the memory cells by means of the power wire, the trenches, the contact holes, and the connecting part. The power wire is arranged on the second side of the substrate, such that power is supplied to the memory cells by means of a backside power delivery network, the space of the layer where a word line or bit line is located can be released, the width of the word line or bit line can be increased without additionally increasing the layout area of the memory cells, the resistance of the word line or bit line can be reduced, and the overall performance of the static random access memory is improved.

Description

Static random access memory, processing circuit chip and electronic equipment

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on November 21, 2023, with application number 202311563518.1 and application name "A static random access memory, processing circuit chip and electronic device", all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of semiconductor technology, and in particular to a static random access memory, a processing circuit chip, and an electronic device. Background Art

[0004] Static random access memory (SRAM) is a memory device with static access capabilities. It retains stored data without requiring a refresh circuit and is widely used in digital and various electronic circuit designs. Typically, SRAM comprises an array of memory cells, and the performance of these cells has a crucial impact on SRAM performance, making it extremely important.

[0005] Summary of the Invention

[0006] The present application provides a static random access memory, a processing circuit chip, and an electronic device for improving performance.

[0007] In a first aspect, the present application provides a static random access memory (SRAM), comprising: a substrate, a plurality of memory cells, a plurality of trenches spaced apart from each other, a power adapter line filled in each trench, a power line, and a first connection layer. The substrate has a first side and a second side along a third direction, and a plurality of memory cells are arrayed on the first side of the substrate. The plurality of trenches extend from a surface of the second side of the substrate into the substrate along the third direction, and the plurality of trenches extend along the second direction and are arranged along the first direction. The distance between the bottom of the trench and the surface of the substrate facing the memory cells is greater than zero, so that the trenches do not penetrate the substrate, thereby preventing the trenches from being restricted by the channel in the first direction and freeing up the width of the trenches in the first direction. The power line is disposed on the second side of the substrate and connected to the power adapter line in the trench. The first connection layer is disposed on the side of the memory cells facing away from the substrate, and the first connection layer includes a connection portion connected to the memory cells. The connection portion is also connected to the power adapter line in the trench via a contact hole that interpenetrates the trenches, thereby positioning the power adapter line between the power line and the connection portion. Thus, power is supplied to the memory cell through the power line, the groove, the contact hole and the connection portion. Moreover, by arranging the power line on the second side of the substrate, that is, transferring the power line to the back side of the substrate, it is realized that the memory cell is powered by the backside power delivery network (BSPDN). Also, in the static random access memory of the prior art, the power line is usually arranged on the side of the substrate facing the memory cell (i.e., the front side of the substrate), thereby limiting the line width of the word line or bit line, resulting in a series of problems caused by RC delay (delay) in the word line or bit line. To this end, the static random access memory provided by the embodiment of the present application, by arranging the power line on the back side of the substrate, can not only free up the space of the layer where the word line or bit line is located, but also can increase the width of the word line or bit line without increasing the layout area of ​​the memory cell, thereby reducing the resistance of the word line or bit line, thereby improving a series of problems caused by RC delay of the word line or bit line during read and write operations, and improving the overall performance of the static random access memory.

[0008] In addition, the third direction is perpendicular to the plane where the substrate is located, and the first direction and the second direction are parallel to the plane where the substrate is located and intersect with each other. For example, the first direction and the second direction are perpendicular to each other.

[0009] Generally, a first power supply voltage needs to be input to the memory cell. To this end, the memory cell has a first side and a second side along a first direction. The plurality of grooves include a first groove and a second groove, with the first groove being provided on the first side of the memory cell and the second groove being provided on the second side of the memory cell. Furthermore, the power lines include a first power line for transmitting the first power supply voltage, and the first power line is connected to power adapter lines in the first groove and the second groove, respectively. Furthermore, the memory cell includes a first pull-down tube and a second pull-down tube, and the connecting portion includes a first connecting portion and a second connecting portion. The first connecting portion is connected to the first pole of the first pull-down tube and is further connected to the power adapter line in the first groove via a first contact hole that interpenetrates the first groove. The second connecting portion is connected to the first pole of the second pull-down tube and is further connected to the power adapter line in the second groove via a second contact hole that interpenetrates the second groove. This arrangement allows the first pole of the first pull-down tube and the first pole of the second pull-down tube to be electrically connected to the first power line, thereby inputting the first power supply voltage to the first pole of the first pull-down tube and the first pole of the second pull-down tube.

[0010] Through the above-mentioned setting, the static random access memory provided by the embodiment of the present application transfers the first power line to the back side of the substrate, realizing a structure in which the first power supply voltage is input to the memory cell in a BSPDN manner. In addition, in the static random access memory of the prior art, the first power line is usually arranged on the side of the substrate facing the memory cell (i.e., the front side of the substrate) and the first power line is arranged on the same layer as the word line, thereby limiting the line width of the word line, resulting in the word line having a problem of a slow high-level voltage rise rate due to RC delay. To this end, in the static random access memory provided by the embodiment of the present application, by transferring the first power line 371 to the back side of the substrate, not only can the space of the layer where the word line is located be freed up, but also the width of the word line can be increased without additionally increasing the layout area of ​​the memory cell, thereby reducing the resistance of the word line, improving the problem of a slow high-level voltage rise rate caused by RC delay of the word line, and thereby increasing the high-level voltage rise rate of the word line.

[0011] In a specific implementation, the static random access memory also includes a second interconnect layer disposed on the side of the first connection layer facing away from the substrate. The second interconnect layer includes a plurality of word lines spaced apart from each other, extending along a first direction and arranged along a second direction. The memory cell also includes a first gate transistor and a second gate transistor, the gates of the first gate transistor and the second gate transistor being respectively connected to the word lines. Furthermore, when the first power line and the word line are disposed on the same layer, the width of the word line in the second direction serves as the first set width. In this application, by removing the first power line from the layer containing the word line, the space originally occupied by the first power line is freed up, allowing the width of each word line in the second direction to be increased by 20% to 40% relative to the first set width. This increases the width of the word line, reduces the resistance of the word line, and improves the slow high-level voltage rise rate caused by RC delay, thereby increasing the high-level voltage rise rate of the word line.

[0012] Generally, a second power supply voltage needs to be input to the memory cell. To this end, the power line includes a second power supply line for transmitting the second power supply voltage, the plurality of grooves includes a third groove, the memory cell includes a first pull-up tube and a second pull-up tube, and the third groove is disposed between the first and second pull-up tubes in the memory cell, and the power adapter line in the third groove is connected to the second power line. Furthermore, the connecting portion includes a third connecting portion and a fourth connecting portion. The third connecting portion is connected to the first electrode of the first pull-up tube and is further connected to the power adapter line in the third groove via a third contact hole that interpenetrates the third groove. The fourth connecting portion is connected to the first electrode of the second pull-up tube and is further connected to the power adapter line in the third groove via a fourth contact hole that interpenetrates the third groove. This arrangement electrically connects the first electrode of the first pull-up tube and the first electrode of the second pull-up tube to the second power supply line, thereby inputting the second power supply voltage to the first electrode of the first pull-up tube and the first electrode of the second pull-up tube.

[0013] Through the above-mentioned setting, the static random access memory provided by the embodiment of the present application transfers the second power line to the back side of the substrate, realizing a structure in which the second power supply voltage is input to the memory cell in a BSPDN manner. In addition, in the static random access memory of the prior art, the second power line is usually arranged on the side of the substrate facing the memory cell (i.e., the front side of the substrate) and the second power line is arranged on the same layer as the bit line, thereby limiting the line width of the bit line, resulting in the problem of slow discharge rate of the bit line due to RC delay. To this end, in the static random access memory provided by the embodiment of the present application, by transferring the second power line to the back side of the substrate, not only the space of the layer where the bit line is located can be freed up, but also the width of the bit line can be increased without additionally increasing the layout area of ​​the memory cell, thereby reducing the resistance of the bit line, improving the problem of slow discharge rate of the bit line due to RC delay during read and write operations, thereby increasing the discharge rate of the bit line and improving the overall performance of the static random access memory.

[0014] In a specific implementation, the static random access memory also includes a first interconnect layer disposed on the side of the first connection layer facing away from the substrate. The first interconnect layer includes a plurality of bit lines spaced apart from each other, extending along the second direction and arranged along the first direction. Furthermore, the memory cell also includes a first gate transistor and a second gate transistor. The plurality of bit lines include a first bit line and a second bit line. The first electrode of the first gate transistor is connected to the first bit line, and the first electrode of the second gate transistor is connected to the second bit line. Furthermore, when the second power line is disposed in the same layer as the bit line, the width of the bit line in the first direction serves as the second set width. In this application, by removing the second power line from the layer where the bit line resides, the space originally occupied by the second power line is freed, allowing the width of each bit line in the first direction to be increased by 20% to 40% relative to the second set width. This increases the width of the bit line, reduces the resistance of the bit line, and improves the slow discharge rate of the bit line caused by RC delay, thereby increasing the discharge rate of the bit line.

[0015] In some embodiments, the second power line and the first power line are insulated from each other. For example, if the second power line and the first power line are arranged on different layers, an insulating layer is provided between the second power line and the first power line. Alternatively, the first power line is provided between the second power line and the substrate, or the second power line is provided between the first power line and the substrate. Alternatively, the second power line and the first power line may be provided on the same layer.

[0016] Exemplarily, the shape of the first power line is set to be a strip structure or a grid structure.

[0017] Exemplarily, the second power line is configured to be in a strip structure or a grid structure.

[0018] In some embodiments, the distance between the trench and the surface of the substrate facing the memory cell is 40 nm to 60 nm.

[0019] In some embodiments, the storage unit is configured as a 6T Cell, that is, the storage unit includes: a first pull-up tube, a second pull-up tube, a first pull-down tube, a second pull-down tube, a first gate tube, and a second gate tube, and the first pull-down tube, the first pull-up tube, the second pull-up tube, and the second pull-down tube are arranged in sequence along the first direction, the first gate tube and the first pull-down tube are arranged in a straight line along the second direction, and the second gate tube and the second pull-down tube are arranged in another straight line along the second direction.

[0020] Because Fin Field-Effect Transistors (Fin FETs) have advantages such as strong current control capability, reduced leakage current, and increased switching speed, the first pull-up transistor, the second pull-up transistor, the first pull-down transistor, the second pull-down transistor, the first gate transistor, and the second gate transistor can be configured as Fin FETs. For example, the fin channel of the first pull-up transistor, the fin channel of the second pull-up transistor, the fin channel of the first pull-down transistor, the fin channel of the second pull-down transistor, the fin channel of the first gate transistor, and the fin channel of the second gate transistor extend along the second direction.

[0021] In order to reduce the complexity of the fin channel patterning, in the same memory cell, the fin channel of the first gate tube and the fin channel of the first pull-down tube are set to be an integrated structure.

[0022] In order to reduce the complexity of the fin channel patterning, in the same memory cell, the fin channel of the second gate tube and the fin channel of the second pull-down tube are set to an integrated structure.

[0023] In some embodiments, the plurality of storage cells in the present application include a plurality of first storage cell groups and a plurality of second storage cell groups, wherein the first storage cell groups are arranged along a first direction F1, and each first storage cell group includes a plurality of storage cells arranged along a second direction. Furthermore, the second storage cell groups are arranged along the second direction, and each second storage cell group includes a plurality of storage cells arranged along the first direction. For example, adjacent first storage cell groups can be arranged in mirror symmetry, or two adjacent second storage cell groups can be arranged in mirror symmetry.

[0024] Exemplarily, the fin channels of adjacent first pull-down transistors along the second direction are configured as an integrated structure, and the fin channels of adjacent first gate transistors along the second direction are also configured as an integrated structure. With this configuration, the fin channels of the first pull-down transistors and the fin channels of the first gate transistors in a plurality of memory cells arranged along the second direction are formed using fin channels extending along the second direction, further reducing the complexity of the channel patterning.

[0025] Exemplarily, the fin-type channels of the second pull-down tubes adjacent to each other along the second direction are formed into an integrated structure, and the fin-type channels of the second gate tubes adjacent to each other along the second direction are also formed into an integrated structure. With this arrangement, the fin-type channels extending along the second direction are used to form the fin-type channels of the second pull-down tubes and the fin-type channels of the second gate tubes in a plurality of memory cells arranged along the second direction, further reducing the complexity of the channel patterning.

[0026] Exemplarily, the fin-type channels of the adjacent first pull-up tubes along the second direction are integrated into a single structure. Thus, the fin-type channels of the first pull-up tubes in the two memory cells are formed using fin-type channels extending along the second direction, further reducing the complexity of the channel patterning.

[0027] Exemplarily, the fin-type channels of the second pull-up tubes adjacent to each other along the second direction are also integrated into a single structure. Thus, the fin-type channels of the second pull-up tubes in the two memory cells are formed by using fin-type channels extending along the second direction, further reducing the complexity of the channel patterning.

[0028] To further increase the density of the memory cells, since two adjacent memory cells arranged along the second direction are arranged in mirror-symmetric fashion, the first connection portions connecting two adjacent first pull-down tubes along the second direction can share a common first contact hole. This arrangement reduces the number of first contact holes and reduces the complexity of the layout design. Furthermore, the first trench can be made to interpenetrate each first contact hole in the corresponding first memory cell group, thereby enabling the same first trench to provide the first power supply voltage VSS to the first pull-down tubes in the corresponding first memory cells.

[0029] To further increase the density of the memory cells, since two adjacent memory cells arranged along the second direction are arranged in mirror symmetry, the second connection portions connecting two adjacent second pull-down tubes along the second direction can share a single second contact hole. This arrangement reduces the number of second contact holes and reduces the complexity of the layout design. Furthermore, the second trench can be made to interpenetrate each second contact hole in the corresponding first memory cell group, thereby enabling the same second trench to provide the first power supply voltage to the second pull-down tubes in the corresponding first memory cells.

[0030] To further increase the density of the memory cells, since two adjacent memory cells arranged along the first direction are arranged in mirror symmetry, the first trench between the two adjacent memory cells along the first direction can be configured as the same trench. This configuration can reduce the number of first trenches and reduce the complexity of the layout design.

[0031] To further increase the density of the memory cells, since two adjacent memory cells arranged along the first direction are arranged in mirror symmetry, the second trenches between the two adjacent memory cells along the first direction can be configured as the same trench. This configuration can reduce the number of second trenches and reduce the complexity of the layout design.

[0032] To further increase the density of storage cells, the first connection portions connecting two adjacent first pull-down tubes along the first direction can share a common first contact hole. This arrangement can further reduce the number of first contact holes and reduce the complexity of the layout design. Furthermore, a first trench can be used to intersect each first contact hole in two adjacent first storage cell groups, thereby enabling the same first trench to provide the first power supply voltage to the first pull-down tubes in two adjacent first storage cells.

[0033] To further increase the density of storage cells, the second connection portions connecting adjacent second pull-down tubes along the first direction can share a common second contact hole. This arrangement can further reduce the number of second contact holes and reduce the complexity of the layout design. Furthermore, a second trench can be used to intersect each second contact hole in two adjacent first storage cell groups, thereby enabling the same second trench to provide the first power supply voltage to the second pull-down tubes in two adjacent first storage cells.

[0034] To further increase the density of memory cells, since two adjacent memory cells arranged along the second direction are arranged in mirror symmetry, the third connection portions connecting two adjacent first pull-up tubes along the second direction can share a single third contact hole. This arrangement can further reduce the number of third contact holes and reduce the complexity of the layout design. Furthermore, a single third trench can be used to intersect with each third contact hole in the corresponding first memory cell group, allowing the same third trench to provide the second power supply voltage to the first pull-up tubes in the first memory cells.

[0035] To further increase the density of memory cells, since two adjacent memory cells arranged along the second direction are arranged in mirror-symmetric fashion, the fourth connection portions connecting two adjacent second pull-up tubes along the second direction can share a single fourth contact hole. This arrangement can further reduce the number of fourth contact holes and reduce layout design complexity. Furthermore, a third trench can be used to intersect with each fourth contact hole in the corresponding first memory cell group, allowing the same third trench to provide the second power supply voltage to the second pull-up tubes in the first memory cells.

[0036] In order to further improve the density of the memory cell, a third trench can be interpenetrated with each third contact hole and each fourth contact hole in the corresponding first memory cell group, so that the same third trench can be used to provide a second power supply voltage for the first pull-up tube and the second pull-up tube in the first memory cell group.

[0037] In a second aspect, the present application also provides a processing circuit chip, which includes any static random access memory in the above-mentioned first aspect and one or more processing circuits, and the static random access memory is used to store data required for the operation of one or more processing circuits.

[0038] Since any of the above static random access memories has good performance, after the static random access memory is applied to a processing circuit chip, the performance of the processing circuit chip can also be improved.

[0039] In a third aspect, the present application further provides an electronic device, comprising a bus and a processing circuit chip according to the second aspect, wherein the bus is connected to the processing circuit chip. The electronic device may be any electrical device, such as a terminal device, a communication device, or an electronic device. Terminal devices include, but are not limited to, mobile phones, computers, televisions, TV set-top boxes, watches, personal computers (PCs), wearable devices, workstations, and the like. Communication devices include, but are not limited to, wireless networks, fixed networks, servers, and smart broadband. Electronic devices include, but are not limited to, device modules, memories, and digital logic circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a structural block diagram of an electronic device provided in an embodiment of the present application;

[0041] FIG2 is a schematic structural diagram of an SRAM provided in an embodiment of the present application;

[0042] FIG3 is a circuit diagram of a memory cell of an SRAM provided in an embodiment of the present application;

[0043] FIG4 is a schematic diagram of a layout structure of an SRAM provided in an embodiment of the present application;

[0044] FIG5a is a schematic cross-sectional view of the structure along the AA' tangent line in FIG4;

[0045] FIG5b is a schematic cross-sectional view of the structure along the BB' tangent line in FIG4;

[0046] FIG6 is a schematic diagram of the layout structure after adding word lines in FIG4;

[0047] FIG7 is a schematic diagram of another layout structure of an SRAM provided in an embodiment of the present application;

[0048] FIG8 is a schematic diagram showing simulation results of a static random access memory provided by an embodiment of the present application when a high-level voltage is input when word lines have different widths;

[0049] FIG9 is a schematic diagram showing simulation results of read and write operations of a static random access memory provided by an embodiment of the present application when the bit lines have different widths.

[0050] Reference numerals

[0051] 100 - electronic device; 110 - processing circuit chip; 111 - processor; 112 - GPU; 113 - first RAM; 120 - second RAM; 130 - communication chip; 140 - power management chip; 150 - bus; 0122 - SRAM; 1021 - row decoding circuit; 1-N - word line circuit; 1022 - read / write driver circuit; 1023 - column decoding circuit; 200 / 200a / 200b / 200c / 200d / 200e / 200f / 200g / 200h - memory cell; T1_S / T2_S / T3_S / T4_S / T5_S / T6_S - first electrode; GT1 - first trench; GT2 - second trench; GT3 - third trench; 300 - substrate; 311 / 312 / 313 - power adapter; 320 - first connection layer; 321 - first connection portion; 322 - second connection portion Connection part; 323-third connection part; 324-fourth connection part; 325-first bit line connection part; 326-second bit line connection part; 331-STI structure; 332-isolation medium; 333 / 334 / 381 / 382-insulating layer; 340-first interconnection layer; 350-second interconnection layer; 371-first power line; 372-second power line; S1-first side; S2-second side; Za_1 / Za_2-first storage cell group; Zb_1 / Zb_2 / Zb_3 / Zb_4-second storage cell group; F1-first direction; F2-second direction; F3-third direction; WL-word line; BL-first bit line BL; BLB-second bit line; CT1-first contact hole; CT2-second contact hole; CT3-third contact hole; CT4-fourth contact hole; BT1-first bit line connection hole; BT2-second bit line connection hole. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The specific operating methods in the method embodiments can also be applied to device embodiments or system embodiments. It should be noted that in the description of the present application, "multiple" can be understood as "at least two". In addition, it should be understood that in the description of the present application, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0053] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be modified as needed, and such modifications are included in the scope of protection of this application. The drawings of this application are only for illustrative purposes and do not represent true proportions.

[0054] The SRAM provided in the embodiments of the present application can be applied to electronic devices having SRAM. For example, electronic devices include but are not limited to terminal devices, communication devices, and electronic devices. Among them, terminal devices include but are not limited to mobile phones, computers, televisions, TV set-top boxes, watches, personal computers (PCs), wearable devices, workstations and other devices. Communication equipment includes but is not limited to wireless networks, fixed networks, servers, smart broadband, etc. Electronic devices include but are not limited to device modules, memories, digital logic circuits, etc., which are not listed here one by one. It is understandable that the specific implementation of SRAM can be determined according to the actual application scenario and is not limited here.

[0055] FIG1 is a block diagram of a structure of an electronic device provided in an embodiment of the present application. Referring to FIG1 , the electronic device 100 includes: a bus 150 and a processing circuit chip 110 connected to the bus 150. The processing circuit chip 110 can be used to process data, such as processing application data, processing image data, and caching temporary data. For example, the processing circuit chip 110 can be a central processing unit (CPU), a system on chip (SOC), an electronic control unit (ECU), etc. In one embodiment, the processing circuit chip 110 may include an application processor (AP) 111 for processing applications, a graphics processing unit (GPU) 112 for processing image data, and a first random access memory (RAM) 113 for caching high-speed data. The first RAM 113 can be SRAM or embedded flash memory (eFlash), etc. The above-mentioned AP 111, GPU 112 and first RAM 113 can be integrated into a die or can be separately provided in multiple dies. The electronic device may further include a second RAM 120 connected to the processing circuit chip via a bus. The second RAM 120 may be a dynamic random access memory (DRAM). The second RAM 120 may be used to store volatile data, such as temporary data generated by the processing circuit chip. The storage capacity of the second RAM 120 is generally greater than that of the first RAM 113, but the reading speed is generally slower than that of the first RAM 113. In addition, the electronic device may further include a communication chip 130 and a power management chip 140 connected to the processing circuit chip via a bus. The communication chip 130 may be used for processing the protocol stack, or for amplifying and filtering analog radio frequency signals, or for performing the above functions simultaneously. The power management chip 140 may be used to power other chips. In one embodiment, the processing circuit chip and the second RAM 120 may be encapsulated in a packaging structure, such as using 2.5D (dimension) or 3D packaging, to obtain a faster data transmission rate between chips. By way of example, there may be one or more processors, the specific number of which may be determined according to the requirements of the actual application scenario and is not limited here.

[0056] FIG2 is a schematic diagram of the structure of an SRAM provided in an embodiment of the present application. Referring to FIG2 , taking the first RAM 113 as an SRAM as an example, the SRAM 0122 mainly includes a plurality of memory cells (cells) 200, and the plurality of memory cells 200 constitute an N×M memory array, wherein M and N are both integers greater than or equal to 1. Exemplarily, the plurality of memory cells 200 are arranged into a plurality of memory cell rows (such as row 1 to row N) along the second direction F2, and the plurality of memory cells 200 are arranged into a plurality of memory cell columns (such as column 1 to column M) along the first direction F1. In addition, the SRAM 0122 further includes a plurality of word lines WL, a plurality of first bit lines BL, and a plurality of second bit lines BLB. The plurality of word lines WL extend along the first direction F1, and the plurality of word lines WL are arranged along the second direction F2. The plurality of first bit lines BL and the plurality of second bit lines BLB extend along a second direction F2 and are alternately arranged along the first direction F1 (i.e., a first bit line BL is provided between two adjacent second bit lines BLB). Multiple memory cell rows correspond one-to-one to multiple word lines, and each memory cell row is connected to a corresponding word line to drive the memory cells via the word lines. Furthermore, multiple memory cell columns correspond one-to-one to the plurality of first bit lines BL and the plurality of second bit lines BLB, and each memory cell column is connected to a corresponding first bit line BL and second bit line BLB to transmit data via the first bit line BL and second bit line BLB.

[0057] 2 , SRAM 0122 further includes: a row decoding circuit 1021, word line circuits 1 to N, a read / write driver circuit 1022, and a column decoding circuit 1023. The inputs of word line circuits 1 to N are respectively connected to the outputs of row decoding circuit 1021, and the outputs of word line circuits 1 to N are respectively connected to the word lines connected to N memory cell rows. For example, word line circuit 1 is connected to the word line connected to a memory cell row (e.g., row 1), word line circuit 2 is connected to the word line connected to a memory cell row (e.g., row 2), ..., word line circuit N-1 is connected to the word line connected to a memory cell row (e.g., row N-1), and word line circuit N is connected to the word line connected to a memory cell row (e.g., row N). Furthermore, the read / write driver circuit 1022 is respectively connected to the column decoding circuit 1023 and each first bit line BL and each second bit line BLB.

[0058] During operation, the processor 111 can read and write data in the SRAM 0122. Specifically, the processor 111 can send address information to the SRAM 0122, and the address information can indicate the storage address of the target data in the SRAM 0122. Exemplarily, the address information sent by the processor 111 includes row address information and column address information. The SRAM 0122 is connected to the processor 111 and can receive the address information output by the processor 111. In the SRAM 0122, the row decoding circuit 1021 is a row decoder that can decode the row address information to determine the target storage cell row where the target data is located, and the target word line circuit corresponding to the target storage cell row. As in the above example, the row decoding circuit 1021 can determine that the target storage cell row is the second row of storage cells (i.e., the storage cell row corresponding to row 2), and the target word line circuit is word line circuit 2.

[0059] The row decoding circuit 1021 can further send decoding selection signals to word line circuits 1 to N. The decoding selection signal sent to the target word line circuit can instruct the target word line circuit to operate, and the decoding selection signal sent to word line circuits other than the target word line circuit can instruct the other word line circuits to wait.

[0060] As in the above example, word line circuit 2 is the target word line circuit, and the decoding selection signal sent to word line circuit 2 can instruct word line circuit 2 to work, and the decoding selection signal sent to word line circuit 1 and word line circuit 3 to word line circuit N can instruct the word line circuit to wait.

[0061] In one example, the decoding selection signal can instruct the word line circuit to work or wait through different level states. For example, when the decoding selection signal is at a high level, the word line circuit receiving the decoding selection signal can be instructed to work, and when the decoding selection signal is at a low level, the word line circuit receiving the decoding selection signal can be instructed to wait.

[0062] In yet another example, the decoded selection signal may also carry selection information, and the word line circuit may determine whether to work or wait next by analyzing the selection information carried by the decoded selection signal.

[0063] The word line circuit can work or wait according to the decoding selection signal. The word line circuit can output a word line signal to the connected word line, and the word line signal can turn on or off the corresponding memory cell row. Generally speaking, the word line signal turns on or off the memory cell row through different level states. For example, when the word line signal is at a high level, the word line signal can turn on the memory cell row, and when the word line signal is at a low level, the word line signal can turn off the memory cell row. When the decoding selection signal indicates that the word line circuit is working, the word line signal output by the word line circuit can be at a high level, thereby turning on the corresponding memory cell row. When the decoding selection signal indicates that the word line circuit is waiting, the word line circuit can remain at a low level, thereby turning off the corresponding memory cell row.

[0064] The column decoding circuit 1023 can decode the column address information to determine the target memory cell column where the target data is located. It then sends instruction information to the read / write driver circuit 1022, instructing the read / write driver circuit 1022 to read or write data in the target memory cell column. At this time, the read / write driver circuit 1022 can read or write data in the target memory cell column in the target memory cell row only when the target memory cell row is enabled.

[0065] FIG3 is a circuit diagram of a memory cell of an SRAM provided in an embodiment of the present application. Referring to FIG3 , the memory cell 200 can be configured as a 6T cell, comprising: a first pull-up transistor T1, a second pull-up transistor T2, a first pull-down transistor T3, a second pull-down transistor T4, a first gate transistor T5, and a second gate transistor T6. The first electrode of the first pull-up transistor T1 and the first electrode of the second pull-up transistor T2 receive a second power supply voltage VDD. The second electrode of the first pull-up transistor T1 is connected to the second electrode of the first pull-down transistor T3, and the second electrode of the second pull-up transistor T2 is connected to the second electrode of the second pull-down transistor T4. The first electrode of the first pull-down transistor T3 and the first electrode of the second pull-down transistor T4 receive a first power supply voltage VSS. The gate of the second pull-up transistor T2 is connected to the gate of the second pull-down transistor T4, the second electrode of the first pull-up transistor T1, the second electrode of the first pull-down transistor T3, and the second electrode of the first gate transistor T5, forming a first storage node Q. The gate of the first pull-up transistor T1, the gate of the first pull-down transistor T3, the second electrode of the second pull-up transistor T2, the second electrode of the second pull-down transistor T4, and the second electrode of the second selection transistor T6 are interconnected to form a second storage node QB. The gate of the first selection transistor T5 and the gate of the second selection transistor T6 are connected to the same word line WL, which drives the first and second selection transistors T5 and T6 to turn on and off. The first electrode of the first selection transistor T5 is connected to the first bit line BL, through which data is transmitted. The first electrode of the second selection transistor T6 is connected to the second bit line BLB, through which data is transmitted. Furthermore, the first pull-up transistor T1 and the first pull-down transistor T3 serve as a first inverter, and the second pull-up transistor T2 and the second pull-down transistor T4 serve as a second inverter. The output of the first inverter is electrically connected to the input of the second inverter, forming a first storage node Q. The output of the second inverter is connected to the input of the first inverter, forming a second storage node QB. Since the first inverter and the second inverter are cross-coupled, they function as a latch circuit. That is, when one storage node is pulled down to a low potential, the other storage node is pulled up to a high potential.

[0066] For example, when the memory cell is working, when the word line signal transmitted on the word line is at a high level, the word line signal can control the first gate tube T5 and the second gate tube T6 to be turned on, so that the data in the memory cell can be read and written through the first bit line and the second bit line.

[0067] Exemplarily, the first pull-up tube T1, the second pull-up tube T2, the first pull-down tube T3, the second pull-down tube T4, the first gating tube T5, and the second gating tube T6 can be set as field effect transistors (FETs). Optionally, the FETs in the memory cell can be set as P-type field effect transistors (PFETs) or N-type field effect transistors (NFETs). For example, the first pull-up tube T1 and the second pull-up tube T2 are respectively set as PFETs, and the first pull-down tube T3, the second pull-down tube T4, the first gating tube T5, and the second gating tube T6 are respectively set as NFETs. In addition, for the convenience of expression, the first pole of each FET in this application can refer to the source, and the second pole refers to the drain. Alternatively, the first pole can also refer to the drain, and the second pole of the transistor refers to the source. The following description takes as an example that the first pull-up transistor T1 and the second pull-up transistor T2 are respectively configured as PFETs, and the first pull-down transistor T3, the second pull-down transistor T4, the first gate transistor T5 and the second gate transistor T6 are respectively configured as NFETs.

[0068] FIG4 is a schematic diagram of a layout structure of an SRAM provided in an embodiment of the present application, FIG5a is a schematic diagram of a cross-sectional structure along the AA' tangent direction in FIG4, FIG5b is a schematic diagram of a cross-sectional structure along the BB' tangent direction in FIG4, and FIG6 is a schematic diagram of the layout structure after adding word lines in FIG4. It is understandable that in order to clearly illustrate the positional relationship of the main film layers or structures in FIG4 to FIG6, some film layers are hidden in FIG4 to FIG6. For example, the word lines, insulating layers, gates of each FET and other film layers are hidden in FIG4, and for example, the substrate, insulating layers, gates of each FET and other film layers are hidden in FIG6. For the positional relationship of these hidden film layers, reference can be made to FIG5a and FIG5b.

[0069] 4 , 5 a , 5 b , and 6 , an SRAM includes a substrate 300 having a first side S1 and a second side S2 along a third direction F3 . A plurality of memory cells 200 are arranged in an array on the first side S1 of the substrate 300 . The memory cells 200 include a first pull-up tube T1 , a second pull-up tube T2 , a first pull-down tube T3 , a second pull-down tube T4 , a first gate tube T5 , and a second gate tube T6 . The first pull-down tube T3 , the first pull-up tube T1 , the second pull-up tube T2 , and the second pull-down tube T4 are sequentially spaced apart along the first direction F1 . The first gate tube T5 and the first pull-down tube T3 are aligned along the second direction F2 , and the second gate tube T6 and the second pull-down tube T4 are aligned along the second direction F2 . Furthermore, the first pull-up tube T1, the first pull-down tube T3, and the second gating tube T6 are arranged in a straight line along the first direction F1, and the second pull-up tube T2, the second pull-down tube T4, and the first gating tube T5 are arranged in another straight line along the first direction F1. In addition, the third direction F3 is perpendicular to the plane where the substrate 300 is located, and the first direction F1 and the second direction F2 are parallel to the plane where the substrate 300 is located and intersect with each other. For example, the first direction F1 and the second direction F2 are perpendicular to each other. Exemplarily, the substrate 300 includes but is not limited to a silicon substrate, a silicon-on-insulator (SOI) substrate, etc. This application is specifically described by taking the substrate as a silicon substrate as an example.

[0070] Because Fin Field-Effect Transistors (Fin FETs) have advantages such as strong current control capability, reduced leakage current, and increased switching speed, each FET in the memory cell of the present application can be configured as a Fin FET. That is, the first pull-up transistor T1, the second pull-up transistor T2, the first pull-down transistor T3, the second pull-down transistor T4, the first gate transistor T5, and the second gate transistor T6 are each configured as a Fin FET. Furthermore, referring to FIG4 and FIG6 , the fin channel of the first pull-up transistor T1, the fin channel of the second pull-up transistor T2, the fin channel of the first pull-down transistor T3, the fin channel of the second pull-down transistor T4, the fin channel of the first gate transistor T5, and the fin channel of the second gate transistor T6 each extend along the second direction F2.

[0071] In order to reduce the complexity of the fin channel patterning, referring to FIG. 4 , in the same memory cell 200 , the fin channel of the first gate transistor T5 and the fin channel of the first pull-down transistor T3 are provided as an integrated structure.

[0072] In order to reduce the complexity of the fin channel patterning, referring to FIG. 4 , in the same memory cell 200 , the fin channel of the second gate tube T6 and the fin channel of the second pull-down tube T4 are set to an integrated structure.

[0073] FIG7 is a schematic diagram of another layout structure of an SRAM provided in an embodiment of the present application. Referring to FIG4 and FIG7 , the multiple memory cells 200 in the present application can form multiple first memory cell groups (e.g., the aforementioned memory cell columns) Za_1 to Za_2 and multiple second memory cell groups (e.g., the aforementioned memory cell rows) Zb_1 to Zb_4. The first memory cell groups Za_1 to Za_2 are arranged along a first direction F1, and each first memory cell group Za_1 to Za_2 includes multiple memory cells 200 arranged along a second direction F2. Furthermore, the second memory cell groups Zb_1 to Zb_4 are arranged along a second direction F2, and each second memory cell group Zb_1 to Zb_4 includes multiple memory cells 200 arranged along the first direction F1. For example, adjacent first memory cell groups can be arranged in mirror symmetry, and two adjacent second memory cell groups can be arranged in mirror symmetry. For example, the first storage cell group Za_1 is arranged in mirror symmetry with the first storage cell group Za_2, the second storage cell group Zb_1 is arranged in mirror symmetry with the second storage cell group Zb_2, the second storage cell group Zb_2 is arranged in mirror symmetry with the second storage cell group Zb_3, and the second storage cell group Zb_3 is arranged in mirror symmetry with the second storage cell group Zb_4. Based on this, two adjacent storage cells arranged along the second direction F2 can be arranged in mirror symmetry, and two adjacent storage cells arranged along the first direction F1 can also be arranged in mirror symmetry. For example, storage unit 200a is arranged in mirror symmetry with storage unit 200b, storage unit 200a is arranged in mirror symmetry with storage unit 200c, and the implementation methods of the remaining storage units 200d, 200e, 200f, 200g, and 200h can be deduced accordingly and will not be repeated here. Of course, two adjacent second storage cell groups can also be arranged in translational symmetry.

[0074] Continuing with FIG4 , the fin channels of adjacent first pull-down tubes T3 along the second direction F2 are configured as an integrated structure, and the fin channels of adjacent first gate tubes T5 along the second direction F2 are also configured as an integrated structure. For example, the fin channels of the first pull-down tubes T3 in memory cells 200b and 200c are integrated, and the fin channels of the first gate tubes T5 in memory cells 200a and 200b are integrated. With this arrangement, fin channels extending along the second direction F2 can be used to form the fin channels of the first pull-down tubes T3 and the fin channels of the first gate tubes T5 in multiple memory cells arranged along the second direction F2, further reducing the complexity of the channel patterning.

[0075] Referring to Figure 4 , the fin channels of the second pull-down tubes T4 adjacent to each other along the second direction F2 are configured as an integrated structure, and the fin channels of the second gate tubes T6 adjacent to each other along the second direction F2 are also configured as an integrated structure. For example, the fin channels of the second pull-down tubes T4 in memory cells 200a and 200b are integrated, while the fin channels of the second gate tubes T6 in memory cells 200b and 200c are integrated. With this arrangement, the fin channels of the second pull-down tubes T4 and the fin channels of the second gate tubes T6 in multiple memory cells arranged along the second direction F2 can be formed using fin channels extending along the second direction F2, further reducing the complexity of the channel patterning.

[0076] 4 , the fin-shaped channels of adjacent first pull-up transistors T1 along the second direction F2 are configured as an integrated structure. For example, the fin-shaped channels of the first pull-up transistors T1 in memory cells 200b and 200c are configured as an integrated structure. With this configuration, the fin-shaped channels of the first pull-up transistors T1 in the two memory cells can be formed using fin-shaped channels extending along the second direction F2, further reducing the complexity of the channel patterning.

[0077] Referring to Figure 4 , the fin-shaped channels of adjacent second pull-up transistors T2 along the second direction F2 are also configured as an integrated structure. For example, the fin-shaped channels of the second pull-up transistors T2 in memory cells 200a and 200b are configured as an integrated structure. This configuration allows the fin-shaped channels of the second pull-up transistors T2 in both memory cells to be formed using fin-shaped channels extending along the second direction F2, further reducing the complexity of the channel patterning.

[0078] It is understandable that the fin channel in each Fin FET may have a channel region, a source region and a drain region arranged on both sides of the channel region. Moreover, the fin channel of each Fin FET in the present application may be one, two, three or more, and its specific value may be determined according to the needs of the actual application scenario, which is not limited here. Also, the structure of each Fin FET in the present application may be basically the same as the structure of the Fin FET in the prior art, which is not described here. In addition, the above content of the present application is described by taking each FET as a Fin FET as an example. In actual applications, each FET in the storage unit of the present application may also be set to a FET of other structures, which is not limited here.

[0079] In order to isolate the channels of each FET, referring to Figures 5a and 5b, a shallow trench isolation (STI) structure 331 is further provided in the substrate 300 to define the area occupied by the channel of each FET in the substrate, and the channels of different FETs are isolated by the STI structure 331.

[0080] Referring to Figures 4 to 6 , an isolation dielectric 332 is provided between different FETs. A first connection layer 320 is provided on the side of the isolation dielectric 332 facing away from the substrate. A first interconnect layer 340 is provided on the side of the first connection layer 320 facing away from the substrate 300. The first interconnect layer 340 includes a plurality of bit lines spaced apart from each other, extending along a second direction F2 and arranged along a first direction F1. To connect the bit lines to the corresponding FETs, the plurality of bit lines may include a plurality of first bit lines BL and a plurality of second bit lines BLB, and the plurality of first bit lines BL and the plurality of second bit lines BLB are arranged alternately along the first direction F1 (i.e., a first bit line BL is provided between two adjacent second bit lines BLB). A first memory cell group corresponds to one first bit line BL and one second bit line BLB. For example, the orthographic projection of the first bit line BL on the substrate 300 can be disposed between the orthographic projection of the first pull-up transistor T1 and the orthographic projection of the first pull-down transistor T3 in the corresponding first memory cell group. The orthographic projection of the second bit line BLB on the substrate 300 can be disposed between the orthographic projection of the second pull-up transistor T2 and the orthographic projection of the second pull-down transistor T4 in the corresponding first memory cell group. Furthermore, the first connection layer 320 also includes a first bit line connection portion 325 and a second bit line connection portion 326 disposed in each memory cell. Furthermore, in the same memory cell, the first bit line connection portion 325 is connected to the first electrode (e.g., the source region of the fin channel of the first gate transistor T5) T5_S. The first electrode of the first gate transistor T5 is also connected to the corresponding first bit line BL through the first bit line connection hole BT1, thereby electrically connecting the first electrode of the first gate transistor T5 to the corresponding first bit line BL. Moreover, in the same memory cell, the second bit line connection portion 326 is connected to the first electrode of the second selection transistor T6 (for example, the source region of the fin channel of the second selection transistor T6) T6_S, and the first electrode of the second selection transistor T6 is also connected to the corresponding second bit line BLB through the second bit line connection hole BT2, thereby electrically connecting the first electrode of the second selection transistor T6 to the corresponding second bit line BLB.

[0081] Continuing with Figures 4 to 6 , a second interconnect layer 350 is provided on the side of the first interconnect layer 340 facing away from the substrate 300. The second interconnect layer 350 includes a plurality of word lines WL spaced apart from each other. The word lines WL extend along a first direction F1 and are arranged along a second direction F2, with each second memory cell group corresponding to a word line WL. To connect the word lines WL to the corresponding FETs, the first connection layer 320 also includes a first word line connection portion and a second word line connection portion provided in each memory cell. The gate of the first gate transistor T5 is connected to the corresponding word line WL via the first word line connection portion, thereby electrically connecting the first gate transistor T5 to the corresponding word line WL. Furthermore, the gate of the second gate transistor T6 is connected to the corresponding word line WL via the second word line connection portion, thereby electrically connecting the second gate transistor T6 to the corresponding word line WL. It is worth noting that the first and second word line connections are not illustrated in Figures 4 to 6 ; their implementation can refer to the implementation of the first and second bit line connections 325 and 326. In addition, an insulating layer 334 is provided between the second interconnection layer 350 and the first interconnection layer 340 , and an insulating layer 333 is provided between the first interconnection layer 340 and the first connection layer 320 .

[0082] Continuing with FIG. 4 to FIG. 5 b , the substrate 300 is further provided with a plurality of trenches (e.g., GT1, GT2, and GT3) spaced apart from one another. The plurality of trenches (e.g., GT1, GT2, and GT3) extend along a second direction F2 and are arranged along a first direction F1. In other words, each trench (e.g., GT1, GT2, and GT3) is configured as a trench-type through-silicon via (TSV) structure, and the direction in which each trench (e.g., GT1, GT2, and GT3) extends is the same as the direction in which the bit lines extend. Furthermore, the plurality of trenches (e.g., GT1, GT2, and GT3) extend along a third direction F3 from the surface of the second side S2 of the substrate 300 into the substrate 300. In other words, the plurality of trenches (e.g., GT1, GT2, and GT3) are embedded in the substrate 300. In addition, the distance d1 between the bottom of the multiple trenches (for example, GT1, GT2, GT3) (that is, the side of the trench close to the memory cell) and the surface of the substrate 300 facing the memory cell (the surface is, for example, the interface between the STI and the substrate 300, or the surface can also be the interface between the bottom of the fin channel of the Fin FET and the substrate 300) is greater than zero, so that the multiple trenches (for example, GT1, GT2, GT3) do not penetrate the substrate. In this way, the groove can be prevented from being restricted by the fin channel in the first direction F1, and the line width of the groove in the first direction F1 can be released. Exemplarily, d1 can be set to 40nm to 60nm. For example, d1 can be set to: 40nm, 45nm, 50nm, 55nm, 60nm. Of course, in actual applications, the specific value of d1 can also be determined according to the needs of the actual application scenario, which is not limited here.

[0083] 4 to 5 b , each groove (e.g., GT1, GT2, GT3) is filled with a power adapter (e.g., 311, 312, 313), that is, the power adapter (e.g., 311, 312, 313) is embedded in the substrate 300. Exemplarily, the material of the power adapter can be a metal material, such as Mo, Ru, Co, etc., which is not limited here. Exemplarily, in order to avoid the power adapter from adversely affecting the substrate, a dielectric layer can also be provided between the substrate and the power adapter. In addition, during the process preparation process, after the groove is formed, a metal material can be filled in the groove to form a power adapter (e.g., 311, 312, 313).

[0084] Referring to Figures 5a and 5b, the second side S2 of the substrate 300 is also provided with a power line, that is, the power line is provided on the back side of the substrate 300. In addition, the power line is connected to the power adapter line in the groove. In addition, the first connection layer 320 is also provided with a connection portion connected to the memory cell, and the connection portion is also connected to the power adapter line in the groove through a contact hole that is mutually connected with the groove, so that the power adapter line (for example, 311, 312, 313) is provided between the power line and the connection portion, so that the memory cell can be powered by the power line, the groove, the contact hole and the connection portion. In addition, by providing the power line on the second side of the substrate, that is, transferring the power line to the back side of the substrate, the memory cell is powered by a backside power delivery network (BSPDN). In addition, in the static random access memory of the prior art, the power line is usually provided on the side of the substrate facing the memory cell (that is, the front side of the substrate), thereby limiting the line width of the word line or bit line, resulting in a series of problems caused by RC delay on the word line or bit line. To this end, the static random access memory provided in the embodiment of the present application, by setting the power line on the back side of the substrate, can not only free up the space of the layer where the word line or bit line is located, but also increase the width of the word line or bit line without increasing the layout area of ​​the storage unit, thereby reducing the resistance of the word line or bit line, thereby improving a series of problems caused by RC delay of the word line or bit line during read and write operations, and improving the overall performance of the static random access memory.

[0085] As shown in FIG3 , a first power supply voltage VSS needs to be input to the memory cell 200. To this end, referring to FIG4 to FIG6 , the power line may include a first power line 371 capable of transmitting the first power supply voltage VSS, with an insulating layer 381 interposed between the first power line 371 and the substrate 300. Furthermore, the plurality of trenches include a plurality of first trenches GT1 and a plurality of second trenches GT2. The power adapter lines 311 filled in the first trenches GT1 and the power adapter lines 312 filled in the second trenches GT2 are connected to the first power line 371 via conductive material filled in conventional vias or trench-type TSV structured vias. This arrangement enables the power adapter lines 311 and 312 in the first trenches GT1 and the second trenches GT2 to be electrically connected to the first power line 371. For example, the conductive material filled in the conventional vias or trench-type vias is the same as that of the first power line 371, and both can be metal. For example, when forming the first power line 371 , the material used to form the first power line 371 may be directly used to fill the ordinary via or the trench type TSV structure via.

[0086] It is understood that the trench-type TSV structure employed in this application can address the problem of memory cell CPP dimensions not meeting the critical dimension (CD) / pitch requirements of backside single-hole TSV vias in advanced processes. Furthermore, compared to single-hole TSVs, trench-type TSVs can also provide a wider alignment window for the TSVs in both the first and second directions.

[0087] Referring to Figures 4 to 5b , the memory cell 200 has a first side and a second side along a first direction F1. A first trench GT1 is provided on the first side of the memory cell 200. The connection portion in the first connection layer 320 may include a first connection portion 321. The first connection portion 321 is connected to the first electrode (e.g., the source region T3_S of the fin channel of the first pull-down transistor T3) of the first pull-down transistor T3. The first connection portion 321 is further connected to the power adapter line 311 in the first trench GT1 via a first contact hole CT1 that penetrates the first trench GT1, thereby positioning the power adapter line 311 between the first power line 371 and the first connection portion 321. Furthermore, the first contact hole CT1 is filled with a conductive material (e.g., a metal material). This arrangement connects the first electrode of the first pull-down transistor T3 to the first power line 371 via the first connection portion 321, the conductive material filled in the first contact hole CT1, and the power adapter line in the first trench GT1, thereby transmitting the first power supply voltage VSS to the first electrode of the first pull-down transistor T3. Exemplarily, the conductive material filled in the first contact hole CT1 can be the same as that of the first connection portion 321. For example, when forming the first connection portion 321, the material forming the first connection portion 321 can be directly used to fill the first contact hole CT1. It is understandable that the first contact hole CT1 extends from the bottom of the first connection portion 321 (i.e., the side of the first connection portion 321 close to the substrate) to the bottom of the first trench GT1 (i.e., the side of the first trench GT1 close to the FinFET) in the third direction F3, thereby forming a deep via structure. In addition, the orthographic projection of the first contact hole CT1 on the substrate is located in the isolation region of the FET between two adjacent first memory cell groups.

[0088] Furthermore, a second trench GT2 is provided on the second side of the memory cell 200. The connection portion in the first connection layer 320 may further include a second connection portion 322. The second connection portion 322 is connected to the first electrode (e.g., the source region T4_S of the fin channel of the second pull-down transistor T4) of the second pull-down transistor T4. The second connection portion 322 is further connected to the power adapter line 312 in the second trench GT2 via a second contact hole CT2 that intersects with the second trench GT2, thereby positioning the power adapter line 312 between the first power line 371 and the second connection portion 322. Furthermore, the second contact hole CT2 is filled with a conductive material (e.g., a metal material). This arrangement allows the first electrode of the second pull-down transistor T4 to be connected to the first power line 371 via the second connection portion 322, the conductive material filled in the second contact hole CT2, and the power adapter line in the second trench GT2, thereby transmitting the first power supply voltage VSS to the first electrode of the second pull-down transistor T4. Exemplarily, the conductive material filled in the second contact hole CT2 can be the same as that of the second connection portion 322. For example, when forming the second connection portion 322, the material forming the second connection portion 322 can be directly used to fill the second contact hole CT2. It is understandable that the second contact hole CT2 extends from the bottom of the second connection portion 322 (i.e., the side of the second connection portion 322 close to the substrate) to the bottom of the second trench GT2 (i.e., the side of the second trench GT2 close to the FinFET) in the third direction F3, thereby forming a deep via structure. In addition, the orthographic projection of the second contact hole CT2 on the substrate is located in the isolation region of the FET between two adjacent first memory cell groups.

[0089] Through the above-mentioned setting, the static random access memory provided by the embodiment of the present application transfers the first power line 371 to the back side of the substrate, realizing a structure in which the first power supply voltage VSS is input to the memory cell in a BSPDN manner. In addition, in the static random access memory of the prior art, the first power line 371 is usually arranged on the side of the substrate facing the memory cell (i.e., the front side of the substrate) and the first power line 371 is arranged on the same layer as the word line, thereby limiting the line width of the word line, resulting in the word line having a problem of a slow high-level voltage rise rate due to RC delay. To this end, in the static random access memory provided by the embodiment of the present application, by transferring the first power line 371 to the back side of the substrate, not only can the space in the layer where the word line is located be freed up, but the width of the word line can be increased without additionally increasing the layout area of ​​the memory cell, thereby reducing the resistance of the word line, improving the problem of a slow high-level voltage rise rate due to RC delay of the word line, and thereby increasing the high-level voltage rise rate of the word line.

[0090] In a specific implementation, when the first power line 371 and the word line WL are arranged on the same layer, the width of the word line WL in the second direction F2 is set as the first set width h10. Referring to FIG6, in the embodiment of the present application, by removing the first power line 371 from the layer where the word line WL resides, freeing up the space originally occupied by the first power line 371, the width h11 of each word line WL in the second direction F2 can be increased by 20% to 40% based on the first set width h10, that is, h11 is h10*120% to h10*140%. This configuration increases the width of the word line WL, reduces the resistance of the word line WL, and improves the slow high-level voltage rise rate of the word line WL caused by RC delay, thereby improving the high-level voltage rise rate of the word line WL. For example, h11 can be set to: h10*120%, h10*125%, h10*130%, h10*135%, h10*140%, etc. Of course, the specific value of h11 can also be determined according to the needs of the actual application scenario and is not limited here. It is understandable that the value of h10 may be different in SRAMs of different process sizes, so the specific value of h10 can be determined according to the needs of the actual application scenario.

[0091] This application uses the structure of the static random access memory (SRAM) shown in FIG4 as an example to simulate the situation where a high-level voltage Vgh is input when the word line has different widths. The simulation results are shown in FIG8 . FIG8 is a schematic diagram of the simulation results of the SRAM provided by the embodiment of the present application when a high-level voltage is input when the word line has different widths. L10 represents the voltage curve when the word line is input with a high-level voltage Vgh when the width h11 is the first set width h10. L11 represents the voltage curve when the word line is input with a high-level voltage Vgh when the width h11 increases by 20% from the first set width h10. L12 represents the voltage curve when the word line is input with a high-level voltage Vgh when the width h11 increases by 40% from the first set width h10. Referring to FIG8 , when the width h11 is the first set width h10, the voltage on the word line reaches Vgh*90% at time t10. When the width h11 is increased by 20% based on the first set width h10, the voltage on the word line reaches Vgh*90% at time t11, which is faster than time t10 by a time t10-t11 (in some structures, this time can be 12ps). When the width h11 is increased by 40% based on the first set width h10, the voltage on the word line reaches Vgh*90% at time t12, which is faster than time t10 by a time t10-t12. Therefore, it can be seen that increasing the word line width h11 by 20% or 40% based on the first set width h10 can improve the problem of slow high-level voltage rise rate of the word line caused by RC delay, increase the high-level voltage rise rate of the word line, and improve the overall performance of the static random access memory.

[0092] As can be seen from FIG3 , a second power supply voltage VDD also needs to be input to the memory cell 200. To this end, referring to FIG4 to FIG6 , the power line may further include a second power line 372 capable of transmitting the second power supply voltage VDD. Furthermore, the plurality of trenches also include a third trench GT3. Each first memory cell group corresponds to a third trench GT3. The third trench GT3 is disposed between the first pull-up transistor T1 and the second pull-up transistor T2 in the corresponding memory cell, and connects the power adapter line 313 in the third trench GT3 to the second power line 372. To input the second power supply voltage VDD to the first pull-up transistor T1 and the second pull-up transistor T2, the connection portion in the first interconnect layer 340 further includes a third connection portion 323 and a fourth connection portion 324. The third connection portion 323 is connected to the first electrode (e.g., the source region of the fin channel of the first pull-up transistor T1) T1_S. The third connection portion 323 is also connected to the power adapter line 313 in the third trench GT3 via a third contact hole CT3 that interpenetrates the third trench GT3, thereby connecting the first pull-up transistor T1 to the second power supply line 372. Furthermore, the fourth connection portion 324 is connected to the first electrode (e.g., the source region of the fin channel of the second pull-up transistor T2) T2_S. The fourth connection portion 324 is also connected to the power adapter line 313 in the third trench GT3 via a fourth contact hole CT4 that interpenetrates the third trench GT3, thereby connecting the second pull-up transistor T2 to the second power supply line 372. Based on this, the power adapter line 313 can be arranged between the second power line 372 and the third connection part 323 and the fourth connection part 324 .

[0093] It can be understood that the third contact hole CT3 extends from the bottom of the third connection portion 323 (i.e., the side of the third connection portion 323 close to the substrate) to the bottom of the third trench GT3 (i.e., the side of the third trench GT3 close to the FinFET) in the third direction F3, thereby forming a deep via structure. In addition, the fourth contact hole CT4 extends from the bottom of the fourth connection portion 324 (i.e., the side of the fourth connection portion 324 close to the substrate) to the bottom of the third trench GT3 (i.e., the side of the fourth trench close to the FinFET) in the third direction F3, thereby forming a deep via structure. In addition, the orthographic projections of the third contact hole CT3 and the fourth contact hole CT4 on the substrate are located in the isolation area between the first pull-up tube T1 and the second pull-up tube T2.

[0094] Through the above-mentioned setting, the static random access memory provided by the embodiment of the present application transfers the second power line 372 to the back side of the substrate, realizing a structure in which the second power supply voltage VDD is input to the memory cell in a BSPDN manner. In addition, in the static random access memory of the prior art, the second power line 372 is usually arranged on the side of the substrate facing the memory cell (i.e., the front side of the substrate) and the second power line 372 is arranged on the same layer as the bit line, thereby limiting the line width of the bit line, resulting in the problem of slow discharge rate of the bit line due to RC delay. To this end, in the static random access memory provided by the embodiment of the present application, by transferring the second power line 372 to the back side of the substrate, not only can the space of the layer where the bit line is located be freed up, but also the width of the bit line can be increased without additionally increasing the layout area of ​​the memory cell, thereby reducing the resistance of the bit line, improving the problem of slow discharge rate of the bit line due to RC delay during read and write operations, thereby increasing the discharge rate of the bit line and improving the overall performance of the static random access memory.

[0095] In a specific implementation, when the second power line 372 is placed on the same layer as the bit line, the width of the bit line in the first direction F1 is set as the second set width h20. Referring to Figure 6, in this embodiment of the present application, by removing the second power line 372 from the bit line layer, freeing up the space originally occupied by the second power line 372, the width h21 of each bit line in the first direction F1 can be increased by 20% to 40% based on the second set width h20, that is, h21 is between h20*120% and h20*140%. This configuration increases the width of the bit line, reduces its resistance, and can improve the slow discharge rate of the bit line caused by RC delay, thereby increasing the discharge rate of the bit line. For example, h21 can be set to: h20*120%, h20*125%, h20*130%, h20*135%, h20*140%, etc. Of course, the specific value of h21 can be determined according to the needs of the actual application scenario and is not limited here. It is understandable that the value of h20 may be different in SRAMs of different process sizes, so the specific value of h20 can be determined according to the requirements of the actual application scenario.

[0096] Taking the structure of a static random access memory (SRAM) shown in FIG4 as an example, this application simulates the discharge behavior during read and write operations when the bit line has different widths. The simulation results are shown in FIG9 . FIG9 is a schematic diagram illustrating the simulation results of a static random access memory (SRAM) according to an embodiment of the present application performing read and write operations when the bit line has different widths. L30 represents the signal on the word line, L20 represents the voltage change curve on the bit line during read and write operations when the width h21 is the second set width h20, L21 represents the voltage change curve on the bit line during read and write operations when the width h21 increases by 20% from the second set width h20, and L22 represents the voltage change curve on the bit line during read and write operations when the width h21 increases by 40% from the second set width h20. Referring to FIG9 , the discharge rate corresponding to a 40% increase in the bit line width h21 from the second set width h20 is greater than the discharge rate corresponding to a 20% increase in the bit line width h21 from the second set width h20, and the discharge rate corresponding to a 20% increase in the bit line width h21 from the second set width h20 is greater than the discharge rate corresponding to a 20% increase in the bit line width h21 from the second set width h20. Furthermore, simulations show that increasing the bit line width h21 by 20% and 40% from the second set width h20 can increase the bit line discharge rate by 5% to 9%, thereby increasing the overall read and write speed by 3% to 5%. This indicates that increasing the bit line width h21 by 20% and 40% from the second set width h20 can alleviate the slow bit line discharge rate caused by RC delay during read and write operations, improve the bit line discharge rate, and enhance the overall performance of the SRAM.

[0097] Exemplarily, the second power line 372 and the first power line 371 are insulated from each other. For example, referring to Figures 5a and 5b, the second power line 372 and the first power line 371 can be arranged in different layers, and an insulating layer 382 is further provided between the second power line 372 and the first power line 371. The first power line 371 is provided between the second power line 372 and the substrate, or the second power line 372 is provided between the first power line 371 and the substrate. Of course, the second power line 372 and the first power line 371 can also be provided in the same layer. In a specific implementation, the second power line 372 and the first power line 371 can be shaped into a strip structure or a grid structure.

[0098] To further increase the density of memory cells, as shown in Figures 4 and 7 , since two adjacent memory cells 200 arranged along the second direction F2 can be arranged symmetrically, the first connection portion 321 connecting two adjacent first pull-down tubes T3 along the second direction F2 can share the same first contact hole CT1. This arrangement can reduce the number of first contact holes CT1 and reduce the complexity of the layout design. Furthermore, the first trench GT1 can be made to interpenetrate each first contact hole CT1 in the corresponding first memory cell group (e.g., Za_1), thereby enabling the same first trench GT1 to provide the first power supply voltage VSS to the first pull-down tubes T3 in the corresponding first memory cell (e.g., Za_1).

[0099] To further increase the density of the memory cells, as shown in Figures 4 and 7 , since two adjacent memory cells 200 arranged along the second direction F2 can be arranged symmetrically, the second connection portion 322 connecting two adjacent second pull-down tubes T4 along the second direction F2 can share the same second contact hole CT2. This arrangement can reduce the number of second contact holes CT2 and reduce the complexity of the layout design. Furthermore, the second trench GT2 can be made to interpenetrate each second contact hole CT2 in the corresponding first memory cell group (e.g., Za_1), thereby enabling the same second trench GT2 to provide the first power supply voltage VSS to the second pull-down tubes T4 in the corresponding first memory cell (e.g., Za_1).

[0100] To further increase the density of the memory cells, as shown in FIG4 and FIG7 , since two adjacent memory cells 200 arranged along the first direction F1 are arranged in mirror symmetry, the first trenches GT1 between the two adjacent memory cells 200 along the first direction F1 can be configured as the same trench. This configuration can reduce the number of first trenches GT1 and reduce the complexity of the layout design.

[0101] Furthermore, the first connection portion 321 connecting two adjacent first pull-down tubes T3 along the first direction F1 can share a common first contact hole CT1. This arrangement can further reduce the number of first contact holes CT1 provided, thereby reducing the complexity of the layout design. Furthermore, a first trench GT1 can be used to intersect each first contact hole CT1 in two adjacent first storage cell groups, thereby enabling the same first trench GT1 to provide the first power supply voltage VSS to the first pull-down tubes T3 in two adjacent first storage cells.

[0102] To further increase the density of the memory cells, as shown in FIG4 and FIG7 , since two adjacent memory cells 200 arranged along the first direction F1 are arranged in mirror symmetry, the second trenches GT2 between the two adjacent memory cells 200 along the first direction F1 can be configured as the same trench. This configuration can reduce the number of second trenches GT2 and reduce the complexity of the layout design.

[0103] Furthermore, the second connection portions 322 connecting adjacent second pull-down tubes T4 along the first direction F1 can share a single second contact hole CT2. This arrangement can further reduce the number of second contact holes CT2 required, thereby reducing layout design complexity. Furthermore, a single second trench GT2 can be interpenetrated with each second contact hole CT2 in two adjacent first storage cell groups (e.g., Za_1 and Za_2), thereby enabling the same second trench GT2 to provide the first power supply voltage VSS to the second pull-down tubes T4 in two adjacent first storage cell groups (e.g., Za_1 and Za_2).

[0104] To further increase the density of memory cells, as shown in Figures 4 and 7 , since two adjacent memory cells 200 arranged along the second direction F2 are arranged in mirror-symmetry, the third connection portions 323 connecting two adjacent first pull-up transistors T1 along the second direction F2 can share a single third contact hole CT3. This arrangement further reduces the number of third contact holes CT3 required, reducing layout design complexity. Furthermore, a single third trench GT3 can intersect with each third contact hole CT3 in the corresponding first memory cell group (e.g., Za_1), enabling the same third trench GT3 to provide the second power supply voltage VDD to the first pull-up transistors T1 in the first memory cell (e.g., Za_1).

[0105] To further increase the density of memory cells, as shown in Figures 4 and 7 , since two adjacent memory cells 200 arranged along the second direction F2 are arranged in mirror-symmetry, the fourth connection portion 324 connecting two adjacent second pull-up transistors T2 along the second direction F2 can share a single fourth contact hole CT4. This arrangement further reduces the number of fourth contact holes CT4 required, reducing layout design complexity. Furthermore, a third trench GT3 can be used to intersect with each fourth contact hole CT4 in the corresponding first memory cell group (e.g., Za_1), thereby enabling the same third trench GT3 to provide the second power supply voltage VDD to the second pull-up transistors T2 in the first memory cell (e.g., Za_1).

[0106] Furthermore, a third trench GT3 can be made to penetrate each third contact hole CT3 and each fourth contact hole CT4 in the corresponding first storage cell group (for example, Za_1), so that the same third trench GT3 can be used to provide the second power supply voltage VDD for the first pull-up tube T1 and the second pull-up tube T2 in the first storage cell group (for example, Za_1).

[0107] It is understood that in the embodiment of the present application, the first power line 371 can also be arranged on the second side S2 of the substrate 300, and the second power line 372 can be arranged on the first side S1 of the substrate 300, and the second power line 372 can be arranged on the same layer as the bit line. Alternatively, the second power line 372 can also be arranged on the second side S2 of the substrate 300, and the first power line 371 can be arranged on the first side S1 of the substrate 300, and the first power line 371 can be arranged on the same layer as the word line.

[0108] The above content is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, and they should all be covered by the protection scope of the present application.

Claims

1. A static random access memory, characterized in that, Comprising: A substrate having a first side and a second side along a third direction, the third direction being perpendicular to the plane of the substrate; A plurality of memory cells, arranged in an array on the first side of the substrate; A plurality of trenches spaced apart from each other, the plurality of trenches extending from the surface of the second side of the substrate into the substrate along the third direction, the plurality of trenches extending along a second direction and arranged along a first direction, the distance between the bottom of the trench and the surface of the substrate facing the memory cell side being greater than zero, the first direction and the second direction being parallel to the plane of the substrate and intersecting each other; A power transfer line filled in each of the trenches; A power supply line provided on the second side of the substrate, the power supply line being connected to the power transfer line in the trench; A first connection layer provided on the side of the memory cell facing away from the substrate, the first connection layer including a connection portion, the connection portion being connected to the memory cell, and the connection portion also being connected to the power transfer line in the trench through a contact hole communicating with the trench; 2. The static random access memory according to claim 1, wherein The memory cell has a first side and a second side along the first direction, the plurality of trenches include a first trench and a second trench, the first trench is provided on the first side of the memory cell, and the second trench is provided on the second side of the memory cell; The power supply line includes a first power supply line for transmitting a first power supply voltage, the first power supply line being respectively connected to the power transfer lines in the first trench and the second trench; The memory cell includes: a first pull-down tube and a second pull-down tube, the connection portion includes a first connection portion and a second connection portion, the first connection portion is connected to the first pole of the first pull-down tube, and the first connection portion is also connected to the power transfer line in the first trench through a first contact hole communicating with the first trench, the second connection portion is connected to the first pole of the second pull-down tube, and the second connection portion is also connected to the power transfer line in the second trench through a second contact hole communicating with the second trench; 3. The static random access memory according to claim 2, wherein Further comprising: A second interconnection layer provided on the side of the first connection layer facing away from the substrate, the second interconnection layer including: a plurality of word lines spaced apart from each other, the plurality of word lines extending along the first direction and arranged along the second direction; The memory cell further includes: a first selection tube and a second selection tube, the gates of the first selection tube and the second selection tube are respectively connected to the word lines, and the width of the word line in the second direction is increased by 20% to 40% based on a first set width; 4. The static random access memory according to any one of claims 1 to 3, characterized in that, The power supply line includes a second power supply line for transmitting a second power supply voltage, the plurality of trenches include a third trench, the memory cell includes a first pull-up tube and a second pull-up tube, the third trench is provided between the first pull-up tube and the second pull-up tube in the memory cell, and the power transfer line in the third trench is connected to the second power supply line; The connecting portion includes a third connecting portion and a fourth connecting portion. The third connecting portion is connected to the first pole of the first pull-up tube. The third connecting portion is further connected to the power supply transfer wire in the third groove through a third contact hole that penetrates the third groove. The fourth connecting portion is connected to the first pole of the second pull-up tube. The fourth connecting portion is further connected to the power supply transfer wire in the third groove through a fourth contact hole that penetrates the third groove.

5. The static random access memory according to claim 4, wherein It further includes: A first interconnect layer disposed on a side of the first connection layer facing away from the substrate. The first interconnect layer includes: a plurality of bit lines arranged at intervals. The plurality of bit lines extend in the second direction and are arranged in the first direction. The width of the bit line in the first direction is increased by 20% - 40% based on a second set width. The storage unit further includes: a first select tube and a second select tube. The plurality of bit lines includes a first bit line and a second bit line. The first pole of the first select tube is connected to the first bit line. The first pole of the second select tube is connected to the second bit line.

6. The static random access memory according to any one of claims 1-5, characterized in that, The distance between the groove and the surface of the substrate facing the storage unit side is 40nm - 60nm.

7. The static random access memory according to any one of claims 1-6, characterized in that, The storage unit includes: a first pull-up tube, a second pull-up tube, a first pull-down tube, a second pull-down tube, a first select tube, and a second select tube. And the first pull-down tube, the first pull-up tube, the second pull-up tube, and the second pull-down tube are sequentially arranged at intervals in the first direction. The first select tube and the first pull-down tube are arranged on a straight line in the second direction. The second select tube and the second pull-down tube are arranged on another straight line in the second direction.

8. The static random access memory according to claim 7, wherein Adjacent two storage units arranged in the second direction are arranged in mirror symmetry; The first connecting portions connected to two adjacent first pull-down tubes arranged in the second direction share the same first contact hole; or, The second connecting portions connected to two adjacent second pull-down tubes arranged in the second direction share the same second contact hole.

9. The static random access memory according to claim 7 or 8, characterized in that, Adjacent two storage units arranged in the first direction are arranged in mirror symmetry; The first groove between two adjacent storage units arranged in the first direction is the same groove; Or, The second groove between two adjacent storage units arranged in the first direction is the same groove.

10. The static random access memory according to any one of claims 7-9, characterized in that, The first connecting portions connected to two adjacent first pull-down tubes arranged in the first direction share the same first contact hole; or, The second connecting portions connected to adjacent second pull-down tubes arranged in the first direction share the same second contact hole.

11. The static random access memory according to any one of claims 7-10, characterized in that, Adjacent two storage units arranged in the second direction are arranged in mirror symmetry; The third connecting portions connected to two adjacent first pull-up tubes arranged in the second direction share the same third contact hole; or, The fourth connecting portions connected to two adjacent second pull-up tubes arranged in the second direction share the same fourth contact hole.

12. The static random access memory according to any one of claims 7-11, characterized in that, The first pull-up transistor, the second pull-up transistor, the first pull-down transistor, the second pull-down transistor, the first select transistor, and the second select transistor are respectively fin field-effect transistors, and the fin channels of the first pull-up transistor, the fin channels of the second pull-up transistor, the fin channels of the first pull-down transistor, the fin channels of the second pull-down transistor, the fin channels of the first select transistor, and the fin channels of the second select transistor respectively extend along the second direction.

13. A processing circuit chip, characterized in that, It includes a static random access memory according to any one of claims 1-12 and one or more processors, and the static random access memory is used to store data required for the operation of the one or more processors.

14. An electronic device, characterized in that, It includes a bus and a processing circuit chip according to claim 13, and the bus is connected to the processing circuit chip.

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