Bus circuit and electronic device

Abstract

Disclosed in the present application are a bus circuit and an electronic device. The bus circuit comprises: a power source interface, a power source control circuit, a non-polarized carrier communication circuit, a positive bus, a negative bus, a first anti-interference circuit, a second anti-interference circuit and a port.

Description

Bus circuits and electronic equipment

[0001] This application claims priority to the Chinese patent application with application number 2023115687824, filed on November 22, 2023, and with invention name “Bus Circuit and Electronic Device”, and claims priority to the Chinese patent application with application number 2023116590968, filed on December 5, 2023, and with invention name “Bus Circuit and Electronic Device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of power line carriers, and in particular to a bus circuit and electronic equipment. Background Art

[0003] Bus technology products are suitable for large-scale control applications such as intelligent buildings and residential communities. The key feature of bus technology is that all device communication and control are based on a single bus. It is a fully distributed intelligent control network technology. Its product modules feature two-way communication, interoperability, and interchangeability, and its control components are fully programmable.

[0004] Generally, devices on the bus operate in master-slave mode. Communication and power supply between the master and slave devices require four lines, which significantly increases the construction difficulty, construction cost, and equipment cost. In addition, the waveform on the communication transmission line has strict requirements on the number of pulses. An occasional interference may cause communication data errors or data loss, and in severe cases, communication may be impossible.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide a bus circuit and an electronic device to address the impact of interference signals in the bus circuit on non-polarity carrier communication signals.

[0007] In a first aspect, an embodiment of the present application provides a bus circuit, the bus circuit comprising: a power interface, a power control circuit, a polarity-free carrier communication circuit, a positive bus, a negative bus, a first anti-interference circuit, a second anti-interference circuit, and a port, wherein:

[0008] The non-polarity carrier communication circuit includes: a first input end, a first transmission end, and a second transmission end; the first anti-interference circuit includes: a second input end, a third input end, a first output end, and a second output end; the second anti-interference circuit includes: a fourth input end, a fifth input end, a third output end, and a fourth output end; the port includes: a first terminal and a second terminal, wherein,

[0009] One end of the positive bus is connected to the power interface, the other end of the positive bus is connected to the second input end of the first anti-interference circuit, the first output end of the first anti-interference circuit is respectively connected to the first terminal of the port and the third output end of the second anti-interference circuit, and the fourth input end of the second anti-interference circuit is connected to the first transmission end of the non-polarity carrier communication circuit; one end of the negative bus is grounded via the power control circuit, the other end of the negative bus is connected to the third input end of the first anti-interference circuit, the second output end of the first anti-interference circuit is respectively connected to the second terminal of the port and the fourth output end of the second anti-interference circuit, and the fifth input end of the second anti-interference circuit is connected to the second transmission end of the non-polarity carrier communication circuit;

[0010] The power interface is configured to receive a power signal;

[0011] The power control circuit is configured to control the on and off of the bus circuit according to the received first control signal;

[0012] The first input terminal of the non-polarity carrier communication circuit is configured to receive a logic level signal, the first transmission terminal of the non-polarity carrier communication circuit is configured to output a first non-polarity carrier communication signal, and the second transmission terminal of the non-polarity carrier communication circuit is configured to output a second non-polarity carrier communication signal;

[0013] The first anti-interference circuit is configured to isolate the first non-polarity carrier communication signal and the second non-polarity carrier communication signal output by the non-polarity carrier communication circuit, and input the power signal in the positive bus into the first terminal of the port and the power signal in the negative bus into the second terminal of the port;

[0014] The second anti-interference circuit is configured to isolate the power supply signal and load the received first non-polarity carrier communication signal into the positive bus containing the power supply signal and load the received second non-polarity carrier communication signal into the negative bus containing the power supply signal.

[0015] In a second aspect, an embodiment of the present application provides an electronic device, including: the bus circuit described above.

[0016] In the embodiments of the present application, a bus can be used to simultaneously transmit power signals and non-polarized carrier communication signals to other devices, effectively reducing device costs. Furthermore, a first anti-interference circuit is used to isolate the non-polarized carrier signal, preventing distortion of the non-polarized carrier communication signal; and a second anti-interference circuit is used to isolate the power signal, preventing the bus power signal from entering the non-polarized carrier communication circuit and damaging the communication circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] FIG1 is an application scenario diagram of a bus circuit provided by an embodiment of the present application;

[0019] FIG2 is a schematic diagram of the internal structure of a bus circuit provided in an embodiment of the present application;

[0020] FIG3 is a schematic diagram of the internal structure of another bus circuit provided in an embodiment of the present application;

[0021] FIG4 is a schematic diagram of the internal structure of another bus circuit provided in an embodiment of the present application;

[0022] FIG5 is a schematic diagram of the internal structure of another bus circuit provided in an embodiment of the present application;

[0023] FIG6 is a schematic diagram of the internal structure of another bus circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0025] In the description of this application, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances. In addition, in the description of this application, unless otherwise specified, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship.

[0026] Refer to the application scenario diagram of a bus circuit provided by the present application shown in Figure 1. The application scenario includes a master device, N slave devices (N is an integer greater than 1), and a bus. Among them, the master device includes the bus circuit provided by the present application (not shown in Figure 1), and the bus includes: a positive bus and a negative bus. The specific bus is a technology that combines the power supply line and the signal line into one relative to the four-wire system (two power supply lines and two communication lines), realizing power supply and communication sharing one bus.

[0027] Optionally, the bus in the embodiment of the present application is a two-core bus. The two-core bus can realize power supply and communication between the air conditioner indoor unit and the wired controller, for example.

[0028] Specifically, the communicating parties in Figure 1 are a master device and a slave device. A master device can be connected to up to multiple slave devices. A master device is a device that controls the bus, such as an air conditioner controller, which can issue control information to control the operation of slave devices. Slave devices, such as the air conditioner's indoor unit and sensors, receive and process control information from the master device and execute specific tasks issued by the master device. The master device can issue queries or write commands to the slave device, which then passively receives the commands and returns the corresponding data results or executes the write command based on the function code and register number. For example, the indoor unit in an air conditioner can receive and execute instructions from the wired controller.

[0029] Next, the bus circuit provided in the embodiment of the present application is introduced with reference to the application scenario diagram introduced in FIG1 .

[0030] 2 is a schematic diagram of a bus circuit provided by the present application. The bus circuit may include: a power interface 00, a power control circuit, a polarity-free carrier communication circuit, a positive bus, a negative bus, a first anti-interference circuit, a second anti-interference circuit, and a port 01.

[0031] The non-polarity carrier communication circuit may include: a first input terminal Input1, a first transmission terminal I / O1, and a second transmission terminal I / O2; the first anti-interference circuit may include: a second input terminal Input2, a third input terminal Input3, a first output terminal Out1, and a second output terminal Out2; the second anti-interference circuit may include: a fourth input terminal Input4, a fifth input terminal Input5, a third output terminal Out3, and a fourth output terminal Out4; and port 01 may include: a first terminal 1 and a second terminal 2. One end of the positive bus is connected to the power interface 00, and the other end of the positive bus is connected to the second input terminal Input2 of the first anti-interference circuit; the first output terminal Out1 of the first anti-interference circuit is respectively connected to the first terminal 1 of port 01 and the third output terminal Out3 of the second anti-interference circuit; and the fourth input terminal Input4 of the second anti-interference circuit is connected to the first transmission terminal I / O1 of the non-polarity carrier communication circuit. One end of the negative bus is grounded through the power control circuit, and the other end of the negative bus is connected to the third input terminal Input3 of the first anti-interference circuit. The second output terminal Out2 of the first anti-interference circuit is respectively connected to the second terminal 2 of port O1 and the fourth output terminal Out4 of the second anti-interference circuit. The fifth input terminal Input5 of the second anti-interference circuit is connected to the second transmission terminal I / O2 of the non-polarity carrier communication circuit.

[0032] The power interface 00 is configured to transmit a power signal. The power control circuit is configured to control the bus circuit's conduction and shutdown based on a received first control signal. The first input terminal Input1 of the polarity-free carrier communication circuit is configured to receive a logic level signal. The first transmission terminal I / O1 of the polarity-free carrier communication circuit is configured to output a first polarity-free carrier communication signal. The second transmission terminal I / O2 of the polarity-free carrier communication circuit is configured to output a second polarity-free carrier communication signal. The first anti-interference circuit is configured to isolate the first and second polarity-free carrier communication signals output by the polarity-free carrier communication circuit, and output the power signal in the positive bus to the first terminal 1 of port 01, and the power signal in the negative bus to the second terminal 2 of port 01. The second anti-interference circuit is configured to isolate the power signal and load the first polarity-free carrier communication signal output by the polarity-free carrier communication circuit into the positive bus containing the power signal, and load the second polarity-free carrier communication signal into the negative bus containing the power signal. Specifically, port 01 in the embodiment of the present application can interconnect a master device containing a bus circuit with multiple external slave devices. The non-polarized carrier communication circuit in the master device can transmit the carrier signal without distinguishing its polarity. That is to say, in the related art, the transmission end of the communication circuit of the master device usually needs to distinguish its polarity, for example, I / O1 can only transmit positive signals and I / O2 can only transmit negative signals. However, in the embodiment of the present application, both transmission ends of the non-polarized carrier communication circuit can transmit positive or negative signals. As long as the polarities of the signals transmitted simultaneously by the two transmission ends are opposite, normal communication between the master and slave devices can be achieved through the bus and port 01.

[0033] Optionally, the polarity-free carrier communication circuit in the embodiments of the present application can implement modulation and demodulation functions by configuring on-off keying. This means that communication data is modulated onto the power line, enabling simultaneous power transmission and data communication on the bus, significantly reducing system costs. Furthermore, on-off keying is unaffected by signal polarity, eliminating the risk of device failure caused by incorrectly connected output terminals.

[0034] Optionally, the embodiment of the present application may also digitally isolate the digital signal before the on-off keying receives it, so as to eliminate bit errors caused by pulse loss that may occur during the pulse modulation process.

[0035] Optionally, the power signal in the embodiment of the present application may be a 24V DC power signal. Furthermore, the bus circuit in the embodiment of the present application may further include a power polarity detection circuit. The input end of the power polarity detection circuit is connected to the negative bus, and the output end of the power polarity detection circuit is connected to the positive bus. The circuit may be configured to detect the positive and negative polarity of the DC power supply connected to the power interface.

[0036] It can be understood that the purpose of setting up a power polarity detection circuit between the positive bus and the negative bus in the embodiment of the present application is to prevent the DC power supply from being reversely connected to the power interface, that is, the positive pole of the DC power supply is connected to the negative end of the power interface, and the negative pole of the DC power supply is connected to the positive end of the power interface.

[0037] Refer to the internal structure diagram of the bus circuit shown in Figure 3. The power polarity detection circuit in the embodiment of the present application can use an optocoupler circuit IC1 to detect whether there is a reverse power supply in the bus. For example, the optocoupler circuit IC1 is reversely connected between the positive bus and the negative bus, that is, the input terminal 1 of the optocoupler circuit IC1 is connected to the negative bus, and the output terminal 2 of the optocoupler circuit IC1 is connected to the positive bus through the resistors R1 and R2 connected in parallel. In this way, when the DC power supply DC is connected to the power interface, the optocoupler circuit IC1 is not turned on and does not emit light. However, when the DC power supply DC is reversely connected to the power interface, the optocoupler circuit IC1 will turn on and emit light. In this way, the reverse connection detection of the DC power supply can be realized, and the user can be prompted that there is a reverse connection problem of the DC power supply in the bus circuit, the master and slave devices cannot be powered normally, and in serious cases, the circuit board may be burned. In addition, the output terminal 3 of the optocoupler circuit IC1 is respectively connected to resistors R4 and R6. The other end of resistor R4 is connected to a second voltage source V2. The bus circuit power status signal POC_STA can be obtained through the line at the other end of resistor R6. When POC_STA outputs a high level, it indicates that the optocoupler circuit IC1 is turned on and the power supply in the bus circuit is reversed. When POC_STA outputs a low level, it indicates that the optocoupler circuit IC1 is disconnected and the power supply in the bus circuit is forward connected. The output terminal 4 of the optocoupler circuit IC1 is grounded. Optionally, the second voltage source V2 in the embodiment of the present application is +3.3V.

[0038] Optionally, the power polarity detection circuit in the embodiment of the present application can also use a buzzer alarm, and the buzzer alarm is reversely connected between the positive bus and the negative pole. In this way, once the DC power supply is reversely connected in the power interface, the buzzer alarm can send an alarm signal to remind the user that there is a reverse connection problem with the DC power supply in the bus circuit.

[0039] Optionally, the embodiment of the present application may also use text, images, symbols or other identification methods to minimize the risk of reverse connection of the DC power supply.

[0040] Optionally, if there are too many slave devices on the bus circuit, the master device may not be able to provide sufficient power using a single DC power supply, so it is necessary to add a DC power supply in the master device. However, in the embodiment of the present application, the bus circuit can still use only one power supply polarity detection circuit to detect the polarity of the current in the positive bus and the negative bus. For example, if any one of the DC power supplies in the positive bus and the negative bus is reversely connected, the optocoupler will turn on and emit light, thereby realizing reverse real-time protection of multiple power supplies.

[0041] Therefore, the embodiment of the present application solves the problem in the related technology that when the equipment may have multiple communication protocols such as residential and building control standards (Konnex, KNX), the corresponding DC carrier communication method can be used to transmit the power supply signal and communication signal in the master device to the slave device together. During the transmission process, it only needs to consider the polarity of the connected DC power supply without considering the polarity of the carrier communication circuit. Correspondingly, it avoids the problem of the master and slave devices not being able to work normally due to incorrect wiring of the carrier communication circuit.

[0042] Optionally, the power signal in the embodiments of the present application may also utilize a low-frequency AC power supply. Optionally, the first interference prevention circuit in the embodiments of the present application may include a common-mode winding. The common-mode winding may include a first winding and a second winding. The first winding may include a third terminal and a fourth terminal, and the second winding may include a fifth terminal and a sixth terminal. The third terminal and the fifth terminal are synonymous terminals.

[0043] Among them, the other end of the positive bus is connected to the fifth terminal of the second winding, and the sixth terminal of the second winding is connected to the third output end of the second anti-interference circuit and the first terminal of the port; the other end of the negative bus is connected to the fourth terminal of the first winding, and the third terminal of the first winding is connected to the fourth output end of the second anti-interference circuit and the second terminal of the port.

[0044] Furthermore, in the embodiment of the present application, the two inductors of the common-mode winding can adopt EE-shaped magnetic cores, polycarbonate PC materials, like-name ends at both ends, and are wound in the same direction, which not only doubles the inductance but also effectively simplifies the wiring in the circuit.

[0045] See Figure 3. The common-mode winding L in the embodiment of the present application includes four terminals, wherein the two ends of one inductor are terminal 1 and terminal 2, respectively, and the two terminals of the other inductor are terminal 3 and terminal 4, respectively. Terminal 1 and terminal 3 are the same-name terminals. Between terminal 2 and terminal 3 are two capacitors C2 and C3 connected in parallel, which are configured to suppress electromagnetic interference and stabilize voltage. Terminal 1 of the common-mode winding L is connected to terminal 2 of port 01 via a negative bus, and terminal 4 of the common-mode winding L is connected to terminal 1 of port 01 via a positive bus.

[0046] Specifically, the common-mode winding operates as follows: Because the third and fifth terminals of the common-mode windings in the present embodiment are located at different ends of the two windings, when an AC signal is present in the two coils, the magnetic flux in the magnetic rings superimposes, resulting in a considerable inductance that suppresses the AC signal. However, when a DC current flows through the two coils, the magnetic flux in the magnetic rings cancels each other out, resulting in almost no inductance, allowing the DC current to pass through without attenuation. Therefore, the common-mode winding can effectively suppress carrier communication signals in a bus circuit while having no effect on the DC power supply signal transmitted in the bus circuit.

[0047] See Figure 3. Optionally, in the embodiment of the present application, a resistor R20 may be connected in series between the common mode winding L and the terminal 1 of the port 01 between the terminal 4. The resistor is configured to prevent the bus circuit from being too large and to balance the current when multiple masters are powering slaves.

[0048] It can be understood that when the power signal in the embodiment of the present application adopts a low-frequency AC power signal, the relevant parameters of the common-mode winding can be adjusted so that the low-frequency AC power signal can pass through, but the high-frequency non-polarity carrier communication signal in the non-polarity carrier element circuit needs to be isolated to prevent the non-polarity carrier communication signal from being distorted.

[0049] Optionally, the non-polarity carrier communication circuit in the embodiment of the present application may include: a non-polarity carrier communication chip, wherein the transmission end of the non-polarity carrier communication chip may include: a first pin and a second pin; the first pin of the non-polarity carrier communication chip is connected to the fourth input end of the second anti-interference circuit; and the second pin of the non-polarity carrier communication chip is connected to the fifth input end of the second anti-interference circuit.

[0050] See Figure 3. The non-polarity carrier communication circuit in the embodiment of the present application can adopt a non-polarity carrier communication chip 02 based on RS485. The non-polarity carrier communication chip 02 may include: pin RO, pin Pin FS, pin DI, pin GND, first pin A, second pin B, and pin VCC. Among them, pin RO is the digital signal output terminal 485_RX, which enables the pin It is the mode selection terminal, that is, the transmit / receive mode selection. When the enable terminal 485_EN input is low, the chip is in receive mode, and when the input is high, the chip is in transmit mode. Pin FS is configured to select the carrier frequency. Specifically, the frequency can be selected using the grounded resistor R17. Pin DI is the digital signal input terminal 485_TX, pin GND is grounded, the first pin A is the first transmission terminal, the second pin B is the second transmission terminal, and pin VCC is connected to the third voltage source V3 (for example, a 3.3V-5V power supply). The non-polar carrier communication chip 02 operates in half-duplex communication mode, that is, only one node on the bus can be in the transmitting state at the same time, and the other nodes are in the receiving state.

[0051] Optionally, a resistor R14 is provided between the pin RO of the RS485 non-polarity carrier communication chip and the UART serial port of the MCU, and a grounding capacitor C8 is provided between the resistor R14 and the UART serial port of the MCU. A ground resistor R16 is provided between the MCU and the UART serial port. A resistor R18 is provided between pin DI and the UART serial port. A capacitor C6 is provided between the third voltage source and the ground.

[0052] Specifically, the signal input terminal 485_TX, signal output terminal 485_RX, and enable terminal 485_EN of the RS485-based non-polarity carrier communication chip are connected to the universal asynchronous receiver / transmitter UART serial port of the microcontroller unit (MCU) to solve the need to change the protocol of carrier communications such as home bus and KNX through the MCU, as well as the physical connection and level logic communication between the RS485-based non-polarity carrier communication chip 02.

[0053] It is understood that when the master device sends a control signal to the slave device, the RS485-based non-polarity carrier communication chip 02 can be used to convert the received logic level signal TTL into a first non-polarity carrier communication signal and a second non-polarity carrier communication signal. Specifically, the input terminal 485-TX of the non-polarity carrier communication chip 02 is not affected by the polarity of the first pin A and the second pin B. Instead, the data comparator in the non-polarity carrier communication chip 02 detects amplitude changes in the input signal and outputs the corresponding first non-polarity carrier communication signal and the second non-polarity carrier communication signal.

[0054] Optionally, when feedback information is sent from the slave device to the master device, the first pin A and the second pin B of the RS485-based non-polar carrier communication chip 02 in the embodiment of the present application can receive the feedback information sent by the slave device, and after further processing the feedback information, output the logic level signal TTL to the MCU of the master device through the output terminal 485-RX of the non-polar carrier communication chip 02.

[0055] Optionally, the second anti-interference circuit in the embodiment of the present application may include: a first capacitor and a second capacitor. One end of the first capacitor is connected to the first pin of the non-polar carrier communication chip, and the other end of the first capacitor is respectively connected to the first transmission end of the first anti-interference circuit and the first terminal of the port. One end of the second capacitor is connected to the second pin of the non-polar carrier communication chip, and the other end of the second capacitor is respectively connected to the second transmission end of the first anti-interference circuit and the second terminal of the port.

[0056] Optionally, the first capacitor and the second capacitor used in the second anti-interference circuit in the embodiment of the present application can be high-frequency capacitors with a frequency of several thousand hertz or more, so as to effectively filter out the power supply signal in the bus and the DC signal of the pin VCC that may be carried in the first non-polarity carrier signal and the second non-polarity carrier signal output by the transmission end of the non-polarity carrier communication chip.

[0057] See Figure 3. In the embodiment of the present application, the first pin A of the RS485-based non-polarity carrier communication chip 02 can be connected to one end of the coupling capacitor C7 via a resettable fuse F2, and the other end of the coupling capacitor C7 is connected to terminal 1 of port 01 via a positive bus. The second pin B of the RS485-based non-polarity carrier communication chip 02 can be connected to one end of the coupling capacitor C5 via a resettable fuse F1, and the other end of the second capacitor C5 is connected to terminal 2 of port 01 via a negative bus.

[0058] Optionally, the power control circuit in an embodiment of the present application may include: a first transistor, a second transistor, a field-effect transistor, and a first voltage source. The base of the first transistor receives a first control signal, the emitter of the first transistor is grounded, the collector of the first transistor is connected to the base of the second transistor, the emitter of the second transistor is connected to the first voltage source, the collector of the second transistor is connected to the gate of the field-effect transistor, one end of a negative bus is connected to the drain of the field-effect transistor, and the source of the field-effect transistor is grounded.

[0059] See Figure 3. In the embodiment of the present application, the first transistor Q3 of the power control circuit can be an NPN transistor, and the second transistor Q1 can be a PNP transistor to control the field effect MOS transistor Q5. The base of the first transistor Q3 can be controlled by the pin of the MCU. When the base of the first transistor Q3 is at a low level, the first transistor Q3 is in the off state, the base of the second transistor Q1 is at a high level, the second transistor Q1 is in the off state, the gate of the MOS transistor Q5 is at a low level, and the MOS transistor is not conducting. When the pin of the MCU outputs a high level to the base of the first transistor Q3, the first transistor Q3 is conducting, and when the base of the second transistor Q1 is at a low level, the second transistor Q1 is conducting, the gate of the MOS transistor is at a high level of the first voltage source V1, the MOS transistor Q5 is conducting, and the bus circuit is conducting.

[0060] Optionally, the first voltage source V1 in the embodiment of the present application is 12V.

[0061] Optionally, an IO pin of the MCU can control the base of the first transistor Q3. The first transistor Q3 can be a conventional transistor or a DT-type transistor. A resistor can be added between the base of the first transistor Q3 and ground, a pull-down resistor can be added between the base and emitter of the first transistor Q3, and a pull-down resistor can also be added between the base and emitter of the second transistor Q1, eliminating the need for external resistors for circuit discharge.

[0062] See Figure 3. A voltage regulator diode Z1 can be placed between the gate and source of MOS transistor Q5 to stabilize the voltage between them. A transient voltage suppressor diode TVS1 is placed between the source and drain of MOS transistor Q5 to provide overvoltage protection. The source of MOS transistor Q5 is connected to current sense resistor R9 and a resistor network (R10, R11, R12, and R13), with the other end of the resistor network connected to ground. The other end of resistor R9 is connected to the sampling terminal of the MCU's analog-to-digital converter (ADC). Capacitor C4 is connected in parallel between resistor R9 and ground (GND).

[0063] Furthermore, the power control circuit in the embodiment of the present application may also include: an overcurrent detection unit; the overcurrent detection unit is connected to the other end of the negative bus; the overcurrent detection unit is configured to detect the current value in the negative bus; when the current value in the negative bus is greater than the current threshold, the first transistor is controlled to be turned off through the first control signal to turn off the bus circuit.

[0064] See Figure 3. The overcurrent detection unit in the embodiment of the present application may use a resistor R9, and after collecting the voltage signal at the POC_AD terminal, calculate the current value in the bus circuit using the formula U=I×R.

[0065] Specifically, the power control circuit in the embodiment of the present application can achieve the following functions:

[0066] 1. Overcurrent protection: Overcurrent detection of the bus circuit is achieved by setting an overcurrent detection resistor in the power control circuit;

[0067] Assuming the bus circuit draws a maximum current of 0.5A during normal operation and the resistor used to measure overvoltage protection is 1.2Ω, the overcurrent protection voltage can be set to 0.5A*1.2=0.6V via software, which corresponds to an ADC sampling value of 0.6V in the circuit. A delay of 5s sets the first control signal to a low level for line protection. After 10s of protection, the first control signal is controlled to a high level to re-check the bus circuit current. If the sampling voltage is less than 0.6V, the first control signal can be maintained at a high level to ensure normal power supply to the bus circuit.

[0068] 2. Short circuit protection: achieved by detecting the current in the bus;

[0069] For example, assuming the short-circuit current threshold is 1A, when the current in the bus is greater than or equal to 1A, the second transistor Q1 can be turned off by directly turning off the first transistor Q3 through hardware (for example, setting a short-circuit protection button outside the master device), so that the bus circuit stops operating;

[0070] 3. Bus circuit reverse voltage protection:

[0071] When STATUS=1 (the first control signal is at a high level), it indicates that there is no voltage in the bus or there is a positive voltage and the power supply can be normal;

[0072] When STATUS=0 (the first control signal is at a low level), it indicates that a reverse voltage exists in the bus and the bus circuit needs to be shut down.

[0073] Optionally, the power control circuit of the bus circuit in the embodiment of the present application may include: a first transistor, a second transistor, a push-pull circuit, a field effect transistor, and a first voltage source.

[0074] Among them, the push-pull circuit may include: a sixth input terminal, a seventh input terminal, and an output terminal; the base of the first transistor receives the first control signal, the emitter of the first transistor is grounded, the collector of the first transistor is connected to the base of the second transistor, the collector of the second transistor is connected to the sixth input terminal of the push-pull circuit, the output terminal of the push-pull circuit is connected to the gate of the field effect transistor, one end of the negative bus is connected to the drain of the field effect transistor, the source of the field effect transistor is grounded, and the first voltage source is respectively connected to the emitter of the second transistor and the seventh input terminal of the push-pull circuit.

[0075] It is understandable that the second transistor Q1 in FIG3 is in a high impedance state (ie, open circuit state) when turned off, which means that the gate of the MOS transistor Q5 in FIG3 cannot be guaranteed to be reliably turned off, that is, the voltage at the gate end cannot be guaranteed to be 0.

[0076] Therefore, the embodiment of the present application adopts a push-pull circuit to control the MOS transistor Q5, and outputs a high or low level control signal to the sixth input terminal of the push-pull circuit through the conduction and shutdown of the second transistor Q1, thereby controlling the conduction and shutdown of the MOS transistor Q5 through the push-pull circuit to control the MOS transistor Q5 to be reliably turned on and off.

[0077] Optionally, the push-pull circuit in the embodiment of the present application may include: a third transistor and a fourth transistor; the base of the third transistor and the base of the fourth transistor are both connected to the collector of the second transistor, the collector of the third transistor is connected to the first voltage source, the collector of the fourth transistor is grounded, and the emitter of the third transistor and the emitter of the fourth transistor are both connected to the gate of the field effect transistor.

[0078] Referring to the schematic diagram of the internal structure of the bus circuit shown in FIG4 , the push-pull circuit may include an NPN transistor Q2 and a PNP transistor Q4. The bases of transistors Q2 and Q4 are both connected to the collector of a second PNP transistor Q1. The collector of transistor Q2 is connected to a first voltage source. The collector of transistor Q4 is grounded. The emitters of transistors Q2 and Q4 are both connected to the gate of MOS transistor Q5.

[0079] It can be understood that when a high-level signal is input to the POC_EN terminal, the base of the first transistor Q3 is at a high level, the first transistor Q3 is turned on, so that the base of the second transistor Q1 is at a low level, the second transistor Q1 is turned on, so that the bases of the transistors Q2 and Q4 in the push-pull circuit are at a high level, the transistor Q2 is turned on, the transistor Q4 is turned off, the gate of the MOS transistor Q5 is at a high level, and the MOS transistor Q5 is turned on.

[0080] When a low-level signal is input to the POC_EN terminal, the base of the first transistor Q3 is at a low level, and the transistor Q3 is turned off, so that the base of the first transistor Q1 is at a high level, and the first transistor Q1 is turned off. Since the bases of the transistors Q2 and Q4 in the push-pull circuit are grounded and at a low level, the transistor Q2 is turned off and the transistor Q4 is turned on, so that the output terminal of the push-pull circuit is grounded, and the gate of the MOS transistor Q5 is at a low level, which can ensure that the MOS transistor Q5 is reliably disconnected.

[0081] Furthermore, the non-polarity carrier communication circuit in the embodiment of the present application may further include: a first anti-interference module, the first anti-interference module including: an eighth input terminal, a ninth input terminal, a fifth output terminal, and a sixth output terminal. The eighth input terminal of the first anti-interference module is connected to the first pin of the non-polarity carrier communication chip, the ninth input terminal of the first anti-interference module is connected to the second pin of the non-polarity carrier communication chip, the fifth output terminal of the first anti-interference module is connected to one end of the first capacitor, and the sixth output terminal of the first anti-interference module is connected to one end of the second capacitor; the first anti-interference module is configured to isolate surge signals generated by lightning.

[0082] Optionally, the first anti-interference module in the embodiment of the present application may adopt an isolation transformer.

[0083] Furthermore, the bus circuit in the embodiment of the present application can isolate the first non-polarity carrier signal and the second non-polarity carrier signal through an isolation transformer based on the push-pull circuit, and the output side of the isolation transformer is respectively connected to the first coupling capacitor and the second coupling capacitor.

[0084] Refer to the schematic diagram of the bus circuit structure shown in Figure 5. The first pin A and the second pin B of the non-polar carrier communication chip 02 are connected to one end of the transient voltage suppressor tube TVS2 and the transient voltage suppressor tube TVS3, respectively. The other ends of TVS2 and TVS3 are grounded. R15 (resistance 100-120Ω) is connected between the first pin A and the second pin B. The first pin A and the second pin B are connected to one end of the resettable fuse F1 and the resettable fuse F2, respectively. The other ends of the resettable fuse F1 and the resettable fuse F2 are connected to pins 1 and 4 of the isolation transformer T1. Pins 2 and 3 of the isolation transformer T1 are short-circuited and grounded through a capacitor. Pins 6 and 7 on the output side of the isolation transformer T1 are grounded through a capacitor. Pins 5 and 8 of the isolation transformer T1 are connected to one end of capacitors C5 and C7, respectively. The other ends of capacitors C5 and C7 are connected to port 01.

[0085] Furthermore, the non-polar carrier communication circuit in the embodiment of the present application also includes: a second anti-interference module, the second anti-interference module includes: a tenth input terminal, a seventh output terminal, and an eighth output terminal; the tenth input terminal of the second anti-interference module receives the second control signal, the seventh output terminal of the second anti-interference module is connected to the first pin of the non-polar carrier communication chip, and the eighth output terminal of the second anti-interference module is connected to the second pin of the non-polar carrier communication chip.

[0086] In which, the second control signal is configured to control the operation of the second anti-interference module. When the distance between the bus circuit and the device connected to the port is greater than the distance threshold, the second control signal is at a high level, and the second anti-interference module works; when the distance between the bus circuit and the device connected to the port is less than or equal to the distance threshold, the second control signal is at a low level, and the second anti-interference module stops working; the second anti-interference module is configured to isolate the reflected voltage generated between the bus circuit and the device connected to the port.

[0087] Optionally, the second anti-interference module in the embodiment of the present application may adopt a solid-state relay.

[0088] It is understood that when the line distance between the master and slave devices is too long, there may be interference from reflected voltage on the line, which in turn disrupts the transmitted waveform carrier signal. Therefore, when the line distance between the master and slave devices exceeds a threshold, a high level can be input to the input terminal of the second anti-interference module; when it does not exceed the threshold, a low level is input.

[0089] See Figure 6 for a schematic diagram of the internal structure of the bus circuit. Pin 1 of solid-state relay IC2 is connected to pin B of RS485-based non-polarity carrier communication chip 02 via resistor R15. Pin 2 of solid-state relay IC2 is connected to pin A of RS485-based non-polarity carrier communication chip 02. Pin 3 of solid-state relay IC2 is connected to power supply VCC1 via resistor R19. Pin 4 of solid-state relay IC2 serves as the second control signal input. Assuming a distance threshold of 50 meters, when the distance between the master and slave devices is greater than 50 meters, the second control signal is high, and solid-state relay IC2 operates. When the distance between the master and slave devices is less than or equal to 50 meters, the second control signal is low, and solid-state relay IC2 stops operating.

[0090] The embodiments described above are merely optional embodiments of the present application and are not intended to limit the scope of the present application. Without departing from the design concept of the present application, various modifications and improvements made to the technical solutions of the present application by ordinary technicians in this field should fall within the scope of protection determined by the claims of the present application.

Claims

1. A bus circuit, wherein: The bus circuit includes: a power interface, a power control circuit, a polarity-free carrier communication circuit, a positive bus, a negative bus, a first anti-interference circuit, a second anti-interference circuit, and a port, wherein: The non-polar carrier communication circuit includes: a first input end, a first transmission end, and a second transmission end; the first anti-interference circuit includes: a second input end, a third input end, a first output end, and a second output end; the second anti-interference circuit includes: a fourth input end, a fifth input end, a third output end, and a fourth output end; the port includes: a first terminal and a second terminal, wherein, One end of the positive bus is connected to the power interface, the other end of the positive bus is connected to the second input end of the first anti-interference circuit, the first output end of the first anti-interference circuit is respectively connected to the first terminal of the port and the third output end of the second anti-interference circuit, and the fourth input end of the second anti-interference circuit is connected to the first transmission end of the non-polarity carrier communication circuit; one end of the negative bus is grounded via the power control circuit, the other end of the negative bus is connected to the third input end of the first anti-interference circuit, the second output end of the first anti-interference circuit is respectively connected to the second terminal of the port and the fourth output end of the second anti-interference circuit, and the fifth input end of the second anti-interference circuit is connected to the second transmission end of the non-polarity carrier communication circuit; The power interface is configured to receive a power signal; The power control circuit is configured to control the on and off of the bus circuit according to the received first control signal; The first input terminal of the non-polarity carrier communication circuit is configured to receive a logic level signal, the first transmission terminal of the non-polarity carrier communication circuit is configured to output a first non-polarity carrier communication signal, and the second transmission terminal of the non-polarity carrier communication circuit is configured to output a second non-polarity carrier communication signal; The first anti-interference circuit is configured to isolate the first non-polarity carrier communication signal and the second non-polarity carrier communication signal output by the non-polarity carrier communication circuit, and input the power signal in the positive bus into the first terminal of the port and the power signal in the negative bus into the second terminal of the port; The second anti-interference circuit is configured to isolate the power supply signal, and load the received first non-polarity carrier communication signal into the positive bus containing the power supply signal, and load the received second non-polarity carrier communication signal into the negative bus containing the power supply signal.

2. The bus circuit according to claim 1, wherein: The bus circuit also includes: a power polarity detection circuit; The input end of the power polarity detection circuit is connected to the negative bus, and the output end of the power polarity detection circuit is connected to the positive bus; The power polarity detection circuit is configured to detect the positive and negative poles of the DC power supply connected to the power interface.

3. The bus circuit according to claim 1, wherein: The first anti-interference circuit comprises: a common mode winding, the common mode winding comprises: a first winding and a second winding, the first winding comprises: a third terminal and a fourth terminal, the second winding comprises: a fifth terminal and a sixth terminal, wherein the third terminal and the fifth terminal are terminals of the same name; The other end of the positive bus is connected to the fifth terminal of the second winding, and the sixth terminal of the second winding is connected to the third output terminal of the second anti-interference circuit and the first terminal of the port; the other end of the negative bus is connected to the fourth terminal of the first winding, and the third terminal of the first winding is connected to the fourth output terminal of the second anti-interference circuit and the second terminal of the port.

4. The bus circuit according to claim 1, wherein: The non-polarity carrier communication circuit comprises: a non-polarity carrier communication chip, and the transmission end of the non-polarity carrier communication chip comprises: a first pin and a second pin; The first pin of the non-polarity carrier communication chip is connected to the fourth input terminal of the second anti-interference circuit; The second pin of the non-polarity carrier communication chip is connected to the fifth input terminal of the second anti-interference circuit.

5. The bus circuit according to claim 4, wherein: The second anti-interference circuit includes: a first capacitor and a second capacitor; One end of the first capacitor is connected to the first pin of the non-polar carrier communication chip, and the other end of the first capacitor is connected to the first output end of the first anti-interference circuit and the first terminal of the port respectively; One end of the second capacitor is connected to the second pin of the non-polar carrier communication chip, and the other end of the second capacitor is connected to the second output end of the first anti-interference circuit and the second terminal of the port respectively.

6. The bus circuit according to claim 1, wherein: The power control circuit comprises: a first triode, a second triode, a field effect transistor, and a first voltage source; The base of the first transistor receives the first control signal, the emitter of the first transistor is grounded, the collector of the first transistor is connected to the base of the second transistor, the emitter of the second transistor is connected to the first voltage source, the collector of the second transistor is connected to the gate of the field effect transistor, one end of the negative bus is connected to the drain of the field effect transistor, and the source of the field effect transistor is grounded.

7. The bus circuit according to claim 1, wherein: The power control circuit includes: a first triode, a second triode, a push-pull circuit, a field effect transistor, and a first voltage source; wherein the push-pull circuit includes: a sixth input terminal, a seventh input terminal, and an output terminal; The base of the first transistor receives the first control signal, the emitter of the first transistor is grounded, the collector of the first transistor is connected to the base of the second transistor, the collector of the second transistor is connected to the sixth input terminal of the push-pull circuit, the output terminal of the push-pull circuit is connected to the gate of the field effect transistor, one end of the negative bus is connected to the drain of the field effect transistor, the source of the field effect transistor is grounded, and the first voltage source is respectively connected to the emitter of the second transistor and the seventh input terminal of the push-pull circuit.

8. The bus circuit as claimed in claim 7, wherein: The push-pull circuit comprises: a third triode and a fourth triode; The base of the third transistor and the base of the fourth transistor are both connected to the collector of the second transistor, the collector of the third transistor is connected to the first voltage source, the collector of the fourth transistor is grounded, and the emitter of the third transistor and the emitter of the fourth transistor are both connected to the gate of the field effect transistor.

9. The bus circuit as claimed in claim 5, wherein: The non-polarity carrier communication circuit further includes: a first anti-interference module, the first anti-interference module including: an eighth input terminal, a ninth input terminal, a fifth output terminal, and a sixth output terminal; The eighth input end of the first anti-interference module is connected to the first pin of the non-polar carrier communication chip, the ninth input end of the first anti-interference module is connected to the second pin of the non-polar carrier communication chip, the fifth output end of the first anti-interference module is connected to one end of the first capacitor, and the sixth output end of the first anti-interference module is connected to one end of the second capacitor; The first anti-interference module is configured to isolate surge signals generated by lightning.

10. The bus circuit according to claim 5 or 9, wherein: The non-polarity carrier communication circuit further includes: a second anti-interference module, the second anti-interference module includes: a tenth input terminal, a seventh output terminal, and an eighth output terminal; The tenth input terminal of the second anti-interference module receives the second control signal, the seventh output terminal of the second anti-interference module is connected to the first pin of the non-polarity carrier communication chip, and the eighth output terminal of the second anti-interference module is connected to the second pin of the non-polarity carrier communication chip; Wherein, the second control signal is configured to control the operation of the second anti-interference module, when the distance between the bus circuit and the device connected to the port is greater than a distance threshold, when the second control signal is at a high level, the second anti-interference module works, and when the distance between the bus circuit and the device connected to the port is less than or equal to the distance threshold, when the second control signal is at a low level, the second anti-interference module stops working; The second anti-interference module is configured to isolate a reflected voltage generated between the bus circuit and a device connected to the port.

11. The bus circuit according to claim 6, wherein: The power supply control circuit further includes: an overcurrent detection unit; the overcurrent detection unit is connected to the other end of the negative bus; The overcurrent detection unit is configured to detect a current value in the negative bus; When the current value in the negative bus is greater than the current threshold, the first transistor is controlled to be turned off by the first control signal, so that the bus circuit is turned off.

12. An electronic device, wherein: include: A bus circuit as claimed in any one of claims 1 to 11.

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