Double superlattices obtained by layer transfer, structure and production method

Abstract

The invention relates to a method (500) for producing a structure comprising a stack of superlattices, comprising the steps of forming (510Car) a first superlattice (Stck1) on a first substrate; forming (520Don) a seed layer (Init) of a second superlattice (Stck2) on a second substrate; forming (550Don) a weakening plane (Imp) in the second substrate; assembling (560) the seed layer (Init) on the first superlattice (Stck1) at a dielectric separation layer that separates the first superlattice (Stck1) and the seed layer (Init) and keeps them attached to each other; removing (570A) a portion of the second substrate by fracturing the second substrate at the weakening plane (Imp) after the assembly step (560); exposing (570B) the seed layer (Init) after the step (570A) of fracturing the second substrate; and forming (580) the second superlattice (Stck2) on the exposed seed layer (Init).

Description

DOUBLE SUPERNETWORKS OBTAINED BY LAYER TRANSFER, STRUCTURE AND MANUFACTURING METHOD TECHNICAL FIELD OF THE INVENTION

[0001] The invention relates generally to superlattices, consisting of at least one periodic stack of thin layers, and particularly to superlattices including layers of semiconductor materials. More particularly, the invention relates to double superlattices. TECHNOLOGICAL BACKGROUND

[0002] Superlattices have attracted attention for their mechanical and semiconducting properties, and for the possibility they offer of forming quantum dots.

[0003] They are also used for the development of so-called nanosheet transistors, also known as Nanosheet transistors or GAAFET for Gate-all-around Field-Effect Transistors in English terminology, whose conduction channels are formed by a stack of layers of nanometric thickness each surrounded by a gate metal, as described in US patents 10,249,739 B2 and US 11,018,222 B1. These are semiconductor structures with an enveloping gate, or GAA for Gate-All-Around in English terminology.

[0004] This principle has been adopted to form so-called CFET transistors, for Complementary Field Effect Transistor in English terminology, presenting a three-dimensional structure formed using a pair of stacked superlattices: a first superlattice formed on a substrate is used to form an n-type transistor while a second superlattice formed on the first superlattice is used to form a p-type transistor, or vice versa. This three-dimensional structure is advantageous in terms of integration compared to conventional approaches used to implement CMOS technology, which usually employs p-type transistors and n-type transistors fabricated side-by-side in the same plane.In particular, the CFET approach makes it possible in principle to halve the size of a pair of p- and n-type transistors, or to shorten the connections between the two transistors and therefore to reduce the electrical resistance of the corresponding connections. This approach is described for example in documents US 2019 / 0319095 A1, US 2021 / 0104523 A1, and US 2023 / 0326925 A1.

[0005] Whether it is Nanosheet transistors or CFET transistors, the manufacturing processes considered involve the fabrication of superlattices comprising stacks of two alternating types of materials: one is intended to form the channel regions of the transistors, the other to form sacrificial layers intended to be removed to be replaced by a gate dielectric and gate metal structure during the fabrication of the transistors.

[0006] Document US 2021 / 082901 A1 discloses a method of fabricating high-density memories and logic circuits, including superlattice stacking.

[0007] Document US 2023 / 197721 A1 discloses a method of manufacturing stacked transistors.

[0008] Document WO 20181 / 30781 A1 discloses a method of manufacturing an image sensor.

[0009] Manufacturing CFET transistors requires stacking two types of transistors, n-type and p-type, on top of each other. Two approaches are possible.

[0010] The first approach is called "sequential", in the sense that the transistors of the two types are formed sequentially, during separate steps. In this approach, a semiconductor structure made of silicon or other semiconductor material, or a superlattice intended to form second Nanosheet transistors, is transferred onto a semiconductor substrate already carrying, for example, first Nanosheet transistors. In a first step, the first transistors are formed on the substrate, then the semiconductor structure is transferred onto it, in which the second transistors are then formed. The thermal budget for the process of transferring the semiconductor structure and for the formation of the second transistors is limited by the need not to degrade the first transistors.Furthermore, the alignment control of the second transistors with the first transistors must be extremely strict and specific electrical contact structures between the two stages must be provided.

[0011] The second approach is called "monolithic", in the sense that the first and second transistors are formed on the same substrate, at least part of the manufacturing steps being applied simultaneously to all of the layers in which the first and second transistors are formed. Reference may be made to document US 2019 / 0319095 A1. One of the main advantages of this approach is the self-alignment of the second transistors on the first transistors, which allows a higher density of transistors on the substrate, and reduces parasitic capacitances and resistances between the first and second transistors.

[0012] The monolithic approach requires thicker superlattices as the starting structure than the sequential approach, since these superlattices form the basic structure of two stacked transistors fabricated simultaneously. Superlattices are generally fabricated epitaxially. However, the number of stackable layers for the formation of these superlattices is limited by the critical epitaxy thickness, a thickness beyond which the quality of the deposited layers degrades due to elastic relaxation and / or plastic relaxation phenomena. The monolithic approach is close to and could require exceeding the critical epitaxy thickness.

[0013] Furthermore, the monolithic approach is technologically more complex to implement than the sequential approach, in particular for the formation of a dielectric separation layer between the first transistors and the second transistors. This favors the integration of the internal spaces of the structure and the formation of the metal layers for the sources and drains of the transistors. The vertical distance between the first transistors and the second transistors can be reduced to the thickness of the dielectric layer, with positive effects on the reduction of parasitic capacitances and resistances between the first and second transistors. However, obtaining such a dielectric layer requires a complex procedure and the use of a sacrificial layer removed to leave space for the dielectric layer.This sacrificial layer associated with the dielectric separation layer must be compatible with a sacrificial layer intended to form a space for receiving the dielectric and gate metal layers. Thus, the two sacrificial layers used must be able to be selectively attacked with respect to each other and with respect to the semiconductor material forming the conduction channel of the transistors. For example, silicon is used for the channel, and silicon alloyed with different percentages of germanium for the sacrificial layers. From a technical point of view, although such structures can be used, obtaining them remains complex and delicate.

[0014] One approach is to form two superlattices independently of each other on two separate substrates and then transfer one of them onto the other using a layer transfer technology such as the so-called "Smart-Cut" method. A possible implementation of this approach is to (a) form an embrittlement plane within one of the two substrates by ion implantation of light species through the superlattice formed on this substrate, (b) assemble the two superlattices to each other using a direct contact bonding process such as molecular bonding, and then (c) fracture the implanted substrate at the embrittlement layer. A disadvantage of this approach is that it generally requires at least one heat treatment to heal the transferred layers damaged by the transfer process, including the ion implantation step.This heat treatment has a negative influence on superlattices due to the fact that it causes the diffusion of germanium ions into silicon.

[0015] Thus, there is a need for a method of manufacturing superlattices or an assembly of superlattices making it possible to exceed the critical epitaxy thickness, while limiting the damage inflicted by the method on the layers forming the superlattices.

[0016] The applicant's objective is to provide a method for manufacturing a structure capable of facilitating the integration and production of Nanosheet transistors, and more specifically CFET transistors, i.e. p-type transistors and stacked n-type transistors. This manufacturing method must preferably be particularly suited to the monolithic approach to the manufacture of CFET transistors.

[0017] To achieve this aim, one aspect of the invention is a method of manufacturing a structure comprising a stack of superlattices, the method comprising the steps of forming a first superlattice on a first substrate, by stacking a plurality of first channel layers alternating with a plurality of first sacrificial layers; forming a seed layer of a second superlattice by adding material to a second substrate; forming a weakening plane of the second substrate by implanting ions of a light species into the second substrate; forming an assembly by assembling the seed layer to the first superlattice at a dielectric separation layer which separates and keeps the first superlattice and the seed layer fixed to each other;removing a first portion of the second substrate by fracturing the second substrate at the weakening plane, and removing this portion of the second substrate, after the assembly step; releasing the primer layer after the fracturing step of the second substrate in such a way that the released primer layer forms an outer face of the assembly, the release step including the removal of a second portion (Don; a ) of the second substrate which remained assembled to the seed layer after the step of removing the first part of the second substrate; and forming the second superlattice on and in direct contact with the outer face of the released seed layer, by stacking a plurality of second channel layers alternating with a plurality of second sacrificial layers.

[0018] A first advantage of the process is to provide a stack of superlattices which can be either identical or distinct in composition and / or orientation.

[0019] A second advantage of the process is the possibility of exceeding the critical epitaxy thickness for the structures obtained, which limits the number and thickness of layers that can be epitaxied on top of each other without losing quality in the crystalline structures of these layers.

[0020] A third advantage of the method lies in the provision within the stack of a separation layer between two superlattices, this layer being able to have structural characteristics incompatible with conventional methods of forming superlattices. Indeed, superlattices are conventionally formed by successive depositions of layers by epitaxy. However, with the present method, the separation layer can be made of a dielectric such as a nitride or an oxide which can be amorphous, incompatible with the formation by epitaxy of semiconductor layers of good crystalline quality on the surface of this amorphous layer: deposition by epitaxy requires on the contrary a crystalline base layer.The present invention thus makes it possible to use any type of dielectric, for example SiN, SiCN, or even SiO2, which can be chosen according to its own dielectric characteristics and its compatibility with the steps planned for the manufacture of transistors based on the stacking of super networks.

[0021] A fourth advantage of the method is a comparative advantage over an approach that would involve transferring the second superlattice from a substrate on which it would be independently formed to the first lattice by the Smart-Cut method. In such a situation, a healing heat treatment of the transferred layer may be necessary, but is not required in the present method. Thus, the present method limits the potential negative impacts of a heat treatment on the superlattices and / or an accompanying structure.

[0022] A fifth advantage arises from the intended applications for this superlattice stack, which is the formation of CFET transistors. The dielectric separation layer can be configured to perform an electrical isolation function between the stacked transistors, but also serve as etch stop layers for differentiated processing between transistors or the integration of such structures on the backside of the carrier substrate.

[0023] Thus, the manufacturing method according to the invention is suitable for the production of structures which can serve as the basis for a monolithic method for producing an electronic circuit integrating CFET transistors.

[0024] According to additional non-limiting characteristics of the method according to the invention, considered individually or according to any technically feasible combination:

[0025] - the embrittlement plane of the second substrate is formed by implantation of ions of a light species into the second substrate through the primer layer;

[0026] - the separation layer can be continuously formed in a plane parallel to a surface of the first substrate on which the first superlattice is formed;

[0027] - the first channel layers and the second channel layers may each be formed of a semiconductor material, and the first sacrificial layers and the second sacrificial layers may each be formed of a material capable of exhibiting a faster etch rate than the first channel layers and the second channel layers, respectively;

[0028] - the first channel layers and the second channel layers may each be formed of silicon, and the first sacrificial layers and the second sacrificial layers may each be formed of an alloy of silicon and germanium;

[0029] - the method may comprise the steps of: forming a first covering layer of the first superlattice before the attaching step; and, forming a second covering layer of the primer layer before the attaching step; wherein the attaching step comprises contacting the first covering layer with the second covering layer, the first covering layer and the second covering layer together forming the separation layer;

[0030] - the first capping layer and the second capping layer may each comprise silicon and at least one of the first capping layer and the second capping layer may be formed of an oxide;

[0031] - at least one of the first covering layer and the second covering layer formed of an oxide can be formed by a step of forming a silicon layer followed by a step of oxidizing this silicon layer;

[0032] - the method may further comprise a step of forming at least one etch stop layer on the second substrate before forming the primer layer, the etch stop layer being removed during the step of removing the primer layer;

[0033] - the at least one etch stop layer may be formed from a layer of the same material as the second sacrificial layers and a layer of the same material as the second channel layers, the layer of the same material as the second sacrificial layers and the layer of the same material as the second channel layers being removed during the step of removing the primer layer. BRIEF DESCRIPTION OF THE FIGURES

[0034] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows with reference to the appended figures in which:

[0035] Illustrates a manufacturing method according to the invention;

[0036] Illustrates a continuation of the process of the;

[0037] Illustrates variants of structures that can be obtained by the process of figures 1 and 2;

[0038] Illustrates variations of the separation layers of the ; and

[0039] This is a diagram summarizing the manufacturing process of Figures 1 and 2. DETAILED DESCRIPTION OF THE INVENTION

[0040] Method of implementation

[0041] An embodiment of the present invention is described by means of Figures 1 to 5 and the associated description below.

[0042] Illustrates in (A) a Strc structure formed from a carrier substrate Car, a first superlattice Stck1, a separating layer Sep, and a second superlattice Stck2, stacked in this order. The first superlattice Stck1 comprises a plurality of first layers Ch1 stacked alternately with a plurality of first layers Sac1, preferably such that each first layer Ch1 is interposed between and in direct contact with two of the first layers Sac1. The second superlattice Stck2 comprises a plurality of second layers Ch2 stacked alternately with a plurality of second layers Sac2, preferably such that each second layer Ch2 is interposed between and in direct contact with two of the second layers Sac2.

[0043] The first Ch1 layers and the second Ch2 layers are layers formed of at least one semiconductor material for forming channel regions of transistors and may be referred to as the first channel Ch1 layers and the second channel Ch2 layers, respectively. These channel layers may be formed of the same material, or of different materials.

[0044] The first Sac1 layers and the second Sac2 layers are layers formed from at least one material capable of exhibiting faster etching rates than the first Ch1 layers and the second Ch2 layers, and may be referred to as the first sacrificial Sac1 layers and the second sacrificial Sac2 layers, respectively. These sacrificial layers may be formed from the same material, or from different materials. In particular, the Sac1 layers may have a Si composition 1-X Ge xand Sac2 layers can have a Si composition 1-y Ge y where x and y represent the proportions of germanium in the Sac1 and Sac2 layers, respectively, with x being different from or equal to y. These Sac1 and Sac2 layers of SiGe alloy can be associated with Ch1 and Ch2 layers of silicon, thanks to the compatibility of epitaxial growth of these two materials which have a fairly close lattice parameter. The proportions x and y are preferably less than 40%, for example between 15% and 35%.

[0045] The second layers Sac1 and Sac2 are intended to serve as sacrificial layers in a Nanosheet transistor formation procedure, during which the layers Sac1 and Sac2 are removed by etching, which may be chemical, so as to obtain a structure of floating ribbons formed by the layers Ch1 and Ch2. These floating ribbons will subsequently be surrounded by a gate dielectric layer and a gate metal so as to form Nanosheet transistors.

[0046] Figures 1, 2 and 5 illustrate a method 500 for manufacturing the Strc structure, which is advantageously based on the separate manufacturing of a first superlattice Stck1 and a primer layer Init of a second superlattice Stck2 on two respective substrates, then the transfer of the primer layer of the second superlattice Stck2 onto the first superlattice Stck1. The Strc structure is then completed by manufacturing the second superlattice Stack 2 by stacking successive layers on the primer Init. The diagram represents a diagram showing the steps of the manufacturing method 500.

[0047] Illustrates in (A) the formation of the first Stck1 supernetwork on a Car carrier substrate, during a step 510 Car . In this example, the carrier substrate Car consists of a monocrystalline silicon wafer.

[0048] On a surface S Carof the Car substrate, Ch1 layers of silicon Si 5 to 15 nm thick, preferably 7 to 10 nm thick, are grown by epitaxy, alternating with Sac1 layers of a first alloy of silicon and germanium of formula Si 1- x Ge x 5 to 10 nm thick, preferably 6 to 9 nm thick, and where x represents the percentage of germanium in the alloy, preferably starting and ending with a Sac1 layer. On the last Sac1 layer, during a step 520 Car, a covering layer Cap1, here formed of silicon Si and having the function of preventing the oxidation of the last layer Sac1. The layer Cap1 may have a thickness less than that of layers Sac1 and Ch1 forming the superlattice Stck1, this thickness preferably being between 1 and 2 nm. The advantage of limiting the thickness to these values ​​is to avoid having, subsequently, the formation of an additional silicon channel in a transistor formed on the basis of the stack of superlattices obtained.

[0049] Illustrates in (B) the formation of the primer layer Init and associated layers on a donor substrate Don, during steps 510 Don at 530 Don . In this example, the donor substrate Don consists of a monocrystalline silicon wafer.

[0050] On a surface S Donof the Don substrate, the primer layer Init is deposited, which is here a layer of the first alloy of silicon and germanium of formula Si 1-x Ge x 5 to 10 nm thick, preferably 6 to 9 nm thick, during a step 520 Don . On this Init layer, a covering layer Cap2, made of silicon, is formed during a step 530 Don. The Cap2 layer has the function of preventing the oxidation of the Init layer, and it is preferentially configured to be oxidized subsequently to form the bonding interface. The thickness of the Cap2 layer depends on the thickness of the future targeted oxidized layer. In other words, by aiming for an oxide layer with a thickness between 10 and 35 nm, the Cap2 layer in this case must have a thickness between approximately 4 and 16 nm. This Cap2 layer is optional, its interest depending on the ease of oxidizing of the material constituting the last layer of the second Stck2 superlattice and the interest in integrating it into a dielectric separation layer between the two superlattices.

[0051] Optionally, before the formation of the primer layer Init, a layer Stp of the first silicon and germanium alloy of formula Si can be formed on the donor substrate Don 1-x Ge xwith a thickness of between 5 and 10 nm, then a protective layer Cap2' of silicon with a thickness of between 1 and 5 nm, during a step 510 Don . These two layers are etch stop layers and are intended to protect the integrity of the Init primer layer during the fabrication steps following the fracture of the donor substrate described later and illustrated in (B) and (C) of the.

[0052] Illustrates in (C) an oxidation of the Cap2 layer of silicon Si to form a covering layer Ox2 of silicon oxide SiO2 of 10 to 35 nm thickness, during a step 540 Don oxidation. The Cap2 layer is preferably oxidized over its entire thickness, or almost, so as to avoid a layer of silicon remaining after etching the sacrificial layers.

[0053] The oxidation temperature and duration used are limited to avoid exceeding the authorized thermal budget to avoid or at least limit the diffusion of germanium from one layer to another of the superlattices, and in particular the contamination of the channel layers by germanium over their entire thicknesses.

[0054] Also illustrated in (C) is an implantation of light species such as hydrogen, helium, or a combination of such species into the donor substrate Don through the S layer Don , the primer layer Init and, where appropriate, the covering layer Ox2, so as to form a weakening plane Imp in the donor substrate Don, during a step 550 Don .

[0055] Following the formation of the embrittlement plane Imp, the donor substrate Don is turned over and the oxide layer Ox2 is brought into intimate contact with the silicon layer Cap1 and is assembled there, for example by molecular bonding or any other assembly technique by bringing into direct contact surfaces of elements to be assembled, so as to obtain the structure illustrated in (A) of the, during an assembly step 560. The structure obtained is designated as the assembly Ass. The separation layer Sep is formed at this step by bonding the last layers formed respectively on the carrier substrate Car and on the donor substrate Don, and corresponds to the assembly formed by the layers separating the first superlattice Stck1 and the second superlattice Stck2, the layers Cap1 and Ox2 in the present embodiment, as illustrated by the. This separation layer Sep preferably completely overlaps the donor substrate Don.Furthermore, the separation layer Sep is continuously formed in a plane parallel to the surface S. Car of the carrier substrate Car supporting the first superlattice Stck1. Even if the separation layer does not strictly overlap the entire carrier substrate Car, it is at least formed continuously over an area intended to form an assembly of semiconductor components such as transistors, possibly an assembly of CFET transistors.

[0056] At this stage of the manufacturing, the primer layer Init is sandwiched between the carrier substrate Car and the donor substrate Don. This primer layer Init must be released in order to make it accessible. This release operation 570 is carried out in two successive steps 570A and 570B. Step 570A here consists of removing the majority of the donor substrate while step 570B consists of releasing the primer layer Init by eliminating the remains of the donor substrate. The released primer layer Init forms an outer face F ext of the assembly Ass.

[0057] Illustrates in (B) the fracture of the donor substrate Don at the level of the embrittlement plane Imp obtained by ion implantation, so that a part Don b is removed from the structure shown in (A) while a part Don aremains fixed there, during the fracture and removal step 570A. This fracture can be obtained by heat treatment, possibly assisted by mechanical stress to initiate the fracture, according to conventional layer transfer techniques well known in the field of microelectronics.

[0058] Preferably, the carrier substrates Car and donor Don respectively comprising the first supernetwork Stck1 and the primer layer Init are substantially identical. This advantageously makes it easy to produce them on a large scale, thus facilitating their industrialization. Furthermore, the use of substantially identical carrier and donor substrates advantageously makes it possible to have a symmetrical assembled structure having similar thermal expansion coefficients, which advantageously avoids mechanical deformation problems following the bonding steps and future heat treatments.

[0059] Following assembly and fracture of the donor substrate, a heat treatment can be applied to consolidate the assembly and heal the assembled layers. The temperature and duration of the heat treatment are limited to avoid exceeding the authorized thermal budget to avoid or at least limit the diffusion of germanium from one layer to another of the superlattices, and in particular the contamination of the channel layers by germanium over their entire thicknesses. The heat treatment can typically consist of an annealing of 2 hours or less at a maximum temperature of 750°C, and preferably below 700°C.

[0060] An alternative to the formation of an embrittlement plane and the fracture of the Don donor substrate at this plane may be to thin the Don donor substrate after its assembly, for example by etching, grinding and / or chemical mechanical polishing (CMP). This thinning may be used to completely remove the second Don substrate if it is pushed, for example, up to the barrier layer Stp.

[0061] Illustrates in (C) the structure illustrated in (B) after it has been subjected to mechanical and / or chemical attacks to eliminate the Don part a of the donor substrate Don, the etch stop layer Stp, and the protective layer Cap2' during step 570B. Thus, the primer layer Init is released during this step, and accessible for the rest of the manufacturing process.

[0062] Then, the second superlattice Stck2 is formed. First, a possible native oxide is removed from the surface of the Init layer within a thin-film deposition frame, using the "in-situ" etching function available in a large number of epitaxy frames, for example by using HF gas. This operation makes it possible to clean the Init layer and guarantee the quality of its surface in order to ensure the quality of the growth of the layers deposited there. The second superlattice Stck2 is then formed directly on the seed layer Init, during an epitaxy step 580, and by epitaxial growth, of the Ch2 layers alternating with Sac2 layers. The operation of cleaning the Init layer prior to the layer depositions is conventional and is considered as part of the step of forming the Ch2 and Sac2 layers by epitaxy.Alternatively, other known cleaning methods could be considered, such as complete oxidation of the Cap2' layer and its removal by HF directly in the frame. The key is to obtain a clean, non-oxidized surface before proceeding with the deposition of thin layers on this surface, whether the deposition sequence is started with a Sac2 layer or a Ch2 layer.

[0063] The Ch2 layers are preferably made of silicon Si and have a thickness of 5 to 15 nm thick, preferably 7 to 10 nm thick, and the Sac2 layers are formed from the first alloy of silicon and germanium of formula Si 1-x Ge x, 5 to 10 nm thick, preferably 6 to 9 nm thick, preferably in such a way that each Ch2 layer is interposed between and in direct contact with two of the first Sac2 layers, the seed layer Init being considered as one of the Sac2 layers. Thus, one can either grow a layer of silicon Ch2 directly on the seed layer Init which is here a layer of the first alloy of silicon and germanium of formula Si 1-x Ge x , either start by forming a layer Sac2 of the first germanium alloy directly on the seed layer Init then form a layer Ch2 of silicon on it, then continue the formation of the layers Ch2 and Sac2 alternately.

[0064] This step 580 conditions the characteristics of the Init seed layer: this Init seed layer is of a chemical nature and crystalline structure suitable for allowing the formation of the second Stck2 superlattice by successive growths of layers by epitaxy. In the present case, the second superlattice being formed by alternating Ch2 and Sac2 layers, it is appropriate to form an Init layer of one of these two types of layers. In the present case, it was chosen to form an Init layer of a silicon and germanium alloy of formula Si 1-x Ge x. It is also possible to form the Init layer from another layer capable of forming a sacrificial layer with respect to the Ch2 layers, i.e. layers likely to have faster etching speeds than the second Ch2 layers. Other alternatives exist, such as forming an Init layer of silicon, or other materials favorable to the formation by epitaxy of a layer of silicon Si or an alloy Si 1-x Ge x .

[0065] The formation of the Stck2 superlattice after the transfer step advantageously allows it to avoid a heat treatment intended to cure the layers of the superlattice from the effects of ion implantation. This type of healing heat treatment can be essential for semiconductor layers serving as an active layer in a transistor. Such a heat treatment can sometimes be implemented at a fairly high temperature, which can cause the diffusion of the germanium present in the adjacent layers into the entire channel layers.

[0066] The structure in (A) of theshows the structure Strc formed of the carrier substrate Car, the first superlattice Stck1, the capping layer Cap1 formed of silicon, the layer Ox2 of silicon oxide, and the seed layer Init, stacked in this order. The capping layer Cap1 and the layer Ox2 of silicon oxide form a dielectric separation layer Sep between the first superlattice Stck1 and the second superlattice Stck2. The separation layer is considered a dielectric layer in that it is formed at least in part of a material considered to be dielectric, such as silicon nitride, silicon carbide nitride, or silicon oxide. This structure is ready to be subjected to a monolithic process for forming CFET transistors.

[0067] The figures are labeled "Si" or "SiGe" at the locations of certain layers, and in particular those forming the Stck1 and Stck2 superlattices, in order to increase their readability by indicating their compositions for a given example. These indications are not, however, to be interpreted as limiting the nature of the layers thus annotated. Other materials, and in particular those cited in this description, may be used to form these layers.

[0068] Illustrated in (A') and (A'') are the Strc' and Strc'' structures, respectively, with possible variations Sep' and Sep'' of the Sep separation layer of the Strc structure. In (A), the Sep separation layer is formed by bonding the Ox2 overlay, formed of oxide, to the Cap1 overlay, constituting the last layers formed on the donor substrate Don and on the carrier substrate Car, respectively.

[0069] A first variation illustrated in (A') consists of forming a silicon oxide layer Ox1 as the last layer formed on the carrier substrate Car and forming a silicon cover layer Cap2 as the last layer formed on the donor substrate Don. Thus, the separation layer Sep' is formed by the assembly by molecular bonding of the Ox1 layer with the Cap2 layer.

[0070] A second variation illustrated in (A'') consists of forming two layers of silicon oxide as the last respective layers formed on the substrates Car and Don. Thus, the separation layer Sep'' is formed by the assembly by molecular bonding of these two layers of silicon oxide, finally forming only one layer Ox of silicon oxide.

[0071] The separating layer Sep, which is also the layer linking the two superlattices to each other, is not limited to being formed from crystalline silicon and / or amorphous silicon oxide obtained by oxidation of silicon. Thus, although illustrates in (A) and (B) a process in which the oxide layer Ox2 is formed by the oxidation of a silicon layer, the Ox2 layer could be formed by direct deposition of a silicon oxide layer. This remark applies to the variations illustrated in (A') and (A'') of the for the Ox1 layer of (A') and to the oxide layers forming the Ox layer of (A'').

[0072] The separation layer may also be composed of layers formed from amorphous silicon or other materials as long as these are compatible with the superlattice processing method envisaged subsequently. Thus, in general, dielectric, semiconductor or metallic materials may be used to form the layers composing the separation layer, the main constraint being that these materials must be in the form of layers of sufficiently high flatness and sufficiently low roughness to be assembled by a direct bonding method such as molecular bonding. In the case where the superlattices are intended to form CFET transistors, dielectric materials and / or semiconductor materials will preferably be used. For example, one or a combination of materials chosen from silicon nitride (SiN), silicon carbide nitride (SiCN), an oxide thereof (SiON, SiCNO x), or silicon oxide (SiO2) deposited or formed by a low-temperature oxidation method. Dielectric materials known as "high k" materials in English terminology, such as HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, their alloys or their alloys with silicon can also be used. More generally, any type of dielectric material used in the semiconductor industry can be used as a dielectric layer, protective layer, hard mask (hard mask in English terminology), via coating (liners for TSVs or through-silicon vias in English terminology).

[0073] Illustrates such alternatives with, in (A), a Sep separation layer formed, in this order, of Sep separation layers a , Sep b and Sep c Molecular bonding is performed at an interface plane Int located between the Sep layers c and Sep b, one of which is formed of silicon, amorphous silicon, or silicon oxide, the other being formed of amorphous silicon or silicon oxide. The Sep layer a can be formed from silicon nitride, silicon carbide nitride, silicon oxide, or other dielectric materials. Sep layers a and Sep b can be formed on the donor substrate Don instead of the Ox2 layer and the Sep layer c can be formed on the carrier substrate Car instead of the Cap1 layer. Alternatively, the Sep layers a and Sep b can be formed on the donor substrate Car instead of the Cap1 layer and the Sep layer c can be formed on the donor substrate Don instead of the Ox2 layer.

[0074] The configuration illustrated in (B) is different from the configuration illustrated in (A) in that it further comprises a separation layer Sep dformed on the same side of the interface plane Int as the Sep layer c , and may be formed from silicon nitride, silicon carbide nitride, silicon oxide, or other dielectric materials.

[0075] The separation layers of the variants illustrated by constitute MDLs, or Multiple Dielectric Layers in English terminology, and can be used to improve molecular bonding and adhesion strength for later manufacturing steps.

[0076] The manufacturing process illustrated in Figures 1 and 2 allows for a superposition of two superlattices. In addition, the process can be repeated to stack an arbitrary number of superlattices. Thus, the critical epitaxy thickness can be exceeded: each of the superlattices taken individually can respect this thickness so as to be formed of high-quality layers, and their stacking allows an assembly of superlattices exceeding the critical thickness while maintaining the quality of the layers composing them.

[0077] The epitaxial formation of the layers constituting the superlattices involves the reproduction of the crystalline structure from one layer to another, so that the Si layers and the SiGe layers formed sequentially one after the other by epitaxy have the same crystalline structure. Usually, it is not possible to epitaxially grow a semiconductor layer of acceptable characteristics for the purpose of forming transistors on an amorphous layer such as a dielectric layer, and more particularly an oxide layer. Indeed, this does not constitute a suitable basis for the epitaxial growth of a high-quality crystalline semiconductor layer. The separation layer obtained by the method according to the invention makes it possible to position a dielectric layer between two superlattices formed from semiconductor layers of sufficient quality to produce transistors for commercial applications.

[0078] Furthermore, the separation layer can be adapted (composition, thickness of the layer(s) forming it) to the intended use of the stacked superlattices. It is thus possible to ensure a desired electrical insulation between the two superlattices Stck1 and Stck2 by modulating, for example, the thickness of the Cap2 layer which, once oxidized into an Ox2 layer, forms a high-quality dielectric layer of chosen thickness covering the entire structure, an entire wafer when the substrates are wafers.

[0079] The separation layer is formed continuously in a plane parallel to the upper surface of the substrate supporting it, covering substantially the entire surface of the substrate. Such a geometry contrasts with the situation found in CFET-type structures, in which a dielectric layer separating the n-type transistors and the p-type transistors follows the reliefs formed by the structures resulting from the formation of the transistors located between the substrate and this dielectric layer, and may be discontinuous.

[0080] Thus, the separation layer according to the invention may be of high quality, of chosen thickness, with in addition good thickness uniformity, and continuous over a portion of interest or over substantially the entire surface of a substrate, which makes it suitable for use as an etch stop layer, during the manufacturing process of the different transistors, or for differentiated treatment between the transistors formed in the first supernetwork and the transistors formed in the second supernetwork. Furthermore, by using a Car substrate of SOI type, it is also possible to produce a power supply network on the back side of the device (called BSPDN for BackSide Power Delivery Network in English terminology), using the BOX as an etch stop layer. A portion of interest may consist of a surface of a substrate intended to require the presence of the separation layer.

[0081] The carrier substrate Car and the donor substrate Don may comprise any semiconductor material. In addition to silicon, the semiconductor material may be germanium (Ge), a silicon-germanium alloy (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), III-V compound semiconductors or II-VI compound semiconductors, or SOI type substrates (Silicon-On-Insulator in English terminology), and more generally any type of semiconductor substrate comprising a buried or surface layer of dielectric material. Such a dielectric layer may serve as an etch stop layer for the formation of structures on the rear face (on the side of the carrier substrate Car) of the structure obtained by the method described in Figures 1 and 2, or, in the case where it is located on the surface, as insulation in order to prevent the so-called "latch-up" phenomenon of an integrated circuit manufactured on the basis of this structure.

[0082] The Ch1 and Ch2 layers may be formed, for example, from silicon or a III-V type semiconductor compound. The Sac1 and Sac2 layers may be formed, for example, from silicon and germanium alloys generically referred to as SiGe. The Ch1 and Ch2 layers may be of the same composition in both Stck1 and Stck2 superlattices, and similarly, the Sac1 and Sac2 layers may be of the same composition Si 1-x Ge x in the two superlattices Stck1 and Stck2. This last point makes it possible to eliminate the sacrificial layers Sac1 and Sac2 during the same step.

[0083] Alternatively, the superlattices Stck1 and Stck2 can be of different natures and / or orientations. The orientation of the second superlattice with respect to the first superlattice is defined during the assembly step. The layers Sac1 (and Ch1) on the one hand and the layers Sac2 (and Ch2) on the other hand can have different orientations, for example with crystallographic axes offset by 45°. One can also consider the use of strained silicon, silicon and germanium alloys SiGe or germanium for the channel layers of one or the other of the two superlattices or for both. When the two superlattices comprise alloys of silicon and germanium, the proportions of germanium in the alloy can be the same or different for the two superlattices. It is of course necessary to adapt the nature and characteristics of the sacrificial layers Sac1 and Sac2 to those of the layers Ch1 and Ch2.Also, it is necessary to adapt the nature and crystallographic structure of the Init seed layer to the characteristics of the Sac2 and Ch2 layers in order to guarantee adequate epitaxial growth of these layers.

[0084] Similarly, the numbers of channel layers and sacrificial layers in the two superlattices may be the same, respectively, or may be different.

[0085] The above embodiment has taken as an example associations between layers of silicon alternating with layers of silicon and germanium alloys to form the first superlattice and the second superlattice. However, the invention is not limited to this particular case, and could be applied for example (i) to superlattices consisting of layers of germanium alternating with layers of a silicon and germanium alloy, (ii) to superlattices consisting of layers formed from a first silicon and germanium alloy with a germanium content for example less than 20% alternating with layers formed from a second silicon and germanium alloy with a high germanium content, for example greater than 75%, (iii) to superlattices having layers of different crystallographic orientations, or (iv) to superlattices comprising layers of III-V semiconductor materials.

[0086] The embodiment described above relates to an association of superlattices intended to form transistors, and more specifically Nanosheet transistors or CFETs. The scope of the invention extends, however, beyond this field, and includes the combination of superlattices in general, not only in the field of semiconductors.

[0087] The invention is not limited to the embodiment described above and variations may be made thereto without departing from the scope of the invention as defined by the claims.

Claims

Method (500) for manufacturing a structure (Strc, Strc', Strc'') comprising a stack of superlattices, comprising the steps of:- forming (510 Car ) a first super network (Stck1) on a first substrate (Car), by stacking a plurality of first channel layers (Ch1) alternating with a plurality of first sacrificial layers (Sac1);- forming (520 Don ) a primer layer (Init) of a second super network (Stck2) by adding material on a second substrate (Don); - form (550 Don ) a weakening plane (Imp) of the second substrate (Don) by implantation of ions of a light species in the second substrate (Don);- forming an assembly (Ass) by assembling (560) the primer layer (Init) to the first superlattice (Stck1) at the level of a dielectric separation layer (Sep, Sep', Sep'') which separates and keeps fixed to each other the first superlattice (Stck1) and the primer layer (Init);- eliminating (570A) a first part (Donb ) of the second substrate (Don) by fracturing the second substrate (Don) at the level of the weakening plane (Imp), and removing this part (Don b ) of the second substrate (Don), after the assembly step (560); - releasing (570B) the primer layer (Init) after the step (570A) of fracturing the second substrate (Don) in such a way that the released primer layer forms an outer face (F ext ) of the assembly (Ass), the release step including the elimination of a second part (Don a ) of the second substrate which remained assembled to the primer layer (Init) after the step of eliminating the first part (Don b ) of the second substrate (Don); and- form (580) the second super network (Stck2) on and in direct contact with the outer face (F ext ) of the released primer layer (Init), by stacking a plurality of second channel layers (Ch2) alternating with a plurality of second sacrificial layers (Sac2). The method of claim 1, wherein the embrittlement plane (Imp) of the second substrate (Don) is formed by implanting ions of a light species into the second substrate (Don) through the primer layer (Init). The method of claim 1 or 2, wherein the separation layer (Sep, Sep', Sep'') is continuously formed in a plane parallel to a surface (S Car ) of the first substrate (Car) on which the first super network (Stck1) is formed. The method according to any one of claims 1 to 3, wherein:- the first channel layers (Ch1) and the second channel layers (Ch2) are each formed of a semiconductor material, and- the first sacrificial layers (Sac1) and the second sacrificial layers (Sac2) are each formed of a material capable of exhibiting a faster etching rate than the first channel layers (Ch1) and the second channel layers (Ch2), respectively. The method according to any one of the preceding claims 1 to 4, wherein:- the first channel layers (Ch1) and the second channel layers (Ch2) are each formed of silicon, and- the first sacrificial layers (Sac1) and the second sacrificial layers (Sac2) are each formed of an alloy of silicon and germanium. The method according to any one of claims 1 to 5, comprising the steps of:- forming (520 Car ) a first covering layer (Cap1, Ox1) of the first super network (Stck1) before the fixing step (560); and- forming (530 Don) a second covering layer (Cap2, Ox2) of the primer layer (Init) before the fixing step (560); wherein the fixing step (560) comprises bringing the first covering layer (Cap1, Ox1) into contact with the second covering layer (Cap2, Ox2), the first covering layer (Cap1, Ox1) and the second covering layer (Cap2, Ox2) together forming the separation layer (Sep, Sep', Sep''). The method of claim 6, wherein the first cover layer (Ox2) and the second cover layer (Cap2) each comprise silicon and at least one of the first cover layer (Ox1) and the second cover layer (Ox2) is formed of an oxide. The method of claim 7, wherein at least one of the first covering layer and the second covering layer formed of an oxide is formed by a forming step (530 Don) of a silicon layer (Cap2) followed by an oxidation step (540 Don ) of this layer of silicon. The method of any one of claims 1 to 8, further comprising a step of forming (510 Don ) of at least one etch stop layer (Stp, Cap2') on the second substrate (Don) before the formation of the primer layer (Init), the etch stop layer being removed during the step (570B) of releasing the primer layer (Init). The method according to claim 9, wherein the at least one etch stop layer is formed of a layer (Stp) of the same material as the second sacrificial layers (Sac2) and a layer (Cap2') of the same material as the second channel layers (Ch2), the layer (Stp) of the same material as the second sacrificial layers (Sac2) and the layer (Cap2') of the same material as the second channel layers (Ch2) being removed during the step (570B) of removing the primer layer (Init).

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