Bonded semiconductor substrate and method for manufacturing bonded semiconductor substrate

Abstract

Provided are a bonded semiconductor substrate capable of preventing occurrence of peeling of a substrate from a bonding interface of the bonded semiconductor substrate, and a method for manufacturing the bonded semiconductor substrate.　A method for manufacturing a bonded semiconductor substrate that comprises a first semiconductor substrate and a second semiconductor substrate that comes into contact with the first semiconductor substrate, the method comprising: an amorphous layer formation step for forming, by amorphizing, an amorphous layer on at least one of a surface of a first bonding target surface, which is a surface of the first semiconductor substrate bonded to the second semiconductor substrate, and a surface of a second bonding target surface, which is a surface of the second semiconductor substrate bonded to the first semiconductor substrate; a bonding step for bonding the first bonding target surface and the second bonding target surface after formation of the amorphous layer and forming a bonded substrate including a bonding interface; and a heat-treatment step for heat-treating the bonded substrate to set an undulation height of the bonding interface to 1.5 nm or higher. The thickness of the amorphous layer formed by the formation of the amorphous layer is 5 nm or greater.

Description

Bonded semiconductor substrate and method for manufacturing the same

[0001] The present invention relates to a bonded semiconductor substrate in which two or more substrates are bonded together via a bonding interface, and to a method for manufacturing the bonded semiconductor substrate, which can prevent peeling at the bonding interface.

[0002] As an example of manufacturing a bonded semiconductor substrate, a technique for bonding a SiC single crystal substrate and a SiC polycrystalline substrate is known. Related techniques include the technique disclosed in Patent Document 1, for example.

[0003] Patent No. 6061251

[0004] When a SiC single crystal substrate and a SiC polycrystalline substrate are directly bonded together, there is a risk that even a small impact will cause delamination at the bonded interface if the bond strength at the bonded interface is low. For example, if delamination occurs at the bonded interface of the bonded semiconductor substrate and dust is generated inside a growth furnace for growing an epitaxial film on the surface of the SiC single crystal substrate of the bonded semiconductor substrate, or inside a device manufacturing apparatus for manufacturing a semiconductor device using the bonded semiconductor substrate after the epitaxial film has been formed, this is undesirable because it can cause the growth furnace or the apparatus to stop due to dust generation inside the furnace or the apparatus, or can reduce the operating rate of the growth furnace or the apparatus due to cleaning inside the growth furnace or the apparatus, resulting in a decrease in production efficiency.

[0005] In the semiconductor substrate manufacturing method of Patent Document 1, an amorphous layer is formed on the surface of the support substrate and the single-crystalline layer before they are brought into contact with each other and then heat-treated, so as to obtain a bonding strength strong enough to withstand semiconductor processes. This method is expected to prevent delamination at the bonding interface during the process of growing an epitaxial film on the bonded semiconductor substrate and then manufacturing a semiconductor device.

[0006] However, after semiconductor devices with electronic circuits formed and cut into chips are incorporated into mobile phones, home appliances, and industrial equipment, they may be subjected to shocks greater than those experienced during the manufacturing process of semiconductor devices. It is important that such shocks do not cause peeling at the bonding interface of bonded semiconductor substrates.

[0007] In order to solve the above problems, an object of the present invention is to provide a bonded semiconductor substrate and a method for manufacturing the bonded semiconductor substrate that can prevent the substrates from peeling off from the bonding interface of the bonded semiconductor substrates.

[0008] In order to solve the above problems, the bonded semiconductor substrate of the present invention is a bonded semiconductor substrate comprising a first semiconductor substrate and a second semiconductor substrate bonded to the first semiconductor substrate via a bonding interface, wherein the height of the undulations at the bonding interface is 1.5 nm or more.

[0009] The fracture strength in a direction perpendicular to the bonded interface may be 70 MPa or more in a stud pull test.

[0010] The first semiconductor substrate and the second semiconductor substrate may be made of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga ２ O ３ ), and diamond.

[0011] The first semiconductor substrate may be a single crystal silicon carbide substrate, and the second semiconductor substrate may be a polycrystalline silicon carbide substrate.

[0012] Furthermore, in order to solve the above-mentioned problems, the present invention provides a method for manufacturing a bonded semiconductor substrate comprising a first semiconductor substrate and a second semiconductor substrate in contact with the first semiconductor substrate, the method comprising: an amorphous layer formation step of forming an amorphous layer on at least one of a surface of a first bonding target surface, which is a surface of the first semiconductor substrate where the first semiconductor substrate is bonded to the second semiconductor substrate, or a surface of a second bonding target surface, which is a surface of the second semiconductor substrate where the second semiconductor substrate is bonded to the first semiconductor substrate; a bonding step of bonding the first bonding target surface and the second bonding target surface to form a bonded substrate having a bonding interface; and a heat treatment step of heat-treating the bonded substrate to make the undulation height of the bonding interface 1.5 nm or more, wherein the amorphous layer formed in the amorphous layer formation step has a thickness of 5 nm or more.

[0013] The first semiconductor substrate and the second semiconductor substrate may be made of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga ２ O ３ ), and diamond.

[0014] The amorphous layer may contain at least one of silicon (Si), carbon (C), helium (He), neon (Ne), argon (Ar), xenon (Xe), hydrogen (H), nitrogen (N), phosphorus (P), boron (B), and aluminum (Al).

[0015] The amorphous layer forming step may be a step of forming the amorphous layer by performing a plasma injection process on at least one of a surface of the first surface to be bonded and a surface of the second surface to be bonded.

[0016] The heat treatment step may be a step of maintaining the temperature of the bonded substrate at 1100°C to 2200°C.

[0017] The method may further include an ion implantation step of implanting hydrogen ions or helium ions into the first bonding target surface to form an ion-implanted layer inside the first semiconductor substrate before or after the amorphous layer formation step.

[0018] The method may further include a peeling step after the bonding step and before the heat treatment step, in which a microbubble layer formed by heating the ion-implanted layer is used as a peeling surface to peel off a portion of the first semiconductor substrate.

[0019] The present invention can provide a bonded semiconductor substrate and a method for manufacturing the bonded semiconductor substrate that can prevent the substrates from peeling off from the bonding interface of the bonded semiconductor substrate.

[0020] FIG. 1 is a flow diagram showing an example of a method for manufacturing a bonded semiconductor substrate of the present invention. FIG. 2 is a schematic perspective view showing an example of a bonded semiconductor substrate of the present invention. FIG. 3 is a schematic side view of a single crystal substrate after formation of a hydrogen-implanted layer in the present invention. FIG. 4 is a schematic side view of a single crystal substrate after formation of an amorphous layer in the present invention. FIG. 5 is an explanatory diagram showing an example of an irradiation step in the present invention. FIG. 6 is a schematic side view showing an example of a state in which a single crystal substrate on which a hydrogen-implanted layer and an amorphous layer have been formed is bonded to a support substrate. FIG. 7 is a schematic side view showing an example of a bonded substrate in the present invention. FIG. 8 is a TEM image (Miller index [1-100] direction) of a cross section of a single crystal substrate on which an amorphous layer has been formed by implanting plasma using nitrogen. FIG. 9 is a TEM image (Miller index [1-100] direction) of a cross section of a single crystal substrate on which an amorphous layer has been formed by implanting plasma using nitrogen. 1 is a TEM image (Miller index [1-100] direction) of a cross section of a single crystal substrate on which an amorphous layer has been formed by injecting plasma using phosphorus. 2 is a TEM image (Miller index [1-100] direction) of a cross section of a single crystal substrate on which an amorphous layer has been formed by injecting plasma using phosphorus. 3 is a TEM image (Miller index [1-100] direction) of a cross section of a single crystal substrate on which an amorphous layer has been formed by injecting plasma using phosphorus. 4 is a TEM image (Miller index [1-100] direction) of a cross section of a bonded interface of a bonded semiconductor substrate of the present invention. 5 is a schematic side view showing a state in which a bonded semiconductor substrate and a stud pin are bonded with an adhesive when a stud-pull test is performed.

[0021] This specification discloses a bonded semiconductor substrate and a method for manufacturing the bonded semiconductor substrate, which is obtained by bonding a first semiconductor substrate and a second semiconductor substrate, and can be manufactured by amorphizing one or both of the surfaces to be bonded of the first semiconductor substrate and the second semiconductor substrate to form an amorphous layer (amorphous layer formation step), then bonding the amorphous layer of the first semiconductor substrate to the amorphous layer of the second semiconductor substrate (bonding step) to produce a bonded substrate having a bonded interface, and then performing a heat treatment (heat treatment step) to form an undulating bonded interface.

[0022] If two semiconductor substrates are directly bonded together without forming an amorphous layer, even a small impact applied to the bonded substrates can cause the bonded substrates to delaminate at the bonded interface if the bond strength at the bonded interface is low. To prevent this delamination, one or both of the bonding surfaces of the first semiconductor substrate and the second semiconductor substrate are made amorphous, thereby facilitating the movement of atoms constituting the semiconductor in the amorphous layer. Furthermore, by bonding the amorphous layer to form an undulating bonded interface, the bonding area between the first semiconductor substrate and the second semiconductor substrate at the bonded interface is increased, thereby increasing the bond strength, thereby preventing delamination at the bonded interface of the bonded semiconductor substrates.

[0023] Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings.

[0024] [Bonded Semiconductor Substrate] The bonded semiconductor substrate includes a first semiconductor substrate and a second semiconductor substrate, which are bonded together via a bonding interface.

[0025] <Configuration of Bonded Semiconductor Substrate> Figure 2 is a perspective view showing an example of a bonded semiconductor substrate of the present invention. Bonded semiconductor substrate 10 of the present invention is formed, for example, in a disk shape with an orientation flat. Note that the shape is not limited to a disk shape (wafer shape) and may be polygonal. Bonded semiconductor substrate 10 shown in Figure 2 includes single-crystal substrate 13, which is an example of a first semiconductor substrate, and support substrate 11, which is an example of a second semiconductor substrate, and single-crystal substrate 13 is bonded to support substrate 11 to form a bonded interface 14.

[0026] The single crystal substrate 13 is made of, for example, a compound semiconductor (e.g., silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga ２ O ３ The carbon (C) may be any of a single element semiconductor (e.g., silicon (Si), carbon (C)), and diamond. These elements are semiconductor materials that can be used to fabricate semiconductor devices. The carbon (C) may be other than diamond, such as graphite.

[0027] Various materials can be used for the support substrate 11. It is preferable that the support substrate 11 has resistance to various thermal processes applied to the single crystal substrate 13. It is also preferable that the support substrate 11 is made of a material that has a small difference in thermal expansion coefficient from the single crystal substrate 13. For example, the support substrate 11 can be made of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga ２ O ３ ), diamond, sapphire (Al ２ O ３ ), and quartz (SiO ２ ) or the like can be used.

[0028] For example, the single crystal substrate 13, which is an example of the first semiconductor substrate, may be a single crystal silicon carbide substrate (SiC single crystal substrate), and the support substrate 11, which is an example of the second semiconductor substrate, may be a polycrystalline silicon carbide substrate (SiC polycrystalline substrate).

[0029] The SiC single crystal substrate may be, for example, a 4H—SiC single crystal substrate produced by sublimation deposition. The SiC single crystal substrate may be, for example, substantially disk-shaped with an orientation flat, and may have a diameter of 4 to 8 inches. The shape is not limited to a disk (wafer shape) and may also be polygonal.

[0030] Furthermore, the SiC polycrystalline substrate may contain a mixture of SiC crystals of various polytypes and plane orientations. A SiC polycrystalline substrate containing a mixture of various polytypes and plane orientations can be manufactured without strict temperature control, thereby reducing the cost of manufacturing the support substrate 11. For example, a 3C-SiC polycrystalline substrate obtained by depositing a SiC polycrystalline film by chemical vapor deposition can be used. The shape of the SiC polycrystalline substrate may be substantially the same as that of the SiC single crystal substrate, and for example, a substantially disk-shaped substrate with an orientation flat and a diameter of 4 to 8 inches can be used. The shape is not limited to a disk shape, and may also be polygonal.

[0031] The thickness TT1 of the support substrate 11 may be determined so as to provide a mechanical strength sufficient to withstand subsequent processes, such as forming an epitaxial layer and then forming a semiconductor element or device thereon. For example, when the diameter of the support substrate 11 is 6 inches (150 mm), the thickness TT1 may be approximately 350 μm, and a substrate having a thickness TT1 of 300 to 500 μm can be used.

[0032] (Fracture strength) The bonded semiconductor substrate preferably has a fracture strength of 70 MPa or more in a stud-pull test in a direction perpendicular to the bonded interface. In the examples described below, when the fracture strength of only the SiC single crystal substrate was measured by the stud-pull test, it was less than 70 MPa. In other words, a fracture strength of 70 MPa or more indicates that the bonded semiconductor substrate has such a strong bonding strength at the bonded interface that it will not peel off even if the fracture strength is less than 70 MPa.

[0033] A fracture strength of 70 MPa or more in a stud-pull test can prevent peeling at the bonding interface during the process from growing an epitaxial film on the bonded semiconductor substrate to manufacturing a semiconductor device, and can also prevent peeling at the bonding interface even after electronic circuits are formed on the substrate, the substrate is cut into chips, and the chips are incorporated into mobile phones, home appliances, and industrial equipment.

[0034] If the fracture strength in the stud-pull test is 70 MPa or more, peeling at the bonded interface can be prevented. As will be described later, there is a possibility that the adhesive may cause fracture, so there is no particular upper limit to the fracture strength. However, when the bonded semiconductor substrate is a substrate in which a SiC single crystal substrate and a SiC polycrystalline substrate are bonded together, the fracture strength in the stud-pull test should be in the range of 70 MPa to 90 MPa.

[0035] Here, the stud-pull test is a test in which two stud pins are attached to the surfaces of the first and second semiconductor substrates of a bonded semiconductor substrate using an adhesive, and then these stud pins are pulled in a direction perpendicular to the bonded interface to fracture the bonded semiconductor substrate. This test makes it possible to measure the fracture strength when fracture occurs and to evaluate whether the bonded semiconductor substrate fractured in the first semiconductor substrate, the second semiconductor substrate, or the bonded interface. Note that if the strength of the first and second semiconductor substrates is high and the bonding strength of the bonded interface is also high, fracture may occur due to the adhesive. However, since the adhesive itself is strong, if fracture occurs due to the adhesive, it can be said that the bonded semiconductor substrate itself has sufficient strength without any problems.

[0036] (Height of undulations at the bonded interface) In the manufacturing process of the bonded semiconductor substrate, elements in the amorphous layer are recrystallized by a heat treatment process described below, and the elements move while recrystallizing, forming an undulating bonded interface. The undulations at the bonded interface increase the bonding area between the first semiconductor substrate and the second semiconductor substrate at the bonded interface, thereby increasing the bonding strength, and making it possible to prevent delamination at the bonded interface of the bonded semiconductor substrate.

[0037] The undulation height of the bonding interface is 1.5 nm or more. If the undulation height is 1.5 nm or more, the bonding area between the first semiconductor substrate and the second semiconductor substrate increases, and the bonding strength of the bonding interface becomes stronger, and the bonding strength of the bonding interface becomes greater than the fracture strength of the first semiconductor substrate and the second semiconductor substrate. There is no particular upper limit to the undulation height, but if the undulation height is 5 nm, the bonding strength can be sufficiently increased, and the bonding strength of the bonding interface becomes clearly greater than the fracture strength of the first semiconductor substrate and the second semiconductor substrate, thereby reliably preventing peeling at the bonding interface.

[0038] [Method for Manufacturing Bonded Semiconductor Substrate] Next, as an example of the method for manufacturing a bonded semiconductor substrate comprising a first semiconductor substrate and a second semiconductor substrate of the present invention, a method for manufacturing bonded semiconductor substrate 10 in which support substrate 11, which is the second semiconductor substrate, is a SiC polycrystalline substrate and single crystal substrate 13, which is the first semiconductor substrate, is a single crystal 4H—SiC substrate will be described. Here, with reference to the flow diagram showing an example of the method for manufacturing a bonded semiconductor substrate shown in FIG. 1 , a case in which bonded semiconductor substrate 10 is manufactured using a technique for delaminating single crystal substrate 13 by ablation of hydrogen atoms will be described.

[0039] First, the support substrate 11 and the single crystal substrate 13 are prepared. The support substrate 11 and the single crystal substrate 13 can be obtained with the surfaces to be bonded already planarized. The planarization may be performed by grinding or cutting, or by a CMP method. Alternatively, the surfaces to be bonded may be planarized by the user.

[0040] <Hydrogen Ion Implantation Step (Step S0)> In step S0 of Fig. 1, a hydrogen ion implantation step is performed in which hydrogen ions are implanted from the bonding target surface 13a of the single crystal substrate 13. When hydrogen ions are implanted into the single crystal substrate 13, the hydrogen ions reach a depth corresponding to the incident energy and are distributed at a high concentration. As a result, a hydrogen-implanted layer 15, indicated by a dotted line, is formed at a predetermined depth from the bonding target surface 13a, as shown in the side schematic diagram of Fig. 3. For example, the hydrogen-implanted layer 15 is formed at a depth of about 0.6 µm from the bonding target surface 13a.

[0041] A helium implantation layer may be formed by ion implanting helium instead of hydrogen, or by alternately implanting hydrogen and helium ions to form an implantation layer, and the same peeling effect can be expected in the peeling step described below.

[0042] The hydrogen ion implantation step is not an essential step in the present invention, and the present invention may be carried out by purchasing a single crystal substrate 13 after hydrogen ion implantation, or by using the same.

[0043] Furthermore, the hydrogen ion implantation process can be employed, for example, in cases where the second semiconductor substrate is a SiC polycrystalline substrate and the first semiconductor substrate is a SiC single crystal substrate, or where the first semiconductor substrate is a Si substrate and the second semiconductor substrate is a Si substrate, and can be performed before or after the amorphous layer formation process described below.

[0044] <Amorphous Layer Forming Step (Step S1)> This step is a step of forming an amorphous layer by amorphizing at least one of the surface of the first bonding target surface, which is the surface where the first semiconductor substrate is bonded to the second semiconductor substrate, or the surface of the second bonding target surface, which is the surface where the second semiconductor substrate is bonded to the first semiconductor substrate. That is, this is a step of forming an amorphous layer on at least one of the bonding target surface 11 a or the bonding target surface 13 a, and examples of the step include forming an amorphous layer on the bonding target surface 11 a but not on the bonding target surface 13 a, forming an amorphous layer on the bonding target surface 13 a without forming an amorphous layer on the bonding target surface 11 a, and forming amorphous layers on both the bonding target surface 11 a and the bonding target surface 13 a.

[0045] The amorphous layer aims to increase the bonding area between single crystal substrate 13 and support substrate 11 at bonding interface 14 by forming undulating bonding interface 14, thereby making the bonding strength between single crystal substrate 13 and support substrate 11 stronger than the fracture strength of single crystal substrate 13. Therefore, when forming an amorphous layer on bonding target surface 11a, it is preferable to form the amorphous layer on the entire surface of bonding target surface 11a, and when forming an amorphous layer on bonding target surface 13a, it is preferable to form amorphous layer 12 on the entire surface of bonding target surface 13a.

[0046] The thickness of the amorphous layer formed in the amorphous layer forming step is 5 nm or more. By making the thickness of the amorphous layer 5 nm or more, it is possible to form a bonding interface 14 with large undulations by the heat treatment step, and the bonding area between the single crystal substrate 13 and the support substrate 11 at the bonding interface 14 can be further increased, so that the bonding strength between the single crystal substrate 13 and the support substrate 11 can be made stronger than the fracture strength of the single crystal substrate 13.

[0047] There is no particular upper limit to the thickness of the amorphous layer, but the upper limit is, for example, 50 nm, depending on the performance of the apparatus for forming the amorphous layer.

[0048] Hereinafter, as an example, a case will be described in which an amorphous layer 12 is formed on the surface to be joined 13a without forming an amorphous layer on the surface to be joined 11a.

[0049] 1, in step S1, an amorphous layer 12 is formed on a surface 13a to be bonded of a single crystal substrate 13. The amorphous layer 12 has no regularity in the arrangement of its constituent elements, that is, it is not crystalline, and may be any layer in which elements are arranged irregularly.

[0050] It is preferable to employ plasma injection using a plasma injector to form the amorphous layer 12. As shown in Fig. 4, the amorphous layer 12 can be effectively formed on the bonding target surface 13a by the plasma injector. Furthermore, by using the plasma injector, it is possible to easily control the plasma injection depth and the like by adjusting the acceleration voltage, dose, and the like.

[0051] Examples of ion elements implanted by the plasma implanter include silicon (Si), carbon (C), helium (He), neon (Ne), argon (Ar), xenon (Xe), hydrogen (H), nitrogen (N), phosphorus (P), boron (B), and aluminum (Al). As a result, when an amorphous layer is formed by the plasma implanter, at least one of silicon (Si), carbon (C), helium (He), neon (Ne), argon (Ar), xenon (Xe), hydrogen (H), nitrogen (N), phosphorus (P), boron (B), and aluminum (Al) may be present in the amorphous layer.

[0052] As an example of an embodiment of the amorphous layer formation process of the present invention, a case where nitrogen (N) is used as the plasma element for forming amorphous layer 12 will be taken. Specifically, single crystal substrate 13 is placed in a plasma implanter, and nitrogen (N) ions are implanted into the surface of bonding target surface 13a of single crystal substrate 13 using the plasma implanter, whereby amorphous layer 12 is formed on the surface layer of single crystal substrate 13 (FIG. 4).

[0053] 8A to 8C show images of a cross section of an amorphous layer 12 formed by plasma implanting nitrogen (N) at room temperature into the bonding target surface 13a of a single crystal substrate 13, observed with a transmission electron microscope (TEM). In all of FIGS. 8A to 8C, the implantation temperature was room temperature, the voltage was 6 kV, and the dose was 7.0 × 10 in FIG. 8A. １４ / cm ２ , and Fig. 8B is 3.5 × 10 １５ / cm ２ , and Fig. 8C is 7.0 × 10 １５ / cm ２ is.

[0054] The amorphous layer 12 is a layer in which the elements are arranged irregularly, without any regularity in the arrangement of the constituent elements, and therefore has a different contrast in the TEM observation image from the single crystal substrate 13 in which the elements are arranged regularly, and is lighter in color than the single crystal substrate 13. Furthermore, since there is no diffraction contrast due to crystals within the amorphous layer 12, the color is uniform, and the amorphous layer 12 and the single crystal substrate 13 can be visually distinguished from each other when observed.

[0055] 8A to 8C, the region at a predetermined depth from the bonding target surface 13a is a region with a uniform, light color compared to the underlying single crystal substrate 13, and this region is the amorphous layer 12 formed by nitrogen (N) plasma injection. The depth of the amorphous layer 12 is 9 nm to 18 nm, and it is observed that the amorphous layer tends to become deeper as the dose of nitrogen (N) increases.

[0056] The acceleration voltage when nitrogen (N) is plasma-implanted can be set within a range of 0.1 to 1000 kV. For example, the plasma implantation process may be performed by controlling the acceleration voltage or the like so that the concentration of nitrogen (N) is maximized at the bonding target surface 13 a of the single crystal substrate 13.

[0057] By forming such an amorphous layer 12 in advance, the elements in the amorphous layer 12 can move more easily in the subsequent heat treatment process, and therefore, an undulating bonded interface 14 can be formed.

[0058] 9A to 9C also show transmission electron microscope (TEM) images of the cross section of the amorphous layer 12 formed by plasma implanting phosphorus (P) at room temperature into the bonding target surface 13a of the single crystal substrate 13. In all of FIGS. 9A to 9C, the implantation temperature was room temperature, the voltage was 10 kV, and the dose was 3.6×10 in FIG. 9A. １４ / cm ２ , and FIG. 9B is 3.6×10 １５ / cm ２ 9C is 3.6 × 10 １６ / cm ２ is.

[0059] 9A to 9C, the region at a predetermined depth from the bonding target surface 13a is a region with a uniform, light color compared to the underlying single crystal substrate 13, and this region is the amorphous layer 12 formed by phosphorus (P) plasma injection. The depth of the amorphous layer 12 is 8 nm to 30 nm, and it is observed that the amorphous layer tends to become deeper as the dose of phosphorus (P) increases.

[0060] The method for forming the amorphous layer 12 is not limited to plasma injection using a plasma injection machine. For example, the amorphous layer 12 may be formed by appropriately setting conditions using an ion injection device or the like so that the amorphous layer 12 is formed on the bonding target surface 13a. However, since the plasma injection method has a high element injection current density, it is possible to shorten the injection time for injecting the same amount of element, making it a highly productive injection method. Therefore, by employing the plasma injection method, it is possible to efficiently form an amorphous layer 12 with a sufficient thickness.

[0061] <Irradiation Step (Step S2)> This step is a step of irradiating the first surface to be joined or the second surface to be joined with an argon beam after the amorphous layer formation step and before the bonding step. That is, this is a step of irradiating the surface to be joined 11 a or the surface to be joined 13 a with an argon beam, and the argon beam may be irradiated to both the surface to be joined 11 a and the surface to be joined 13 a.

[0062] In step S2 of Fig. 1, an irradiation step is performed. As shown in Fig. 5, the single crystal substrate 13 and the support substrate 11 are set in the chamber 101. Next, the relative positions of the single crystal substrate 13 and the support substrate 11 are aligned. The alignment is performed so that the two substrates can be brought into contact with each other in the correct positional relationship in the bonding step described below. Next, the chamber 101 is evacuated. The degree of vacuum in the chamber 101 is, for example, 1 x 10 －４ ~1 x 10 －６ It may be about Pa.

[0063] Next, a fast atomic beam gun (FAB gun) 102 is used to irradiate the bonding target surface 11a of the support substrate 11 and the bonding target surface 13a of the single-crystal substrate 13 with a neutral element beam 103 of argon (Ar). The neutral element beam of argon (Ar) is uniformly irradiated onto the entire surfaces of the bonding target surfaces 11a and 13a. This removes oxide films and adsorption layers from the bonding target surfaces 11a and 13a, exposing bonds. This state is called an activated state. Furthermore, because the irradiation process is performed in a vacuum, the bonding target surfaces 11a and 13a are not oxidized, and can maintain their activated state.

[0064] The irradiation step is not an essential step, and can be omitted if the single-crystal substrate 13 and the support substrate 11 can be bonded to form the bonded semiconductor substrate 10 without any problems by the bonding step described below. The irradiation step is a step in which atoms or molecules collide with the surface to remove oxides and adsorption layers on the surface through a sputtering phenomenon. However, instead of this step, a step can be performed in which a reactive gas is used to chemically react with surface contaminants and remove them by etching. Also, if the adsorption material is easily sublimated, the adsorption material can be removed by sublimation simply by applying heat or light. These steps can be used instead of the irradiation step to remove oxide films and adsorption layers on the surfaces to be bonded, exposing bonds.

[0065] <Bonding Step (Step S3)> This step is a step of bonding the first surface to be bonded and the second surface to be bonded together after the amorphous layer forming step, to form a bonded substrate having a bonding interface.

[0066] 1, a bonding step is performed. In the bonding step, the bonding target surface 11a of the support substrate 11 and the bonding target surface 13a of the single crystal substrate 13 are brought into contact in a vacuum within the chamber 101. As a result, bonds existing on the bonding target surface 11a and the bonding target surface 13a in an active state bond with each other, thereby bonding the support substrate 11 and the single crystal substrate 13. As a result, a structure in which the support substrate 11 and the single crystal substrate 13 are bonded is formed, as shown in the schematic diagram of FIG.

[0067] <Delamination Step (Step S4)> This step can be performed after the bonding step and before the heat treatment step, in which a microbubble layer is formed in the hydrogen-implanted layer 15 by applying heat during the delamination step, and the microbubble layer is used as a delamination surface to delaminate a portion of the single-crystal substrate 13. In other words, the single-crystal substrate 13 is delaminated using the hydrogen-implanted layer 15 on which the microbubble layer has been formed in the single-crystal substrate 13 as a delamination surface.

[0068] 1, a separation step is performed. Specifically, the support substrate 11 and the single crystal substrate 13 bonded together are heated to about 800°C or higher. The atmosphere during separation may be at least one of an inert gas atmosphere such as argon (Ar) or nitrogen (N), or a vacuum atmosphere. The degree of vacuum is, for example, 1×10 －４ ~1 x 10 －６ The pressure may be about 100 Pa. The separation may be performed by rapid thermal annealing (RTA) or using a furnace. This allows the single crystal substrate 13 to be separated at the hydrogen-implanted layer 15. As a result, as shown in the schematic diagram of FIG. 7 , a bonded substrate 30 can be formed in which a thin single crystal substrate 13, for example, 0.6 μm thick, is bonded to a support substrate 11.

[0069] <Heat Treatment Step (Step S5)> This step is a step of heat treating the bonded substrate to make the height of the undulations at the bonded interface 10 equal to or greater than 1.5 nm. Bonded semiconductor substrate 10 is completed by this heat treatment step.

[0070] In step S5 of FIG. 1 , a heat treatment process is performed. In this heat treatment process, the bonded substrate 30 including the support substrate 11, the amorphous layer 12, and the single-crystal substrate 13 is heat-treated. The heat treatment temperature may be set so that the temperature of the bonded substrate 30 is 1100°C to 2200°C, preferably 1600°C to 1800°C, and more preferably about 1700°C. By setting the heat treatment temperature (i.e., the temperature of the bonded substrate 30) to 1100°C to 2200°C, the undulation height of the bonded interface can be 1.5 nm or more without any problems. If the heat treatment temperature is less than 1100°C, the undulation height may be less than 1.5 nm. Furthermore, if the heat treatment temperature exceeds 2200°C, the substrate material may sublimate, causing roughness on the surface of the bonded substrate 30.

[0071] The atmosphere for the heat treatment may be at least one of an inert gas atmosphere such as argon (Ar) or nitrogen (N) and a vacuum atmosphere. The degree of vacuum is, for example, 1×10 －４ ~1 x 10 －６The pressure may be about Pa. The heat treatment step may be performed in the furnace in which the delamination step was performed. Furthermore, if the heat treatment temperature is maintained for 1 minute or more, the height of the undulations at the bonding interface can be made 1.5 nm or more. There is no particular upper limit to the time for which the heat treatment temperature is maintained, but in consideration of manufacturing efficiency, the upper limit may be set to, for example, 100 hours. For example, the time for which the heat treatment temperature is maintained can be set between 1 minute and 10 hours.

[0072] Furthermore, although the height of the undulations at the bonding interface varies depending on the thickness of the amorphous layer, the heat treatment temperature, and the time for which the heat treatment temperature is maintained, the object of the present invention can be fully achieved if the upper limit of the undulation height is set to 5 nm.

[0073] Bonded semiconductor substrate 10 manufactured by the above manufacturing method has a fracture strength of 70 MPa or more in a stud-pull test in a direction perpendicular to bonded interface 14. When the fracture strength of only the SiC single crystal substrate is measured by the stud-pull test, it is less than 70 MPa. In other words, a fracture strength of 70 MPa or more indicates that bonded semiconductor substrate 10 does not peel at bonded interface 14, and indicates that the SiC single crystal substrate fractures while bonded interface 14 remains bonded.

[0074] Having a breaking strength of 70 MPa or more in a stud-pull test makes it possible to prevent peeling at the bonding interface during the process from growing an epitaxial film on the bonded semiconductor substrate 10 to manufacturing a semiconductor device thereafter, and also makes it possible to prevent peeling at the bonding interface even after electronic circuits are formed, the substrate is cut into chips, and the chips are incorporated into mobile phones, home appliances, and industrial equipment.

[0075] If the fracture strength in the stud-pull test is 70 MPa or more, peeling at the bonded interface can be prevented, and therefore there is no particular upper limit to the fracture strength; however, when the bonded semiconductor substrate 10 is a substrate in which a SiC single crystal substrate and a SiC polycrystalline substrate are bonded together, the fracture strength in the stud-pull test will be within the range of 70 MPa to 90 MPa.

[0076] Although one embodiment of the present invention has been described in detail above, these are merely examples and do not limit the scope of the present invention. For example, as described below, the present invention includes various modifications and alterations of the specific example exemplified above.

[0077] The element used to form the amorphous layer 12 may be silicon (Si) as an element other than nitrogen (N) or phosphorus (P). In this case, the composition ratio of elements at the bonded interface 14 is such that the proportion of silicon is higher than that of carbon, and the bonded interface 14 is made of silicon-rich SiC. For example, the composition ratio of silicon to carbon at the bonded interface 14 is Si:C=50-60 atomic %:40-50 atomic %.

[0078] The element used to form the amorphous layer 12 may also be carbon (C). In this case, the composition ratio of elements at the bonding interface 14 is such that the proportion of carbon is higher than that of silicon, and the bonding interface 14 is made of carbon-rich SiC. For example, the carbon composition ratio is in the range of 50 to 60 atomic %.

[0079] The element used to form the amorphous layer 12 may be an element that is unlikely to become a carrier and has a high effect of forming the amorphous layer 12. For example, at least one of a rare gas such as helium (He), neon (Ne), argon (Ar), or xenon (Xe), or hydrogen (H) may be used.

[0080] The element used to form the amorphous layer 12 may be an element that easily becomes a carrier and easily becomes amorphous. For example, in addition to the already mentioned nitrogen (N) and phosphorus (P), boron (B) and aluminum (Al) may be used, and at least one of these four elements may be used. In particular, using an element with a large mass, such as phosphorus (P), is more likely to destroy the crystal structure and cause amorphous formation than using an element with a small mass.

[0081] The amorphous layer forming step (step S1) may be performed between the separation step (step S4) and the heat treatment step (step S5). In this case, ions may be implanted from the surface of the single-crystal substrate 13 toward the bonded interface by ion implantation. In this case, various parameters of the ion implantation conditions, such as acceleration energy and incident angle, may be set so that the ion concentration is maximized near the bonded interface. For example, a multi-stage implantation method may be used in which ions are implanted multiple times while changing the acceleration energy, thereby controlling the ion concentration to be maximized near the bonded interface.

[0082] Furthermore, in the present invention, after the heat treatment step (step S5), a single crystal layer of a required thickness may be formed by epitaxial growth on the single crystal substrate 13. This epitaxial layer becomes a region where various elements, such as semiconductor elements that are components of electronic circuits, are formed. The thickness of the epitaxial layer required for forming various elements is not particularly limited, but is, for example, approximately 5 μm or more when the epitaxial layer is SiC single crystal.

[0083] Furthermore, when SiC is used for the single crystal substrate 13, it is not limited to 4H-SiC single crystal. SiC single crystals of various polytypes, such as 3C-SiC and 6H-SiC, can be used as the single crystal substrate 13. Furthermore, when SiC polycrystal is used for the support substrate 11, it is not limited to 3C-SiC polycrystal. SiC polycrystals of various polytypes can be used.

[0084] The present invention will be explained in more detail below by showing examples thereof, but the present invention is not limited to the following examples in any way.

[0085] Example 1 <Production of Bonded Semiconductor Substrate 10> A 4H-SiC single crystal substrate with a diameter of 6 inches, produced by sublimation deposition, was used as single crystal substrate 13. A 3C-SiC polycrystalline substrate with a diameter of 6 inches, obtained by depositing a polycrystalline SiC film by chemical vapor deposition, was used as support substrate 11. First, prior to the hydrogen ion implantation step, the bonding surfaces 11a and 13a of single crystal substrate 13 and support substrate 11 were mirror-polished and cleaned.

[0086] (Hydrogen ion implantation step S0) Hydrogen ions were implanted into the bonding target surface 13a of the single crystal substrate 13 at a position about 0.6 μm deep from the bonding target surface 13a to form a hydrogen implanted layer 15. This layer is delaminated by the formation of microbubbles due to the heat applied in the subsequent delamination step S4.

[0087] (Amorphous layer forming step S1) The single crystal substrate 13 was placed in a plasma injector (manufactured by ULVAC), and nitrogen (N) ions were injected into the entire surface of the bonding target surface 13a of the single crystal substrate 13, thereby forming an amorphous layer 12 with a thickness of 6 nm on the entire surface of the bonding target surface 13a. The plasma injection conditions were as follows: N gas, ２ The plasma power supply output for generating nitrogen ions was constant, the plasma injection temperature was room temperature (23°C), the acceleration voltage of the injected ions was 6 kV, and the dose was 5.5 × 10 １４ / cm ２ It was decided.

[0088] (Irradiation Step S2) The surfaces 11a and 13a to be joined were mirror-polished and cleaned, and then the surfaces 11a and 13a to be joined were irradiated with an argon beam.

[0089] Specifically, as shown in Fig. 5, the single crystal substrate 13 and the support substrate 11 were set in the chamber 101, and the relative positions of the single crystal substrate 13 and the support substrate 11 were aligned. Next, the chamber 101 was evacuated to a vacuum of 1 x 10 －４ ~1 x 10 －６ A vacuum was created so that the pressure in the chamber reached Pa.

[0090] Next, the surfaces 11a to be joined of the support substrate 11 and the surfaces 13a to be joined of the single crystal substrate 13 were irradiated with a neutral element beam of argon using the FAB gun 102. The neutral element beam of argon was uniformly irradiated onto the entire surfaces 11a to be joined and the entire surfaces 13a to be joined.

[0091] (Bonding process S3) After the irradiation process, the bonding surface 11 a of the activated support substrate 11 and the bonding surface 13 a of the single crystal substrate 13 were brought into contact with each other in the chamber 101 while maintaining a vacuum state, and further pressurization was applied to obtain a bonded substrate of the support substrate 11 and the single crystal substrate 13.

[0092] (Peeling step S4) Using a furnace, the bonded substrate was heated in an inert atmosphere filled with nitrogen gas, and single crystal substrate 13 was separated at hydrogen implanted layer 15 to form bonded substrate 30 bonded with thin single crystal substrate 13 having a thickness of 0.6 μm.

[0093] (Heat Treatment Step S5) After the separation step, bonded substrate 30 was heated at 1700° C. in an inert atmosphere filled with argon gas in a furnace to recrystallize amorphous layer 12, thereby obtaining bonded semiconductor substrate 10.

[0094] <Evaluation of Bonded Semiconductor Substrate 10> (Measurement of the Height of the Ripples at the Bonded Interface 14) Bonded semiconductor substrate 10 was cut so that the height of the ripples at the bonded interface 14 between support substrate 11 and single-crystal substrate 13 could be confirmed, and the cut surface was observed using a transmission electron microscope (TEM). FIG. 10 shows a TEM image of the cut surface. The observation direction of the cross section using TEM is [1-100] in Miller indices. As can be seen from FIG. 10, it was observed that support substrate 11 and single-crystal substrate 13 were bonded together in a completely intimate state with no gaps at bonded interface 14. Bonded interface 14 was not linear, but rather curved with wide ripples, as shown by the dotted line in FIG. 10. The width indicated by the dotted line is the width of the ripples at bonded interface 14, and assuming this to be the height of the ripples, the height of the ripples was 1.5 nm.

[0095] The undulation height of the bonding interface 14 was calculated as follows: First, a total of six points were selected from the undulating curve with a length of 50 nm at the bonding interface 14 in the TEM observation image of the cut surface: three points at the top of the undulations and three points at the bottom of the undulations. Next, the slope was calculated using the least squares method at these six points, and with the slope fixed, the least squares method was used to calculate the line connecting the three points at the top of the undulations and the line connecting the three points at the bottom of the undulations. The difference between the intercepts was taken as the undulation height.

[0096] (Measurement of fracture strength by stud-pull test) A stud-pull test was performed to confirm that the peel strength of the bonded interface 14 of the bonded semiconductor substrate 10 having the undulating bonded interface 14 observed in FIG. 10 is greater than the fracture strength of the single crystal substrate 13.

[0097] First, a chip measuring 10 mm in length and 10 mm in width was cut from bonded semiconductor substrate 10 and used as a test specimen. As shown in FIG. 11 , the surface of single-crystal substrate 13 in the test specimen was bonded to stud pin 50 with adhesive 40, and the surface of support substrate 11 was bonded to stud pin 51 with adhesive 41. After adhesives 40 and 41 hardened, stud pins 50 and 51 were pulled in directions P1 and P2, respectively, using a precision universal testing machine AGX-50kNVD (manufactured by Shimadzu Corporation), thereby pulling bonded semiconductor substrate 10 in a direction perpendicular to bonding interface 14 to fracture it. Eight test specimens were prepared, and a stud-pull test was performed eight times. The load at fracture of bonded semiconductor substrate 10 in the stud-pull test was measured as the maximum point load. The maximum point stress was calculated by dividing the maximum point load by the surface area where stud pin 50 contacts adhesive 40, and the average of the maximum point stresses over the eight tests was taken as the fracture strength. It was also confirmed whether the fractured portion was in the support substrate 11, the bonding interface 14, or the single crystal substrate 13.

[0098] For comparison, a stud-pull test was similarly carried out using only the single crystal substrate 13 to break the single crystal substrate 13, and the average value of the maximum stress calculated from eight measurements was taken as the breaking strength.

[0099] (Results of the stud-pull test) Bonded semiconductor substrate 10 fractured at support substrate 11, and bonded interface 14 after the stud-pull test did not peel off and maintained a good bonded state. The fracture strength of bonded semiconductor substrate 10 was 75.0 MPa. The in-plane distribution of maximum point stress in bonded semiconductor substrate 10 was the same at the center of the substrate and at the edge of the substrate. No decrease in maximum point stress due to the location of the substrate was observed.

[0100] On the other hand, the breaking strength of single crystal substrate 13 was 64.8 MPa. The reason why the breaking strength of single crystal substrate 13 was smaller than the breaking strength of bonded semiconductor substrate 10 is thought to be that in the case of single crystal substrate 13, cracks present at the substrate edge were the starting point, and the cracks extended along the crystal plane to cause fracture.

[0101] The amorphous layer forming step was carried out under the same conditions as in Example 1, and an amorphous layer 12 having a thickness of 6 nm was formed on the entire surface of the bonding target surface 13 a of the single crystal substrate 13, and an amorphous layer having a thickness of 6 nm was formed on the entire surface of the bonding target surface 11 a of the support substrate 11. The other steps were carried out under the same conditions as in Example 1, and a bonded semiconductor substrate was manufactured.

[0102] The cut surface was observed with a transmission electron microscope (TEM) in the same manner as in Example 1, and the height of the undulations at the bonding interface was measured, which was found to be 3.0 nm. It was confirmed that the height of the undulations also increased by increasing the thickness of the amorphous layer.

[0103] <Effects> In the present invention, by amorphizing either or both of the bonding surface 11 a of the support substrate 11 and the bonding surface 13 a of the single-crystal substrate 13, the atoms constituting the substrates are made more mobile, and an uneven bonding interface is formed. This increases the bonding area between the support substrate 11 and the single-crystal substrate 13 and strengthens the bonding strength, thereby preventing delamination at the bonding interface 14.

[0104] (Summary) As described above, the present invention can provide a bonded semiconductor substrate and a method for manufacturing a bonded semiconductor substrate that can prevent peeling at the bonded interface, and is therefore industrially useful.

[0105] 10: bonded semiconductor substrate, 11: support substrate, 11a: surface to be bonded, 12: amorphous layer, 13: single crystal substrate, 13a: surface to be bonded, 14: bonded interface, 15: hydrogen implanted layer, 30: bonded substrate, 40: adhesive layer, 41: adhesive layer, 50: stud pin, 51: stud pin, 101: chamber, 102: FAB gun, 103: neutral element beam, P1: direction, P2: direction

Claims

1. A bonded semiconductor substrate comprising a first semiconductor substrate and a second semiconductor substrate bonded to the first semiconductor substrate via a bonding interface, wherein the undulation height of the bonding interface is 1.5 nm or more.

2. The bonded semiconductor substrate according to claim 1, which has a fracture strength of 70 MPa or more in a direction perpendicular to the bonded interface in a stud pull test.

3. The first semiconductor substrate and the second semiconductor substrate are made of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga ２ O ３ 2. The bonded semiconductor substrate of claim 1, wherein the bonded semiconductor substrate is one of: SiO 2 , SiO 2 , and diamond.

4. The bonded semiconductor substrate of claim 1, wherein said first semiconductor substrate is a monocrystalline silicon carbide substrate and said second semiconductor substrate is a polycrystalline silicon carbide substrate.

5. A method for manufacturing a bonded semiconductor substrate comprising a first semiconductor substrate and a second semiconductor substrate in contact with the first semiconductor substrate, comprising: an amorphous layer formation step of forming an amorphous layer on at least one of a surface of a first bonding target surface, which is the surface of the first semiconductor substrate where the first semiconductor substrate is bonded to the second semiconductor substrate, or a surface of a second bonding target surface, which is the surface of the second semiconductor substrate where the second semiconductor substrate is bonded to the first semiconductor substrate; a bonding step of bonding the first bonding target surface and the second bonding target surface to form a bonded substrate having a bonding interface; and a heat treatment step of heat treating the bonded substrate to set the undulation height of the bonding interface to 1.5 nm or more, wherein the thickness of the amorphous layer formed in the amorphous layer formation step is 5 nm or more.

6. The first semiconductor substrate and the second semiconductor substrate are made of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga ２ O ３ 6. The method of claim 5, wherein the material is one of the following: silicon dioxide; 7. The method for producing a junction semiconductor substrate according to claim 5, wherein at least one of silicon (Si), carbon (C), helium (He), neon (Ne), argon (Ar), xenon (Xe), hydrogen (H), nitrogen (N), phosphorus (P), boron (B), and aluminum (Al) is present in the amorphous layer.

8. A method for manufacturing a bonded semiconductor substrate as described in claim 5, wherein the amorphous layer formation step is a step of forming the amorphous layer by performing a plasma injection process on at least one of the surface of the first bonding target surface or the surface of the second bonding target surface.

9. The method for producing a bonded semiconductor substrate according to claim 5, wherein the heat treatment step is a step of maintaining the temperature of the bonded substrate at 1100°C to 2200°C.

10. A method for manufacturing a bonded semiconductor substrate as set forth in claim 5, further comprising an ion implantation step of implanting hydrogen ions or helium ions into said first bonding surface before or after said amorphous layer formation step to form an ion implantation layer inside said first semiconductor substrate.

11. The method for manufacturing a bonded semiconductor substrate as described in claim 10, further comprising a peeling step after the bonding step and before the heat treatment step, the peeling step being a step of peeling off a part of the first semiconductor substrate using a microbubble layer formed by heating the ion implantation layer as a peeling surface.

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