Gamma voltage generation circuit and source driver circuit

Abstract

This embodiment provides a gamma voltage generation circuit and a source driver circuit including same, the gamma voltage generation circuit comprising: a first voltage distribution unit for outputting a plurality of voltages having different voltage levels; a plurality of amplifiers for outputting, as gamma reference voltages, the voltages output from the first voltage distribution unit; a second voltage distribution unit including a plurality of reference nodes for outputting the gamma reference voltages and distribution nodes for outputting a plurality of gamma distribution voltages by using resistors connected between the plurality of reference nodes; and a connection circuit for short-circuiting a reference node, in which a gamma reference voltage has been changed, with an adjacent distribution node.

Description

Gamma voltage generation circuit and source driver circuit

[0001] The embodiment relates to a gamma voltage generation circuit and a source driver circuit.

[0002] Various flat panel displays are known, including liquid crystal displays (LCDs), organic light emitting diode displays (OLEDs), electroluminescence displays (ELDs), field emission displays (FEDs), plasma display panels (PDPs), and electrophoresis displays (EPDs).

[0003] A display device may include a display panel on which pixels for displaying an input image are arranged, and a display panel driving circuit for writing data into the pixels of the display panel. The display panel driving circuit may include a data driving circuit for supplying data signals of source data to data lines of the display panel, and a gate driving circuit for supplying gate signals to gate lines of the display panel.

[0004] The display panel driving circuit may include a gamma voltage generation circuit that supplies a gamma voltage to a data driving circuit. Since the gamma voltage output from the gamma voltage generation circuit is generated by driving an amplifier and a voltage distribution circuit, there is a problem that the connected gamma voltage changes as the data voltage changes, and the settling time until the amplifier reaches the gamma voltage level again becomes longer.

[0005] The embodiment provides a gamma voltage generation circuit and a source driver circuit capable of improving settling time.

[0006] The tasks of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0007] A gamma voltage generation circuit according to one feature of the present invention includes: a first voltage distribution unit that outputs a plurality of voltages having different voltage levels; a plurality of amplifiers that output voltages output from the first voltage distribution unit as gamma reference voltages; a second voltage distribution unit that includes a plurality of reference nodes that output the gamma reference voltages and a distribution node that outputs a plurality of gamma distribution voltages by a resistor connected between the plurality of reference nodes; and a connection circuit that short-circuits a reference node at which a gamma reference voltage is varied with an adjacent distribution node.

[0008] The above-mentioned connection circuit may include a switch circuit including a plurality of switches that form a path bypassing a resistor arranged between the reference node and the distribution node to short-circuit the reference node and an adjacent distribution node; and a sensing circuit that senses a voltage change of the plurality of amplifiers to turn on the plurality of switches.

[0009] The sensing circuit may include a plurality of sensing units that are respectively connected to the plurality of amplifiers and sense changes in control voltages of the amplifiers, and the switch circuit may include a switch array that is respectively connected to the plurality of sensing units, and the switch array may include a high-potential connection switch that is connected to a first distribution node having a higher voltage than the reference node and a low-potential connection switch that is connected to a second distribution node having a lower voltage than the reference node.

[0010] Among the plurality of sensing units, a low-potential connection switch connected to a first sensing unit and a high-potential connection switch connected to a second sensing unit adjacent to the first sensing unit can be connected to the same distribution node.

[0011] The plurality of sensing units may include a first sensor that detects a change in a first control voltage applied to a first output transistor of the amplifier, a second sensor that detects a change in a second control voltage applied to a second output transistor of the amplifier, and a switch control unit that outputs a signal for driving a plurality of switches according to an output signal of the first sensor or the second sensor.

[0012] The first sensor can apply an output signal to the switch control unit when the first control voltage applied to the first output transistor falls below a predetermined voltage level.

[0013] The second sensor can apply an output signal to the switch control unit when the second control voltage of the second output transistor rises above a predetermined voltage level.

[0014] The above switch control unit can output a turn-on signal to the high-potential connection switch and the low-potential connection switch when an output signal is applied from the first sensor or the second sensor.

[0015] The sensing circuit may include a sensing unit that detects voltage changes of the plurality of amplifiers; and a switch control unit that selectively applies a turn-on signal to a plurality of switches according to the voltage change level detected by the sensing unit.

[0016] A source driver circuit according to one feature of the present invention includes a data driving unit that converts source data into data voltages based on gamma voltages; and a gamma voltage generating unit that generates the gamma voltages, wherein the gamma voltage generating unit includes: a first voltage distribution unit that outputs a plurality of voltages having different voltage levels; a plurality of amplifiers that output voltages output from the first voltage distribution unit as gamma reference voltages; a second voltage distribution unit that includes a plurality of reference nodes that output the gamma reference voltages and a distribution node that outputs a plurality of gamma distribution voltages by a resistor connected between the plurality of reference nodes; and a connection circuit that connects a reference node from which a gamma reference voltage with a changed voltage level is output to an adjacent distribution node.

[0017] In an embodiment, the settling time for the gamma voltage to be restored to a reference level can be improved, resulting in high-speed operation of the display (e.g., 120 Hz).

[0018] The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

[0019] FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention.

[0020] Figure 2 is a block diagram schematically showing the circuit configuration of the data drive unit.

[0021] FIG. 3 is a block diagram showing a gamma voltage generation unit according to one embodiment of the present invention.

[0022] FIG. 4 is a circuit diagram showing a gamma voltage generation unit according to one embodiment of the present invention.

[0023] FIG. 5 is a diagram showing the structure of an amplifier, a sensing circuit, and a switching circuit according to one embodiment of the present invention.

[0024] Fig. 6 is a waveform diagram of the output voltage of the amplifier connected in a low voltage state of the data voltage, the first control voltage of the amplifier, the first sensing signal, and the second sensing signal.

[0025] Fig. 7 is a waveform diagram of the output voltage of the amplifier connected in a high voltage state with the data voltage, the first control voltage of the amplifier, the first sensing signal, and the second sensing signal.

[0026] FIG. 8 is a diagram showing a state in which switches connected to the first to third sensing units are turned on and the first to seventh nodes are connected according to one embodiment of the present invention.

[0027] FIG. 9 is a diagram showing a state in which switches connected to a first sensing unit and a second sensing unit are turned on and nodes 1 to 5 are connected according to one embodiment of the present invention.

[0028] Fig. 10 is a circuit diagram showing a gamma voltage generation unit according to another embodiment of the present invention.

[0029] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. The embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0030] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the details depicted in the drawings. Throughout the specification, the same reference numerals designate substantially the same components. Furthermore, in describing the present invention, detailed descriptions of related known technologies will be omitted if they are deemed to unnecessarily obscure the gist of the present invention.

[0031] In the specification, when “comprising,” “may include,” “have,” and “consist of,” other parts may be added unless “only” is used. When a component is expressed in the singular, it may be interpreted as plural unless there is a special explicit statement.

[0032] When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

[0033] When the positional relationship and interconnectedness between two components are described as ‘on’, ‘above’, ‘below’, ‘next to’, ‘connect, couple’, crossing, intersecting, etc., one or more other components may be interposed between the components unless there is a mention of ‘directly’ or ‘directly’.

[0034] When the temporal relationship is explained with phrases such as ‘after’, ‘following’, ‘next to’, or ‘before’, it may not be continuous on the time axis unless ‘right away’ or ‘directly’ is used.

[0035] Although first, second, etc. may be used to distinguish components, the function or structure of these components is not limited by the ordinal number or component name attached to the front of the component.

[0036] The following embodiments can be partially or fully combined or combined with one another, enabling various technically diverse interconnections and operations. Each embodiment can be implemented independently of the other, or can be implemented together in a related manner.

[0037] In the following embodiments, the transistor is a three-electrode device including a gate, a source, and a drain. In the case of an n-channel transistor, since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In the n-channel transistor, the direction of current flows from the drain to the source. In the case of a p-channel transistor (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In the p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. The source and drain of the transistor are not fixed. In the following description, the source and drain of the transistor will be referred to as the first and second electrodes.

[0038] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

[0039] FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention.

[0040] Referring to FIG. 1, a display device according to an embodiment of the present invention may include a display panel (100) and a display panel driving circuit for writing source data into pixels of the display panel (100). The source data may be interpreted as pixel data.

[0041] The substrate of the display panel (100) may be, but is not limited to, a plastic substrate, a thin glass substrate, or a metal substrate. The display panel (100) may be, but is not limited to, a rectangular panel having a length in a first direction, a width in a second direction, and a thickness in a third direction. In Fig. 1, X, Y, and Z may be, but are not limited to, the first direction, the second direction, and the third direction, respectively.

[0042] In the case of a liquid crystal display (LCD), a backlight unit (BLU) may be placed under the display panel (100). In the case of a self-luminous display such as an electroluminescent display, a separate light source such as a backlight unit is not required.

[0043] The display area (AA) of the display panel (100) may include a pixel array that displays an input image. The pixel array may include a plurality of data lines (102), a plurality of gate lines (103) intersecting the data lines (102), and pixels (101) connected to the data lines (102) and the gate lines (103).

[0044] Each of the pixels (101) may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color implementation. Each of the pixels may further include a white sub-pixel. In a liquid crystal display, the pixels may include a liquid crystal cell. In an electroluminescent display, the pixels may include a light-emitting element such as an OLED. Each of the sub-pixels may include a pixel circuit for driving the liquid crystal cell or the light-emitting element.

[0045] The display panel driving circuit writes source data of an input image to pixels of the display panel (100) under the control of a timing controller (130). The display panel driving circuit may include a source driver circuit that converts the source data into a data voltage and a gate driver (120). The source driver circuit may include a gamma voltage generator (200) and a data driver (110).

[0046] The display panel driving circuit may further include a touch sensor driving unit for driving touch sensors. The touch sensor driving unit is omitted in Fig. 1. In a mobile terminal or wearable terminal, the timing controller (130), data driving unit (110), touch sensor driving unit, etc. may be integrated into a single drive IC.

[0047] The data driving unit (110) receives the source data of the input image as a digital signal from the timing controller (130) and outputs a data voltage. The data driving unit (110) converts the source data of the input image into a gamma compensation voltage using a DA conversion unit (Digital to Analog Converter) and outputs the data voltage.

[0048] The gamma voltage generation unit (200) can generate a plurality of gamma voltages having different voltage levels and provide them to the data driving unit (110). The gamma voltage can be interpreted as including a gamma reference voltage, a gamma tap voltage, and a gamma distribution voltage. In the case of a light-emitting element, the light-emitting efficiency can be different for each color. In accordance with such light-emitting efficiency characteristics for each color, the gamma voltages can be separated into independent voltages for each color according to the colors of the sub-pixels. The gamma voltage generation unit (200) can be included in the data driving unit (110) to configure a source driver circuit.

[0049] The gamma voltages generated by the gamma voltage generation unit (200) are supplied to the data driving unit (110). The gamma voltages can be divided into grayscale voltages corresponding to each grayscale of the source data in the data driving unit (110) and supplied to the DA conversion unit. The DA conversion unit converts the source data, which is a digital signal, into an analog data voltage by outputting a grayscale voltage corresponding to the grayscale value of the source data using a plurality of transistors. The data voltage output from the DA conversion unit is output to the data line (102) through an output buffer from each of the data output channels of the data driving unit (110).

[0050] The circuit of the gate driver (120) may be placed in a non-display area (NA) outside the display area (AA) of the display panel (100), or at least part of it may be placed in the display area (AA). The gate driver (120) may be integrated into a separate gate drive IC and electrically connected to the gate lines (103) of the display panel (100).

[0051] The gate driver (120) sequentially outputs pulses of gate signals to the gate lines under the control of the timing controller (130). The gate driver (120) can sequentially supply pulses of gate signals to the gate lines (103) by shifting the pulses of the gate signals using a shift register.

[0052] The timing controller (130) receives the source data of the input image from an external host system (10) and a timing signal synchronized with the data. The timing signal may include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), a main clock, etc. Since the vertical period and the horizontal period can be known by counting the data enable signal (DE), the vertical synchronization signal (Vsync) and the horizontal synchronization signal (Hsync) may be omitted. The vertical synchronization signal (Vsync) has a cycle of one frame period. The horizontal synchronization signal (Hsync) and the data enable signal (DE) have cycles of one horizontal period (1H).

[0053] The timing controller (130) controls the operation timing of the display panel driving circuit (110, 120) based on the timing signal (Vsync, Hsync, DE) received from the host system (10).

[0054] The host system (10) can scale a video signal from a video source to match the resolution of the display panel (100) and transmit the scaled signal along with a timing signal to the timing controller (130). In a mobile system, the host system (10) can be implemented as an AP (Application Processor). The host system (10) can transmit source data of an input image to the drive IC through a MIPI (Mobile Industry Processor Interface). The host system (10) can be electrically connected to the drive IC through a flexible printed circuit, for example, an FPC (Flexible Printed Circuit). The drive IC can be bonded onto the display panel (100) in a COG (Chip on glass) process. The drive IC can be a COF (Chip on film) mounted on a flexible circuit film. The COF can be bonded to data pads arranged in a non-display area of ​​the display panel (100) in a bonding process and electrically connected to data lines on the display panel (100).

[0055] Fig. 2 is a block diagram schematically showing the circuit configuration of a data driving unit. Fig. 3 is a block diagram showing a gamma voltage generation unit according to one embodiment of the present invention.

[0056] Referring to FIGS. 2 and 3, the data driving unit (110) may include a receiving unit (111), a logic control unit (112), a shift register (113), a first latch (114), a second latch (115), a DA conversion unit (117), and an output buffer (118).

[0057] The receiving unit (111) can receive data (DATA) serially received from the timing controller (130), restore a clock from the data (DATA), and sample control data and source data of an input image from the data (DATA) using the restored clock, and provide the sampled data to the logic control unit (112). The timing controller (130) can convert the clock and data into differential signals and transmit them to the data driving unit (110) through a serial interface.

[0058] The logic control unit (112) rearranges pixel data supplied from the receiving unit (111) into sub-pixel units. The logic control unit (112) supplies a start pulse and a clock to the shift register (113) using the restored clock and control data, and can control the output timing of the first and second latch units (114, 115) and the output buffer (118).

[0059] The shift register (113), the first latch (114), and the second latch (115) convert data in a serial system into data in a parallel system. When a start pulse is input, the shift register (113) shifts the clock and outputs it to the channels of the first latch (114). The first latch (114) samples the source data input from the receiving unit (111) through the logic control unit (112) in response to the clock sequentially input from the shift register (113), and when the source data is latched in all channels, the latched data can be simultaneously output to the channels of the second latch (115). The second latch (115) latches data simultaneously received from the first latch (114), and can simultaneously output the latched data to the DA conversion unit (117) in response to an output enable signal from the logic control unit (112).

[0060] The gamma voltage generation unit (200) can supply a plurality of gamma voltages to the DA conversion unit (117). Between the gamma voltage generation unit (200) and the DA conversion unit (117), a grayscale voltage generation unit can be arranged that divides the plurality of gamma voltages to generate grayscale voltages corresponding to each grayscale of the source data and supplies the generated grayscale voltages to the DA conversion unit (117).

[0061] The DA converter (117) can select a grayscale voltage corresponding to the grayscale value of source data input from the second latch (115) and output it as a data voltage (Vdata). The data voltage (Vdata) can be output through the output buffer (118) and applied to the data lines (102) of the display panel (100).

[0062] As the grayscale of the source data decreases, the data voltage (Vdata) output through the DA converter (117) may decrease. On the other hand, as the grayscale of the source data increases, the data voltage (Vdata) may increase. Therefore, the data voltage may change instantaneously according to the grayscale value of the pixel, and the gamma voltage may also change according to the change in the data voltage at the output node of the gamma voltage generator (200) connected to the DA converter (117). The amplifier of the gamma voltage generator (200) may receive the output voltage as feedback and restore it to the original gamma voltage level, but it may take a considerable amount of time, which may increase the settling time. Therefore, the constrained driving of the display may become difficult.

[0063] Referring to FIG. 3, the gamma voltage generation unit (200) may include an amplifier unit (220) including a plurality of amplifiers that output gamma voltages, a second voltage distribution unit (250) that divides a gamma reference voltage into a plurality of gamma distribution voltages, a sensing circuit (230) that senses a control voltage of the amplifier, and a switch circuit (240) that selectively turns on a switch connected to the second voltage distribution unit (250) according to a control signal of the sensing circuit (230).

[0064] According to an embodiment, a sensing circuit (230) can sense a change in a gamma reference voltage output from a plurality of amplifiers to detect an amplifier whose gamma reference voltage (output voltage) has changed, and adjust a switching circuit (240) so that the changed gamma reference voltage can be quickly restored to the original voltage level.

[0065] FIG. 4 is a circuit diagram showing a gamma voltage generation unit according to one embodiment of the present invention.

[0066] Referring to FIG. 4, the gamma voltage generation unit (200) includes a first voltage distribution unit (210) that outputs a plurality of voltages having different voltage levels, a plurality of amplifiers (AMP1 to ANPn) connected to the first voltage distribution unit (210), a second voltage distribution unit (250) connected to the plurality of amplifiers (AMP1 to ANPn), and a connection circuit (230, 240) that connects a reference node where a gamma reference voltage is changed to an adjacent distribution node.

[0067] A high-potential reference voltage (GVDD), a low-potential reference voltage (GVSS), an amplifier driving voltage, etc. are applied to the gamma voltage generation unit (200). The voltage levels of the high-potential reference voltage (GVDD) and the low-potential reference voltage (GVSS) may vary when the brightness is adjusted by the host system. For example, the low-potential reference voltage may increase when the brightness becomes dark depending on the illumination of the user interface or the usage environment.

[0068] The gamma voltage generation unit (200) can output 2n+1 gamma voltages (n is a natural number) having different voltage levels. The gamma voltage can be defined as including a gamma reference voltage output from a plurality of amplifiers (AMP1 to ANPn) and a gamma distribution voltage output from a distribution node (DN) arranged between the resistors of the second voltage distribution unit (250). The gamma voltages output from the gamma voltage generation unit (200) through adjacent output nodes have a predetermined voltage difference.

[0069] The first voltage distribution unit (210) includes a plurality of resistors connected in series. The first voltage distribution unit (210) divides the high-potential reference voltage (GVDD) between the high-potential reference voltage (GVDD) and the low-potential reference voltage (GVSS) to generate n input voltages (G1 to Gn) having different voltage levels (n is a natural number) through distribution nodes.

[0070] A plurality of amplifiers (AMP1 to AMPn) can be interpreted as a buffer or voltage follower composed of operational amplifiers. Each amplifier includes a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal.

[0071] A plurality of amplifiers (AMP1 to AMPn) can output an input voltage (G1 to Gn) input to a non-inverting input terminal (+) as a gamma reference voltage. The inverting input terminal (-) and the output terminal of the amplifiers can be connected to an output node of a second voltage distribution unit (250) from which the gamma reference voltage is output.

[0072] The second voltage divider (250) includes a plurality of resistors connected in series. The second voltage divider (250) can divide the gamma reference voltage between the first gamma voltage (V1) and the second n+1 gamma voltage (V2n+1).

[0073] The dynamic range of the data voltage (Vdata) output from each channel of the data driving unit can be determined by the voltage range of the first gamma voltage (V1) and the second n+1 gamma voltage (V2n+1). However, the present embodiments are not limited thereto. For example, the first gamma voltage (V1) to the second n+1 gamma voltage (V2n+1) may be divided to generate grayscale voltages corresponding to each grayscale of the source data and supply the voltages to the DA conversion unit (117).

[0074] The output nodes (RN, DN) of the second voltage distribution unit (250) may include a plurality of reference nodes (RN) from which a plurality of gamma reference voltages are output, and a plurality of distribution nodes (DN) that output a plurality of gamma distribution voltages by resistors connected between the plurality of reference nodes. The reference nodes (RN) and distribution nodes (DN) may be defined to distinguish their positions, and both may be defined as output nodes or output terminals.

[0075] The second voltage distribution unit (250) may include a first output node to a 2n+1 output node (OTN1 to OTN2n+1) from which a gamma voltage is output. The second output node (OTN2), the fourth output node (OTN4), the sixth output node (OTN6) to the 2nth output node (OTN2n) may be a reference node (RN) from which a gamma reference voltage is output. The first output node (OTN1), the third output node (OTN3), the fifth output node (OTN5), the 2n-1th output node (OTN2n-1), and the 2n+1th output node (OTN2n+1) may be a distribution node (DN) from which a gamma distribution voltage is output.

[0076] The connection circuit (230, 240) can connect the output nodes of the second voltage distribution unit (250) whose gamma voltage fluctuates in the process of being connected to the DA conversion unit (117) according to changes in the source data. The DA conversion unit (117) can convert the source data, which is a digital signal, into an analog data voltage by selecting a gamma voltage corresponding to the grayscale value of the source data using a plurality of transistors. Therefore, the DA conversion unit (117) can connect the corresponding gamma voltage according to the grayscale value of the source data. However, if the output data voltage is connected to a gamma voltage with a high voltage level in a low voltage state, the connected gamma voltage may be lowered momentarily.

[0077] Conversely, if a high output data voltage is connected to a relatively low-voltage gamma voltage, the connected gamma voltage may momentarily increase. While the amplifier can receive feedback on the output gamma voltage and control it, there is a problem in that it takes a relatively long time until the gamma voltage is adjusted to the same level as the input voltage.

[0078] The connection circuit (230, 240) according to the embodiment has the advantage of reducing the settling time by connecting and short-circuiting the output nodes of the second voltage distribution unit (250) whose gamma voltage fluctuates in the process of being connected to the DA conversion unit (117) according to the change in the grayscale of the source data.

[0079] The connection circuit (230, 240) may include a sensing circuit (230) that senses a change in the output voltage of the amplifier and a switch circuit (240) that includes a plurality of switches (SW1 to SWn) that selectively connect and short-circuit the output node.

[0080] The sensing circuit (230) may include a plurality of sensing units (SP1 to SPn) each connected to a plurality of amplifiers (AMP1 to ANPn). The first sensing unit (SP1) may be connected to the first amplifier (AMP1) to sense a change in the output voltage, the second sensing unit (SP2) may be connected to the second amplifier (AMP2) to sense a change in the output voltage, and the n-th sensing unit (SPn) may be connected to the n-th amplifier (AMPn) to sense a change in the output voltage.

[0081] The switch circuit (240) may include a switch array connected to each sensing unit. The switch array may include a high-potential connection switch connected to a first distribution node having a higher voltage than a reference node, and a low-potential connection switch connected to a second distribution node having a lower voltage than the reference node. For example, one sensing unit may be connected to two switches. However, the present embodiments are not limited thereto. For example, the switch circuit (240) may include three or more switches connected to one sensing unit.

[0082] A first switch (SW1) can connect a second output node (OTN2) from which a second gamma voltage (V2) is output to a first output node (OTN1) from which a first gamma voltage (V1) is output. The first switch (SW1) can be a high-potential connection switch.

[0083] The second switch (SW2) can connect the second output node (OTN2) from which the second gamma voltage (V2) is output to the third output node (OTN3) from which the third gamma voltage (V3) is output. The second switch (SW2) can be a low-voltage connection switch.

[0084] The second output node (OTN2) can be connected to the first output node (OTN1) by the first switch (SW1) and can be connected to the third output node (OTN3) by the second switch (SW2).

[0085] The second output node (OTN2) may be a reference node from which a gamma reference voltage is output, the first output node (OTN1) may be a first voltage dividing node or a high-potential voltage dividing node having a higher voltage than the reference node, and the third output node (OTN3) may be a second voltage dividing node or a low-potential voltage dividing node having a lower voltage than the reference node. Accordingly, a pair of switches connected to one sensing unit may connect the reference node to the adjacent first voltage dividing node and second voltage dividing node.

[0086] The third switch (SW3) can connect the fourth output node (OTN4) from which the fourth gamma voltage (V4) is output to the third output node (OTN3) from which the third gamma voltage (V3) is output.

[0087] The fourth switch (SW4) can connect the fourth output node (OTN4) to the fifth output node (OTN5) from which the fifth gamma voltage (V5) is output.

[0088] The third output node (OTN3) can be connected to the second output node (OTN2) by the second switch (SW2) and can be connected to the fourth output node (OTN4) by the third switch (SW3).

[0089] The fifth switch (SW5) can connect the sixth output node (OTN6) from which the sixth gamma voltage (V6) output from the third amplifier (AMP3) is output to the fifth output node (OTN5) from which the fifth gamma voltage (V5) is output.

[0090] The sixth switch (SW6) can connect the sixth output node (OTN6) to the seventh output node (OTN7) from which the seventh gamma voltage (V7) is output.

[0091] The fifth output node (OTN5) can be connected to the fourth output node (OTN4) by the fourth switch (SW4) and can be connected to the sixth output node (OTN6) by the fifth switch (SW5).

[0092] FIG. 5 is a diagram showing the structure of an amplifier, a sensing circuit, and a switch circuit according to one embodiment of the present invention.

[0093] Referring to Figure 5, the amplifier may include a plurality of transistors and capacitors. Figure 5 shows a connection circuit connected to the second amplifier.

[0094] The amplifier may include a voltage follower structure including an input stage (221), a current adding stage (222), and an output stage (223). The operational amplifier may differentially amplify the difference between an input voltage (VIN) and an output voltage (VOUT) to generate an output voltage (VOUT) that quickly follows the input voltage (VIN).

[0095] The input stage (221) can monitor the difference between the input voltage (VIN) input to the non-inverting terminal and the output voltage (VOUT) fed back and input to the inverting terminal, thereby controlling the control currents (I1 to I4) provided from the current adding stage (222).

[0096] The current adding stage (222) can generate control currents (I1 to I4) that are provided to the input stage (221) by amplifying the current according to the difference between the input voltage (VIN) and the output voltage (VOUT) together with the input stage (221), and can generate output currents and control voltages (HIP, HIN) that are adjusted according to the control currents (I1 to I4) and provide them to the output stage (223).

[0097] Among the control currents (I1 to I4) generated in the current adding stage (222), the currents (I1, I2) flowing from the current adding stage (222) to the input stage (221) are sink currents, and the control currents (I3, I4) flowing from the input stage (221) to the current adding stage (222) are source currents.

[0098] The output stage (223) can output an output voltage (VOUT) that follows the input voltage (VIN) through an output terminal by performing a pull-up operation and a pull-down operation according to the control voltage (HIP, HIN) provided from the current adding stage (222).

[0099] The input stage (221) may include a first input section composed of PMOS transistors (PM1, PM2), a second input section composed of NMOS transistors (NM1, NM2), a first bias circuit composed of a PMOS transistor (PM3), and a second bias circuit composed of an NMOS transistor (NM3).

[0100] The PMOS transistors (PM1, PM2) of the first input section are controlled by the input voltage (VIN) and the output voltage (VOUT), respectively, and the source current (I3, I4) provided by the current adding stage (222) can be adjusted according to the input voltage (VIN) and the output voltage (VOUT).

[0101] The NMOS transistors (NM1, NM2) of the second input section are controlled by the input voltage (VIN) and the output voltage (VOUT), respectively, and the sink current (I1, I2) provided by the current adding stage (222) can be adjusted according to the input voltage (VIN) and the output voltage (VOUT).

[0102] The PMOS transistor (PM3) of the first bias circuit is connected between the supply line of the first power source (high-potential power source) (AVDDH) and the first input section, and can provide a bias current to the PMOS transistors (PM1, PM2) of the first input section by being controlled by the bias voltage (VB1).

[0103] The NMOS transistor (NM3) of the second bias circuit is connected between the second input section and the second power (low potential power) (AVSS) supply line, and can provide a bias current to the NMOS transistors (NM1, NM2) of the second input section by being controlled by the second bias voltage (VB2).

[0104] The current adding stage (222) may include a first current mirror composed of PMOS transistors (PM4, PM5), a first cascode circuit composed of PMOS transistors (PM6, PM7), a second current mirror composed of NMOS transistors (NM4, NM5), a second cascode circuit composed of NMOS transistors (NM6, NM7), a third bias circuit composed of PMOS and NMOS transistors (PM8, NM8), and a fourth bias circuit composed of PMOS and NMOS transistors (PM9, NM9). The third and fourth bias circuits may each be defined as floating bias circuits.

[0105] The PMOS transistors (PM4, PM5) of the first current mirror are connected to the NMOS transistors (NM1, NM2) of the second input section of the input stage (221) and are connected in the form of a current mirror between the supply line of the first power source (AVDDH) and the first cascode circuit. The gate electrodes of the PMOS transistors (PM4, PM5) of the first current mirror are connected to the output node (N3) of the first cascode circuit. The PMOS transistors (PM4, PM5) of the first current mirror can provide sink currents (I1, I2) to the NMOS transistors (NM1, NM2) of the first input section through the output nodes (N2, N1), provide output currents through the first cascode circuit, and provide output currents to the capacitor (C1) of the output stage (223) through the output nodes.

[0106] The PMOS transistors (PM6, PM7) of the first cascode circuit are connected between the first current mirror and the third and fourth bias circuits, and are controlled by the third bias voltage (VB3) to provide the first control voltage (HIP) to the output stage (223) through the output node (N7).

[0107] The fourth and fifth NMOS transistors (NM4, NM5) of the second current mirror are connected to the first input PMOS transistors (PM1, PM2) of the input stage (221) and are connected in the form of a current mirror between the second cascode circuit and the supply line of the second power source (VSS). The gate electrodes of the NMOS transistors (NM4, NM5) of the second current mirror are connected to the output node (N5) of the second cascode circuit. The NMOS transistors (NM4, NM5) of the second current mirror can provide source currents (I3, I4) to the PMOS transistors (PM1, PM2) of the second input section through the output nodes, provide output current through the second cascode circuit, and provide output current to the capacitor (C2) of the output stage (223) through the output node (N6).

[0108] The NMOS transistors (NM6, NM7) of the second cascode circuit are connected between the third and fourth bias circuits and the second current mirror, and are controlled by the fourth bias voltage (VB3) to provide the second control voltage (HIN) to the output stage (223) through the output node (N8).

[0109] The PMOS transistor (PM8) and the NMOS transistor (NM8) of the third bias circuit are connected between the PMOS transistor (PM6) of the first cascode circuit and the NMOS transistor (NM6) of the second cascode circuit, and are controlled by the fifth and sixth bias voltages (VB5, VB6), respectively, to provide a bias current flowing from the output node (N3) of the first cascode circuit to the output node (N5) of the second cascode circuit.

[0110] The PMOS transistor (PM9) and the NMOS transistor (NM9) of the fourth bias circuit are connected between the PMOS transistor (PM7) of the first cascode circuit and the NMOS transistor (NM7) of the second cascode circuit, and are controlled by the seventh and eighth bias voltages (VB7, VB8), respectively, to provide a bias current flowing from the output node (N7) of the first cascode circuit to the output node (N8) of the second cascode circuit.

[0111] The output stage (223) may include a pull-up PMOS transistor (PM10), a pull-down NMOS transistor (NM10), and capacitor sections (C1, C2). The pull-up PMOS transistor (PM10) may be defined as a first output transistor, and the pull-down NMOS transistor (NM10) may be defined as a second output transistor.

[0112] A pull-up PMOS transistor (PM10) is controlled by a first control voltage (HIP) provided from a first output node (N7) of a current adding stage (222) and is connected between a first power supply (AVDDH) supply line and an output terminal. The pull-up PMOS transistor (PM10) can perform a pull-up operation under the control of the first control voltage (HIP) to increase the output voltage (VOUT).

[0113] The pull-down NMOS transistor (NM10) is controlled by a second control voltage (HIN) provided from the second output node (N8) of the current adding stage (222) and is connected between the output terminal and the second power supply (VSS) line. The pull-down NMOS transistor (NM10) can perform a pull-down operation under the control of the second control voltage (HIN) to reduce the output voltage (VOUT).

[0114] The capacitor section may include a first capacitor (C1) connected between the third output node (N4) of the current adding stage (222) and the output terminal, and a second capacitor (C2) connected between the fourth output node (N6) of the current adding stage (222) and the output terminal. The capacitor section may stabilize the output voltage (VOUT) so that it does not oscillate when it rises or falls.

[0115] The current adding stage (222) can provide output current to the first capacitor (C1) through the third output node (N4) connected to the first current mirror, and can provide output current to the second capacitor (C2) through the fourth output node (N6) connected to the second current mirror.

[0116] The sensing circuit (230) may include a first sensor (231) that applies a first output signal (SOR) when a first control voltage (HIP) applied to a pull-up PMOS transistor (PM10) satisfies a predetermined level, a second sensor (232) that applies a second output signal (SOF) when a second control voltage (HIN) applied to a pull-down NMOS transistor (NM10) satisfies a predetermined level, and a switch control unit (233) that outputs a control signal for turning on a switch connected to an output terminal when the first output signal (SOR) or the second output signal (SOF) is applied.

[0117] The first sensor (231) can apply an output signal when the first control voltage (HIP) is below a predetermined level. Accordingly, when the first control voltage (HIP) falls to a predetermined level, the first output signal (SOR) is transmitted, and when the first control voltage (HIP) rises above the predetermined level, the first output signal (SOR) may not be transmitted. The first output signal (SOR) may be a high signal, but the embodiment of the present invention is not limited thereto. The first sensor (231) may be a Schmitt trigger, but is not limited thereto.

[0118] The second sensor (232) can apply an output signal only when the second control voltage (HIN) is above a predetermined level. Accordingly, when the second control voltage (HIN) rises to a predetermined level, the second output signal (SOF) may be transmitted, and when it falls below the predetermined level again, the second output signal (SOF) may not be transmitted. The second output signal (SOF) may be a high signal, but the embodiment of the present invention is not limited thereto. The second sensor (232) may be a Schmitt trigger, but is not limited thereto.

[0119] The switch control unit (233) can apply a turn-on signal to both a pair of switches connected to a reference node from which the gamma voltage of the amplifier is output when the first output signal (SOR) or the second output signal (SOF) is applied. The switch control unit (233) can be an OR gate, but various other logic circuits can also be applied.

[0120] The third switch (SW3) can connect the third output node (OTN3) adjacent to the fourth output node (OTN4) connected to the output terminal of the amplifier. The fourth switch (SW4) can connect the fifth output node (OTN5) adjacent to the fourth output node (OTN4). Therefore, when the third switch (SW3) and the fourth switch (SW4) are turned on simultaneously, the third output node (OTN3), the fourth output node (OTN4), and the fifth output node (OTN5) can be connected to each other.

[0121] Fig. 6 is a waveform diagram of the output voltage of an amplifier connected in a low voltage state of the data voltage, the first control voltage of the amplifier, the first sensing signal, and the second sensing signal. Fig. 7 is a waveform diagram of the output voltage of an amplifier connected in a high voltage state of the data voltage, the first control voltage of the amplifier, the first sensing signal, and the second sensing signal.

[0122] Referring to FIGS. 5 and 6, when the data voltage is low and connected to the fourth output node (OTN4) with a relatively high voltage, the gamma voltage of the fourth output node (OTN4) decreases, so that the input voltage of the amplifier becomes greater than the output voltage. Accordingly, the second amplifier (AMP2) can increase the source current (t1) by reducing the first control voltage (HIP) of the pull-up PMOS transistor (PM10). As the source current increases, the output voltage can increase.

[0123] When the first control voltage (HIP) decreases below a predetermined level, the first sensor (231) can generate a first output signal (SOR) (t2). For example, the predetermined level can be set to generate the first output signal (SOR) when it falls below 90%, 70%, or 50% of the reference first control voltage (HIP), but can also be adjusted to various other levels.

[0124] When the first output signal (SOR) is applied, the switch control unit (233) can apply a turn-on signal to the third switch (SW3) and the fourth switch (SW4). Accordingly, the third output node (OTN3), the fourth output node (OTN4), and the fifth output node (OTN5) can be connected to each other. The second amplifier (AMP2) can be connected to all of the third output node (OTN3), the fourth output node (OTN4), and the fifth output node (OTN5) to perform feedback control. Accordingly, the voltages of the third output node (OTN3), the fourth output node (OTN4), and the fifth output node (OTN5) can all increase. At this time, if any one of the third output node (OTN3), the fourth output node (OTN4), and the fifth output node (OTN5) reaches the input voltage first, the feedback control for the corresponding node can be stopped.

[0125] When the first control voltage (HIP) becomes higher than a predetermined level, the first sensor (231) can output a low signal again (t3). In this case, since the second control voltage (HIN) does not change, the second voltage can continue to output a low signal. Therefore, the switch control unit (233) can output a switch turn-off signal because low signals are output from both the first sensor (231) and the second sensor (232). Therefore, the second amplifier (AMP2) can be disconnected from the third output node (OTN3) and the fifth output node (OTN5) and can receive only the output voltage of the fourth output node (OTN4) as feedback to increase the voltage until it reaches the input voltage.

[0126] Referring to FIGS. 5 and 7, when the data voltage is connected from a high voltage to a relatively low voltage fourth output node (OTN4), the fourth output node (OTN4) may have an increased output voltage and the output voltage may become greater than the input voltage. Accordingly, the amplifier may increase the second control voltage (HIN) to lower the output voltage (t5).

[0127] When the second control voltage (HIN) rises above a predetermined level, the second sensor (232) can generate a second output signal (SOF) (t6). For example, the predetermined level can be adjusted to generate the second output signal (SOF) when it rises above 10%, 30%, or 50% of the reference second control voltage (HIN), but can also be set to various other levels.

[0128] When the second output signal (SOF) is applied, the switch control unit (233) can apply a turn-on signal to the third switch (SW3) and the fourth switch (SW4). Accordingly, the third output node (OTN3), the fourth output node (OTN4), and the fifth output node (OTN5) can be connected to each other. Accordingly, the second amplifier (AMP2) can be connected to all of the third output node (OTN3), the fourth output node (OTN4), and the fifth output node (OTN5) to perform feedback control. Accordingly, the voltages of the third output node (OTN3), the fourth output node (OTN4), and the fifth output node (OTN5) can all decrease. At this time, if any one of the third output node (OTN3), the fourth output node (OTN4), and the fifth output node (OTN5) reaches the input voltage first, the feedback control for the corresponding node can be stopped.

[0129] When the second control voltage (HIN) becomes lower than a predetermined level, the second sensor (232) can output a low signal again (t7). In this case, since the first control voltage (HIP) does not change, the first sensor (231) can continue to output a low signal. Therefore, the switch control unit (233) can output a switch turn-off signal since low signals are output from both the first sensor (231) and the second sensor (232). Therefore, the second amplifier (AMP2) can again receive only the output voltage of the fourth output node (OTN4) as feedback and lower the voltage until it matches the input voltage.

[0130] According to an embodiment, when the gamma voltage fluctuates due to fluctuations in the data voltage, multiple gamma voltages can be simultaneously increased or decreased by connecting adjacent output nodes. Therefore, when the gamma voltage fluctuates, the gamma voltage can be quickly adjusted to the input voltage level.

[0131] FIG. 8 is a diagram showing a state in which switches connected to the first sensing unit to the third sensing unit are turned on and the first output node to the seventh output node are connected according to one embodiment of the present invention.

[0132] Referring to FIGS. 6 and 8, when the grayscale change is large and the data voltage changes significantly from a low voltage to a high voltage or from a high voltage to a low voltage, not only the gamma voltage connected to the DA converter (117) but also the neighboring gamma voltages may change together.

[0133] For example, when the data voltage of the DA converter is connected to the fourth output node (OTN4) with a relatively high voltage level at a low voltage, the first control voltage (HIP) of the pull-up PMOS transistor of the second amplifier (AMP2) may be lowered below a preset level, so that the third switch (SW3) and the fourth switch (SW4) may be turned on. At this time, the gamma voltage of the second output node (OTN2) and the sixth output node (OTN6) connected to the fourth output node (OTN4) by a resistor may also change. At this time, the voltage fluctuation of the second output node (OTN2) and the sixth output node (OTN6) may be smaller than the voltage fluctuation of the fourth output node (OTN4) connected to the DA converter (117).

[0134] Accordingly, the first control voltage (HIP) of the pull-up PMOS transistor of the first amplifier (AMP1) becomes lower than a preset level, so that the first switch (SW1) and the second switch (SW2) can be turned on. In addition, the first control voltage (HIP) of the pull-up PMOS transistor of the third amplifier (AMP3) becomes lower than a preset level, so that the fifth switch (SW5) and the sixth switch (SW6) can be turned on. As a result, the first output node (OTN1) to the seventh output node (OTN1 to OTN7) can be connected. Accordingly, since the first to sixth resistors (R1 to R6) are short-circuited, the total resistance within the second voltage distribution unit (250) decreases, so that the current applied to the second voltage distribution unit (250) increases, so that the voltage of the fourth output node (OTN4) can increase.

[0135] The first amplifier (AMP1) can be connected to the first output node (OTN1), the second output node (OTN2), and the third output node (OTN3) to perform feedback control. Therefore, the voltages of the first output node (OTN1), the second output node (OTN2), and the third output node (OTN3) can increase simultaneously.

[0136] The second amplifier (AMP2) is connected to the third output node (OTN3), the fourth output node (OTN4), and the fifth output node (OTN5) to perform feedback control. Therefore, the voltages of the third output node (OTN3), the fourth output node (OTN4), and the fifth output node (OTN5) can increase simultaneously.

[0137] The third amplifier (AMP3) is connected to all of the fifth output node (OTN5), the sixth output node (OTN6), and the seventh output node (OTN7) to perform feedback control. Therefore, the voltages of the fifth output node (OTN5), the sixth output node (OTN6), and the seventh output node (OTN7) can increase simultaneously.

[0138] According to an embodiment, the third output node (OTN3) may have its output voltage increased by the first amplifier (AMP1) and the second amplifier (AMP2), and the fifth output node (OTN5) may have its output voltage increased by the second amplifier (AMP2) and the third amplifier (AMP3).

[0139] In addition, since the first to seventh output nodes (OTN1 to OTN7) are short-circuited, the output voltage according to the feedback control of the first amplifier (AMP1) can also be transmitted to the fourth output node (OTN4). Since the input voltage (G1) of the first amplifier (AMP1) is higher than the input voltage (G2) of the second amplifier (AMP2), the feedback current can be the largest. Therefore, the high output voltage of the first amplifier (AMP1) can be applied to the fourth output node (OTN4), so that the voltage can quickly increase. In addition, the third amplifier (AMP3) can also apply the output voltage to the fourth output node (OTN4).

[0140] According to the embodiment, neighboring amplifiers cooperate to restore the voltage of the fourth output node (OTN4), thereby accelerating the voltage charge and reducing the settling time. Consequently, the voltage curve can be adjusted from SC1 to SC2, and the settling time can be reduced from t4 to t4' (see Fig. 6). Measurement results confirm that the settling time is reduced from 0.511 μs to 0.459 μs.

[0141] The first amplifier (AMP1) can receive only the gamma voltage of the second output node (OTN2) as a feedback again by turning off the switch when the first control voltage (HIP) of the pull-up PMOS transistor becomes higher than the set level. The second amplifier (AMP2) can receive only the gamma voltage of the fourth output node (OTN4) as a feedback again by turning off the switch when the first control voltage (HIP) of the pull-up PMOS transistor becomes higher than the set level. The third amplifier (AMP3) can receive only the gamma voltage of the sixth output node (OTN6) as a feedback again by turning off the switch when the first control voltage (HIP) of the pull-up PMOS transistor becomes higher than the set level. Since the voltage fluctuations of the second output node (OTN2) and the sixth output node (OTN6) are smaller than the voltage fluctuations of the fourth output node (OTN4) connected to the DA converter (117), the switches connected to the first amplifier (AMP1) and the third amplifier (AMP3) can be turned off faster than the switch connected to the second amplifier (AMP2). However, this is not necessarily limited to this, and the switches connected to the first amplifier (AMP1) and the third amplifier (AMP3) can be turned off slower than the switch connected to the second amplifier (AMP2). That is, the turn-off times of the switches connected to the multiple amplifiers can be different from each other.

[0142] According to an embodiment, as the variation range of the data voltage increases, in addition to the amplifier that feedback-controls the gamma voltage connected to the DA converter (117), the output voltages of neighboring amplifiers also change, so that the output voltages can be adjusted together. When the setting level of the sensor is lowered, more amplifiers can participate in adjusting the gamma voltage that has changed when the data voltage is connected.

[0143] In the above example, the DA conversion unit (117) is connected to the gamma voltage when the data voltage is relatively low. However, conversely, the DA conversion unit (117) may be connected to the gamma voltage when the data voltage is relatively high. When the data voltage is connected to the fourth output node (OTN4) with a relatively low voltage when the data voltage is relatively high, the second control voltage (HIN) of the pull-down NMOS transistor of the second amplifier (AMP2) becomes higher than a preset level, so that the third switch (SW3) and the fourth switch (SW4) may be turned on.

[0144] At this time, the gamma voltage of the second output node (OTN2) and the sixth output node (OTN6) connected to the fourth output node (OTN4) by a resistor may also increase. Accordingly, the second control voltage (HIN) of the pull-down NMOS transistors of the first amplifier (AMP1) and the third amplifier (AMP3) may become higher than a preset level, so that the first switch (SW1), the second switch (SW2), the fifth switch (SW5), and the sixth switch (SW6) may be turned on. Accordingly, the first to seventh output nodes (OTN1 to OTN7) may be connected.

[0145] As a result, the first to sixth resistors (R1 to R6) are short-circuited, so that the overall resistance within the second voltage distribution unit (250) is lowered, which can help discharge the voltage of the fourth output node (OTN4).

[0146] The first amplifier (AMP1) is connected to the first output node (OTN1), the second output node (OTN2), and the third output node (OTN3) to perform feedback control. Accordingly, the voltages of the first output node (OTN1), the second output node (OTN2), and the third output node (OTN3) can all be lowered.

[0147] The second amplifier (AMP2) is connected to the third output node (OTN3), the fourth output node (OTN4), and the fifth output node (OTN5) to perform feedback control. Therefore, the voltages of the third output node (OTN3), the fourth output node (OTN4), and the fifth output node (OTN5) can all be lowered.

[0148] The third amplifier (AMP3) is connected to all of the fifth output node (OTN5), the sixth output node (OTN6), and the seventh output node (OTN7) to perform feedback control. Therefore, the voltages of the fifth output node (OTN5), the sixth output node (OTN6), and the seventh output node (OTN7) can all be lowered.

[0149] According to an embodiment, since the first to seventh output nodes (OTN1 to OTN7) are short-circuited, the output voltage according to the feedback control of the third amplifier (AMP3) can also be transmitted to the fourth output node (OTN4). Since the input voltage (G3) of the third amplifier (AMP3) is lower than the input voltage (G2) of the second amplifier (AMP2), the sink current can be the largest. Therefore, when the third amplifier (AMP3) is connected to the fourth output node (OTN4), the voltage can be quickly lowered. In addition, the first amplifier (AMP1) can also be connected to the fourth output node (OTN4) to lower the voltage.

[0150] According to the embodiment, neighboring amplifiers cooperate to lower the voltage of the fourth output node (OTN4), thereby reducing the settling time by lowering the voltage more quickly. Consequently, the voltage curve can be adjusted from SC3 to SC4, and the settling time can be reduced from t8 to t8' (see Fig. 7). Measurement results confirm that the settling time is reduced from 0.506 μs to 0.451 μs.

[0151] FIG. 9 is a diagram showing a state in which switches connected to a first sensing unit (SP1) and a second sensing unit (SP2) are turned on and the first to fifth nodes are connected according to one embodiment of the present invention.

[0152] Referring to FIG. 9, the gamma voltage connected to the DA converter (117) may be a gamma divided voltage output from a voltage divider node rather than a gamma reference voltage output from a reference node.

[0153] For example, if the third output node (OTN3) is connected to the DA converter (117), and the data voltage does not differ significantly from the voltage of the third output node (OTN3), the gamma voltage fluctuations may not be large at the second output node (OTN2) and the fourth output node (OTN4). In this case, the setting level of the sensing unit may not be satisfied, so the first switch (SW1) to the fourth switch (SW4) may remain in a turn-on state.

[0154] However, if the difference between the data voltage and the voltage of the third output node (OTN3) is large, the gamma voltage fluctuations may be large at the second output node (OTN2) and the fourth output node (OTN4). In this case, the first sensing unit (SP1) and the second sensing unit (SP2) detect fluctuations in the first control voltage (HIP) or the second control voltage (HIN), so that the first switch (SW1) to the fourth switch (SW4) may be turned on. At this time, the gamma voltage of the relatively distant sixth output node (OTN6) does not change significantly, so that the fifth switch (SW5) and the sixth switch (SW6) may be maintained in a turned-off state.

[0155] When connected to the third output node (OTN3) in a low data voltage state, the first amplifier (AMP1) can receive the gamma voltage of the third output node (OTN3) as feedback and increase the source current to increase the output voltage. The second amplifier (AMP2) can receive the gamma voltage of the fifth output node (OTN5) as feedback and increase the source current to increase the output voltage. Therefore, the gamma voltage of the third output node (OTN3) located between the second output node (OTN2) of the first amplifier (AMP1) and the fourth output node (OTN4) of the second amplifier (AMP2) can be quickly restored to the input voltage, thereby reducing the settling time.

[0156] Fig. 10 is a circuit diagram showing a gamma voltage generation unit according to another embodiment of the present invention.

[0157] Referring to FIG. 10, a gamma voltage generation unit (200) according to an embodiment includes a first voltage distribution unit (210) that outputs a plurality of voltages having different voltage levels, a plurality of amplifiers (AMP1 to ANPn) connected to the first voltage distribution unit (210), a second voltage distribution unit (250) connected to the plurality of amplifiers (AMP1 to ANPn), and a connection circuit (230, 240) that connects nodes at which output voltages change among the output nodes of the second voltage distribution unit (250).

[0158] The connection circuit (230, 240) may include a sensing circuit (230) that senses the control voltage of a plurality of amplifiers (AMP1 to ANPn) and a switch circuit (240) that controls a plurality of switches that connect each neighboring node of the second voltage distribution unit (250).

[0159] The sensing circuit (230) can sense the first control voltage (HIP) and the second control voltage (HIN) of the plurality of amplifiers (AMP1 to ANPn). For example, when the DA converter (117) is connected to the fourth output node (OTN4) that outputs a relatively high gamma voltage in a state where the data voltage is low, the sensing circuit (230) can sense in which amplifier the gamma voltage has changed. For example, when the first control voltage (HIP) of the first to third amplifiers (AMP1 to AMP3) has changed, the switch circuit (240) can turn on the first to sixth switches (SW1 to SW6).

[0160] According to this configuration, since the sensing unit is individually connected to each amplifier, one sensing circuit (230) can sense the voltage fluctuations of multiple amplifiers (AMP1 to ANPn) without controlling the switches, and since multiple switches can be individually switched, there is an advantage in that the switches can be selectively turned on and off so as to minimize the settling time.

[0161] Since the content of the specification described in the problem to be solved, the means for solving the problem, and the effect described above does not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the specification.

[0162] While the embodiments of the present invention have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be implemented without departing from the scope of the technical spirit of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to illustrate, rather than limit, the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims

1. A first voltage distribution unit that outputs multiple voltages with different voltage levels; A plurality of amplifiers that output voltages output from the first voltage distribution unit as gamma reference voltages; A second voltage distribution unit including a plurality of reference nodes outputting the gamma reference voltage and a distribution node outputting a plurality of gamma distribution voltages by a resistor connected between the plurality of reference nodes; and A gamma voltage generation circuit comprising a connecting circuit for short-circuiting a reference node having a changed gamma reference voltage to an adjacent distribution node.

2. In paragraph 1, The above connection circuit is, A switch circuit including a plurality of switches that form a path bypassing a resistor arranged between the reference node and the distribution node to short-circuit the reference node and the adjacent distribution node; and A gamma voltage generation circuit comprising a sensing circuit that senses voltage changes of the plurality of amplifiers and turns on the plurality of switches.

3. In paragraph 2, The above sensing circuit includes a plurality of sensing units each connected to a plurality of amplifiers to sense a change in the control voltage of the amplifiers, The above switch circuit includes a switch array each connected to a plurality of sensing units, A gamma voltage generation circuit, wherein the switch array includes a high-potential connection switch connected to a first distribution node having a higher voltage than the reference node and a low-potential connection switch connected to a second distribution node having a lower voltage than the reference node.

4. In paragraph 3, A gamma voltage generation circuit, wherein a low-potential connection switch connected to a first sensing unit among the plurality of sensing units and a high-potential connection switch connected to a second sensing unit adjacent to the first sensing unit are connected to the same distribution node.

5. In paragraph 3, The above multiple sensing units, A first sensor for detecting a change in a first control voltage applied to a first output transistor of the amplifier; A second sensor for detecting a change in a second control voltage applied to a second output transistor of the amplifier, and A gamma voltage generation circuit comprising a switch control unit that outputs a signal for driving a plurality of switches according to an output signal of the first sensor or the second sensor.

6. In paragraph 5, A gamma voltage generation circuit, wherein the first sensor applies an output signal to the switch control unit when the first control voltage applied to the first output transistor falls below a predetermined voltage level.

7. In paragraph 6, The second sensor is a gamma voltage generation circuit that applies an output signal to the switch control unit when the second control voltage of the second output transistor rises above a predetermined voltage level.

8. In paragraph 6, The switch control unit is a gamma voltage generation circuit that outputs a turn-on signal to the high-potential connection switch and the low-potential connection switch when an output signal is applied from the first sensor or the second sensor.

9. In paragraph 2, The above sensing circuit, A sensing unit for detecting voltage changes of the above plurality of amplifiers; and A gamma voltage generation circuit including a switch control unit that selectively applies turn-on signals to a plurality of switches according to the voltage change level detected by the sensing unit.

10. A data driving unit that converts source data into data voltages based on gamma voltages; and It includes a gamma voltage generation unit that generates the above gamma voltages, The above gamma voltage generating unit is, A first voltage distribution unit that outputs multiple voltages having different voltage levels; A plurality of amplifiers that output voltages output from the first voltage distribution unit as gamma reference voltages; A second voltage distribution unit including a plurality of reference nodes outputting the gamma reference voltage and a distribution node outputting a plurality of gamma distribution voltages by a resistor connected between the plurality of reference nodes; and A source driver circuit comprising a connecting circuit for short-circuiting a reference node having a varied gamma reference voltage to an adjacent distribution node.

11. In paragraph 10, The above connection circuit is, A switch circuit including a plurality of switches that form a path bypassing a resistor arranged between the reference node and the distribution node to short-circuit the reference node and the adjacent distribution node; and A source driver circuit including a sensing circuit that senses voltage changes of the plurality of amplifiers and turns on the plurality of switches.

12. In paragraph 11, The above sensing circuit includes a plurality of sensing units each connected to a plurality of amplifiers to sense a change in the control voltage of the amplifiers, The above switch circuit includes a switch array each connected to a plurality of sensing units, A source driver circuit, wherein the switch array includes a high-potential connection switch connected to a first distribution node having a higher voltage than the reference node and a low-potential connection switch connected to a second distribution node having a lower voltage than the reference node.

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