Method and apparatus for realizing physical design layout of encryption operation die, and die

Abstract

Disclosed in the present application are a method and apparatus for realizing a physical design layout of an encryption operation die. For a first-level engine of an encryption operation die, the method comprises: first, on the basis of a data structure of a reference-level functional module in the core of the encryption operation die, determining a layout position of each component in the reference-level functional module; then, on the basis of the width of the reference-level functional module and a relative position between the reference-level functional module and a functional module to be laid out, determining a placement position of the functional module to be laid out, and according to the layout position of each component in the reference-level functional module, laying out each component in the functional module to be laid out; and finally, laying out each functional module to obtain a physical design layout of the first-level engine of the encryption operation die.

Description

Method, device and chip for realizing physical design layout of encryption computing chip Technical Field

[0001] The present application relates to, but is not limited to, semiconductor design technology, and in particular to a method, device, and chip for implementing the physical design layout of an encryption computing chip. Background Art

[0002] Physical design is the process of converting a circuit description into a physical layout, which specifies the placement of cells and their connections.

[0003] A cryptographic computing chip is a specially designed application-specific integrated circuit (ASIC) chip. During the wiring planning phase of the physical design layout of a cryptographic computing chip, the location and spatial allocation of each functional module on the chip are determined. Traditional chip physical design typically uses electronic design automation (EDA) tools to place modules, automatically placing components such as latches and cell macros based on the EDA tool's own algorithms. This placement method can cause some problems. For example, when placing modules, the EDA tool may resize the cells to meet timing requirements, resulting in increased power consumption and wasted chip die area. The chip die area refers to the actual physical area on the integrated circuit chip used to place electronic components.

[0004] How to save chip die area, reduce power consumption, and achieve an optimal computing power ratio (i.e., the ratio of power consumption to frequency) is an urgent problem that needs to be solved in the physical design layout of the chip.

[0005] SUMMARY OF THE INVENTION

[0006] The present application provides a method, device, and chip for implementing the physical design layout of an encryption computing chip, which can solve any of the above-mentioned technical problems.

[0007] The present application provides a method for implementing a physical design layout of a cryptographic computing chip, for a first-level engine of the cryptographic computing chip, including:

[0008] Determining the layout position of each component in the reference functional module according to the data structure of the reference functional module in the core of the encryption operation chip;

[0009] Determine the placement position of the functional module to be laid out according to the width of the reference-level functional module and the relative position between the reference-level functional module and the functional module to be laid out, and lay out each component in the functional module to be laid out according to the layout position of each component in the reference-level functional module;

[0010] Performing physical design and layout on the cores of different functional modules in the first-level engine of the encryption computing chip;

[0011] The cores included in the first-level engine of the encryption operation chip are laid out to obtain a physical design layout of the first-level engine of the encryption operation chip.

[0012] In an exemplary embodiment, determining the layout position of each component in the reference functional module includes:

[0013] The data structure of the reference-level functional module receives an excitation signal, and obtains an output result after processing the data structure of the reference-level functional module; based on the output result, the placement position of each component in the reference-level functional module is determined to ensure smooth data flow.

[0014] In an exemplary embodiment, the reference-level functional module is a functional module including the most complete components in the core where the reference-level functional module is located; and the pipeline Pipe is used as the functional module.

[0015] In an exemplary embodiment, the first-level engine of the cryptographic computing chip is composed of four cores including a first calculation stage-a second calculation stage-a second write stage S1C-S2C-S2W and a first write stage S1W;

[0016] The reference-level functional modules include:

[0017] The S1C structure includes an odd-numbered pipe with the most complete components and an even-numbered pipe with the most complete components, and the S2W structure includes an odd-numbered pipe with the most complete components and an even-numbered pipe with the most complete components.

[0018] In an exemplary embodiment, the functional modules to be laid out include a first functional module to be laid out and a second functional module to be laid out;

[0019] The step of determining the placement position of the functional module to be laid out and laying out each component in the functional module to be laid out according to the layout position of each component in the reference-level functional module includes:

[0020] For the first functional module to be laid out, determining the placement position of the first functional module to be laid out based on the width of the reference functional module and the relative position between the reference functional module and the first functional module to be laid out, and then laying out the corresponding components in the first functional module to be laid out according to the layout position of each component in the reference functional module;

[0021] For the second functional module to be laid out, the placement position of the second functional module to be laid out is determined based on the width of the reference-level functional module and the relative position between the reference-level functional module and the second functional module to be laid out. Then, the corresponding components in the second functional module to be laid out are laid out according to the layout position of each component in the reference-level functional module, and the components not included in the second functional module to be laid out are deleted.

[0022] In an exemplary embodiment, the width of the reference-level functional module depends on the sum of the widths of the components included after the first-level functional module is implemented, and the height of each component is the height of (n+1) rows, where n indicates that the latch in the component is an n-bit latch; the relative position of the reference-level functional module and the functional module to be laid out depends on the product of the difference in the number of functional modules and the width of the first-level functional module.

[0023] In an exemplary embodiment, the functional module to be laid out belongs to the S1C, the level of the functional module to be laid out is smaller than the level of the corresponding reference-level functional module in the S1C, and is moved along the X direction; the level of the functional module to be laid out is larger than the level of the corresponding reference-level functional module in the S1C, and is moved along the negative X direction;

[0024] The functional module to be laid out belongs to the S2C, and the level of the functional module to be laid out is greater than the level of the corresponding reference-level functional module in the S1C, and moves along the X direction; the functional module to be laid out has a level less than the level of the corresponding reference-level functional module in the S1C, and moves along the negative X direction;

[0025] The functional module to be laid out belongs to the S2W, and the level of the functional module to be laid out is greater than the level of the corresponding reference-level functional module in the S2W, and is moved along the X direction; the level of the functional module to be laid out is less than the level of the corresponding reference-level functional module in the S2W, and is moved along the negative X direction; wherein, in the physical design layout of Pipe28 to Pipe43 in the S2W, the latches placed at the positions of the first variable latch Reg wt1 / the second variable latch Reg wt2 in the reference-level functional module in the S2W are respectively decreased one by one from the 34th latch Reg r-39 / the 52nd latch Reg r-40 to the 17th latch Reg a-39 / the 35th latch Reg a-40;

[0026] The functional module to be laid out belongs to the S1W, the level of the functional module to be laid out is smaller than the level of the corresponding reference-level functional module in the S2W, and the module moves along the X direction; the level of the functional module to be laid out is larger than the level of the corresponding reference-level functional module in the S2W, and the module moves along the negative X direction; wherein, in the physical design layout of Pipe32 to Pipe47 in the S1W, the latches placed at the positions of the first variable latch Reg wt1 / the second variable latch Reg wt2 in the reference-level functional module in the S2W decrease one by one from the 34th latch Reg r-39 / the 52nd latch Reg r-40 to the 17th latch Reg a-39 / the 35th latch Reg a-40, respectively.

[0027] In an exemplary embodiment, the cores of the first-level engine of the encryption computing chip including different functional modules are physically designed and laid out separately, including: four cores including S1C–S2C–S2W and one S1W in the first-level engine of the encryption computing chip are laid out separately; in the core including S1C–S2C–S2W, S2C–S2W is placed above S1C.

[0028] In an exemplary embodiment, the pipes in the S1C are arranged in a row, and the levels of the pipes are arranged from large to small from left to right;

[0029] The physical design layout of the S2C-S2W includes a first row and a second row arranged in sequence along the negative Y-axis direction. The first row of the physical design layout of the S2C-S2W includes the pipes in the S2C, and the pipes are arranged in ascending order from left to right along the X-direction. The second row of the physical design layout of the S2C-S2W includes the pipes in the S2W, and the pipes are arranged in ascending order from left to right along the X-direction. The pipes in the first row of the physical design layout of the S2C-S2W are aligned with the pipes in the second row of the physical design layout of the S2C-S2W according to the same sequence number.

[0030] The physical design layout of the S1W includes three rows, namely the first row, the second row, and the third row along the negative Y-axis. The first row of the physical design layout of the S1W includes pulse generators s1-Pulse Generators corresponding to the pipes in S1C, which are arranged in descending order from left to right along the X-direction. The second row of the physical design layout of the S1W includes pulse generators s2-Pulse Generators corresponding to the pipes in S2C, which are arranged in descending order from left to right along the X-direction. The third row of the physical design layout of the S1W includes the pipes in the S1W, which are arranged in descending order from left to right along the X-direction in terms of the number of pipes. The Engine Control component in the S1W is placed at the rightmost end of the S1W part, to the right of Pipe 14 in the S1W along the X-direction.

[0031] In an exemplary embodiment, the physical design layout of the first-level engine of the cryptographic computing chip includes:

[0032] The four cores are arranged in parallel along the Y direction. From bottom to top, they are: the fourth core, the third core, the second core, and the first core. The S1W is placed between the third and second cores.

[0033] Among them, all four cores contain S1C–S2C–S2W.

[0034] The embodiment of the present application further provides a device for implementing the physical design layout of an encryption computing chip, comprising: a reference layout unit and a batch layout unit; wherein,

[0035] A reference layout unit, for the first-level engine of the cryptographic computing chip, is used to determine the layout position of each component in the reference functional module according to the data structure of the reference functional module in the core of the cryptographic computing chip;

[0036] A batch layout unit is used to determine the placement of the functional modules to be laid out based on the width of the reference-level functional modules and the relative positions of the reference-level functional modules and the functional modules to be laid out, and to layout each component in the functional modules to be laid out according to the layout position of each component in the reference-level functional modules; to perform physical design layout on the cores of the first-level engine of the encryption computing chip including different functional modules respectively; and to layout the cores included in the first-level engine of the encryption computing chip to obtain the physical design layout of the first-level engine of the encryption computing chip.

[0037] The embodiment of the present application further provides a chip, wherein the first-level engine of the chip includes four cores including S1C-S2C-S2W and one S1W;

[0038] The physical design layout of the first-level engine is implemented using any of the above-mentioned methods for implementing the physical design layout of the encryption computing chip.

[0039] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0040] Summary of the Figures

[0041] The accompanying drawings are used to provide a further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0042] FIG1 is a flow chart of a method for implementing a physical design layout of a chip according to an embodiment of the present application;

[0043] FIG2 is a schematic diagram of the data structure of Pipe33 and Pipe34 in S1C in an embodiment of the present application;

[0044] FIG3 is a schematic diagram of the physical design layout of each component in Pipe33 in S1C in an embodiment of the present application;

[0045] FIG4 is a schematic diagram of the physical design layout of each component in Pipe34 in S1C in an embodiment of the present application;

[0046] FIG5 is a schematic diagram of the data structure of Pipe39 and Pipe40 in S2W in an embodiment of the present application;

[0047] FIG6 is a schematic diagram of the physical design layout of each component in Pipe39 in S2W in an embodiment of the present application;

[0048] FIG7 is a schematic diagram of the physical design layout of each component in Pipe40 in S2W in an embodiment of the present application;

[0049] FIG8 is a schematic diagram of the physical design layout of the S1C structure in an embodiment of the present application;

[0050] FIG9 is a schematic diagram of the physical design layout of the S2C-S2W structure in an embodiment of the present application;

[0051] FIG10 is a schematic diagram of the physical design layout of the S1W structure in an embodiment of the present application;

[0052] FIG11 is a schematic diagram of the physical design layout of the first-level Engine in an embodiment of the present application;

[0053] FIG12 is a schematic diagram of the physical design layout of the core including S1C-S2C-S2W in an embodiment of the present application;

[0054] FIG13 is a schematic diagram of the composition structure of an apparatus for implementing the physical design layout of a chip in an embodiment of the present application.

[0055] Details

[0056] To make the purpose, technical solutions and advantages of this application more clear, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of this application can be combined with each other in any way.

[0057] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0059] The architecture of a cryptographic computing chip is divided into two main parts at the top level: Miscellaneous (MISC) and Engine. The Engine is the core engine of the cryptographic computing chip, responsible for processing components related to the core functions of the blockchain. Functionally, the Engine is responsible for accepting computing tasks from the MISC, performing the calculations on them, and feeding back the results to the MISC. The Engine structure can include rounds 4 in stage 1 through rounds 61 in stage 2 of the SHA-256d algorithm. The top level includes multiple Engines. In the SHA-256d algorithm, the Engine structure consists of two main parts: stage 1 and stage 2. Stage 1 includes rounds 4, while stage 2 includes rounds 5 through 61. Specifically, each round in the SHA-256d algorithm consists of a series of operations, including bit operations, logic functions, and constants. In the Engine structure, stage 1 includes the first four rounds (rounds 4), while stage 2 covers operations from rounds 5 through 61. The purpose of these rounds is to encrypt and process the input data through multiple iterations and mixing operations to generate the output of the SHA-256d algorithm. Each round involves processing blocks of the input data and performing specific operations to ensure security and cryptographic performance. MISCs typically include components related to network communication, user interfaces, and other support functions. Functionally, the MISC is responsible for receiving computation tasks from the host computer, generating computation tasks for the Engine, distributing computation tasks to the Engine, collecting computation results from the Engine, processing the Engine's computation results, and feeding back the results to the host computer. Structurally, the MISC includes input / output modules (IO), a phase-locked loop (PLL), and a host computer interface module. It also includes computation modules for the base transaction (coinbase), MerkleRoot, stage0, and stage1_rounds0123. It includes full SHA-256d functionality for secondary computation of the random number (nonce) selected by the Engine.

[0060] The first-level engine of the cryptographic computing chip consists of four cores (S1C, S2C, and S2W) and one S1W. The first stage (S1C, Stage 1 Compute) performs the first stage of the SHA-256d algorithm. S1C is responsible for initial processing and calculation of input data. The second stage (S2C, Stage 2 Compute) performs the second stage of the SHA-256d algorithm. S2C performs further calculations on the data processed by the first stage. The second write stage (S2W, Stage 2 Write) writes the results of the second stage calculation to memory or cache for subsequent operations and processing. The first write stage (S1W, Stage 1 Write) writes the results of the first stage calculation to memory or cache for subsequent operations and processing. The core processes input data and generates intermediate results through a series of pipelines.

[0061] The physical design of cryptographic computing chips can be achieved by placing modules through the automatic placement function of EDA tools. Automatic placement in EDA tools uses the EDA tool Innovus for gate-level synthesis and layout. This generally involves: first, inputting the synthesized gate-level Verilog code, that is, providing the gate-level netlist (GDSII or Verilog format) generated after synthesis as input to Innovus; then, inputting the Library Exchange Format (LEF) information of standard cells and latches, that is, providing the LEF file related to the cells and latches used in the design to Innovus. The LEF file describes the physical characteristics and layout information of each standard cell; then, performing the placement operation, that is, using the layout layout commands or graphical interface in Innovus to layout the gate-level netlist. Here, standard cells and latches are placed according to design constraints (such as clock network routing, area constraints, etc.). However, when placing cells, EDA tools will increase the size of the cells to meet timing requirements, which increases power consumption and wastes chip die area.

[0062] In order to save chip die area, reduce power consumption, and achieve an optimal computing power ratio, an embodiment of the present application provides a method for implementing the physical design layout of the chip. The physical design layout method provided in the embodiment of the present application no longer relies on the auto-place of the EDA tool to complete the layout of cells and latches, but through the reference functional module in the selected chip. After determining the position of each component in the reference functional module, the physical design layout of the remaining functional modules to be laid out with the same structure and streamlined structure is directly determined according to the physical design layout of the reference functional module to achieve batch layout, thereby shortening the layout time, reducing the power consumption generated by using the auto-place tool, and thus saving the chip die area.

[0063] FIG1 is a flow chart of a method for implementing a physical design layout of a cryptographic computing chip according to an embodiment of the present application. As shown in FIG1 , a first-level engine of a cryptographic computing chip may include:

[0064] Step 100: Determine the layout position of each component in the reference functional module according to the data structure of the reference functional module in the core of the encryption operation chip.

[0065] In an exemplary embodiment, the reference-level functional module is a functional module that includes the most complete components in the core in which it is located. In an embodiment, the functional module can be a pipeline.

[0066] In one embodiment, taking the structure of S1C as an example, S1C's 63-level structure indicates that in the first phase of the SHA-256d algorithm, the computation process is divided into 63 consecutive stages or steps. Each stage corresponds to a pipeline, and from Pipe4 to Pipe66, a 63-level structure is included, comprising a total of 63 pipelines. Specifically, in the structure of Pipe15 to Pipe62, the structures of odd-numbered and even-numbered Pipes correspond to the same structure. The remaining structures of Pipe4 to Pipe14 and Pipe63 to Pipe66 are simplifications of the Pipe15-Pipe62 structure. That is, compared to the Pipe15-Pipe62 structure, some modules are omitted from Pipe4-Pipe14 and Pipe63-Pipe66.

[0067] In one embodiment, taking the S2C-S2W structure as an example, Pipe0 to Pipe61 in the S2C structure and Pipe1 to Pipe59 in the S2W structure. Among them, in the structure of Pipe15 to Pipe57 in S2C, the structure of odd-level Pipes and the structure of even-level Pipes respectively correspond to the same structure, and the remaining Pipe0 to Pipe14 and Pipe58 to Pipe61 in S2C are simplified structures of Pipe15 to Pipe57, that is, compared with Pipe15 to Pipe57, some components are omitted in Pipe0 to Pipe14 and Pipe58 to Pipe61. In the structure of Pipe29 to Pipe41 in S2W, the structure of the odd-level Pipes and the structure of the even-level Pipes correspond to the same structure respectively. The remaining Pipes in S2W, namely Pipe1 to Pipe28 and Pipe42 to Pipe59, are a simplification of the structure of Pipe29 to Pipe41. That is, compared with Pipe29 to Pipe41, some components are omitted in Pipe1 to Pipe28 and Pipe42 to Pipe59.

[0068] In one embodiment, the S1W structure is used as an example, which includes 63 pulse generators, an engine controller, and Pipes 14 to 62. Among them, in the structure of Pipes 32 to 47 in S1W, the structures of odd-numbered and even-numbered Pipes are identical, and the remaining Pipes 14 to 31 and Pipes 48 to 62 are simplified versions of the Pipes 32 to 47 structure.

[0069] In an exemplary instance, the reference-level functional module may include: an odd-level Pipe such as Pipe33 including the most complete components and an even-level Pipe such as Pipe34 including the most complete components in the S1C structure, and an odd-level Pipe such as Pipe39 including the most complete components and an even-level Pipe such as Pipe40 including the most complete components in the S2W structure.

[0070] In an exemplary embodiment, determining the layout position of each component in the reference functional module according to the data structure of the reference functional module in the core of the cryptographic computing chip in step 100 may include:

[0071] The data structure of the reference-level functional module receives the stimulus signal and obtains the output result after being processed by the data structure of the reference-level functional module. Based on the output result, the placement position of each component in the reference-level functional module is determined to ensure smooth data flow and avoid timing violations and route congestion.

[0072] Timing violation and route congestion are both concepts related to electronic design and chip manufacturing. Timing violation refers to timing violations that occur in digital circuits. When designing a chip, each signal needs to be transmitted and processed according to a specific timing. If the arrival time or transmission time of a signal exceeds the specified time limit, a timing violation will occur, resulting in functional errors or performance degradation of the chip. To avoid timing violations, strict timing analysis, clock tree design, and routing optimization are required. Route congestion refers to resource congestion problems that occur during chip layout and routing. In chip design, signals need to connect different circuit components through a series of wires and channels. If certain wires or channels carry too many signals, exceeding their capacity limits, congestion will occur. To solve the routing congestion problem, reasonable resource allocation, layout planning, and signal path optimization are required to ensure that signals can be transmitted smoothly within the chip.

[0073] The data structure of the reference-level functional module describes the signal flow and data transfer at each stage. By inputting stimulus signals into the data structure, the output can be analyzed for timing conflicts, path congestion, and other issues. This allows the layout of each component in the reference-level functional module to be understood. The positions of these components can then be adjusted to optimize the output results and avoid issues such as timing violations and path congestion. It should be noted that these adjustments can be made multiple times until the optimal placement of each component in the reference-level functional module is determined.

[0074] Taking the reference functional module including Pipe33 and Pipe34 in S1C as an example, Figure 2 is a schematic diagram of the data structure of Pipe33 and Pipe34 in S1C in an embodiment of the present application. As shown in Figure 2, the data structure of Pipe33 is shown below round33, and the data structure of Pipe34 is shown below round34. For clarity, the data structure of Pipe33 and the data structure of Pipe34 in Figure 2 are separated by dotted lines. As shown below round33 in Figure 2, the data structure of Pipe33 includes the following modules: the first latch Reg a-33, the second latch Reg b-33, the third latch Reg c-33, the fourth latch Reg d-33, the fifth latch Reg e-33, the sixth latch Reg f-33, the seventh latch Reg g-33 and the eighth latch Reg h-33 are respectively customized n-bit latches, each latch occupies the SHA256_engine The height of (n+1) rows in the Y direction; the first XOR gate SIGn0-33 and the second XOR gate SIGn1-33 are used to implement a 3-input XOR operation; the first adder adderan, the second adder adderdn, the third adder adderen and the fourth adder adderhn are four adders; the first carry generator Majn-33 is a three-input carry generator, used to implement Maj(x,y,z)=(x&y)^(x&z)^(y&z); the first data selector CHn-33 is a 2-input 1-select bit data selector, used to implement Ch(x,y,z)=(x&y)^(~x&z); the first full adder CSNa-33, the second full adder CSNe-33, the third full adder CSNhn and the fourth full adder CSKn are used to implement the full adder function.As shown below round34 in Figure 2, the data structure of Pipe34 includes the following modules: the ninth latch Reg a-34, the tenth latch Reg b-34, the eleventh latch Reg c-34, the twelfth latch Reg d-34, the thirteenth latch Reg e-34, the fourteenth latch Reg f-34, the fifteenth latch Reg g-34 and the sixteenth latch Reg h-34 are customized n-bit latches, each of which occupies one bit along the SHA256_engine The third and fourth XOR gates SIGn0-34 and SIGn1-34 implement a three-input XOR operation. The fifth, sixth, and seventh adders adderap, adderdp, and adderep, as well as the eighth adderhp, form four adders. The second carry generator Majn-34 is a three-input carry generator. The second data selector CHn-34 is a two-input, one-bit selector. The fifth, sixth, and seventh full adders CSNa-34, CSNe-34, CSNhp, and CSKp implement full adder functionality. In physical implementation, the height of each module in Figure 2 is the same as the latch height, and its Y-direction height is equal to the height of the (n+1) row.

[0075] In one exemplary embodiment, a CSN is configured to perform a logical operation on three input operands and output two operands, one of which is the bitwise inverse of the sum of the three input operands, and the other is the bitwise inverse of the carry bit of the addition of the three input operands. In one embodiment, the CSN includes one or more 1-bit full adder inversion circuits, wherein the 1-bit full adder inversion circuit is obtained by eliminating an inverter in a 1-bit full adder.

[0076] In an exemplary embodiment, CSK is configured to perform a logic operation based on two input operands g and a and a constant K, and output two operands s and c, where s is equal to The bitwise inverse of the sum of a and K, c is equal to The bitwise inverse value of the carry of the addition of a and K. In one embodiment, CSK may include one or more 1-bit arithmetic circuits, wherein the 1-bit arithmetic circuit satisfies: when K=0, the two operands s and c outputted satisfy: When K=1, the two output operands s and c satisfy: in, represents the exclusive OR operator, Represents the logical NOT operator (negation), and ∧ represents the logical AND operator.

[0077] Under the logical framework of Pipe33 and Pipe34 shown in Figure 2, the data structure of Pipe33-Pipe34 can be expressed as follows. Taking Pipe33 as an example, the data direction of Pipe33 is shown: rega-sign0-csna-adderan-rega Rega-cskn-csnhn-adderhn-regh Regb-MAJn-csna-adderan-rega Regc-MAjn-CSNa-adderan-rega Rega-regb Regb-regc Regc-adderdn-regd Regd-CSNa-adderan-rega Rege-adderdn-regd Rege-SIGn1-CSNe-adderen-rege Rege-CHn-CSNe-adderen-rege Rege-regf Regf-CHn-CSNe-adderen-regf Regf-regg Regg-CHn-CSNe-adderen-rege Regg-CSKn-CSNhn-adderhn-regh Regh-CSNe-adderen-rege

[0078] The above data structure describes the signal flow and data transfer at each stage from Pipe33 to Pipe34. The signal flow uses a dash symbol "-" to connect the output of the previous level component with the input of the next level component. In one embodiment, taking the data flow direction Rege-CHn-CSNe-adderen-rege as an example, this data flow direction has the deepest logic depth and is the most difficult to meet the timing critical path. After Innovus place the relevant module, check Innovus routing congestion and the result is no congestion, and there is no problem with the routing. After the routing is completed, parasitic parameters are extracted, and based on certain timing constraints, the timing analysis report generated by the prime time timing analysis tool shows that there is no timing violation. Therefore, the implementation of the corresponding layout is not a problem.

[0079] In an exemplary embodiment, taking the reference functional module including Pipe33 and Pipe34 in S1C as an example, according to step 100, stimulus signals are repeatedly input to Pipe33 and Pipe34 in S1C. Then, based on the output results obtained after processing the data structures of Pipe33 and Pipe34 in S1C, the placement of each component in Pipe33 and Pipe34 in S1C is continuously adjusted. In this way, when a timing violation occurs, the violation path and critical path are analyzed one by one to perform timing repair. The resulting physical design layout of each component in Pipe33 in S1C is shown in Figure 3, and the physical design layout of each component in Pipe34 in S1C is shown in Figure 4. After continuous testing, it has been found that the physical design layouts shown in Figures 3 and 4 not only ensure smooth data flow in Pipe33 and Pipe34 in S1C, but also effectively avoid problems such as timing violations and path congestion. The physical design layout of Pipe33 in S1C is shown in Figure 3. The components in Pipe33 in S1C are arranged in two rows, and the components in the upper and lower rows are aligned (allowing a certain error). Among them, the components arranged from left to right in the upper row include: adderan, CSNa-33, SIGn0-33, Majn-33, Reg d-33, SIGn1-33, adderdn, Reg c-33, Reg b-33 and Reg a-33; the components arranged from left to right in the lower row include: adderen, CSNe-33, CHn-33, Reg h-33, adderhn, CSNhn, CSKn, Reg g-33, Reg f-33 and Reg e-33. The physical design layout of Pipe34 in S1C is shown in Figure 4. The components in Pipe34 in S1C are arranged in two rows, and the components in the upper and lower rows are aligned (allowing a certain error). Among them, the components arranged from left to right in the upper row include: adderap, CSNa-34, SIGn0-34, Majn-34, Reg d-34, SIGn1-34, adderdp, Reg c-34, Reg b-34 and Reg a-34; the components arranged from left to right in the lower row include: adderep, CSNe-34, CHn-34, Reg h-34, adderhp, CSNhp, CSKp, Reg g-34, Reg f-34 and Reg e-34.It should be noted that Figures 3 and 4 indicate the physical design layout of Pipe33 and the physical design layout of Pipe34, respectively. Therefore, -33 and -44 are not shown in the identification of each component in the figure. For example, CSNa-33 in Figure 3 only shows CSNa in the definition of Pipe33, and Reg e-34 in Figure 4 only shows Reg e in the definition of Pipe34.

[0080] Taking the reference functional module including Pipe39 and Pipe40 in S2W as an example, Figure 5 is a schematic diagram of the data structure of Pipe39 and Pipe40 in S2W in an embodiment of the present application. As shown in Figure 5, the data structure of Pipe39 is on the left side of the dotted line, and the data structure of Pipe40 is on the right side of the dotted line. As shown on the left side of the dotted line in Figure 5, the data structure of Pipe39 includes the following modules: the 17th latch Reg a-39 to the 34th latch Reg r-39, a total of 18 customized n-bit latches, each latch occupies the height of (n+1) rows along the Y direction of SHA256_engine; the fifth XOR gate SIG1n1-39, the sixth XOR gate SIG1n0-39, the seventh XOR gate SIG0n1-39 and the eighth XOR gate SIG0n0-39 are used to implement the XOR operation on the input; the ninth adder adderwn1-39 and the tenth adder adderwn0-39 are two adders; the ninth full adder CSA01-39, the tenth full adder CSA00-39, the eleventh full adder CSA3-39, and the twelfth full adder CSA2-39 are used to implement the full adder function. As shown on the right side of the dotted line in Figure 5, the data structure of Pipe40 includes the following modules: the 35th latch Reg a-40 to the 52nd latch Reg r-40, a total of 18 customized n-bit latches, each latch occupies the height of (n+1) rows along the Y direction of SHA256_engine; the 9th XOR gate SIG1p1-40, the 10th XOR gate SIG1p0-40, the 11th XOR gate SIG0p1-40 and the 12th XOR gate SIG0p0-40 are used to implement the XOR operation on the input; the 11th adder adderwpp1-40 and the 12th adder adderwpp0-40 are two adders; the 13th full adder CSA11-40, the 14th full adder CSA10-40, the 15th full adder CSA3-40 and the 16th full adder CSA2-40 are used to implement the full adder function. In physical implementation, the height of each module in Figure 5 is the same as the height of the latch, and the height along the Y direction is equal to the height of (n+1) rows.

[0081] According to step 100, stimulus signals are repeatedly input to Pipe 39 and Pipe 40 in S2W. Based on the output results obtained after processing the data structures of Pipe 39 and Pipe 40 in S2W, the placement of the components in Pipe 39 and Pipe 40 in S2W is continuously adjusted. This allows for analysis of violation paths and critical paths one by one to perform timing repairs when timing violations occur. The resulting physical design layouts for the components in Pipe 39 and Pipe 40 in S2W are shown in Figure 6, and in Figure 7, respectively. Continuous testing has shown that the physical design layouts shown in Figures 6 and 7 not only ensure smooth data flow in Pipe 39 and Pipe 40 in S2W, but also effectively avoid issues such as timing violations and path congestion. Combined with the numbers in Figure 5, the physical design layout of Pipe39 in S2W is shown in Figure 6. The components in Pipe39 in S2W are arranged in two rows, and the components in the upper and lower rows are aligned (allowing a certain error). Among them, the components arranged from left to right in the upper row include: Reg n-39, Reg o-39, Reg c-39, Reg m-39, Reg b-39, Reg g-39, Reg e-39, Reg wt1 (for Pipe39, Reg wt1 (Reg wt shown in Figure 6) is Reg k-39), Reg r-39, SIG0n1-39, CSA3-39, SIG1n1-39, CSA01-39 and adderwn1-39; the components arranged from left to right in the lower row include: Reg h-39, Reg p-39, Reg f-39, Reg j-39, Reg i-39, Reg d-39, Reg a-39, Reg l-39, Reg q-39, SIG0n0-39, CSA2-39, SIG1n0-39, CSA00-39, and adderwn0-39.Combined with the numbers in Figure 5, the physical design layout of Pipe40 in S2W is shown in Figure 7. The components in Pipe40 in S2W are arranged in two rows, and the components in the upper and lower rows are aligned (a certain error is allowed). Among them, the components arranged from left to right in the upper row include: Reg i-40, Reg o-40, Reg c-40, Reg m-40, Reg b-40, Reg g-40, Reg e-40, Reg wt2 (for Pipe40, Reg wt2 (Reg wt shown in Figure 7) is Reg j-40), Reg r-40, SIG0p1-40, CSA3-40, SIG1p1-40, CSA11-40 and adderwpp1-40; the components arranged from left to right in the lower row include: Reg h-40, Reg p-40, Reg l-40, Reg k-40, Reg n-40, Reg d-40, Reg a-40, Reg f-40, Reg q-40, SIG0p0-40, CSA2-40, SIG1p0-40, CSA10-40, and adderwpp0-40. It should be noted that Figures 6 and 7 indicate the physical design layout of Pipe39 and Pipe40, respectively. Therefore, -39 and -40 are not shown in the identification of each component in the figures. For example, CSN1-39 in Figure 6 only shows CSN1 in the definition of Pipe39, and Regn-40 in Figure 7 only shows Regw6 in the definition of Pipe40.

[0082] Since data will be exchanged between Pipe28 to Pipe43 in S2W and the Pipes in S2C with the same level, in the physical design layout of Pipe28 to Pipe43 in S2W, the latches placed at the position of Reg wt1 are respectively decreased one by one from Reg r-39 (corresponding to w15 on the left side of the dotted line in Figure 5) to Reg a-39 (corresponding to w0 on the left side of the dotted line in Figure 5), and the latches placed at the position of Reg wt2 are respectively decreased one by one from Reg r-40 (corresponding to w15 on the right side of the dotted line in Figure 5) to Reg a-40 (corresponding to w0 on the right side of the dotted line in Figure 5). For example, in the physical layout of Pipe28 in S2W, Reg r-40 (corresponding to w15 in Figure 5) is placed at the position corresponding to Reg wt; in the physical layout of Pipe29 in S2W, Reg q-39 (corresponding to w14 on the left side of the dotted line in Figure 5); in the physical layout of Pipe30 in S2W, Reg p-40 (corresponding to w13 on the right side of the dotted line in Figure 5) is placed at the position corresponding to Reg wt2. Similarly, in the physical layout of Pipe42 in S2W, Reg b-40 (corresponding to w1 on the right side of the dotted line in Figure 5) is placed at the position corresponding to Reg wt2. In the physical layout of Pipe43 in S2W, Reg a-39 (corresponding to w0 on the left side of the dotted line in Figure 5) is placed at the position corresponding to Reg wt1.

[0083] The eighteen customized n-bit latches in FIG6 (corresponding to the latch w on the left side of the dotted line in FIG5) include: the seventeenth latch Reg a-39 (w0), the eighteenth latch Reg b-39 (w1), the nineteenth latch Reg c-39 (w2), the twentieth latch Reg d-39 (w1s0), the twenty-first latch Reg e-39 (w2s0), the twenty-second latch Reg f-39 (w3), the twenty-third latch Reg g-39 (w4), the twenty-fourth latch Reg h-39 (w5), the twenty-fifth latch Reg i-39 (w6), the twenty-sixth latch Reg j-39 (w7), the twenty-seventh latch Reg k-39 (w8), the twenty-eighth latch Reg l-39 (w9), the twenty-ninth latch Reg m-39 (w10), the thirtieth latch Reg n-39 (w11), the thirty-first latch Reg o-39 (w12), the thirty-second latch Reg p-39 (w13), the thirty-third latch Reg q-39 (w14), and the thirty-fourth latch Reg r-39 (w15).

[0084] The eighteen customized n-bit latches in FIG7 (corresponding to the latch w on the right side of the dotted line in FIG5 ) include: the thirty-fifth latch Reg a-40 (w0), the thirty-sixth latch Reg b-40 (w1), the thirty-seventh latch Reg c-40 (w2), the thirty-eighth latch Reg d-40 (w1s0), the thirty-ninth latch Reg e-40 (w2s0), the fortieth latch Reg f-40 (w3), the forty-first latch Reg g-40 (w4), the forty-second latch Reg h-40 (w5), the forty-third latch Reg i-40 (w6), the forty-fourth latch Reg j-40 (w7), the forty-fifth latch Reg k-40 (w8), the forty-sixth latch Reg l-40 (w9), the forty-seventh latch Reg m-40 (w10), the forty-eighth latch Reg n-40 (w11), the forty-ninth latch Reg o-40 (w12), the fiftieth latch Reg p-40 (w13), the fifty-first latch Reg q-40 (w14), and the fifty-second latch Reg r-40 (w15).

[0085] Step 101: Determine the placement position of the functional module to be laid out according to the width of the reference functional module and the relative position between the reference functional module and the functional module to be laid out, and lay out each component in the functional module to be laid out according to the layout position of each component in the reference functional module.

[0086] In an exemplary embodiment, step 101 may include:

[0087] For a first functional module to be laid out that has the same structure as a reference functional module, determine the placement of the first functional module based on the width of the reference functional module and the relative positions of the reference functional module and the first functional module to be laid out, and then lay out the corresponding components in the first functional module to be laid out according to the layout positions of each component in the reference functional module;

[0088] For a second functional module to be laid out that is more streamlined than a reference-level functional module, the placement of the second functional module to be laid out is determined based on the width of the reference-level functional module and the relative positions of the reference-level functional module and the second functional module to be laid out. Then, the corresponding components in the second functional module to be laid out are positioned according to the layout positions of each component in the reference-level functional module, and the components not included in the second functional module to be laid out are deleted.

[0089] In one exemplary embodiment, the width of the reference-level functional module is determined by the sum of the widths of each module after the implementation of the first-level functional module, such as a Pipe. The height of each module is (n+1) rows, where n represents an n-bit latch in the component. For example, the width of the first-level reference-level Pipe is W. The data direction of the pipes S1C and S1W is in the -X direction, i.e., the negative direction of the X-axis, while the data direction of the pipes S2C and S2W is in the X direction, i.e., the positive direction of the X-axis. The relative position of the reference-level functional module and the functional module to be laid out is determined by the product of the difference in the order of the functional modules, such as Pipes, and the width of the first-level functional module, such as Pipes. For example, the position of the pipe to be laid out is the product of W and the absolute value of the difference in the order of the reference-level Pipe and the pipe to be laid out. If the pipe to be laid out in S1C and S1W has a smaller order than the reference-level pipe, the pipe to be laid out is arranged along the X direction with the reference-level pipe as the center. If the pipe to be laid out has a larger order than the reference-level pipe, the pipe to be laid out is arranged along the -X direction with the reference-level pipe as the center. The layout of S2C and S2W is opposite to the above situation. That is, if the Pipe to be laid out in S2C and S2W is smaller than the reference-level Pipe level, the Pipe to be laid out is laid out along the -X direction with the reference level as the center. If the Pipe to be laid out is larger than the reference-level Pipe level, it is laid out along the X direction with the reference-level Pipe as the center.

[0090] Step 102: Physically design and layout the cores of different functional modules in the first-level engine of the encryption computing chip.

[0091] In one embodiment, four cores including S1C-S2C-S2W and one S1W in the first-level engine of the encryption computing chip are laid out separately to obtain the physical design layout of each core constituting the first-level engine of the encryption computing chip.

[0092] Step 101 and step 102 are described in detail below with reference to different examples.

[0093] In an exemplary embodiment, taking the reference functional modules including Pipe33 and Pipe34 in S1C as an example, first, the position of each module of the reference-level functional modules, i.e., Pipe33 and Pipe34 in S1C, is determined according to step 100, as shown in Figures 3 and 4; then, the first-level Pipe width of Pipe33 and Pipe34 in S1C is determined according to the design of the encryption computing chip; thereafter, a command (such as the regexp command of Tcl) is used to convert the name of the instantiated module in Pipe33 / Pipe34 in S1C into the instantiated name of the module corresponding to the functional module to be placed, and the relative position of the functional module to be placed, i.e., the Pipe to be placed, and Pipe33 / Pipe34 in S1C used as a reference is determined and placed. In one embodiment, an example of using Tcl's regexp command to change the name of an instantiated module is as follows: if the name of an instantiated cell of the reference level Pipe33 is pipe33 / aa, then the regexp command can be used to change pipe33 / aa to PipeXX / aa, where XX represents the Pipe level to be replaced.

[0094] In one embodiment, taking the functional module to be laid out as Pipe 20 in S1C as an example, in S1C, the even-numbered Pipes and the odd-numbered Pipes correspond to Pipe 34 and Pipe 33 in S1C, respectively. If the level of the functional module to be laid out is greater than the level of the reference functional module, the pipeline moves along the -X direction, i.e., the negative direction of the X-axis. If the level of the functional module to be laid out is less than the level of the reference functional module, the pipeline moves along the X direction, i.e., the positive direction of the X-axis. In this embodiment, Pipe 20 in S1C uses Pipe 34 in S1C as a reference, copies the physical design layout of Pipe 34 in S1C, and shifts the module position of the copied Pipe 34 in S1C in the X direction by 34-20=14 widths of Pipe 34 in S1C. The copied module is then placed in the shifted position. The module name of each copied Pipe 34 in S1C is then changed to the name of the corresponding module of Pipe 20 in S1C. For example, the name of Majn-34 is changed to Majn-20. In this way, the physical design layout of Pipe 20 in S1C is completed.

[0095] Following the physical design layout for Pipe20 in S1C, the physical design layout for even-and-odd-level Pipes in S1C, which share the same structure as the reference-level Pipe33 / Pipe34, can be completed. For streamlined Pipes relative to the reference-level Pipe33 / Pipe34 in S1C, the layout is similarly implemented using the physical design layout for Pipe20 in S1C, and the streamlined components can be deleted. The resulting physical design layout for S1C is shown in Figure 8. In Figure 8, the Pipes in the S1C structure are arranged in a row, with the Pipe levels arranged from largest to smallest along the X-direction from left to right.

[0096] It should be noted that Figures 3 and 4 are merely a physical design layout of Pipe33 and Pipe34 in S1C, and do not limit the absolute positional relationship of the components in Pipe33 and Pipe34 in S1C. In other words, the positions of some components in Pipe33 and Pipe34 in S1C can be appropriately adjusted according to actual needs. Similarly, Figure 8 is also merely a physical design layout of the S1C structure, and does not limit the absolute positional relationship of the Pipes in the S1C structure. In other words, the positions of some Pipes in the S1C structure can be appropriately adjusted according to actual needs. The embodiment of the present application emphasizes that batch layout is achieved through predetermined reference-level Pipes, which shortens the layout time and reduces the power consumption caused by the auto-place tool.

[0097] In one exemplary embodiment, the functional modules to be laid out are pipes in S2C-S2W. For S2C, the structures of the odd- and even-numbered pipes in Pipes 15 through 57 in S2C are identical to those of the odd and even-numbered pipes in S1C, respectively. The remaining pipes, Pipes 0 through 14 and Pipes 58 through 61 in S2C, are simplifications of the structures of Pipes 15 through 57. Therefore, the physical design layout of the pipes in S2C can be performed using Pipes 33 and 34 in S1C as reference levels. However, in the physical layout of S2C, the pipe layout direction is opposite to that of S1C. That is, if the number of levels of the functional module to be laid out is greater than that of the reference functional module, the pipes are moved in the positive X-direction. If the number of levels of the functional module to be laid out is less than that of the reference functional module, the pipes are moved in the negative X-direction. In this way, the physical location of the Pipes with the same structure as Pipe33 and Pipe34 in S1C can be determined, and the Pipes and the modules included in the S2C structure can be placed in batches. For S2W, because the structures of the odd-level Pipes and the even-level Pipes in Pipe29 to Pipe41 in S2W correspond to the same structure, the remaining Pipes in S2W, namely Pipe1 to Pipe28 and Pipe42 to Pipe59, are the simplification of the Pipe29 to Pipe41 structure. For the physical design layout of the S2W structure, we can take the reference functional module including Pipe39 and Pipe40 in S2W as an example. First, determine the position of each module of the reference functional module, namely Pipe39 and Pipe40 in S2W, according to step 100. As shown in Figures 6 and 7, the first-level Pipe width of Pipe39 and Pipe40 in S2W is determined according to the design of the encryption operation chip. After that, a command is used to convert the name of the instantiated module in Pipe39 / Pipe40 in S2W into the instantiated name of the module corresponding to the functional module to be placed, and the relative position of the functional module to be placed, that is, the Pipe to be placed and the Pipe39 / Pipe40 in S2W as a reference is determined and placed. Among them, in the physical design layout of Pipe28 to Pipe43 in S2W, the Reg The latches placed at the position of wt1 decrease one by one from Reg r-39 (corresponding to w15 on the left side of the dotted line in Figure 5) to Reg a-39 (corresponding to w0 on the left side of the dotted line in Figure 5), and the latches placed at the position of Reg wt2 decrease one by one from Reg r-40 (corresponding to w15 on the right side of the dotted line in Figure 5) to Reg a-40 (corresponding to w0 on the right side of the dotted line in Figure 5).In the encryption computing chip provided in the embodiment of the present application, in the physical layout of S2W, the layout direction of the Pipe is opposite to the layout direction of the Pipe in S1C. That is, if the number of levels of the functional modules to be laid out is greater than the number of levels of the reference functional modules, it moves along the X direction, i.e., the positive direction of the X axis; if the number of levels of the functional modules to be laid out is less than the number of levels of the reference functional modules, it moves in the -X direction, i.e., the negative direction of the X axis.

[0098] The physical design layout of S2C-S2W can be shown in Figure 9. In Figure 9, the physical design layout of S2C-S2W includes two rows, namely the first row and the second row along the -Y direction. The first row (located at the top) includes the pipes in the S2C structure, and the pipe levels are arranged from small to large from left to right along the X direction. The second row (located at the bottom) includes the pipes in the S2W structure, and the pipe levels are arranged from small to large from left to right along the X direction. In one embodiment, since data will be exchanged between the Pipes in S2W and the Pipes in S2C of the same level, the Pipes in the first row and the Pipes in the second row are aligned with the same serial number (a certain error is allowed). For example, Pipe1 in S2W is placed directly below Pipe1 in S2C (marked as Wpipe1 in Figure 9 ). For another example, Pipe16 in S2W is placed directly below Pipe16 in S2C (marked as Wpipe16 in Figure 9 ). For another example, because S2W does not include Pipe0, there is no Pipe placed directly below Pipe0 in S2C.

[0099] It should be noted that Figures 6 and 7 are only a physical design layout of Pipe39 and Pipe40 in S2W, and do not limit the absolute position relationship of each component in Pipe39 and Pipe40 in S2W. In other words, the positions of some components in Pipe39 and Pipe40 of S2W can be appropriately adjusted according to actual needs. Similarly, Figure 9 is also only a physical design layout of the S2C-S2W structure, and does not limit the absolute position relationship of each Pipe in the S2C-S2W structure. In other words, the positions of some Pipes in the S2C-S2W structure can be appropriately adjusted according to actual needs. The embodiment of the present application emphasizes that batch layout is achieved through predetermined reference-level Pipes, which shortens the layout time and reduces the power consumption caused by the auto-place tool.

[0100] In an exemplary embodiment, the functional module to be laid out is taken as the Pipe in S1W. For S1W, since the structures of the odd-level Pipes and the even-level Pipes in the structures of Pipe32 to Pipe47 in S1W are respectively the same as the odd-level structures and the even-level structures in the S2W structure, the remaining Pipe14 to Pipe31 and Pipe48 to Pipe62 in S1W are simplified structures of Pipe32 to Pipe47. Therefore, the physical design layout of the Pipe in S1W can be laid out with Pipe39 and Pipe40 in S2W as reference levels. Similarly, in the physical design layout of Pipe32 to Pipe47 in S1W, the latches placed at the positions of Reg wt1 decrease one by one from Reg r-39 (corresponding to w15 on the left side of the dotted line in FIG5 ) to Reg a-39 (corresponding to w0 on the left side of the dotted line in FIG5 ), and the latches placed at the positions of Reg wt2 decrease one by one from Reg r-39 (corresponding to w15 on the left side of the dotted line in FIG5 ). r-40 (corresponding to w15 on the right side of the dotted line in Figure 5) decreases one by one to Reg a-40 (corresponding to w0 on the right side of the dotted line in Figure 5). The difference is that in the physical layout of S1W, the layout direction of the Pipe is opposite to the layout direction of the Pipe in S2W. That is, if the number of levels of the functional modules to be laid out is greater than the number of levels of the reference functional modules, then it moves along the -X direction, that is, the negative direction of the X axis. If the number of levels of the functional modules to be laid out is less than the number of levels of the reference functional modules, then it moves in the X direction, that is, the positive direction of the X axis. In this way, the Pipes with the same structure as Pipe39 and Pipe40 in S2W can determine the physical position, realizing the batch placement of the Pipes and the modules included in the S1W structure.

[0101] The physical design layout of the pipes in the S1W structure can be shown in FIG10 . In FIG10 , the pipes in the S1W structure are arranged in a row, and the levels of the pipes are arranged from large to small along the X direction from left to right.

[0102] The remaining components in the S1W structure include the pulse generator and the engine controller. The pulse generator includes the s1-Pulse Generator corresponding to the pipe in S1C and the s2-Pulse Generator corresponding to the pipe in S2C.

[0103] The s1-Pulse Generators are arranged in a row, from pulse-gen-s1-Pipe66 to pulse-gen-s1-Pipe4 from left to right along the X direction. At the same time, each pulse-gen-s1 corresponds to directly below each Pipe in S1C in the same core. For example, pulse-gen-s1-Pipe4 corresponds to directly below Pipe4 in S1C. As shown in Figure 10, the row of pulse-gen-s1 in S1W is arranged at the top, that is, the first row in S1W.

[0104] The s2-Pulse Generators are arranged in a row, from left to right along the X direction from pulse-gen-s2-Pipe1 to pulse-gen-s2-Pipe61. At the same time, each pulse-gen-s2 corresponds to directly below each Pipe in S2C. For example, pulse-gen-s2-Pipe1 corresponds to directly below Pipe1 in S2C. As shown in Figure 10, the row of pulse-gen-s2 in S1W is arranged in the middle row (the second row) in S1W, that is, the row of pulse-gen-s2 in S1W is below the row of pulse-gen-s1 in S1W and above the row where the Pipes in S1W are located.

[0105] The Engine Control component (labeled "engine-ctl" in Figure 10) in the S1W is located at the far right of the S1W. Pipes 14 through 62 are arranged in a row from right to left along the -X axis, with the row of pipes at the bottom of the S1W. Pipe 14 is located to the left of engine-ctl along the -X axis.

[0106] The physical design layout of S1W can be shown in Figure 10. In Figure 10, the physical design layout of S1W consists of three rows. The first row (top) includes the s1-Pulse Generators, arranged from left to right along the X direction from largest to smallest. In this embodiment, they are arranged from pulse-gen-s1-Pipe 66 to pulse-gen-s1-Pipe 4. The second row (center) includes the s2-Pulse Generators, arranged from left to right along the X direction from smallest to largest. In this embodiment, they are arranged from pulse-gen-s2-Pipe 1 to pulse-gen-s2-Pipe 61. The third row (bottom) includes Pipes 14 through 62 of S1W, arranged from left to right along the X direction from largest to smallest. The Engine Control component of S1W is placed at the far right of the S1W, to the right of Pipe 14 in the X direction.

[0107] It should be noted that Figure 10 is only a physical design layout of the S1W structure and does not limit the absolute position relationship of each pipe in the S1W structure. In other words, the positions of some pipes in the S1W structure can be adjusted appropriately according to actual needs. The embodiments of this application emphasize that batch layout is achieved through the use of pre-determined reference-level pipes, which shortens layout time and reduces power consumption caused by the auto-place tool.

[0108] Step 103: Layout the cores included in the first-level engine of the encryption computing chip to obtain the physical design layout of the first-level engine of the encryption computing chip.

[0109] In an exemplary embodiment, the physical design layout of the first-level engine of the present application is shown in Figure 11. Four cores are arranged in parallel along the Y direction. From bottom to top, along the Y direction, they are: the fourth core, core 3; the third core, core 2; the second core, core 1; and the first core, core 0. S1W is placed between core 2 and core 1. Specifically, the four cores, core 3, core 2, core 1, and core 0, all contain S1C–S2C–S2W. The physical design layout of the core including S1C–S2C–S2W is shown in Figure 12, with S2C–S2W placed above S1C.

[0110] The method for implementing chip physical design layout in the embodiments of the present application no longer relies on the auto-place tool of an EDA tool to complete the layout of cells and latches. Instead, it implements batch layout through pre-determined reference-level pipes. By simply determining the position of the reference-level pipe and the modules it includes, the physical positions of other pipes with the same structure and streamlined structures are determined, completing the physical design layout of the cryptographic computing chip. Components are not resized during the layout, saving chip die area. Furthermore, the method for implementing chip physical design layout provided by the embodiments of the present application shortens the time required for physical design layout and reduces the power consumption caused by the auto-place tool resizing cells to meet timing requirements during placement.

[0111] An embodiment of the present application provides a chip, the first-level engine of which includes four cores containing S1C–S2C–S2W and one S1W; wherein the physical design layout of the first-level engine is implemented using any method for implementing the physical design layout of an encryption computing chip provided in an embodiment of the present application.

[0112] FIG13 is a schematic diagram of the structure of the device for implementing the physical design layout of the chip in the embodiment of the present application, as shown in FIG13 , including: a reference layout unit and a batch layout unit; wherein,

[0113] A reference layout unit, for the first-level engine of the cryptographic computing chip, is used to determine the layout position of each component in the reference functional module according to the data structure of the reference functional module in the core of the cryptographic computing chip;

[0114] A batch layout unit is used to determine the placement of the functional modules to be laid out based on the width of the reference-level functional modules and the relative positions of the reference-level functional modules and the functional modules to be laid out, and to layout each component in the functional modules to be laid out according to the layout position of each component in the reference-level functional modules; to perform physical design layout on the cores of the first-level engine of the encryption computing chip including different functional modules respectively; and to layout the cores included in the first-level engine of the encryption computing chip to obtain the physical design layout of the first-level engine of the encryption computing chip.

[0115] In an exemplary embodiment, determining the placement positions of the functional modules to be laid out in the batch layout unit may include:

[0116] For a first functional module to be laid out that has the same structure as a reference functional module, determine the placement of the first functional module based on the width of the reference functional module and the relative positions of the reference functional module and the first functional module to be laid out, and then lay out the corresponding components in the first functional module to be laid out according to the layout positions of each component in the reference functional module;

[0117] For a second functional module to be laid out that is more streamlined than a reference-level functional module, the placement of the second functional module to be laid out is determined based on the width of the reference-level functional module and the relative positions of the reference-level functional module and the second functional module to be laid out. Then, the corresponding components in the second functional module to be laid out are positioned according to the layout positions of each component in the reference-level functional module, and the components not included in the second functional module to be laid out are deleted.

[0118] In an exemplary embodiment, the batch layout unit layouts the cores included in the first-level engine of the encryption computing chip to obtain the physical design layout of the first-level engine of the encryption computing chip, which may include:

[0119] The physical design layout of the cryptographic computing chip's first-level engine is as follows: four cores are arranged in parallel along the Y direction. From bottom to top, they are core 3, core 2, core 1, and core 0. S1W is placed between core 2 and core 1. All four cores consist of S1C–S2C–S2W.

[0120] In an exemplary embodiment, performing physical design layout on cores of different functional modules in a first-level engine of a cryptographic computing chip in a batch layout unit includes:

[0121] In the core consisting of S1C–S2C–S2W, S2C–S2W are placed above S1C.

[0122] In one exemplary embodiment, the physical design layout of the S1W includes three rows: the first, second, and third rows along the -Y direction. The first row (at the top) includes the s1-Pulse Generators, arranged from left to right along the X direction from largest to smallest. In this embodiment, they are arranged from pulse-gen-s1-Pipe66 to pulse-gen-s1-Pipe4. The second row (at the center) includes the s2-Pulse Generators, arranged from left to right along the X direction from smallest to largest. In this embodiment, they are arranged from pulse-gen-s2-Pipe1 to pulse-gen-s2-Pipe61. The third row (at the bottom) includes Pipes 14 through 62 in the S1W, arranged from left to right in ascending order of Pipe number. The S1W Engine Control component is placed at the far right of the S1W, to the right of Pipe 14 in the X direction.

[0123] In one exemplary embodiment, the physical design layout of the S2C-S2W structure includes two rows, the first and second rows along the -Y direction. The first row (located at the top) includes the pipes in the S2C structure, arranged in ascending order from left to right along the X direction. The second row (located at the bottom) includes the pipes in the S2W structure, arranged in ascending order from left to right along the X direction. The pipes in the first row and the second row are aligned with the same sequence number (a certain error is allowed).

[0124] In an exemplary embodiment, determining the layout position of each component in the reference functional module in the reference layout unit in the reference level physical design layout in S2W, as shown in FIG7 , includes:

[0125] The components in the odd-numbered reference-level Pipe in S2W are arranged in two rows, and the components in the upper and lower rows are aligned (a certain error is allowed). The components in the upper row from left to right include: Reg n-39, Reg o-39, Reg c-39, Reg m-39, Reg b-39, Reg g-39, Reg e-39, the first variable latch Reg wt1 (for Pipe39, Reg wt1 is Reg k-39), Reg r-39, SIG0n1-39, CSA3-39, SIG1n1-39, CSA01-39 and adderwn1-39; the components in the lower row from left to right include: Reg h-39, Reg p-39, Reg f-39, Reg j-39, Reg i-39, Reg d-39, Reg a-39, Reg l-39, Reg q-39, SIG0n0-39, CSA2-39, SIG1n0-39, CSA00-39 and adderwn0-39. The components in the even-numbered reference-level Pipe in S2W are arranged in two rows, and the components in the upper and lower rows are aligned (a certain error is allowed). Among them, the components in the upper row from left to right include: Reg i-40, Reg o-40, Reg c-40, Reg m-40, Reg b-40, Reg g-40, Reg e-40, the second variable latch Reg wt2 (for Pipe40, Reg wt2 is Reg j-40), Reg r-40, SIG0p1-40, CSA3-40, SIG1p1-40, CSA11-40 and adderwpp1-40; the components in the lower row from left to right include: Reg h-40, Reg p-40, Reg l-40, Reg k-40, Reg n-40, Reg d-40, Reg a-40, Reg f-40, Reg q-40, SIG0p0-40, CSA2-40, SIG1p0-40, CSA10-40, and adderwpp0-40.

[0126] In an exemplary embodiment, the physical design layout of S1C is as follows: the pipes in the S1C structure are arranged in a row, and the levels of the pipes are arranged from large to small from left to right.

[0127] In an exemplary embodiment, determining the layout position of each component in the reference functional module in the reference layout unit in the reference level physical design layout in S1C, as shown in FIG3 , includes:

[0128] The components in the odd-numbered reference-level Pipe in S1C are arranged in two rows, and the components in the upper and lower rows are aligned (a certain error is allowed). Among them, the components in the upper row from left to right include: adderan, CSNa-33, SIGn0-33, Majn-33, Reg d-33, SIGn1-33, adderdn, Reg c-33, Reg b-33 and Reg a-33; the components in the lower row from left to right include: adderen, CSNe-33, CHn-33, Reg h-33, adderhn, CSNhn, CSKn, Reg g-33, Reg f-33 and Reg e-33. The components in the even-numbered reference-level Pipe in S1C are arranged in two rows, and the components in the upper and lower rows are aligned (a certain error is allowed). Among them, the components in the upper row arranged from left to right include: adderap, CSNa-34, SIGn0-34, Majn-34, Reg d-34, SIGn1-34, adderdp, Reg c-34, Reg b-34 and Reg a-34; the components in the lower row arranged from left to right include: adderep, CSNe-34, CHn-34, Reg h-34, adderhp, CSNhp, CSKp, Reg g-34, Reg f-34 and Reg e-34.

[0129] In an exemplary embodiment, the batch layout unit places each component in the functional module to be placed according to the placement position of each component in the reference-level functional module, for:

[0130] If the functional module to be laid out belongs to S1C, the physical design layout of the corresponding reference-level functional module in S1C is copied, and the position of the components of the corresponding reference-level functional module in the copied S1C is shifted in the X direction / negative X direction by the difference between the number of reference-level levels and the number of levels of the functional module to be laid out, times the width of the corresponding reference-level functional module in S1C; the copied physical design layout is placed at the shifted position, and the names of the components of the corresponding reference-level functional module in each copied S1C are changed to the names of the corresponding components in the functional module to be laid out; wherein, if the level of the functional module to be laid out is smaller than the level of the corresponding reference-level functional module in S1C, the components are shifted in the X direction; if the level of the functional module to be laid out is larger than the level of the corresponding reference-level functional module in S1C, the components are shifted in the negative X direction;

[0131] If the functional module to be laid out belongs to S2C, the physical design layout of the corresponding reference-level functional module in S1C is copied, and the position of the components of the corresponding reference-level functional module in the copied S1C is shifted in the X direction / negative X direction by the difference between the number of reference-level levels and the number of levels of the functional module to be laid out, times the width of the corresponding reference-level functional module in S1C; the copied physical design layout is placed at the shifted position, and the names of the components of the corresponding reference-level functional module in each copied S1C are changed to the names of the corresponding components in the functional module to be laid out; wherein, if the level of the functional module to be laid out is greater than the level of the corresponding reference-level functional module in S1C, the components are shifted in the X direction; if the level of the functional module to be laid out is less than the level of the corresponding reference-level functional module in S1C, the components are shifted in the negative X direction;

[0132] If the functional module to be laid out belongs to an S2W, the physical design layout of the corresponding reference-level functional module in the S2W is copied, and the position of the components of the copied reference-level functional module in the S2W is shifted in the X direction or the negative X direction by the difference between the number of reference-level levels and the number of levels of the functional module to be laid out, times the width of the corresponding reference-level functional module in the S2W; the copied physical design layout is placed at the shifted position, and the names of the components of the corresponding reference-level functional module in the S2W in each copy are changed to the names of the corresponding components in the functional module to be laid out; wherein, if the level of the functional module to be laid out is greater than the level of the corresponding reference-level functional module in the S2W, the shift is made in the X direction; and if the level of the functional module to be laid out is less than the level of the corresponding reference-level functional module in the S2W, the shift is made in the negative X direction; wherein, in the physical design layout of Pipe 28 to Pipe 43 in the S2W, the latches placed at the positions of the first variable latch Reg wt1 / the second variable latch Reg wt2 in the reference-level functional module in the S2W are respectively changed from the thirty-fourth latch Reg r-39 / the fifty-second latch Reg r-40. r-40 decreases one by one to the seventeenth latch Reg a-39 / the thirty-fifth latch Reg a-40;

[0133] If the functional module to be laid out belongs to S1W, the physical design layout of the corresponding reference-level functional module in S2W is copied, and the position of the components of the corresponding reference-level functional module in the copied S2W is shifted in the X direction / negative X direction by the difference between the number of reference-level levels and the number of levels of the functional module to be laid out, times the width of the corresponding reference-level functional module in S2W; the copied physical design layout is placed at the shifted position, and the names of the components of the corresponding reference-level functional module in each copied S2W are changed to the names of the corresponding components in the functional module to be laid out; wherein, if the level of the functional module to be laid out is less than the level of the corresponding reference-level functional module in S2W, the shift is made in the X direction; and if the level of the functional module to be laid out is greater than the level of the corresponding reference-level functional module in S2W, the shift is made in the negative X direction; wherein, in the physical design layout of Pipe32 to Pipe47 in S1W, the latches placed at the positions of the first variable latch Reg wt1 / the second variable latch Reg wt2 in the reference-level functional module in S2W are respectively changed from the thirty-fourth latch Reg r-39 / the fifty-second latch Reg r-40. r-40 is decremented one by one to the seventeenth latch Reg a-39 / the thirty-fifth latch Reg a-40.

[0134] Although the embodiments disclosed in this application are as described above, the contents described are merely embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any person skilled in the art to which this application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application. However, the scope of patent protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A method for implementing the physical design layout of an encryption operation chip. For the first-level engine of the encryption operation chip, including: Determining the layout positions of each component in the reference function module according to the data structure of the reference-level function module in the core of the encryption operation chip; Determining the placement position of the to-be-layout function module according to the width of the reference-level function module and the relative position between the reference-level function module and the to-be-layout function module, and laying out each component in the to-be-layout function module according to the layout positions of each component in the reference-level function module; Separately performing physical design layout on the cores including different function modules in the first-level engine of the encryption operation chip; Laying out the cores included in the first-level engine of the encryption operation chip to obtain the physical design layout of the first-level engine of the encryption operation chip.

2. The method according to claim 1, wherein, The determining the layout positions of each component in the reference function module includes: The data structure of the reference-level function module receives an excitation signal, and an output result is obtained after being processed by the data structure of the reference-level function module; according to the output result, the placement position of each component in the reference-level function module is determined to make the data flow smooth.

3. The method according to claim 2, wherein, The reference-level function module is a function module including the most complete components in the core where the reference-level function module is located; the pipeline Pipe is used as the function module.

4. The method according to claim 3, wherein, The first-level engine of the encryption operation chip consists of four cores containing the first calculation stage - the second calculation stage - the second write stage S1C–S2C–S2W and a first write stage S1W; The reference-level function module includes: An odd-level Pipe including the most complete components and an even-level Pipe including the most complete components in the S1C structure, and an odd-level Pipe including the most complete components and an even-level Pipe including the most complete components in the S2W structure.

5. The method according to claim 1, wherein, The to-be-layout function module includes a first to-be-layout function module and a second to-be-layout function module; The determining the placement position of the to-be-layout function module and laying out each component in the to-be-layout function module according to the layout positions of each component in the reference-level function module includes: For the first to-be-layout function module, determining the placement position of the first to-be-layout function module according to the width of the reference-level function module and the relative position between the reference-level function module and the first to-be-layout function module, and then laying out the corresponding components in the first to-be-layout function module according to the layout positions of each component in the reference-level function module; For the second functional module to be laid out, determine the placement position of the second functional module to be laid out according to the width of the reference-level functional module and the relative position between the reference-level functional module and the second functional module to be laid out. Then, layout the corresponding components in the second functional module to be laid out according to the layout positions of each component in the reference-level functional module, and delete the components not included in the second functional module to be laid out.

6. The method according to claim 5, wherein, the width of the reference-level functional module depends on the sum of the widths of each component included after the implementation of the first-level functional module. The height of each component is the height of (n + 1) rows, where n represents the latch in the component is an n-bit latch; the relative position between the reference-level functional module and the functional module to be laid out depends on the product of the difference in the number of levels of the functional modules and the width of the first-level functional module.

7. The method according to claim 4, wherein, the functional module to be laid out belongs to the S1C. When the number of levels of the functional module to be laid out is less than the number of levels of the corresponding reference-level functional module in the S1C, it moves along the X direction; when the number of levels of the functional module to be laid out is greater than the number of levels of the corresponding reference-level functional module in the S1C, it moves along the negative X direction; the functional module to be laid out belongs to the S2C. When the number of levels of the functional module to be laid out is greater than the number of levels of the corresponding reference-level functional module in the S1C, it moves along the X direction; when the number of levels of the functional module to be laid out is less than the number of levels of the corresponding reference-level functional module in the S1C, it moves along the negative X direction; the functional module to be laid out belongs to the S2W. When the number of levels of the functional module to be laid out is greater than the number of levels of the corresponding reference-level functional module in the S2W, it moves along the X direction; when the number of levels of the functional module to be laid out is less than the number of levels of the corresponding reference-level functional module in the S2W, it moves along the negative X direction. Among them, in the physical design layout of Pipe28 to Pipe43 in the S2W, the latches placed at the positions of the first variable latch Reg wt1 / second variable latch Reg wt2 in the reference-level functional module in the S2W are sequentially decremented from the thirty-fourth latch Reg r-39 / fiftieth latch Reg r-40 to the seventeenth latch Reg a-39 / thirty-fifth latch Reg a-40; The to-be-layout functional module belongs to the S1W. If the level of the to-be-layout functional module is less than that of the corresponding reference-level functional module in the S2W, it moves along the X direction; if the level of the to-be-layout functional module is greater than that of the corresponding reference-level functional module in the S2W, it moves along the negative X direction. Among them, in the physical design layout of Pipe32 to Pipe47 in the S1W, the latches placed at the positions of the first variable latch Reg wt1 / second variable latch Reg wt2 in the reference-level functional module in the S2W are successively decreased from the thirty-fourth latch Reg r-39 / fifty-second latch Reg r-40 to the seventeenth latch Reg a-39 / thirty-fifth latch Reg a-40 one by one.

8. The method according to claim 1, wherein, physically designing and laying out the cores of different functional modules in the first-level engine of the encryption operation chip respectively includes: laying out the four cores including S1C–S2C–S2W and one S1W in the first-level engine of the encryption operation chip; in the core including S1C–S2C–S2W, S2C–S2W is placed above S1C.

9. The method according to claim 8, wherein, each Pipe in the S1C is arranged in a row, and the levels of the Pipes decrease from large to small from left to right in sequence; the physical design layout of S2C-S2W includes a first row and a second row arranged in sequence along the negative Y-axis direction. The first row in the physical design layout of S2C-S2W includes each Pipe in the S2C, and the levels of the Pipes increase from small to large from left to right along the X direction. The second row in the physical design layout of S2C-S2W includes each Pipe in the S2W, and the levels of the Pipes increase from small to large from left to right along the X direction; the Pipes in the first row in the physical design layout of S2C-S2W and the Pipes in the second row in the physical design layout of S2C-S2W are aligned and placed according to the same serial number; the physical design layout of the S1W includes three rows, which are the first row, the second row, and the third row in sequence along the negative Y-axis direction. The first row in the physical design layout of the S1W includes the pulse generator s1-Pulse Generator corresponding to the Pipe in the S1C, and the levels decrease from large to small from left to right along the X direction. The second row in the physical design layout of the S1W includes the pulse generator s2-Pulse Generator corresponding to the Pipe in the S2C, and the levels increase from small to large from left to right along the X direction. The third row in the physical design layout of the S1W includes each Pipe in the S1W, and the levels of the Pipes decrease from large to small from left to right along the X direction; the Engine Control component in the S1W is placed at the rightmost end of the S1W part, on the right side of Pipe14 in the S1W along the X direction.

10. The method according to claim 1, wherein, The physical design layout of the first-level engine of the encryption operation chip includes: Four cores are arranged in parallel along the Y direction. From bottom to top along the Y direction, they are: the fourth core, the third core, the second core, and the first core. S1W is placed between the third core and the second core; Among them, all four cores contain S1C–S2C–S2W.

11. A device for implementing the physical design layout of an encryption operation chip, including: A reference layout unit and a batch layout unit; among them, The reference layout unit is used for the first-level engine of the encryption operation chip to determine the layout position of each component in the reference function module according to the data structure of the reference-level function module in the core of the encryption operation chip; The batch layout unit is used to determine the placement position of the function module to be laid out according to the width of the reference-level function module and the relative position between the reference-level function module and the function module to be laid out, and layout each component in the function module to be laid out according to the layout position of each component in the reference-level function module; perform physical design layout on the cores including different function modules in the first-level engine of the encryption operation chip respectively; perform layout on the cores included in the first-level engine of the encryption operation chip to obtain the physical design layout of the first-level engine of the encryption operation chip.

12. A chip, the first-level engine of the chip includes four cores containing S1C–S2C–S2W and one S1W; The physical design layout of the first-level engine is implemented by using the method for implementing the physical design layout of an encryption operation chip according to any one of claims 1 to 10.

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