Wiring substrate and manufacturing method therefor, and electronic device

Abstract

The present disclosure provides a wiring substrate and a manufacturing method therefor, and an electronic device. The wiring substrate comprises: a base substrate, comprising a first surface and a second surface arranged opposite to each other, wherein the second surface comprises a binding area extending along a first direction and fan-out areas located on two sides of the binding area in a second direction, a plurality of via holes are formed in the fan-out areas, and the first direction intersects with the second direction; a plurality of signal lines located on the side where the first surface is located, wherein the orthographic projections of the plurality of signal lines on the base substrate penetrate through the binding area and the fan-out areas along the second direction; and a plurality of connecting lines located on the side where the second surface is located, wherein the plurality of connecting lines extend from the fan-out areas to the binding area, and the plurality of connecting lines and the plurality of signal lines are coupled by means of the plurality of via holes.

Description

Wiring substrate, manufacturing method thereof, and electronic device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a wiring substrate, a manufacturing method thereof, and an electronic device. Background Art

[0002] Mini LEDs (Micro LEDs) are increasingly being used in display products due to their smaller size, ultra-high brightness, and long lifespan. They are typically mounted on printed circuit boards (PCBs) or glass substrates. Glass substrates offer excellent thermal conductivity, high flatness, and a low coefficient of expansion and contraction, which better support the packaging process and ensure quality.

[0003] Summary of the Invention

[0004] The wiring substrate, its manufacturing method and electronic device provided by the present disclosure are as follows:

[0005] In one aspect, an embodiment of the present disclosure provides a wiring substrate, comprising:

[0006] A base substrate, the base substrate comprising a first surface and a second surface opposite to each other, wherein the second surface comprises a binding region extending along a first direction and a fan-out region located on both sides of the binding region in a second direction, a plurality of vias being provided in the fan-out region, and the first direction intersects the second direction;

[0007] a plurality of signal lines located on the side where the first surface is located, wherein the orthographic projections of the plurality of signal lines on the substrate pass through the binding area and the fan-out area along the second direction;

[0008] A plurality of connection lines are located on the side where the second surface is located, the plurality of connection lines extend from the fan-out area to the binding area, and the plurality of connection lines are coupled to the plurality of signal lines through the plurality of vias.

[0009] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, the binding area is located in a middle area of ​​the second surface.

[0010] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, the fan-out areas located on both sides of the binding area are respectively a first fan-out area and a second fan-out area;

[0011] The plurality of connection lines include constant voltage signal connection lines and common voltage signal connection lines, wherein the constant voltage signal connection lines extend from the first fan-out area to the binding area, and the common voltage signal connection lines extend from the second fan-out area to the binding area.

[0012] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, the constant voltage signal connection line includes a first constant voltage signal connection portion extending along the second direction, and the common voltage signal connection line includes a first common voltage signal connection portion extending along the second direction; wherein,

[0013] The first constant voltage signal connection portion extends from the first fan-out area to the binding area, the first common voltage signal connection portion extends from the second fan-out area to the binding area, and the first common voltage signal connection portion and the first constant voltage signal connection portion are staggered with each other in the first direction.

[0014] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, the plurality of signal lines include a plurality of constant voltage signal lines extending along the second direction and arranged along the first direction;

[0015] The constant voltage signal connection line further includes a second constant voltage signal connection portion integrally provided with the first constant voltage signal connection portion, the second constant voltage signal connection portion extending along the first direction within the first fan-out area, and the second constant voltage signal connection portion coupled to the plurality of constant voltage signal lines.

[0016] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, a line width of the second constant voltage signal connection portion in the second direction is greater than or equal to 28 mm.

[0017] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, the multiple connecting lines also include multiple connecting line groups, and the multiple connecting line groups include multiple first connecting line groups. The multiple first connecting line groups are located on a side of the first constant voltage signal connecting part close to the first common voltage signal connecting part, and on a side of the second constant voltage signal connecting part close to the binding area.

[0018] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, the first surface includes 2n*2m pad areas, where n and m are both integers greater than 2;

[0019] The multiple signal lines also include 2m signal line groups arranged in sequence along the first direction, the signal line groups are located between adjacent constant voltage signal lines and pass through the pad area along the second direction, wherein the (m+1)th signal line group to the 2mth signal line group are coupled to the multiple first connecting line groups in the (nq)th row of the pad area, q is the integer closest to W1 / W2 and greater than W1 / W2, W1 is the size of the binding area in the second direction, and W2 is the size of the pad area in the second direction.

[0020] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, the plurality of signal lines further include a plurality of common voltage signal lines extending along the second direction and arranged along the first direction;

[0021] The common voltage signal connection line also includes a second common voltage signal connection portion integrally arranged with the first common voltage signal connection portion, the second common voltage signal connection portion extends along the first direction within the second fan-out area, and the second common voltage signal connection portion is coupled to the multiple common voltage signal lines.

[0022] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, the line width of the second common voltage signal connection portion in the second direction is greater than or equal to 28 mm.

[0023] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, the multiple connecting lines also include multiple connecting line groups, and the multiple connecting line groups include multiple second connecting line groups. The multiple second connecting line groups are located on the side of the first common voltage signal connecting part close to the first constant voltage signal connecting part, and on the side of the second common voltage signal connecting part close to the binding area.

[0024] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, the first surface includes 2n*2m pad areas, where n and m are both integers greater than 2;

[0025] The multiple signal lines also include 2m signal line groups arranged in sequence along the first direction, and the signal line groups pass through the pad area along the second direction, wherein the 1st signal line group to the mth signal line group are coupled to the multiple second connection line groups in the pad area of ​​the nth row.

[0026] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, the signal line group includes an address signal line, a power signal line, and a feedback signal line, and the connection line group includes an address signal connection line, a power signal connection line, and a feedback signal connection line; wherein,

[0027] The address signal connection line is coupled to the address signal line, the power signal connection line is coupled to the power signal line, the feedback signal connection line is coupled to the feedback signal line, and the address signal line and the feedback signal line of the same signal line group in the pad area of ​​the 2nth row are integrally arranged.

[0028] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, the line width of the address signal connection line is greater than or equal to 0.1 mm, the line width of the power signal connection line is greater than or equal to 0.2 mm, and the line width of the feedback signal connection line is greater than or equal to 0.1 mm.

[0029] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, the first surface includes 2n*2m pad areas, where n and m are both integers greater than 2;

[0030] A first pad group and a second pad group are provided in the pad area. The first pad group includes at least two sub-pad groups. At least in the 2nth row of pad area, the second pad group is located between adjacent sub-pad groups.

[0031] In some embodiments, the above-mentioned wiring substrate provided in the embodiments of the present disclosure further includes an insulating layer located on the side of the multiple connecting lines away from the base substrate, the insulating layer includes multiple openings located in the binding area, and within the binding area, the orthographic projections of the multiple connecting lines on the base substrate are located within the orthographic projections of the multiple openings on the base substrate.

[0032] On the other hand, an embodiment of the present disclosure provides an electronic device, comprising at least one of the above-mentioned wiring substrates provided by an embodiment of the present disclosure, and a plurality of light-emitting structures coupled to the plurality of signal lines.

[0033] In some embodiments, in the above-mentioned electronic device provided in the embodiments of the present disclosure, the first surface includes a plurality of pad areas, a first pad group and a second pad group are arranged in the pad areas, and the light-emitting structure includes an electronic component coupled to the first pad group, and a micro-driving chip coupled to the second pad group.

[0034] In some embodiments, the electronic device provided in the embodiments of the present disclosure further includes a driving circuit board, wherein the driving circuit board is coupled to the plurality of connection lines in the binding area.

[0035] In some embodiments, in the electronic device provided by the embodiments of the present disclosure, the driving circuit board includes a chip on film.

[0036] In another aspect, an embodiment of the present disclosure provides a method for manufacturing a wiring substrate, comprising:

[0037] Providing a substrate, the substrate comprising a first surface and a second surface disposed opposite to each other, wherein the second surface comprises a binding region extending along a first direction and fan-out regions located on both sides of the binding region in a second direction, the first direction intersecting the second direction;

[0038] forming a plurality of via holes penetrating the base substrate in a direction perpendicular to the first surface and the second surface at predetermined positions of the fan-out region;

[0039] A plurality of signal lines are formed on the side where the first surface is located, and the orthographic projections of the plurality of signal lines on the substrate penetrate the binding area and the fan-out area along the second direction; and a plurality of connecting lines are formed on the side where the second surface is located, extending from the fan-out area to the binding area, and the plurality of connecting lines are coupled to the plurality of signal lines through the plurality of vias. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a schematic structural diagram of a wiring substrate in the related art;

[0041] FIG2 is a schematic structural diagram of a wiring substrate provided in an embodiment of the present disclosure;

[0042] FIG3 is a schematic diagram of wiring on the side where the first surface is located in the wiring substrate shown in FIG2;

[0043] FIG4 is a schematic diagram of wiring on the side of the second surface of the wiring substrate shown in FIG2 ;

[0044] FIG5 is a schematic diagram of the cross-sectional splicing structure along lines I-II and III-IV in FIG2 ;

[0045] FIG6 is a schematic diagram showing the structural division of a wiring substrate provided in an embodiment of the present disclosure;

[0046] FIG7 is a schematic diagram of current flow in a pad area PA of a wiring substrate provided by an embodiment of the present disclosure;

[0047] FIG8 is an enlarged structural diagram of the Z1 region in FIG3 ;

[0048] FIG9 is an enlarged structural diagram of the Z2 area in FIG3 ;

[0049] FIG10 is a schematic diagram of the enlarged structure of the Z3 area in FIG3 ;

[0050] FIG11 is an enlarged structural diagram of the Z4 region in FIG8 ;

[0051] FIG12 is an enlarged structural diagram of the Z5 region in FIG9 ;

[0052] FIG13 is a schematic diagram of the enlarged structure of the Z6 region in FIG10 ;

[0053] FIG14 is a schematic structural diagram of an electronic device provided in an embodiment of the present disclosure;

[0054] FIG15 is a schematic diagram of another structure of an electronic device provided in an embodiment of the present disclosure;

[0055] FIG16 is a schematic structural diagram of the side of the electronic device shown in FIG15 where the first surface is located;

[0056] FIG17 is an enlarged structural diagram of the Z7 region in FIG16 ;

[0057] FIG18 is a schematic structural diagram of a micro driver chip provided in an embodiment of the present disclosure;

[0058] FIG19 is a schematic structural diagram of the side of the electronic device shown in FIG15 where the second surface is located;

[0059] FIG20 is a flow chart of a method for manufacturing a wiring substrate according to an embodiment of the present disclosure;

[0060] FIG21 is a flow chart of via fabrication and filling according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] To further clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be described below in conjunction with the accompanying drawings. It should be noted that, to further clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be described below in conjunction with the accompanying drawings. It should be noted that in the accompanying drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. Example embodiments are described in this disclosure with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures as a result of, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape resulting from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features; sharp corners illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their sizes and shapes are not intended to depict the precise shapes of the regions or reflect true scale. They are intended solely to illustrate the present disclosure. The same or similar reference numerals throughout the text represent the same or similar elements or elements having the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0062] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0063] In the following description, when an element or layer is referred to as being “on” or “connected to” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as being “disposed on one side of” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intermediate elements or intermediate layers. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0064] In recent years, the advantages of glass substrates have become increasingly prominent in emerging display technologies. Compared to printed circuit boards, glass substrates offer superior thermal conductivity, high flatness, and a low coefficient of expansion. These characteristics allow them to better support chip-on-board (COB) packaging of micro-LEDs, eliminating the potential for adhesive cracking caused by the difference in thermal expansion coefficients between the encapsulant and the printed circuit board material. Furthermore, when creating high-definition backlight zoning, glass substrates enable narrow bezels and low OD values ​​(the distance between the bottom surface of the diffuser and the top surface of the circuit board), making products thinner and more stylish. Furthermore, glass substrates allow for larger backplane areas as needed, enabling unlimited splicing at a relatively low cost, and possess excellent high-frequency electrical properties.

[0065] Glass material is an insulating material with a dielectric constant of only about 1 / 3 of that of silicon material, and a loss factor 2 to 3 orders of magnitude lower than that of silicon material, which greatly reduces substrate loss and parasitic effects, ensuring the integrity of the transmitted signal. Large-size ultra-thin glass substrates are easy to obtain. For example, relevant glass manufacturers can provide ultra-large-size (>2m*2m) and ultra-thin (<50μm) panel glass and ultra-thin flexible glass materials. Benefiting from the easy availability of large-size ultra-thin panel glass and the lack of the need to deposit an insulating layer, the production cost of a glass-based adapter plate is only about 1 / 8 of that of a silicon-based adapter plate. In addition, even when the thickness of the glass-based adapter plate is less than 100μm, the warping is still small, showing good mechanical stability.

[0066] Micro-light-emitting diode display technology combines many advantages of liquid crystal display technology and organic light-emitting display technology. In particular, when micro-light-emitting diode display technology is applied to backlight sources, it can achieve more precise dynamic backlight effects. While effectively improving screen brightness and contrast, it can also solve the glare phenomenon caused by traditional dynamic backlight between bright and dark areas of the screen, optimize the visual experience, and is more suitable for ultra-large screen products.

[0067] FIG1 is a schematic diagram of the structure of an electronic device in the related art. As shown in FIG1 , the electronic device includes a light-emitting area AA, a fan-out area FA, and a bonding area BA, which are arranged in sequence along the longitudinal direction. The light-emitting area AA is provided with a plurality of sub-pixels SPX arranged in an array. Each sub-pixel SPX includes multiple light-emitting diodes (LEDs) (e.g., mini LEDs, Micro LEDs, etc.) and a micro driver chip (IC). Each column of sub-pixels SPX is coupled to a signal line group. Each signal line group, along with the LEDs and the micro driver chip (IC), is co-located on the same side of a substrate 101. A signal line group includes a constant voltage signal line (VLED), an address signal line (ADDR), a power signal line (PWR), a common voltage signal line (GND), and a feedback signal line (FB). These signal lines extend from the light-emitting area AA to the fan-out area FA and are then coupled to the driver circuit (e.g., chip-on-film (COF)) in the bonding area BA. However, the fan-out area FA and the bonding area BA occupy a large space, resulting in a wide lower frame, which is not conducive to the splicing of large-scale electronic devices.

[0068] In order to at least improve the above technical problems existing in the related art, an embodiment of the present disclosure provides a wiring substrate, as shown in Figures 2 to 5, comprising:

[0069] A base substrate 101 includes a first surface S1 and a second surface S2 disposed opposite to each other, wherein the second surface S2 includes a bonding area BA extending along a first direction X and a fan-out area FA located on both sides of the bonding area BA in a second direction Y. A plurality of vias H are disposed in the fan-out area FA. The first direction X intersects the second direction Y. In some embodiments, the base substrate 101 may be a substrate that allows visible light to pass through, such as glass, quartz, plastic, or the like.

[0070] A plurality of signal lines 102 are located on the side where the first surface S1 is located. The orthographic projections of the plurality of signal lines 102 on the base substrate 101 extend along the second direction Y through the bonding area BA and the fan-out area FA. As shown in FIG3 , the first surface S1 only includes the light-emitting area AA. Optionally, the material of the signal lines 102 includes, but is not limited to, a metal such as copper (Cu).

[0071] Multiple connecting lines 103 are located on the side where the second surface S2 is located. The multiple connecting lines 103 extend from the fan-out area FA to the binding area BA, and the multiple connecting lines 103 are coupled to the multiple signal lines 102 through multiple vias H in the fan-out area FA; optionally, the material of the signal line 102 includes but is not limited to metals such as copper (Cu).

[0072] In the wiring substrate provided in the embodiments of the present disclosure, multiple signal lines 102 in the light-emitting area AA are arranged on the side of the first surface S1 of the base substrate 101, and the fan-out area FA and the bonding area BA are moved to the side of the second surface S2 of the base substrate 101. At the same time, multiple connecting lines 103 are arranged on the side of the second surface S2. Through holes H extending through the base substrate 101 are used to electrically connect the connecting lines 103 and the signal lines 102, ensuring that the driving circuit (e.g., a chip-on-film (COF)) in the bonding area BA can apply driving signals to the signal lines 102 via the connecting lines 103. Since the fan-out area FA and the bonding area BA at the bottom frame are moved to the opposite side of the light-emitting area AA, the width of the bottom frame of the base substrate 101 can be reduced, facilitating the splicing of large-size display panels.

[0073] In addition, compared with laying out the connecting line 103 on one side of the binding area BA, the present disclosure sets up fan-out areas FA on both sides of the binding area BA in the second surface S2, and lays out the connecting line 103 in the fan-out areas FA on both sides, thereby ensuring that there is sufficient wiring space in the fan-out areas FA on both sides, which can increase the width of the connecting line 103, reduce the thickness of the layer where the connecting line 103 is located, reduce resistance, and improve signal uniformity; and the wider connecting line 103 can achieve better heat dissipation effect; furthermore, the wider connecting line 103 increases the proportion of copper in the copper process, so that the etching part is less, thereby reducing the amount of etching solution used, which is beneficial to reducing the cost of the etching process.

[0074] Furthermore, in large-scale products, to ensure signal uniformity, the light-emitting area AA needs to be divided into multiple areas, and multiple driver circuits (e.g., eight chip-on-film (COF)) are provided to load drive signals to the signal lines 102 within each area. In the present disclosure, since there is ample wiring space within the fan-out areas FA on both sides, the resistance can be reduced and signal uniformity improved by increasing the width of the connecting lines 103. Therefore, in large-scale products, a single driver circuit (e.g., one chip-on-film (COF)) can be used to load drive signals to all signal lines 102. Based on this, the present disclosure can save seven driver circuits (e.g., seven chip-on-film (COF)) compared to related technologies, and after mass production, it can demonstrate significant economic benefits, convenient connections, and simpler assembly.

[0075] In some embodiments, to ensure simple wiring and no short circuits, the related art places the constant voltage signal line (VLED), address signal line (ADDR), power signal line (PWR), common voltage signal line (GND) and feedback signal line (FB), as well as the fan-out lines corresponding to these signal lines, on the same side of two conductive layers, that is, a single-sided double-layer copper process is used to manufacture the constant voltage signal line (VLED), address signal line (ADDR), power signal line (PWR), common voltage signal line (GND) and feedback signal line (FB), as well as the fan-out lines corresponding to these signal lines. The present disclosure can place all signal lines 102 (including constant voltage signal lines, address signal lines, power signal lines, common voltage signal lines and feedback signal lines) on the same layer and with the same material on the side where the first surface S1 is located, and place all connecting lines 103 on the same layer and with the same material on the side where the second surface S2 is located, that is, the present disclosure can use a single-sided single-layer copper process to complete the production of all signal lines 102 and all connecting lines 103. The single-sided single-layer copper process is relatively simpler than the single-sided double-layer copper process and has a higher yield.

[0076] In some embodiments, in the wiring substrate provided in the embodiments of the present disclosure, as shown in Figures 2 and 4, the bonding area BA can be positioned in the middle region of the second surface S2, so that there is ample wiring space in the fan-out areas FA on both sides of the bonding area BA. This allows the connection lines 103 dispersed in the fan-out areas FA to be arranged wider, thereby reducing resistance and improving signal uniformity. It should be noted that the "middle region of the second surface S2" in the present disclosure can be understood as the region near the central axis of the second surface S2 along the first direction X, for example, the region approximately two rows of sub-pixels SPX away from the central axis of the second surface S2 along the first direction X along the second direction Y. For example, if there are 24 rows of sub-pixels SPX along the second direction Y, the middle region of the second surface S2 can be the region where the sub-pixels SPX in the 10th row through the 14th row are located.

[0077] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, as shown in Figures 2 to 4, the fan-out areas FA located on both sides of the bonding area BA are respectively a first fan-out area FA1 and a second fan-out area FA2; the multiple connection lines 103 include a constant voltage signal connection line 1031 and a common voltage signal connection line 1032, wherein the constant voltage signal connection line 1031 is coupled to the multiple constant voltage signal lines 1021 extending along the second direction Y and arranged along the first direction X, and the constant voltage signal connection line 1031 extends from the first fan-out area FA1 to the bonding area BA; the common voltage signal connection line 1032 is coupled to the multiple common voltage signal lines 1022 extending along the second direction Y and arranged along the first direction X, and the common voltage signal connection line 1032 extends from the second fan-out area FA2 to the bonding area BA.

[0078] By configuring the constant voltage signal connection line 1031 to extend from the first fan-out area FA1 on one side of the binding area BA to the binding area BA, and configuring the common voltage signal connection line 1032 to extend from the second fan-out area FA2 on the other side of the binding area BA to the binding area BA, it is beneficial to ensure that both the constant voltage signal connection line 1031 and the common voltage signal connection line 1032 have a larger line width (for example, greater than or equal to 28 μm), reducing the resistance of the constant voltage signal connection line 1031 and the common voltage signal connection line 1032, thereby reducing the difference in constant voltage signals provided by the constant voltage signal connection line 1031 to the multiple constant voltage signal lines 1021, and reducing the difference in common voltage signals provided by the common voltage signal connection line 1032 to the multiple common voltage signal lines 1022. At the same time, the larger line widths of the constant voltage signal connection line 1031 and the common voltage signal connection line 1032 on both sides of the binding area BA ensure that the pattern density on both sides of the binding area BA is comparable, which is beneficial to improving the etching effect.

[0079] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, as shown in Figures 2 to 4, the constant voltage signal connection line 1031 includes a first constant voltage signal connection portion 311 extending along the second direction Y, and the common voltage signal connection line 1032 includes a first common voltage signal connection portion 321 extending along the second direction Y; wherein, the first constant voltage signal connection portion 311 extends from the first fan-out area FA1 to the binding area BA, and the first common voltage signal connection portion 321 extends from the second fan-out area FA2 to the binding area BA. In some embodiments, in order to ensure simple wiring and no short-circuiting, the first common voltage signal connection portion 321 and the first constant voltage signal connection portion 311 can be set to be staggered with each other in the first direction X.

[0080] In some embodiments, in the wiring substrate provided in the embodiments of the present disclosure, as shown in Figures 2 to 4 , the constant-voltage signal connection line 1031 may further include a second constant-voltage signal connection portion 312 integrally provided with the first constant-voltage signal connection portion 311. The second constant-voltage signal connection portion 312 extends along the first direction X within the first fan-out area FA1, and the second constant-voltage signal connection portion 312 is coupled to the plurality of constant-voltage signal lines 1021. Optionally, the second constant-voltage signal connection portion 312 is coupled to the plurality of constant-voltage signal lines 1021 within the area where the first row of sub-pixels SPX is located. Optionally, to ensure a low resistance of the second constant-voltage signal connection portion 312, a line width d1 of the second constant-voltage signal connection portion 312 in the second direction Y may be set to be greater than or equal to 28 mm. In some embodiments, if there is sufficient wiring space, the line width d2 of the first constant-voltage signal connection portion 311 in the first direction X can be set to be greater than or equal to the line width d1 of the second constant-voltage signal connection portion 312 in the second direction Y. For example, the line width d2 of the first constant-voltage signal connection portion 311 in the first direction X is greater than or equal to 28 mm. In the case of limited wiring space, the line width d2 of the first constant-voltage signal connection portion 311 in the first direction X can be set to be less than the line width d1 of the second constant-voltage signal connection portion 312 in the second direction Y. For example, the line width d2 of the first constant-voltage signal connection portion 311 in the first direction X is less than 28 mm. This is not specifically limited in the present disclosure.

[0081] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, as shown in Figures 2 to 4, the multiple connecting lines 103 may also include multiple connecting line groups CL, and the multiple connecting line groups CL include multiple first connecting line groups CL1. The multiple first connecting line groups CL1 are located on the side of the first constant voltage signal connection part 311 close to the first common voltage signal connection part 321, and on the side of the second constant voltage signal connection part 312 close to the binding area BA. That is, the multiple first connecting line groups CL1 are arranged in an area surrounded by the first constant voltage signal connection part 311, the second constant voltage signal connection part 312 and the binding area BA and close to the first common voltage signal connection part 321. The wiring space in this area is relatively large, which is conducive to the flexible arrangement of multiple first connecting line groups CL1.

[0082] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, as shown in Figures 2 to 4 and 6, the first surface S1 includes 2n*2m pad areas PA, and one pad area PA can be coupled with multiple light-emitting diodes LED and a micro driver chip (IC) to form an area where a sub-pixel SPX is located, where n and m are both integers greater than 2, for example, n is 12 and m is 24; optionally, the plurality of signal lines 102 further include 2m signal line groups SL arranged in sequence along the first direction X, and the signal line group SL is located adjacent to the constant voltage signal line. 1021 and pass through the pad area PA along the second direction Y, wherein the (m+1)th signal line group to the 2mth signal line group are coupled to the multiple first connection line groups CL1 in the (nq)th row pad area PA, optionally, each of the (m+1)th signal line group to the 2mth signal line group is coupled one-to-one with each of the multiple first connection line groups CL1, q is the integer closest to W1 / W2 and greater than W1 / W2, W1 is the size of the binding area BA in the second direction Y, and W2 is the size of the pad area PA in the second direction Y.

[0083] Since the nth row of pad area PA is centrally located on the first surface S1, and the (nq)th row of pad area PA is offset from the nth row of pad area PA by the width of a binding area BA in the second direction Y, the (nq)th row of pad area PA can be considered to be located in the middle region of the first surface S1. On this basis, the (m+1)th to 2mth signal line groups are coupled to the plurality of first connection line groups CL1 within the (nq)th row of pad area PA. This allows the drive signals provided by the first connection line groups CL1 to the (m+1)th to 2mth signal line groups to be transmitted from the (nq)th row of pad area PA to both the first and last row of pad areas PA simultaneously, thereby reducing differences in the drive signals of the pad areas PA in each row due to line resistance and improving the uniformity of the drive signals.

[0084] In some embodiments, in the wiring substrate provided in the embodiments of the present disclosure, as shown in Figures 2 to 4 , the common voltage signal connection line 1032 may further include a second common voltage signal connection portion 322 integrally provided with the first common voltage signal connection portion 321. The second common voltage signal connection portion 322 extends along the first direction X within the second fan-out area FA2, and the second common voltage signal connection portion 322 is coupled to the plurality of common voltage signal lines 1022. Optionally, the second common voltage signal connection portion 322 is coupled to the plurality of common voltage signal lines 1022 within the region where the last row of sub-pixels SPX is located. Optionally, to ensure a low resistance of the second common voltage signal connection portion 322, a line width d3 of the second common voltage signal connection portion 322 in the second direction Y may be set to be greater than or equal to 28 mm. In some embodiments, if there is sufficient wiring space, the line width d4 of the first common voltage signal connection portion 321 in the first direction X can be set to be greater than or equal to the line width d3 of the second common voltage signal connection portion 322 in the second direction Y, for example, the line width d4 of the first common voltage signal connection portion 321 in the first direction X is greater than or equal to 28 mm; and if the wiring space is limited, the line width d4 of the first common voltage signal connection portion 321 in the first direction X can be set to be smaller than the line width d3 of the second common voltage signal connection portion 322 in the second direction Y, for example, the line width d4 of the first common voltage signal connection portion 321 in the first direction X is less than 28 mm; this disclosure does not make any specific limitations on this.

[0085] In some embodiments, in the wiring substrate provided in the embodiments of the present disclosure, as shown in Figures 2 to 4 , the multiple connection line groups CL may further include multiple second connection line groups CL2. The multiple second connection line groups CL2 are located on a side of the first common voltage signal connection portion 321 close to the first constant voltage signal connection portion 311, and on a side of the second common voltage signal connection portion 322 close to the bonding area BA. In other words, the multiple second connection line groups CL2 are arranged in an area surrounded by the first common voltage signal connection portion 321, the second common voltage signal connection portion 322, and the bonding area BA, and close to the first constant voltage signal connection portion 311. This area provides ample wiring space, facilitating flexible layout of the multiple second connection line groups CL2. Furthermore, the multiple first connection line groups CL1 and the multiple second connection line groups CL2 are located on either side of the bonding area BA, effectively ensuring that the pattern density on both sides of the bonding area BA is comparable, which improves the etching effect.

[0086] In some embodiments, in the wiring substrate provided in the embodiments of the present disclosure, as shown in Figures 2 to 4 and 6, the first to mth signal line groups are coupled to a plurality of second connection line groups CL2 within the nth row pad area. Optionally, each of the first to mth signal line groups is coupled to each of the plurality of second connection line groups CL2 in a one-to-one correspondence. Because the nth row pad area PA is centrally located on the first surface S1, the first to mth signal line groups are coupled to the plurality of second connection line groups CL2 within the nth row pad area. This allows the drive signals provided by the second connection line groups CL2 to the first to mth signal line groups to be transmitted from the nth row pad area PA to both the first row pad area PA and the last row pad area PA simultaneously, thereby reducing differences in the drive signals of each row pad area PA due to line resistance and improving the uniformity of the drive signals.

[0087] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, as shown in Figures 2 to 4, the signal line group SL includes an address signal line 1023, a power signal line 1024 and a feedback signal line 1025, and the connection line group CL includes an address signal connection line 1033, a power signal connection line 1034 and a feedback signal connection line 1035; wherein, the address signal connection line 1033 is coupled to the address signal line 1023, the power signal connection line 1034 is coupled to the power signal line 1024, and the feedback signal connection line 1035 is coupled to the feedback signal line 1025, and the address signal line 1023 and the feedback signal line 1025 of the same signal line group CL in the 2nth row pad area PA (i.e., the last row pad area PA) are integrally arranged, so that a current loop is formed in the same column pad group PA.

[0088] In some embodiments, to ensure signal uniformity, the width of the address signal connection line 1033 can be set to be greater than or equal to 0.1 mm, the width of the power signal connection line 1034 can be set to be greater than or equal to 0.2 mm, and the width of the feedback signal connection line 1035 can be set to be greater than or equal to 0.1 mm. It should be understood that the upper limit of the width of the address signal connection line 1033, the power signal connection line 1034, and the feedback signal connection line 1035 can be set based on the manufacturing process accuracy and wiring space, and is not limited here.

[0089] To better understand the current flow in the present disclosure, the following explanation is based on an example of a wiring substrate with 24*48 pad areas PA. As shown in Figures 6 and 7, the 24*48 pad areas PA are equally divided into left and right. For the left half of the screen: for the pad areas PA in columns 1 to 24 and rows 1 to 12, the address signal addr and the power signal pwr flow into the pad area PA in row 12 and out of the pad area PA in row 1, and the feedback signal fb flows from the pad area PA in row 1 to the pad area PA in row 12; for the pad areas PA in columns 1 to 24 and rows 13 to 24, the address signal addr and the power signal pwr flow into the pad area PA in row 12 and out of the pad area PA in row 24, and the feedback signal fb flows from the pad area PA in row 24 to the pad area PA in row 12. For the right half of the screen: For pad areas PA in columns 25 to 48 and rows 1 to 10, the address signal addr and power signal pwr flow from pad area PA in row 10 and out of pad area PA in row 1, and the feedback signal fb flows from pad area PA in row 1 to pad area PA in row 10. For pad areas PA in columns 25 to 48 and rows 11 to 24, the address signal addr and power signal pwr flow from pad area PA in row 10 and out of pad area PA in row 24, and the feedback signal fb flows from pad area PA in row 24 to pad area PA in row 10. Furthermore, for both the left and right half of the screen, the constant voltage signal vled flows from pad area PA in row 1 to pad area PA in row 24, and the common voltage signal gnd flows from pad area PA in row 24 to pad area PA in row 1.

[0090] In some embodiments, in the above-mentioned wiring substrate provided by the embodiments of the present disclosure, as shown in Figures 2, 3, 8 to 10, a first pad group 104 and a second pad group 105 are provided in the pad area PA, and the first pad group 104 includes at least two sub-pad groups 1041. Optionally, at least two sub-pad groups 1041 in the same first pad group 104 can be arranged in series, in parallel, or in series and parallel. In some embodiments, in order to further reduce the width of the lower frame, the second pad group 105 can be provided at least in the 2nth row of pad areas PA (i.e., the last row of pad areas PA), and is located between adjacent sub-pad groups 1041. For example, in Figure 10, the second pad group 105 is located between two adjacent sub-pad groups 1041 on the right. Of course, in some embodiments, the second pad group 105 can also be located in the center of the area enclosed by the four sub-pad groups 1041, which is not limited here. 2 , 3 , 8 and 9 , it can be seen that in the 1st to (2n-1)th row of pad areas PA of the present disclosure, the second pad group 105 may be located on a side of the first pad group 104 close to the next row of pad areas PA.

[0091] In some embodiments, as shown in FIG. 8 to FIG. 10 , a sub-pad group 1041 may include a first pad P and a second pad N. The first pad P and the second pad N may be coupled to the positive and negative electrodes of a light emitting diode LED, respectively.

[0092] In some embodiments, as shown in Figures 11 to 13, the second pad group 105 may include an output pad Out, an address pad Di-in, a power pad Pwr, and a ground pad Gnd. As shown in Figures 11 and 12, within the pad areas PA of the 1st to (2n-1)th rows, the address pads Di-in and the power pad Pwr belonging to the same second pad group 105 are spaced apart in the first direction X and spaced apart in the second direction Y from the output pad Out, and the ground pad Gnd is spaced apart in the second direction Y from the power pad Pwr and spaced apart in the first direction X from the output pad Out; illustratively, the output pad Out is located at the upper left corner of the second pad group 105, the address pad Di-in is located at the lower left corner of the second pad group 105, the ground pad Gnd is located at the upper right corner of the second pad group 105, and the power pad Pwr is located at the lower right corner of the second pad group 105. As shown in Figure 13, in the 2nth row of pad area PA, the address pad Di-in and the ground pad Gnd belonging to the same second pad group 105 are spaced apart in the first direction X and spaced apart from the output pad Out in the second direction Y, and the power supply pad Pwr and the ground pad Gnd are spaced apart in the second direction Y and spaced apart from the output pad Out in the first direction X; illustratively, the output pad Out is located at the lower left corner of the second pad group 105, the address pad Di-in is located at the upper left corner of the second pad group 105, the ground pad Gnd is located at the upper right corner of the second pad group 105, and the power supply pad Pwr is located at the lower right corner of the second pad group 105.

[0093] In some embodiments, each second pad group 105 can be coupled to a micro driver chip (IC), and the address pad Di-in can receive an address signal for selecting the micro driver chip (IC) of the corresponding address. The power supply pad Pwr can provide the micro driver chip (IC) with an operating voltage and communication data, and the communication data can be used to control the working state of the corresponding light emitting diode LED. The output pad Out can output a relay signal and a drive signal respectively in different time periods. Optionally, the relay signal is an address signal provided to the address pad Di-in in the second pad group 105 in the next row in the same column, and the drive signal is a drive current for driving the light emitting diode LED coupled to the second pad group 105 where the output pad Out is located. The ground pad Gnd receives a common voltage signal.

[0094] In some embodiments, in the above-mentioned wiring substrate provided in the embodiment of the present disclosure, as shown in Figures 8 to 13, a first insulating layer 106 located on the side of the plurality of signal lines 102 away from the base substrate 101 may also be included. Optionally, the material of the first insulating layer 106 may be silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc. The first insulating layer 106 may be a single layer or a multi-layer structure. For example, the first insulating layer 106 includes a stacked silicon nitride layer and a Silicon oxide layer; the first insulating layer 106 may have a plurality of first openings K1, the first openings K1 may expose a portion of the common voltage signal line 1022 as a ground pad Gnd, expose a portion of the power signal line 1024 as a power supply pad Pwr, expose a portion of the address signal line 1023 in the last row of pad areas PA as an address pad Di-in, expose the two ends of the address signal line 1023 connected between two adjacent rows of pad areas PA as the address pad Di-in in the previous row of pad areas PA, and expose the output pad Out in the next row of pad areas PA. In addition, as shown in Figures 8 to 10, the wiring substrate may also be provided with a plurality of traces 107 of the same layer and material as the signal line 102, and the first insulating layer 106 may also include a plurality of second openings K2, the second openings K2 exposing a portion of the trace 107 as a first pad P and a second pad N.

[0095] In some embodiments, the wiring substrate provided in the embodiments of the present disclosure may further include a reflective layer 108 located on the side of the first insulating layer 106 away from the base substrate 101, as shown in Figures 8 to 13. For example, an insulating reflective material such as white oil may be coated on the first insulating layer 106 to form the reflective layer 108. The reflective layer 108 includes a plurality of third openings K3 for exposing the second pad group 105 and a plurality of fourth openings K4 for exposing the sub-pad group 1041. The reflective layer 108 is used to reflect incident light toward the light-emitting side of the wiring substrate, thereby improving the utilization rate of the light emitted by the light-emitting diode (LED).

[0096] In some embodiments, in the above-mentioned wiring substrate provided in the embodiments of the present disclosure, as shown in Figure 4, it may also include a second insulating layer 109 located on the side of the multiple connecting lines 103 away from the base substrate 101. The material of the second insulating layer 109 can be silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc. The second insulating layer 109 can be a single-layer or multi-layer structure. For example, the second insulating layer 109 includes a stacked silicon nitride layer and a silicon oxide layer; optionally, the second insulating layer 109 includes a plurality of fifth openings K5 located in the binding area BA, and in the binding area BA, the orthographic projections of the multiple connecting lines 103 on the base substrate 101 are located within the orthographic projections of the multiple fifth openings K5 on the base substrate 101, so that the multiple fifth openings K5 expose the portions of the multiple connecting lines 103 located in the binding area BA, thereby facilitating the subsequent electrical connection of the multiple connecting lines 103 with the driving circuit (for example, chip-on-film COF) in the binding area BA.

[0097] In some embodiments, in the wiring substrate provided in the embodiments of the present disclosure, as shown in FIG5 , in order to increase the adhesion of the signal line 102 and the connecting line 103 to the base substrate 101, a first buffer layer 110 may be provided between the base substrate and the layer where the signal line 102 is located, and a second buffer layer 111 may be provided between the layer where the connecting line 103 is located and the base substrate 101. The first buffer layer 110 and the second buffer layer 111 are hollowed out at the via H. Optionally, the material of the first buffer layer 110 and the second buffer layer 111 includes at least one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc. In addition, as can be seen from FIG2 , FIG3 , and FIG8 to FIG10 , the wiring substrate may further include an electrostatic ring 112. The electrostatic ring 112 is provided in the same layer and material as the signal line 102 and surrounds the light-emitting area AA to prevent static electricity from damaging components within the light-emitting area AA. It should be understood that other essential components of the wiring substrate are well understood by those skilled in the art and are not described in detail herein and should not be construed as limiting the present disclosure.

[0098] Based on the same inventive concept, embodiments of the present disclosure provide an electronic device, as shown in Figures 14 and 15 , comprising at least one wiring substrate 001 provided in embodiments of the present disclosure, and a plurality of light-emitting structures 002 coupled to a plurality of signal lines 102. The specific implementation of the electronic device provided in embodiments of the present disclosure can be referenced to the specific implementation of the wiring substrate provided in embodiments of the present disclosure, and any repetitions will not be repeated.

[0099] When splicing multiple wiring substrates 001 to form a large electronic device, the size of the seam between adjacent wiring substrates 001 can affect the visual effect. Taking the splicing of multiple wiring substrates 001 along the second direction Y as an example, Figure 15 shows a schematic diagram of the splicing of two side-by-side wiring substrates 001. d5 is the distance between two adjacent rows of pad areas PA on a wiring substrate 001, d6 is the distance between two adjacent rows of pad areas PA at the splice of the two wiring substrates 001, and the distance d7 between the pad area PA closest to the spliced ​​side edge of the wiring substrate 001 and the spliced ​​side edge. To achieve a better splicing visual effect, d5 should be equal to d6. During the splicing of two wiring substrates 001, if d5 is greater than d6, the two wiring substrates 001 to be spliced ​​can be spaced a certain distance apart, that is, the spacing between the two wiring substrates 001 can be increased; however, if d5 is less than d6, then in order to achieve an ideal splicing effect, the side of the wiring substrate 001 used for splicing has a narrower size, that is, the distance d7 between the pad area PA closest to the splicing side of the wiring substrate 001 and the splicing side needs to be reduced. The present disclosure can reduce the size of the lower frame (that is, the distance d7 between the pad area PA closest to the splicing side of the wiring substrate 001 and the splicing side) by arranging the fan-out area FA and the binding area BA on the side where the second surface S2 is located. Therefore, the present disclosure is conducive to the splicing of large-sized electronic devices and can ensure good visual effects.

[0100] In some embodiments, in the electronic device provided by the embodiments of the present disclosure, as shown in FIG16 and FIG17 , the light emitting structure 002 includes an electronic component 003 coupled to the first pad group 104, and a micro driver chip 004 coupled to the second pad group 105. Optionally, the orthographic projection area of ​​the micro driver chip 004 on the base substrate 101 is not greater than 300,000 μm. 2 Electronic component 003 is a light-emitting diode, the light-emitting area of ​​which does not exceed 300,000 μm 2 , specifically, may not exceed 40000μm 2 The light-emitting diode has two pins, and each sub-pad group 1041 includes a first pad P and a second pad N, which are respectively connected to the two pins of the light-emitting diode. It is understood that when electronic component 003 is another component, it can have another number of pins. Accordingly, each sub-pad group 1041 has the same number of pads as the pins of the other component.

[0101] In some embodiments, the electronic device provided in the embodiments of the present disclosure may further include a plurality of first transparent protective structures 005, as shown in FIG16 and FIG17, wherein the orthographic projections of the first transparent protective structures 005 on the base substrate 101 respectively cover the orthographic projections of the electronic components 003 on the base substrate 101, so as to protect the electronic components 003 through the first transparent protective structures 005, and when the electronic components 003 are light-emitting diodes, the first transparent protective structures 005 may also serve to enhance the light efficiency.

[0102] In some embodiments, the first transparent protective structure 005 can be fabricated by dispensing or screen printing. Alternatively, to achieve better protection and effectively improve light efficiency, the first transparent protective structure 005 can be formed in a dome shape over the electronic component 003 (e.g., a light-emitting diode). This type of first transparent protective structure 005 can be referred to as a droplet lens. As shown in FIG17 , the orthographic projection radius r of the first transparent protective structure 005 on the base substrate 101 can be 1450 μm. However, considering that there may be deviations in the actual fabrication of the first transparent protective structure 005, for example, the deviation can be within ±150 μm, that is, the maximum radius rmax of the orthographic projection of the first transparent protective structure 005 on the base substrate 101 is 1600 μm, and the minimum radius rmin is 1400 μm.

[0103] Continuing with FIG. 17 , it can be seen that in some embodiments, the orthographic projection of the fourth opening K4 on the base substrate 101 can be located within the orthographic projection of the first transparent protective structure 005 on the base substrate 101, i.e., the first transparent protective structure 005 completely covers the fourth opening K4, thereby effectively reducing the probability of water and oxygen entering the interior of the wiring substrate 001 through the fourth opening K4 and causing corrosion of the signal line 102. Of course, in some embodiments, the orthographic projection of the fourth opening K4 on the base substrate 101 may be larger than the orthographic projection of the first transparent protective structure 005 on the base substrate 101, i.e., the first transparent protective structure 005 partially covers the fourth opening K4. In this case, a white glue pattern can be provided in the area where the fourth opening K4 extends beyond the first transparent protective structure 005 to fill the gap between the two, thereby reducing the probability of water and oxygen entering the interior of the wiring substrate 001, thereby effectively protecting the signal line 102.

[0104] In some embodiments, the electronic device provided in the embodiments of the present disclosure may further include a second transparent protective structure 006, as shown in Figures 16 and 17. The orthographic projection of the second transparent protective structure 006 on the base substrate 101 covers the orthographic projection of the micro-driver chip 004 on the base substrate 101, thereby protecting the micro-driver chip 004 via the second transparent protective structure 006. To facilitate manufacturing, the second transparent protective structure 006 and the first transparent protective structure 005 can have the same manufacturing requirements, and both can be formed in the same process flow.

[0105] Continuing with FIG. 17 , it can be seen that in some embodiments, the orthographic projection of the third opening K3 on the base substrate 101 can be located within the orthographic projection of the second transparent protective structure 006 on the base substrate 101, i.e., the second transparent protective structure 006 completely covers the third opening K3, thereby effectively reducing the probability of water and oxygen entering the interior of the wiring substrate 001 through the third opening K3 and causing corrosion of the signal line 102. Of course, in some embodiments, the orthographic projection of the third opening K3 on the base substrate 101 may be larger than the orthographic projection of the second transparent protective structure 006 on the base substrate 101, i.e., the second transparent protective structure 006 partially covers the third opening K3. In this case, a white glue pattern can be provided in the area where the third opening K3 extends beyond the second transparent protective structure 006 to fill the gap between the two, thereby reducing the probability of water and oxygen entering the interior of the wiring substrate 001, thereby effectively protecting the signal line 102.

[0106] In some embodiments, in the above-mentioned electronic device provided in the embodiments of the present disclosure, as shown in Figure 18, the micro-driving chip 004 may include a demodulation circuit 401, a physical layer interface circuit 402, a data processing control circuit 403, a pulse width modulation circuit 404, a driving signal generating circuit 405, a relay signal generating circuit 406 and a power supply circuit 407.

[0107] In some embodiments, the demodulation circuit 401 is electrically connected to the power supply pad Pwr and the physical layer interface circuit 402, and is configured to demodulate the power line carrier communication signal input by the power supply pad Pwr to obtain communication data, and transmit the communication data to the physical layer interface circuit. In the case where the electronic component 003 is a light-emitting diode, the communication data may be data reflecting the duration of the light emission, thereby representing the required light-emitting brightness. Compared to the conventional serial peripheral interface (SPI) protocol, the embodiment of the present disclosure adopts the power line carrier communication (PLC) protocol to superimpose the communication data on the power signal, which can effectively reduce the number of signal lines.

[0108] In some embodiments, the physical layer interface circuit 402 is further electrically connected to the data processing and control circuit 403 and is configured to process the communication data to obtain data frames (e.g., frame rate data) and transmit the data frames to the data processing and control circuit 403. The data frames obtained by the physical layer interface circuit 402 include information that needs to be transmitted to the micro driver chip 004, such as information related to the light-emitting time (e.g., the specific duration of the light-emitting time). Optionally, the physical layer interface circuit 402 is a conventional port physical layer (PHY). A detailed description can refer to conventional designs and will not be described in detail here.

[0109] In some embodiments, the data processing and control circuit 403 is further electrically connected to the address pad Di, the pulse width modulation circuit 404, and the relay signal generation circuit 406. The data processing and control circuit 403 is configured to generate a pulse width control signal based on the data frame and transmit the pulse width control signal to the pulse width modulation circuit 404, and to generate a relay control signal based on the address signal and transmit the relay control signal to the relay signal generation circuit 406. For example, the required light-emitting duration of the light-emitting diode connected to the micro-driver chip 004 can be obtained based on the data frame, and a corresponding pulse width control signal is generated based on the light-emitting duration. For example, the relay control signal is a signal generated after the data processing and control circuit 403 processes the first input signal. By processing the address signal (e.g., parsing, latching, decoding, etc.), the address signal corresponding to the micro-driver chip 004 can be obtained, and a relay control signal corresponding to a subsequent address can be generated, and the subsequent address corresponds to another micro-driver chip 004. Optionally, the data processing control circuit 403 may be implemented as a single chip microcomputer, a central processing unit (CPU), a digital signal processor, etc.

[0110] In some embodiments, the pulse width modulation circuit 404 is further electrically connected to the drive signal generation circuit 405 and is configured to generate a pulse width modulation signal in response to the pulse width control signal and transmit the pulse width modulation signal to the drive signal generation circuit 405. For example, the pulse width modulation signal generated by the pulse width modulation circuit 404 determines the light-emitting duration of the light-emitting diode, for example, the effective pulse width duration is equal to the light-emitting duration of the light-emitting diode.

[0111] In some embodiments, the drive signal generating circuit 405 is further electrically connected to the output pad Out and is configured to generate a drive signal in response to the pulse width modulation signal and output the drive signal from the output pad Out. Here, outputting the drive signal from the output pad Out may mean that the drive signal (e.g., drive current) flows from the output pad Out to the light-emitting diode, or may mean that the drive signal (e.g., drive current) flows from the light-emitting diode into the output pad Out. The specific current direction is not limited.

[0112] For example, in some examples, when the drive signal is a drive current, the drive signal generation circuit 405 may include a current source A and a transistor MOS. The control electrode of the transistor MOS receives the pulse width modulation signal transmitted by the pulse width modulation circuit 404, thereby turning on or off under the control of the pulse width modulation signal. The first electrode of the transistor MOS is connected to the output pad Out, the second electrode of the transistor MOS is connected to the first electrode of the current source A, and the second electrode of the current source A is connected to the ground pad Gnd to receive a common voltage. Optionally, the current source A may be a constant current source. When the pulse width modulation signal is at an active level, the transistor MOS is turned on, and the current source A provides the drive current through the output pad Out. When the pulse width modulation signal is at an inactive level, the transistor MOS is turned off, and the output pad Out does not provide the drive current. The duration of the pulse width modulation signal being at an active level is equal to the duration of the conduction of the transistor MOS, and the duration of the conduction of the transistor MOS is equal to the duration of the output pad Out providing the drive current. This can further control the light-emitting duration of the light-emitting diode, thereby controlling the visual brightness of the light. In some embodiments, when the transistor MOS is turned on, the drive current flows from the output pad Out into the micro-driver chip 004, flows sequentially through the transistor MOS and the current source A, and then flows into the ground terminal (e.g., the ground pad Gnd). It should be noted that in the embodiments of the present disclosure, the drive signal generation circuit 405 can also adopt other circuit structures, and the embodiments of the present disclosure are not limited thereto.

[0113] In some embodiments, the relay signal generating circuit 406 is also electrically connected to the output pad Out, and is configured to generate a relay signal based on the relay control signal and output the relay signal from the output pad Out. For example, the relay control signal corresponds to a subsequent address, and the relay signal generated based on the relay control signal includes a subsequent address, which corresponds to another micro-driver chip 004. After the relay signal is output from the output pad Out, it is provided to the address pad Di of the next cascaded micro-driver chip 004, so that the next cascaded micro-driver chip 004 obtains the corresponding address signal. The relay signal generating circuit 406 can be implemented by a latch, a decoder, an encoder, etc., and the embodiments of the present disclosure are not limited to this.

[0114] It should be noted that in the embodiment of the present disclosure, although the drive signal generating circuit 405 and the relay signal generating circuit 406 are both electrically connected to the output pad Out, the drive signal generating circuit 405 and the relay signal generating circuit 406 output the drive signal and the relay signal respectively in different time periods, and the drive signal and the relay signal are transmitted through the output pad Out in a time-sharing manner, and therefore will not affect each other.

[0115] In some embodiments, the power supply circuit 407 is electrically connected to the demodulation circuit 401 and the data processing and control circuit 403, respectively, and is configured to receive electrical energy and supply power to the data processing and control circuit 403. In some embodiments, after the demodulation circuit 401 demodulates the power line carrier communication signal input by the power pad Pwr, the DC power component (i.e., electrical energy) in the power line carrier communication signal is transmitted to the power supply circuit 407, which is then provided to the data processing and control circuit 403 by the power supply circuit 407. Of course, the embodiments of the present disclosure are not limited to this. The power supply circuit 407 can also be electrically connected to other circuits in the micro-driver chip 004 to provide electrical energy. The power supply circuit 407 can be implemented by a switching circuit, a voltage conversion circuit, a voltage stabilization circuit, etc., and the embodiments of the present disclosure are not limited to this.

[0116] It should be noted that the micro-driver chip 004 provided by the present disclosure may also include more circuits and components, not limited to the above-mentioned demodulation circuit 401, physical layer interface circuit 402, data processing control circuit 403, pulse width modulation circuit 404, drive signal generation circuit 405, relay signal generation circuit 406 and power supply circuit 407. This can be determined according to the functions to be implemented, and the embodiments of the present disclosure do not limit this.

[0117] In some embodiments, in the above-mentioned electronic device provided by the embodiment of the present disclosure, as shown in FIG19 , a driver circuit board 007 may also be included, and the driver circuit board 007 is coupled to the plurality of connection lines 103 in the binding area BA. Optionally, in the present disclosure, since the wiring in the fan-out area FA on both sides is sufficient, the resistance can be reduced and the signal uniformity can be improved by increasing the width of the connection line 103. Therefore, in a large-scale electronic device, one driver circuit 007 (for example, one chip-on-film COF) can be used to load the drive signal for all signal lines 102. Based on this, the present disclosure can save 7 driver circuits (for example, 7 chip-on-film COFs) compared to the related art, and after mass production, it can reflect obvious economy, convenient connection, and simpler assembly.

[0118] In some embodiments, the electronic device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, etc. Optionally, the electronic device provided in the present disclosure includes but is not limited to components such as a camera module, an ambient light sensor, a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip is a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and may realize power supply and signal input and output functions through additionally provided wires, etc. For example, the control chip may also include hardware circuits and computer executable codes, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0119] In addition, those skilled in the art will understand that the above structure does not constitute a limitation on the above electronic device provided in the embodiment of the present disclosure. In other words, the above electronic device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

[0120] Based on the same inventive concept, the present disclosure also provides a method for manufacturing a wiring substrate, as shown in FIG20 , which may include the following steps:

[0121] S2001. Provide a substrate, the substrate comprising a first surface and a second surface disposed opposite to each other, wherein the second surface comprises a binding region extending along a first direction and fan-out regions located on both sides of the binding region in a second direction, the first direction intersecting the second direction;

[0122] S2002, forming a plurality of via holes penetrating the base substrate in a direction perpendicular to the first surface and the second surface at a preset position of the fan-out region;

[0123] S2003, forming a plurality of signal lines on the side where the first surface is located, and the orthographic projections of the plurality of signal lines on the substrate penetrate the binding area and the fan-out area along the second direction;

[0124] S2004 , forming a plurality of connection lines extending from the fan-out area to the binding area on the side where the second surface is located, and coupling the plurality of connection lines to the plurality of signal lines through a plurality of vias.

[0125] It should be understood that in the above-mentioned manufacturing method provided in the embodiment of the present disclosure, the plurality of signal lines and the plurality of connecting lines are separated on both sides of the base substrate, so the order of their manufacturing does not affect each other. Therefore, the present disclosure can first execute step S2003 to manufacture the signal lines and then execute step S2004 to manufacture the connecting lines, or can first execute step S2004 to manufacture the connecting lines and then execute step S2003 to manufacture the signal lines, without specific limitation here. In addition, since the principle of solving the problem of this manufacturing method is similar to the principle of solving the problem of not being limited to the substrate, the implementation of the manufacturing method provided in the embodiment of the present disclosure can refer to the implementation of the above-mentioned wiring substrate provided in the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0126] To better understand the wiring substrate manufacturing method of the present disclosure, the following is a detailed description thereof. Optionally, the manufacturing method of the wiring substrate shown in FIG2 provided in the embodiment of the present disclosure may include the following steps:

[0127] The first step is to provide a base substrate 101. The base substrate 101 includes a first surface S1 and a second surface S2 disposed opposite each other. The second surface S2 includes a bonding area BA extending along a first direction X, and fan-out areas FA (labeled as a first fan-out area FA1 and a second fan-out area FA2) located on either side of the bonding area BA in a second direction Y. The first direction X intersects the second direction Y. Optionally, the base substrate 101 can be a glass substrate. Glass substrates have excellent thermal conductivity, high flatness, and a low expansion / contraction coefficient, making them suitable for COB packaging of light-emitting diodes. Glass substrates are also relatively low-cost and readily available, making them suitable for large-scale products.

[0128] In the second step, before drilling, the position coordinates of each via hole in the base substrate 101 (that is, the coupling position of the signal line 102 and the connecting line 103) can be determined through the design drawings, and then laser drilling technology or etching liquid etching can be used to form multiple via holes H (for example, the diameter of the via hole H is 0.2 mm) passing through the base substrate 101 in a direction perpendicular to the first surface S1 and the second surface S2.

[0129] Laser drilling technology utilizes a high-power density laser beam to irradiate the material being processed, rapidly heating it to its vaporization temperature and evaporating it to form holes. Laser drilling technology is widely used in industrial production due to its high speed, high efficiency, good economic benefits, and wide range of applications. The laser drilling and conductive material filling process in this disclosure is illustrated in Figure 21. Specifically, a plurality of via holes H can be formed on the prepared base substrate 101 using a laser drilling process according to coordinates. Subsequently, a conductive material CM (e.g., Cu) can be deposited on at least one side of the first surface S1 and the second surface S2 of the drilled base substrate 101, so that the conductive material CM completely fills each via hole H in the base substrate 101, and the first surface S1 and the second surface S2 of the base substrate 101 are both covered with the conductive material CM. Then, a chemical-mechanical planarization (CMP) method can be used to remove excess conductive material CM on the first surface S1 and the second surface S2, leaving only the conductive material CM within the via hole H to prevent interference with the subsequently fabricated signal lines 102 and connecting lines 103. It should be noted that due to the different temperatures and burning ranges at the periphery and center of the base substrate 101 during the laser drilling process, the inner and outer diameters of the openings are different. FIG19 only illustrates the approximate shape of the via hole H. In some embodiments, the shape of the via H can be various, for example, it can be a circle, an ellipse, a triangle, a square, a rectangle, a rhombus, a trapezoid, a pentagon, a regular polygon (such as a regular octagon), or any other regular or irregular shape, which is not limited here.

[0130] In the third step, a second buffer layer 111 is formed on the side of the second surface S2 . The second buffer layer 111 is hollowed out at the via H to expose the via H, so as to facilitate coupling of the connecting line 103 and the signal line 102 at the via H that is subsequently produced.

[0131] In the fourth step, a plurality of connection lines 103 extending from the fan-out area FA to the bonding area BA are formed on the second buffer layer 111 , and the plurality of connection lines 103 are coupled to the plurality of signal lines 102 to be fabricated through a plurality of vias H.

[0132] Step 5: Form a second insulating layer 109 on the layer where the multiple connecting wires 103 are located. Optionally, the second insulating layer 109 has a fifth opening K5 in the binding area BA to expose the connecting wires 103 in the binding area BA, so as to facilitate the binding connection between the connecting wires 103 and the driving circuit (such as the chip-on-film COF) in the binding area BA.

[0133] In the sixth step, a first buffer layer 110 is formed on the side where the first surface S1 is located. The first buffer layer 110 is hollowed out at the via H to expose the via H, so as to facilitate coupling of the subsequently produced signal line 102 and the connecting line 103 produced in the fourth step at the via H.

[0134] Step 7: Form multiple signal lines 102 and multiple routing lines 107 on the first buffer layer 110, and the positive projections of the multiple signal lines 102 on the base substrate 101 pass through the binding area BA and the fan-out area FA along the second direction Y, and are coupled to the connecting line 103 at the via H. Optionally, parts of the multiple signal lines 102 serve as the output pad Out, address pad Di-in, power supply pad Pwr and ground pad Gnd of the second pad group 105, and parts of the multiple routing lines 107 serve as the first pad P and the second pad N of the sub-pad group 1041.

[0135] In the eighth step, a first insulating layer 106 is formed on the side of the layer where the multiple signal lines 102 are located away from the base substrate 101 . The first insulating layer 106 includes a second opening K2 exposing the sub-pad group 1041 and a first opening K1 exposing the second pad group 105 .

[0136] In the ninth step, a reflective layer 108 is formed on the first insulating layer 106 . The reflective layer 108 includes a fourth opening K4 exposing the sub-pad group 1041 and a third opening K3 exposing the second pad group 105 .

[0137] At this point, the production of the wiring substrate shown in FIG. 2 is completed.

[0138] It should be noted that the present disclosure first completes the production of the film layer on the side where the second surface S2 is located through the production process of the above-mentioned third to fifth steps, and then completes the production of the film layer on the side where the first surface S1 is located through the production process of the above-mentioned sixth to ninth steps. In some embodiments, the present disclosure may also first execute the production process of the above-mentioned sixth to ninth steps to complete the production of the film layer on the side where the first surface S1 is located, and then execute the production process of the above-mentioned third to fifth steps to realize the production of the film layer on the side where the second surface S2 is located. In other embodiments, the present disclosure may also complete the production of the film layer on the side where the first surface S1 is located and the side where the second surface S2 is located in the production order of the third step → the sixth step → the fourth step → the seventh step → the fifth step → the eighth step → the ninth step. The present disclosure does not deliberately limit the production order of the film layer on the side where the first surface S1 is located and the side where the second surface S2 is located.

[0139] Furthermore, after completing the fabrication of the wiring substrate shown in FIG2 , electronic components 003 (e.g., light-emitting diodes) can be bonded to the sub-pad group 1041 , and micro driver chips 004 can be bonded to the second pad group 105 . Furthermore, a first transparent protective structure 005 covering the electronic components 003 and a second transparent protective structure 006 covering the micro driver chips 004 can be provided. Finally, a driver circuit 007 (e.g., a chip-on-film (COF)) can be bonded to the bonding area BA. This completes the fabrication of the electronic device.

[0140] It should be noted that in the above-mentioned manufacturing method provided in the embodiment of the present disclosure, the patterning process involved in forming each film layer structure may include not only part or all of the process steps such as deposition, photoresist coating, mask template masking, exposure, development, etching, photoresist stripping, etc., but may also include other process steps, which are subject to the formation of the required patterned pattern in the actual manufacturing process and are not limited here. For example, a post-baking process may be included after development and before etching. Among them, the deposition process may be chemical vapor deposition, plasma enhanced chemical vapor deposition or physical vapor deposition, which are not limited here; the mask plate used in the masking process may be a half-tone mask plate (Half Tone Mask), a single slit diffraction mask plate (Single Slit Mask) or a gray tone mask plate (Gray Tone Mask), which are not limited here; etching may be dry etching or wet etching, which are not limited here.

[0141] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0142] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A wiring substrate, wherein, comprising: a substrate, the substrate includes a first surface and a second surface arranged opposite to each other, wherein the second surface includes a bonding region extending in a first direction, and fan-out regions located on both sides of the bonding region in a second direction, a plurality of vias are provided in the fan-out regions, and the first direction intersects the second direction; a plurality of signal lines, located on the side where the first surface is located, and the orthographic projection of the plurality of signal lines on the substrate penetrates the bonding region and the fan-out regions along the second direction; a plurality of connection lines, located on the side where the second surface is located, the plurality of connection lines extend from the fan-out regions to the bonding region, and the plurality of connection lines are coupled to the plurality of signal lines through the plurality of vias.

2. The wiring substrate according to claim 1, wherein, the bonding region is located in the middle region of the second surface.

3. The wiring substrate according to claim 1 or 2, wherein, the fan-out regions located on both sides of the bonding region are a first fan-out region and a second fan-out region respectively; the plurality of connection lines include constant voltage signal connection lines and common voltage signal connection lines, wherein the constant voltage signal connection lines extend from the first fan-out region to the bonding region, and the common voltage signal connection lines extend from the second fan-out region to the bonding region.

4. The wiring substrate according to claim 3, wherein, the constant voltage signal connection lines include a first constant voltage signal connection portion extending in the second direction, and the common voltage signal connection lines include a first common voltage signal connection portion extending in the second direction; wherein, the first constant voltage signal connection portion extends from the first fan-out region to the bonding region, the first common voltage signal connection portion extends from the second fan-out region to the bonding region, and the first common voltage signal connection portion and the first constant voltage signal connection portion are staggered from each other in the first direction.

5. The wiring substrate according to claim 4, wherein, the plurality of signal lines include a plurality of constant voltage signal lines extending in the second direction and arranged in the first direction; the constant voltage signal connection lines further include a second constant voltage signal connection portion integrally provided with the first constant voltage signal connection portion, the second constant voltage signal connection portion extends in the first direction in the first fan-out region, and the second constant voltage signal connection portion is coupled to the plurality of constant voltage signal lines.

6. The wiring substrate according to claim 5, wherein, the line width of the second constant voltage signal connection portion in the second direction is greater than or equal to 28 mm.

7. The wiring substrate according to claim 5 or 6, wherein, the plurality of connection lines further include a plurality of connection line groups, the plurality of connection line groups include a plurality of first connection line groups, and the plurality of first connection line groups are located on one side of the first constant voltage signal connection portion close to the first common voltage signal connection portion and on one side of the second constant voltage signal connection portion close to the bonding region.

8. The wiring substrate according to claim 7, wherein, the first surface includes 2n*2m pad regions, and both n and m are integers greater than 2; The multiple signal lines further include 2m signal line groups arranged in sequence along the first direction, the signal line groups being located between adjacent constant voltage signal lines and penetrating the pad region along the second direction. Among them, the (m + 1)-th to 2m-th signal line groups are coupled to the multiple first connection line groups in the (n - q)-th row of the pad region, where q is an integer closest to and greater than W1 / W2, W1 is the dimension of the bonding region in the second direction, and W2 is the dimension of the pad region in the second direction.

9. The wiring substrate according to any one of claims 4 to 8, wherein, the multiple signal lines further include multiple common voltage signal lines extending along the second direction and arranged along the first direction; the common voltage signal connection line further includes a second common voltage signal connection portion integrally provided with the first common voltage signal connection portion, the second common voltage signal connection portion extending along the first direction in the second fan-out region, and the second common voltage signal connection portion being coupled to the multiple common voltage signal lines.

10. The wiring substrate according to claim 9, wherein, the line width of the second common voltage signal connection portion in the second direction is greater than or equal to 28 mm.

11. The wiring substrate according to claim 9 or 10, wherein, the multiple connection lines further include multiple connection line groups, the multiple connection line groups include multiple second connection line groups, and the multiple second connection line groups are located on one side of the first common voltage signal connection portion close to the first constant voltage signal connection portion and on one side of the second common voltage signal connection portion close to the bonding region.

12. The wiring substrate according to claim 11, wherein, the first surface includes 2n * 2m pad regions, and both n and m are integers greater than 2; the multiple signal lines further include 2m signal line groups arranged in sequence along the first direction, the signal line groups penetrating the pad region along the second direction. Among them, the 1st to m-th signal line groups are coupled to the multiple second connection line groups in the n-th row of the pad region.

13. The wiring substrate according to claim 8 or 12, wherein, the signal line group includes an address signal line, a power supply signal line, and a feedback signal line, and the connection line group includes an address signal connection line, a power supply signal connection line, and a feedback signal connection line; wherein, the address signal connection line is coupled to the address signal line, the power supply signal connection line is coupled to the power supply signal line, the feedback signal connection line is coupled to the feedback signal line, and in the 2n-th row of the pad region, the address signal line and the feedback signal line of the same signal line group are integrally provided.

14. The wiring substrate according to any one of claims 1 to 13, wherein, the line width of the address signal connection line is greater than or equal to 0.1 mm, the line width of the power supply signal connection line is greater than or equal to 0.2 mm, and the line width of the feedback signal connection line is greater than or equal to 0.1 mm.

15. The wiring substrate according to any one of claims 1 to 14, wherein, The first surface includes 2n*2m pad regions, where both n and m are integers greater than 2; A first pad group and a second pad group are provided in the pad region. The first pad group includes at least two sub-pad groups. At least in the 2n-th row of pad regions, the second pad group is located between adjacent sub-pad groups.

16. The wiring substrate according to any one of claims 1 to 15, wherein, It further includes an insulating layer on the side of the plurality of connection lines away from the substrate. The insulating layer includes a plurality of openings in the bonding region, and in the bonding region, the orthographic projection of the plurality of connection lines on the substrate is located within the orthographic projection of the plurality of openings on the substrate.

17. An electronic device, wherein, It includes at least one wiring substrate according to any one of claims 1 to 16, and a plurality of light-emitting structures coupled to the plurality of signal lines.

18. The electronic device according to claim 17, wherein, The first surface includes a plurality of pad regions. A first pad group and a second pad group are provided in the pad region. The light-emitting structure includes an electronic component coupled to the first pad group and a micro driving chip coupled to the second pad group.

19. The electronic device according to claim 17 or 18, wherein, It further includes a driving circuit board, and the driving circuit board is coupled to the plurality of connection lines in the bonding region.

20. The electronic device according to claim 19, wherein, The driving circuit board includes a chip-on-film.

21. A manufacturing method of a wiring substrate, wherein, It includes: Providing a substrate, the substrate includes a first surface and a second surface which are oppositely arranged. Wherein, the second surface includes a bonding region extending in a first direction and fan-out regions located on both sides of the bonding region in a second direction. The first direction intersects with the second direction; Forming a plurality of vias penetrating the substrate in a direction perpendicular to the first surface and the second surface at preset positions in the fan-out regions; Forming a plurality of signal lines on the side where the first surface is located, and the orthographic projection of the plurality of signal lines on the substrate penetrates the bonding region and the fan-out regions along the second direction; and forming a plurality of connection lines extending from the fan-out regions to the bonding region on the side where the second surface is located, and enabling the plurality of connection lines to be coupled to the plurality of signal lines through the plurality of vias.

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