Array substrate, display panel and display apparatus

Abstract

Provided in the embodiments of the present disclosure are an array substrate, a display panel, and a display apparatus. The array substrate comprises: a substrate; and a plurality of pixel electrode groups located on a side of the substrate; the plurality of pixel electrode groups comprises two pixel electrode sub-groups arranged in a first direction, at least one pixel electrode sub-group of the two pixel electrode sub-groups comprising two pixel electrode parts arranged in a second direction; the brightness of some of the pixel electrode parts in the pixel electrode groups is greater than the driven brightness of the remaining pixel electrode parts. The pixel electrode parts comprise slits; at least some of the pixel electrode parts in the same pixel electrode group further comprise planar electrodes.

Description

Array substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] The name UV2A comes from the multiplication of ultraviolet (UV) light and the VA method of the liquid crystal panel. This technology can precisely manipulate the alignment of liquid crystal molecules through ultraviolet light, greatly improving the light transmittance.

[0003] The key to UV2A lies in its use of a special polymer material as an alignment film, precisely controlling the tilt of liquid crystal molecules along the direction of ultraviolet light. This accuracy is measured in picometers (one trillionth of a meter). UV2A's advantage lies in its simple LCD panel structure, free of protrusions and slits. This "dream of LCD technicians" was explored as early as 30 years ago. Today, thanks to the availability of new materials, production equipment, and a refined processing process, this dream has become a reality. This simple LCD panel structure not only improves production efficiency but also offers numerous advantages in image quality.

[0004] Summary of the Invention

[0005] The present disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0006] substrate;

[0007] a plurality of pixel electrode groups located on one side of the substrate, the plurality of pixel electrode groups comprising: two pixel electrode subgroups arranged along a first direction; at least one pixel electrode subgroup of the two pixel electrode subgroups comprising: two pixel electrode portions arranged along a second direction; a brightness of some of the pixel electrode portions in the pixel electrode group being greater than a brightness of the remaining pixel electrode portions when driven;

[0008] The pixel electrode portion includes a slit; and at least part of the pixel electrode portions in the same pixel electrode group further includes a planar electrode.

[0009] In a possible implementation, the plurality of pixel electrode portions in the pixel electrode group include: two first pixel electrode portions and two second pixel electrode portions; the brightness of the first pixel electrode portions is greater than the brightness of the second pixel electrode portions;

[0010] At least one of the first pixel electrode portions includes the planar electrode.

[0011] In a possible implementation manner, both of the two first pixel electrode portions include the planar electrode; and the two second pixel electrode portions only include the slit.

[0012] In a possible implementation manner, in a possible implementation manner, only one of the two first pixel electrode portions includes the planar electrode; and only one of the two second pixel electrode portions includes the planar electrode.

[0013] In a possible implementation, the array substrate includes: a plurality of sub-pixel electrodes; and at least one pixel electrode group among the plurality of pixel electrode groups includes one sub-pixel electrode.

[0014] In a possible implementation, the array substrate further includes: a gate line extending along the second direction, a first pixel connecting portion extending along the first direction, and a second pixel connecting portion;

[0015] The two pixel electrode subgroups are respectively located on different sides of the gate line; the two first pixel electrode portions are arranged along the first direction and are electrically connected through the first pixel connecting portion; the two second pixel electrode portions are arranged along the first direction and are electrically connected through the second pixel connecting portion.

[0016] In a possible implementation, the array substrate further includes: data lines extending along the first direction, a plurality of first pixel driving circuits, and a first routing line; wherein the first pixel driving circuit is configured to drive the pixel electrode group, and the first pixel driving circuit includes: a first transistor, a second transistor, and a third transistor;

[0017] The gate of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first pixel electrode portion;

[0018] A gate of a second transistor is electrically connected to the gate line, a first electrode of the second transistor is reused as the first electrode of the first transistor, and a second electrode of the second transistor is electrically connected to the second pixel electrode portion;

[0019] The gate of the third transistor is electrically connected to the gate line, the first electrode of the third transistor reuses the second electrode of the second transistor, and the second electrode of the third transistor is electrically connected to the first wiring.

[0020] In a possible implementation, the array substrate further includes: a first overlapping portion electrically connected to one of the first pixel electrode portions, and a second overlapping portion electrically connected to one of the second pixel electrode portions;

[0021] The orthographic projection of the first pixel electrode portion on the substrate overlaps with the orthographic projection of the second electrode of the first transistor on the substrate, and the first pixel electrode portion is electrically connected to the second electrode of the first transistor via the first pixel overlapping portion;

[0022] The orthographic projection of the second pixel electrode portion on the substrate has an overlapping area with the orthographic projection of the second pole of the second transistor on the substrate, and the second pixel electrode portion is electrically connected to the second pole of the second transistor through the second pixel overlapping portion.

[0023] In a possible implementation, the first pixel overlapping portion and the second pixel overlapping portion are both located between the first pixel connecting portion and the second pixel connecting portion.

[0024] In a possible implementation manner, the first pixel overlapping portion and the second pixel overlapping portion are located on different sides of the gate line.

[0025] In a possible implementation, the first pixel overlapping portion has a first side extending along the first direction; the second pixel overlapping portion has a second side extending along the first direction;

[0026] The orthographic projection of the extended line of the first side on the substrate overlaps with the orthographic projection of the second pixel overlapping portion on the substrate; the orthographic projection of the extended line of the second side on the substrate overlaps with the orthographic projection of the first pixel overlapping portion on the substrate.

[0027] In a possible implementation, the second electrode of the first transistor includes: a first main portion extending along the second direction, and a first branch portion extending from one end of the first main portion along the first direction;

[0028] The orthographic projection of the first branch on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate; the orthographic projection of the first main part on the substrate has an overlapping area with the orthographic projection of the first pixel overlapping part on the substrate.

[0029] In a possible implementation, the second electrode of the second transistor includes: a second main portion extending along the second direction, and a second branch portion extending from one end of the first main portion along the first direction;

[0030] The orthographic projection of the second branch on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate; the orthographic projection of the second main part on the substrate has an overlapping area with the orthographic projection of the second pixel overlapping part on the substrate.

[0031] In a possible implementation, the first wiring extends along the first direction, and an orthographic projection of the first wiring on the substrate overlaps with an orthographic projection of a gap between two adjacent pixel electrode portions on the substrate.

[0032] In a possible implementation manner, the first wiring includes: a first bending portion located between adjacent pixel electrode subgroups and bent toward one side of the first pixel electrode portion;

[0033] The first pixel connecting portion has a second bent portion bent toward the first pixel electrode portion;

[0034] At least a portion of the orthographic projection of the first bent portion on the substrate does not overlap with at least a portion of the orthographic projection of the second bent portion on the substrate.

[0035] In a possible implementation, the array substrate further includes: a plurality of first common routing groups extending along the second direction; the common routing groups include: a first sub-common routing located on one side of the gate line, and a second sub-common routing located on the other side of the gate line;

[0036] The first sub-common routing line includes: a first sub-common routing line main portion, and a first sub-common routing line convex portion extending from the first sub-common routing line main portion toward one side of the gate line; the second sub-common routing line includes: a second sub-common routing line main portion, and a second sub-common routing line convex portion extending from the second sub-common routing line main portion toward one side of the gate line;

[0037] The orthographic projection of the first sub-common routing protrusion on the substrate has an overlapping area with the orthographic projection of the first pixel overlapping portion on the substrate; the orthographic projection of the second sub-common routing protrusion on the substrate has an overlapping area with the orthographic projection of the second pixel overlapping portion on the substrate.

[0038] In a possible implementation, the array substrate includes: a plurality of sub-pixel electrodes; and at least one pixel electrode group among the plurality of pixel electrode groups includes two sub-pixel electrodes.

[0039] In a possible implementation, the array substrate further includes: a gate line extending along the second direction; the pixel electrode group includes: a first sub-pixel electrode and a second sub-pixel electrode arranged along the second direction;

[0040] The first sub-pixel electrode includes: the first pixel electrode portion located on one side of the gate line, and the second pixel electrode portion located on the other side of the gate line; the second sub-pixel electrode includes: the first pixel electrode portion located on one side of the gate line, and the second pixel electrode portion located on the other side of the gate line;

[0041] The first pixel electrode portion of the first sub-pixel electrode and the first pixel electrode portion of the second sub-pixel electrode are located on different sides of the gate line.

[0042] In one possible implementation, the array substrate further includes: data lines extending along the first direction, a plurality of second pixel driving circuits, and a plurality of second traces; wherein the second pixel driving circuit is configured to drive the first sub-pixel electrode to emit light; and the second pixel driving circuit includes: a fourth transistor, a fifth transistor, and a sixth transistor;

[0043] A gate of a fourth transistor is electrically connected to the gate line, a first electrode of the fourth transistor is electrically connected to the data line, and a second electrode of the fourth transistor is electrically connected to the second pixel electrode portion of the first sub-pixel electrode;

[0044] a gate of the fifth transistor being electrically connected to the gate line, a first electrode of the fifth transistor being reused as the first electrode of the fourth transistor, and a second electrode of the fifth transistor being electrically connected to the first pixel electrode portion of the first sub-pixel electrode;

[0045] The gate of the sixth transistor is electrically connected to the gate line, the first electrode of the sixth transistor reuses the second electrode of the fourth transistor, and the second electrode of the sixth transistor is electrically connected to the second wiring.

[0046] In a possible implementation, the array substrate further includes: a plurality of third pixel driving circuits and a plurality of third traces; wherein the third pixel driving circuit is configured to drive the second sub-pixel electrode to emit light; the third pixel driving circuit includes: a seventh transistor, an eighth transistor, and a ninth transistor;

[0047] a gate of the seventh transistor is electrically connected to the gate line, a first electrode of the seventh transistor is electrically connected to the data line, and a second electrode of the seventh transistor is electrically connected to the first pixel electrode portion of the second sub-pixel electrode;

[0048] a gate of the eighth transistor being electrically connected to the gate line, a first electrode of the eighth transistor being reused as the first electrode of the seventh transistor, and a second electrode of the eighth transistor being electrically connected to the second pixel electrode portion of the second sub-pixel electrode;

[0049] The gate of the ninth transistor is electrically connected to the gate line, the first electrode of the ninth transistor reuses the second electrode of the eighth transistor, and the second electrode of the ninth transistor is electrically connected to the third wiring.

[0050] In one possible implementation, the second electrode of the fourth transistor includes: a second electrode first main portion extending along the second direction, a second electrode first branch portion extending from the second electrode first main portion along the first direction, and a second electrode second branch portion; an orthographic projection of the second electrode first branch on the substrate overlaps with an orthographic projection of the gate line on the substrate; the second electrode second branch is reused as the first electrode of the sixth transistor;

[0051] The second pole of the eighth transistor includes: a second pole second main portion extending along the second direction, a second pole third branch extending from the second pole second main portion along the first direction, and a second pole fourth branch; the orthographic projection of the second pole third branch on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate; the second pole fourth branch is reused as the first pole of the ninth transistor.

[0052] In a possible implementation manner, the second electrode of the sixth transistor is located on a side of the second branch of the second electrode away from the data line;

[0053] The second electrode of the ninth transistor is located on a side of the fourth branch of the second electrode away from the data line.

[0054] In one possible embodiment, the second routing line includes: a second routing line main portion extending along the first direction, and a second routing line overlap portion extending from the second routing line main portion along the second direction toward a side of the first sub-pixel electrode; an orthographic projection of the second routing line overlap portion on the substrate overlaps an orthographic projection of the second electrode of the sixth transistor on the substrate, and the second routing line is electrically connected to the second electrode of the sixth transistor via the second routing line overlap portion;

[0055] The third routing includes: a third routing main portion extending along the first direction, and a third routing overlap portion extending from the second main portion along the second direction toward the side of the second sub-pixel electrode; the orthographic projection of the third routing overlap portion on the substrate has an overlapping area with the orthographic projection of the second electrode of the ninth transistor on the substrate, and the third routing is electrically connected to the second electrode of the ninth transistor through the third routing overlap portion.

[0056] In a possible implementation manner, an orthographic projection of the second wiring main portion on the substrate and an orthographic projection of the gap between the first sub-pixel electrode and the second sub-pixel electrode in the same pixel electrode group on the substrate have an overlapping area;

[0057] The orthographic projection of the main portion of the third wiring on the substrate has an overlapping area with the orthographic projection of the gap between two adjacent pixel electrode groups on the substrate.

[0058] In a possible implementation, the array substrate further includes: a plurality of first common routing groups extending along the second direction; the common routing groups include: a first sub-common routing located on one side of the gate line, and a second sub-common routing located on the other side of the gate line;

[0059] The orthographic projection of the second routing link portion on the substrate is located on a side of the gate line facing the first sub-common routing line;

[0060] The orthographic projection of the third routing link portion on the substrate is located on a side of the gate line facing the second sub-common routing line.

[0061] In one possible embodiment, the multiple sub-pixel electrodes include: a first color sub-pixel electrode, a second color sub-pixel electrode, and a third color sub-pixel electrode; wherein the light emitting wavelength range of the region where the first color sub-pixel electrode is located is greater than the light emitting wavelength range of the region where the second color sub-pixel electrode is located, and the light emitting wavelength range of the region where the second color sub-pixel is located is greater than the light emitting wavelength range of the region where the third color sub-pixel electrode is located;

[0062] At least two of the first color sub-pixel electrode, the second color sub-pixel electrode, and the third color sub-pixel electrode have different areas of the planar electrodes.

[0063] In one possible embodiment, the area of ​​the planar electrode of the first color sub-pixel electrode is greater than the area of ​​the planar electrode of the second color sub-pixel electrode; the area of ​​the planar electrode of the second color sub-pixel electrode is greater than the area of ​​the planar electrode of the third color sub-pixel electrode.

[0064] In a possible implementation manner, an area of ​​the planar electrode of the second color sub-pixel electrode is greater than an area of ​​the planar electrode of the first color sub-pixel electrode.

[0065] In a possible implementation, at least one of the pixel electrode sections includes: two sub-pixel electrode sections arranged along the first direction; the slits of the two sub-pixel electrode sections in the same pixel electrode section extend in different directions;

[0066] The planar electrode covers at least a portion of a junction area between the two sub-pixel electrode portions.

[0067] In a possible implementation manner, the pixel electrode portion includes a first axis extending along the second direction, and the two sub-pixel electrode portions of the same pixel electrode portion are symmetrical about the first axis;

[0068] The planar electrodes in the same pixel electrode portion are symmetrical about the first axis.

[0069] In a possible implementation, the pixel electrode group includes two planar electrodes, and the two planar electrodes are located in different pixel electrode sub-groups.

[0070] In a possible implementation, in the same pixel electrode group, two planar electrodes are arranged along the first direction.

[0071] In a possible implementation manner, in the same pixel electrode group, the two planar electrodes are cross-distributed.

[0072] In a possible implementation manner, at least one edge of the planar electrode is parallel to an extension direction of the slit.

[0073] In a possible implementation manner, at least one edge of the area electrode is perpendicular to an extension direction of the slit.

[0074] In a possible implementation manner, in the same pixel electrode group, the planar electrodes in different pixel electrode portions have the same shape.

[0075] In a possible implementation manner, in the same pixel electrode group, the planar electrodes in different pixel electrode portions have different shapes.

[0076] In a possible implementation, the planar electrode has a shape including: a triangle, a rectangle, a diamond, a trapezoid, a circle, or an ellipse.

[0077] In a possible implementation manner, in the same pixel electrode group, the planar electrodes in different pixel electrode portions have the same area.

[0078] In a possible implementation manner, in the same pixel electrode group, the planar electrodes in different pixel electrode portions have different areas.

[0079] In a possible implementation manner, the area of ​​the planar electrode is one tenth to nine tenths of the area of ​​the pixel electrode portion.

[0080] Based on the same inventive concept, an embodiment of the present disclosure also provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure, and also includes an opposing substrate arranged opposite to the array substrate, and the opposing substrate is provided with a common electrode layer on the side facing the array substrate.

[0081] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] Figure 1 is a schematic diagram of the sub-pixel distribution of 1P4D;

[0083] FIG2 is a schematic diagram showing the principle of dark lines appearing in conventional SUVA pixel design;

[0084] FIG3A is a schematic top view of an array substrate according to an embodiment of the present disclosure; ...

[0085] FIG3B is an enlarged schematic diagram of the dotted line frame S1 in FIG3A ;

[0086] FIG3C is a schematic diagram of a single film layer of the gate line layer in FIG3A ;

[0087] FIG3D is a schematic diagram of a single film layer of the data line layer in FIG3A ;

[0088] FIG3E is a schematic diagram of a single film layer of the active layer in FIG3A ;

[0089] FIG3F is a schematic diagram of a single film layer of the first insulating layer in FIG3A ;

[0090] FIG3G is a schematic diagram of a single film of the first electrode layer in FIG3A ;

[0091] FIG3H is a schematic diagram of a single film layer of the second insulating layer in FIG3A ;

[0092] FIG3I is a schematic diagram of a single film layer of the pixel electrode layer in FIG3A ;

[0093] FIG3J is a schematic diagram of an equivalent circuit corresponding to FIG3A ;

[0094] FIG4A is a second schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0095] FIG4B is an enlarged schematic diagram of the dotted line frame S2 in FIG4A ;

[0096] FIG4C is a schematic diagram of a single film layer of the gate line layer in FIG4A ;

[0097] FIG4D is a schematic diagram of a single film layer of the data line layer in FIG4A ;

[0098] FIG4E is a schematic diagram of a single film layer of the active layer in FIG4A ;

[0099] FIG4F is a schematic diagram of a single film layer of the first insulating layer in FIG4A ;

[0100] FIG4G is a schematic diagram of a single film layer of the pixel electrode layer in FIG4A ;

[0101] FIG5A is a schematic diagram of the electric field at the location of a planar electrode;

[0102] FIG5B is a schematic diagram of the electric field at the position of the slit;

[0103] FIG6 is a schematic diagram of a planar electrode at a sub-pixel electrode of different colors;

[0104] FIG7 is a third schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0105] FIG8 is a fourth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0106] FIG9 is a fifth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0107] FIG10 is a sixth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0108] FIG11 is a seventh schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0109] FIG12 is an eighth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0110] FIG13 is a ninth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0111] FIG14 is a tenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0112] FIG15 is an eleventh schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0113] FIG16 is a twelfth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0114] FIG17 is a thirteenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0115] FIG18 is a fourteenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0116] FIG19 is a fifteenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0117] FIG20 is a sixteenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0118] FIG21 is the seventeenth schematic top view of the array substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0119] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0120] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0121] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0122] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0123] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0124] Compared with the UV2A pixel design, ultra-fine photo alignment (SUVA) is an upgraded version of UV2A, as shown in Figures 1 and 2. Figure 1 shows the 1P4D (one sub-pixel contains four domains) SUVA pixel design. Compared with the UV2A pixel design, the SUVA pixel design can effectively reduce the dark lines of the pixels. However, as shown in Figure 2, the area between the liquid crystal area 1 and the liquid crystal area 2, the liquid crystal area 1-2, still has dark lines. Because of the presence of dark lines and slits, the response time and color shift characteristics of the display panel are still affected.

[0125] In view of this, refer to Figures 3A-3I and Figures 4A-4G, wherein Figure 3A is one of the schematic top views of the array substrate provided in an embodiment of the present disclosure, Figure 3B is an enlarged schematic view of the dotted line frame S1 in Figure 3A, Figure 3C is a schematic view of a single film layer of the gate line layer in Figure 3A, Figure 3D is a schematic view of a single film layer of the data line layer in Figure 3A, Figure 3E is a schematic view of a single film layer of the active layer in Figure 3A, Figure 3F is a schematic view of a single film layer of the first insulating layer in Figure 3A, Figure 3G is a schematic view of a single film layer of the first electrode layer in Figure 3A, and Figure 3H is a schematic view of a single film layer of the second insulating layer in Figure 3A. 3I is a schematic diagram of a single film layer of the pixel electrode layer in FIG3A , FIG4A is a second schematic diagram of a top view of an array substrate provided in an embodiment of the present disclosure, FIG4B is an enlarged schematic diagram of the dotted line frame S2 in FIG4A , FIG4C is a schematic diagram of a single film layer of the gate line layer in FIG4A , FIG4D is a schematic diagram of a single film layer of the data line layer in FIG4A , FIG4E is a schematic diagram of a single film layer of the active layer in FIG4A , FIG4F is a schematic diagram of a single film layer of the first insulating layer in FIG4A , and FIG4G is a schematic diagram of a single film layer of the pixel electrode layer in FIG4A . An embodiment of the present disclosure provides an array substrate, which includes:

[0126] Substrate 1;

[0127] Multiple pixel electrode groups P are located on one side of the substrate 1. The multiple pixel electrode groups P include: two pixel electrode sub-groups PX arranged along a first direction X; at least one pixel electrode sub-group PX of the two pixel electrode sub-groups PX includes: two pixel electrode portions PXY arranged along a second direction Y; the brightness of some pixel electrode portions PXY in the pixel electrode group P is greater than the brightness of other pixel electrode portions PXY;

[0128] The pixel electrode portion PXY includes a slit F; at least part of the pixel electrode portions PXY in the same pixel electrode group P further includes a planar electrode M.

[0129] In the embodiment of the present disclosure, the brightness of some pixel electrode portions PXY in the pixel electrode group P is greater than the brightness of the remaining pixel electrode portions PXY, which can achieve a multi-domain display effect and improve color deviation; moreover, at least some pixel electrode portions PXY in the same pixel electrode group 2 also include: a planar electrode M, that is, some slits F are removed from some pixel electrode portions PXY, so that the same pixel electrode portion PXY has two different electric field intensities, which will produce two different brightnesses, further achieving a multi-domain display effect and improving the color deviation problem of the display panel; in addition, in the area without the planar electrode M, due to the existence of a fringe electric field between the slits F, the liquid crystal is disordered and the electric field forces interfere with each other, affecting the response time. The arrangement of the planar electrode M in the pixel electrode portion PXY in the embodiment of the present disclosure can improve the response time; moreover, the arrangement of the planar electrode M can reduce the number of slits F in the pixel electrode portion PXY, reducing the risk of dark lines and disorder in the low and medium grayscales of the display panel due to line width fluctuations during the slit F process.

[0130] 5A and 5B , in the same pixel electrode portion PXY, the area where the planar electrode M is located has no slits F, so the liquid crystal is subjected to a uniform vertical electric field force, and the electric field is stronger than that in the area without the planar electrode M. Therefore, the brightness is also higher than that in the area without the planar electrode M.

[0131] It should be noted that in Figure 3A, H represents a brighter area, L represents a darker area, H1 to H8 represent further dividing the brighter area into 8 areas, and L1 to L4 represent further dividing the darker area into 4 areas. Here, brighter means that more backlight is transmitted, and darker means that less backlight is transmitted. That is, when different voltages are applied to different areas, the voltage difference formed with the common electrode of the opposite substrate is different. The larger the pressure difference, the stronger the ability to drive the liquid crystal to rotate, the more backlight is transmitted, and the brighter the area. Conversely, the smaller the pressure difference, the weaker the ability to drive the liquid crystal to rotate, the less backlight is transmitted, and the darker the area.

[0132] Specifically, the array substrate may further include a pixel driving circuit, and the brightness of some pixel electrode portions PXY is greater than the brightness of other pixel electrode portions PXY. It can be understood that under the drive of the pixel driving circuit, the brightness of some pixel electrode portions PXY is greater than the brightness of other pixel electrode portions PXY.

[0133] In one possible embodiment, as shown in FIG. 3A or FIG. 4A , the multiple pixel electrode portions PXY in the pixel electrode group P include: two first pixel electrode portions P1 and two second pixel electrode portions P2; the brightness of the first pixel electrode portions P1 is greater than that of the second pixel electrode portions P2; and at least one first pixel electrode portion P1 includes a planar electrode M. Compared to placing the planar electrode M in the darker second pixel electrode portion P2, placing the planar electrode M in the brighter first pixel electrode portion P1 in the disclosed embodiment results in a greater improvement in color shift, resulting in a more pronounced improvement.

[0134] In a possible implementation, referring to FIG. 3A or FIG. 4A , the two first pixel electrode portions P1 each include a planar electrode M; and the two second pixel electrode portions P2 only include slits F.

[0135] In a possible implementation, as shown in FIG. 14 , the second pixel electrode portion P2 may be provided with a planar electrode M, while the first pixel electrode portion P1 may not be provided with a planar electrode M.

[0136] In a possible implementation, referring to FIG. 7 and FIG. 15 , only one of the two first pixel electrode portions P1 includes the planar electrode M; and only one of the two second pixel electrode portions P2 includes the planar electrode M.

[0137] In one possible embodiment, in combination with FIG3A to FIG3I , the array substrate includes: a plurality of sub-pixel electrodes 2; at least one pixel electrode group P in the plurality of pixel electrode groups P includes a sub-pixel electrode 2. That is, one sub-pixel electrode 2 corresponds to one pixel electrode group P. In the embodiment of the present disclosure, the conventional SUVA structure is divided along the first direction X (longitudinal direction) into two 4Domains on the left and right, the left side is set as the first pixel electrode part P1, and the right side is set as the second pixel electrode part P2, forming an 8Domain, and then the slit F in the middle part of the left first pixel electrode part P1 is removed to make the electric field strength in different areas different, thereby achieving a further brightness difference within the first pixel electrode part P1, and the first pixel electrode part P1 of the 4Domain is changed to an 8Domain, and the overall pixel becomes a 1P12D structure. This design has a simple pixel structure and is relatively easy to achieve different ratios of bright and dark areas.

[0138] In one possible embodiment, referring to Figures 3A, 3B, and 3I, the array substrate further includes: a gate line 3 extending along a second direction Y, a first pixel connection portion PL1 extending along a first direction Y, and a second pixel connection portion PL2; two pixel electrode subgroups PX are respectively located on different sides of the gate line 3; two first pixel electrode portions P1 are arranged along the first direction X and electrically connected via the first pixel connection portion PL1; two second pixel electrode portions P2 are arranged along the first direction X and electrically connected via the second pixel connection portion PL2. In the disclosed embodiment, the array substrate further includes: a first pixel connection portion PL1 and a second pixel connection portion PL2; the two first pixel electrode portions P1 are electrically connected via the first pixel connection portion PL1; and the two second pixel electrode portions P2 are electrically connected via the second pixel connection portion PL2. This can make the wiring layout of the sub-pixels neater and avoid the risk of short circuit defects.

[0139] In one possible embodiment, referring to FIG. 3A , FIG. 3B , and FIG. 3J , the array substrate further includes: data lines 4 extending along a first direction X, a plurality of first pixel driving circuits, and a first trace 5 ; wherein the first pixel driving circuit is configured to drive the pixel electrode group P, and the first pixel driving circuit includes: a first transistor T1 , a second transistor T2 , and a third transistor T3 ;

[0140] The gate electrode T1A of the first transistor is electrically connected to the gate line 3 , the first electrode T1B of the first transistor is electrically connected to the data line 4 , and the second electrode T1C of the first transistor is electrically connected to the first pixel electrode portion P1 ;

[0141] The gate electrode T2A of the second transistor is electrically connected to the gate line 3 , the first electrode T2B of the second transistor reuses the first electrode T1B of the first transistor, and the second electrode T2C of the second transistor is electrically connected to the second pixel electrode portion P2 ;

[0142] The gate electrode T3A of the third transistor is electrically connected to the gate line 3 , the first electrode T3B of the third transistor is reused as the second electrode T2C of the second transistor, and the second electrode T3C of the third transistor is electrically connected to the first wiring 5 .

[0143] Specifically, the array substrate also includes a first liquid crystal capacitor Cpx1 and a second liquid crystal capacitor Cpx2, wherein the first liquid crystal capacitor Cpx1 can be formed by the first pixel electrode portion P1 and the common electrode layer of the opposite substrate, and the second liquid crystal capacitor Cpx2 can be formed by the second pixel electrode portion P2 and the common electrode layer of the opposite substrate. The first capacitor C1 can be formed by the first pixel electrode portion P1 and the first sub-common wiring 71, and the second capacitor C2 can be formed by the second pixel electrode portion P2 and the second sub-common wiring 72.

[0144] In an embodiment of the present invention, the first pixel electrode portion P1 can be electrically connected to the gate line 3 and the data line 4 through the first transistor T1, the second pixel electrode portion P2 can be electrically connected to the gate line 3 and the data line 4 through the second transistor T2, and the second pole T3C of the third transistor is electrically connected to the first wiring 5. The stored charge in the second capacitor C2 corresponding to the second pixel electrode portion P2 can be released to the first wiring 5 through the third transistor T3, thereby making the brightness of the first pixel electrode portion P1 greater than the brightness of the second pixel electrode portion P2, so that the first pixel electrode portion P1 and the second pixel electrode portion P2 have different light and dark pixels.

[0145] In a possible embodiment, referring to FIG. 3A , FIG. 3B , and FIG. 3I , the array substrate further includes: a first connecting portion PD1 electrically connected to one of the first pixel electrode portions P1 , and a second connecting portion PD2 electrically connected to one of the second pixel electrode portions P2 ;

[0146] The orthographic projection of the first pixel electrode portion P1 on the substrate 1 overlaps with the orthographic projection of the second electrode T1C of the first transistor on the substrate 1 , and the first pixel electrode portion P1 is electrically connected to the second electrode T1C of the first transistor via the first pixel bonding portion PD1 ;

[0147] The orthographic projection of the second pixel electrode portion P2 on the substrate 1 overlaps with the orthographic projection of the second transistor second electrode T2C on the substrate 1 , and the second pixel electrode portion P2 is electrically connected to the second transistor second electrode T2C through the second pixel bonding portion PD2 .

[0148] In one possible embodiment, referring to Figures 3A, 3B, and 3I, the first pixel connecting portion PD1 and the second pixel connecting portion PD2 are both located between the first pixel connecting portion PL1 and the second pixel connecting portion PL2. It is understood that the first pixel connecting portion PD1 and the second pixel connecting portion PD2 are both located between the first pixel connecting portion PL1 and the second pixel connecting portion PL2, and are located between the first pixel connecting portion PL1 and the second pixel connecting portion PL2 of the same sub-pixel electrode 2.

[0149] In one possible embodiment, referring to Figures 3A, 3B, and 3I, the first pixel bonding portion PD1 and the second pixel bonding portion PD2 are located on different sides of the gate line 3. For example, as shown in Figure 3A, the first pixel bonding portion PD1 is located on the upper side of the gate line 3, and the second pixel bonding portion PD2 is located on the lower side of the gate line 3.

[0150] In a possible embodiment, referring to Figures 3A, 3B and 3I, the first pixel overlapping portion PD1 has a first side w1 extending along the first direction X; the second pixel overlapping portion PD2 has a second side w2 extending along the first direction X; the orthographic projection of the extended line of the first side w1 on the substrate 1 overlaps with the orthographic projection of the second pixel overlapping portion PD2 on the substrate 1; the orthographic projection of the extended line of the second side w2 on the substrate 1 overlaps with the orthographic projection of the first pixel overlapping portion PD2 on the substrate 1.

[0151] In one possible implementation, the orthographic projection of the first side w1 on the substrate 1 can coincide with the orthographic projection of the extension of the second side w2 on the substrate 1. This allows the left and right edges of the first pixel pad PD1 and the second pixel pad PD2 to be roughly aligned, resulting in a neater layout and avoiding the risk of short circuits.

[0152] In one possible embodiment, referring to Figures 3A, 3B, and 3D, the second electrode T1C of the first transistor includes: a first main portion T1C1 extending along the second direction Y, and a first branch portion T1C2 extending from one end of the first main portion T1C1 along the first direction X; the orthographic projection of the first branch portion T1C2 on the substrate 1 overlaps with the orthographic projection of the gate line 3 on the substrate 1; the orthographic projection of the first main portion T1C1 on the substrate 1 overlaps with the orthographic projection of the first pixel connecting portion PD1 on the substrate 1, so that the first main portion T1C1 and the first pixel connecting portion PD1 are electrically connected by drilling at the overlapping position. Specifically, the first main portion T1C1 and the first pixel connecting portion PD1 can be electrically connected through a first via K1 and a third via K3.

[0153] In one possible embodiment, referring to Figures 3A, 3B, and 3D, the second electrode T2C of the second transistor includes: a second main portion T2C1 extending along the second direction Y, and a second branch portion T2C2 extending from one end of the first main portion T2C1 along the first direction X; the orthographic projection of the second branch portion T2C2 on the substrate 1 overlaps with the orthographic projection of the gate line 3 on the substrate 1; the orthographic projection of the second main portion T2C1 on the substrate 1 overlaps with the orthographic projection of the second pixel connecting portion PD2 on the substrate 1, so that the second main portion T2C1 and the second pixel connecting portion PD2 are electrically connected by drilling at the overlapping position. Specifically, the second main portion T2C1 and the second pixel connecting portion PD2 can be electrically connected through a second via K2 and a fourth via K4.

[0154] In a possible embodiment, referring to Figures 3A, 3B and 3D, the first routing line 5 extends along the first direction X, and the orthographic projection of the first routing line 5 on the substrate 1 has an overlapping area with the orthographic projection of the gap between two adjacent pixel electrode portions PXY on the substrate 1. Optionally, the first routing line 5 may at least partially overlap with the first pixel electrode portion P1 and / or the second pixel electrode portion P2; optionally, the first routing line 5 does not overlap with either the first pixel electrode portion P1 or the second pixel electrode portion P2.

[0155] 3A , 3B and 3D , the first traces 5 can be made of the same layer and material as the data lines 4. Thus, the first traces 5 are formed simultaneously with the data lines 4, simplifying the manufacturing process of the array substrate.

[0156] In one possible embodiment, as shown in Figures 3A, 3B, 3D, and 3I, the first trace 5 includes a first bent portion 51 located between adjacent pixel electrode subgroups PX and bent toward the first pixel electrode portion P1. The second pixel connection portion PL2 includes a second bent portion PL21 bent toward the first pixel electrode portion P1. At least a portion of the orthographic projection of the first bent portion 51 onto the substrate 1 does not overlap with at least a portion of the orthographic projection of the second bent portion PL21 onto the substrate 1. This prevents the formation of overlapping coupling capacitance between the first trace 5 and the second pixel connection portion PL2, which could affect normal sub-pixel display. Continuing to refer to Figure 3B, the position where the gate line 3 overlaps with the second pixel connection portion PL2 is narrower than other parts of the gate line, which can reduce the coupling capacitance between the two, and the shape of the bent portion connected to the two ends of the second pixel connection portion PL2 is coordinated with the shape of the gate line (as shown in Figure 3B, with respect to the second pixel connection portion PL2, the extension direction of the bent portion inclined toward the lower left is the same as the extension direction of the relative gate line, and the extension direction of the bent portion inclined toward the lower right is the same as the extension direction of the relative gate line in Figure 3B); the shape of the bent portion connected to the two ends of the first bent portion 51 is coordinated with the shape of the gate line (as shown in Figure 3B, with respect to the first bent portion 51, the extension direction of the bent portion inclined toward the lower left is the same as the extension direction of the relative gate line, and the extension direction of the bent portion inclined toward the lower right is the same as the extension direction of the relative gate line in Figure 3B).

[0157] In a possible implementation, referring to FIG. 3A , FIG. 3B , FIG. 3D and FIG. 3I , at least a portion of the first bent portion 51 is located on a side of the second bent portion PL21 close to the data line 4 electrically connected to the sub-pixel.

[0158] In a possible embodiment, referring to Figures 3A, 3B and 3C, the array substrate further includes: a plurality of first common routing groups 7 extending along the second direction Y; the common routing group 6 includes: a first sub-common routing 71 located on one side of the gate line 3, and a second sub-common routing 72 located on the other side of the gate line 3; the first sub-common routing 71 includes: a first sub-common routing main portion 711, and a first sub-common routing convex portion 712 extending from the first sub-common routing main portion 711 toward one side of the gate line; the second sub-common routing 72 includes: a second sub-common routing main portion 721, and a second sub-common routing convex portion 722 extending from the second sub-common routing main portion 721 toward one side of the gate line 3; the orthographic projection of the first sub-common routing convex portion 712 on the substrate 1 has an overlapping area with the orthographic projection of the first pixel overlapping portion PD1 on the substrate 1; the orthographic projection of the second sub-common routing convex portion 722 on the substrate 1 has an overlapping area with the orthographic projection of the second pixel overlapping portion PD2 on the substrate 1.

[0159] In a possible embodiment, referring to Figures 3A, 3B and 3C, the width of the first sub-common routing protrusion 712 in the first direction X is greater than the width of the first sub-common routing main portion 711 in the first direction X, so that the first sub-common routing protrusion 712 and the first pixel electrode portion P1 form a first capacitor C1; the width of the second sub-common routing protrusion 722 in the first direction X is greater than the width of the second sub-common routing main portion 721 in the first direction X, so that the second sub-common routing protrusion 722 and the second pixel electrode portion P2 form a second capacitor C2.

[0160] In a possible embodiment, referring to Figures 4A-4G, Figure 4B is an enlarged schematic diagram of the dotted line frame S2 in Figure 4A, Figure 4C is a single-film schematic diagram of the gate line layer in Figure 4A, Figure 4D is a single-film schematic diagram of the data line layer in Figure 4A, Figure 4E is a single-film schematic diagram of the active layer in Figure 4A, Figure 4F is a single-film schematic diagram of the first insulating layer in Figure 4A, and Figure 4G is a single-film schematic diagram of the pixel electrode layer in Figure 4A. The array substrate includes: multiple sub-pixel electrodes 2; at least one pixel electrode group P among the multiple pixel electrode groups P includes two sub-pixel electrodes 2, that is, one pixel electrode group P corresponds to two sub-pixel electrodes 2.

[0161] In a possible embodiment, referring to Figures 4A to 4G, the array substrate further includes: a gate line 3 extending along a second direction Y; the pixel electrode group P includes: a first sub-pixel electrode 21 and a second sub-pixel electrode 22 arranged along the second direction Y; the first sub-pixel electrode 21 includes: a first pixel electrode portion P1 located on one side of the gate line 3, and a second pixel electrode portion P2 located on the other side of the gate line 3; the second sub-pixel electrode 22 includes: a first pixel electrode portion P1 located on one side of the gate line 3, and a second pixel electrode portion P2 located on the other side of the gate line 3; the first pixel electrode portion P1 of the first sub-pixel electrode 21 and the first pixel electrode portion P2 of the second sub-pixel electrode 22 are located on different sides of the gate line 3.

[0162] In the disclosed embodiment, the first pixel electrode portion P1 and the second pixel electrode portion P2 are located on different sides of the gate line 3 and are not located in the same column, that is, the first pixel electrode portion P1 and the second pixel electrode portion P2 are arranged in an intersecting manner, and the conventional SUVA structure is changed into a 2P8D structure, and then the slit F in the middle part of the first pixel electrode portion P1 is removed to make the electric field strength in different areas different, thereby achieving a further brightness difference within the first pixel electrode portion P1, and the first pixel electrode portion P1 of 4Domain is changed into 8Domain, and the overall pixel becomes a 2P12D structure. This design has a simple pixel structure and is relatively easy to achieve different ratios of bright and dark areas.

[0163] In one possible embodiment, referring to FIG. 4A to FIG. 4G , the array substrate further includes: a data line 4 extending along a first direction X, a plurality of second pixel driving circuits, and a plurality of second traces 8; wherein the second pixel driving circuit is configured to drive the first sub-pixel electrode 21 to emit light; the second pixel driving circuit includes: a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6;

[0164] The gate electrode T4A of the fourth transistor is electrically connected to the gate line 3 , the first electrode T4B of the fourth transistor is electrically connected to the data line 4 , and the second electrode T4C of the fourth transistor is electrically connected to the second pixel electrode portion P2 of the first sub-pixel electrode 21 ;

[0165] The gate electrode T5A of the fifth transistor is electrically connected to the gate line 3 , the first electrode T5B of the fifth transistor is reused as the first electrode T5B of the fourth transistor, and the second electrode T5C of the fifth transistor is electrically connected to the first pixel electrode portion P1 of the first sub-pixel electrode 21 ;

[0166] The gate electrode T6A of the sixth transistor is electrically connected to the gate line 3 , the first electrode T6B of the sixth transistor is reused as the second electrode T4C of the fourth transistor, and the second electrode T6C of the sixth transistor is electrically connected to the second wiring 8 .

[0167] In the embodiment of the present disclosure, in the first sub-pixel electrode 21, the first pixel electrode portion P1 can be electrically connected to the gate line 3 and the data line 4 through the fifth transistor T5, the second pixel electrode portion P2 can be electrically connected to the gate line 3 and the data line 4 through the fourth transistor T4, and the second pole T6C of the sixth transistor is electrically connected to the second wiring 8. The stored charge corresponding to the second pixel electrode portion P2 can be released to the second wiring 8 through the sixth transistor T6, thereby making the brightness of the first pixel electrode portion P1 greater than the brightness of the second pixel electrode portion P2, so that the first pixel electrode portion P1 and the second pixel electrode portion P2 have different light and dark pixels.

[0168] In one possible embodiment, referring to FIG. 4A to FIG. 4G , the array substrate further includes: a plurality of third pixel driving circuits and a plurality of third traces 9 ; wherein the third pixel driving circuit is configured to drive the second sub-pixel electrode 22 to emit light; the third pixel driving circuit includes: a seventh transistor T7 , an eighth transistor T8 , and a ninth transistor T9 ;

[0169] The gate electrode T7A of the seventh transistor is electrically connected to the gate line 3 , the first electrode T7B of the seventh transistor is electrically connected to the data line 4 , and the second electrode T7C of the seventh transistor is electrically connected to the first pixel electrode portion P1 of the second sub-pixel electrode 22 ;

[0170] The gate electrode T8A of the eighth transistor is electrically connected to the gate line 3 , the first electrode T8B of the eighth transistor is reused as the first electrode T7B of the seventh transistor, and the second electrode T8C of the eighth transistor is electrically connected to the second pixel electrode portion P2 of the second sub-pixel electrode 22 ;

[0171] The gate electrode T9A of the ninth transistor is electrically connected to the gate line 3 , the first electrode T9B of the ninth transistor is multiplexed with the second electrode T8C of the eighth transistor, and the second electrode T9C of the ninth transistor is electrically connected to the third wiring 9 .

[0172] In the embodiment of the present disclosure, in the second sub-pixel electrode 22, the first pixel electrode portion P1 can be electrically connected to the gate line 3 and the data line 4 through the seventh transistor T7, the second pixel electrode portion P2 can be electrically connected to the gate line 3 and the data line 4 through the eighth transistor T8, and the second electrode T9C of the ninth transistor is electrically connected to the third wiring 9. The storage capacitor corresponding to the second pixel electrode portion P2 can be released to the third wiring 9 through the ninth transistor T9, thereby making the brightness of the first pixel electrode portion P1 greater than the brightness of the second pixel electrode portion P2, so that the first pixel electrode portion P1 and the second pixel electrode portion P2 have different light and dark pixels.

[0173] In one possible embodiment, referring to FIG. 4A and FIG. 4D , the second electrode T4C of the fourth transistor includes: a second electrode first main portion T4C1 extending along the second direction Y, and a second electrode first branch portion T4C2 extending from the second electrode first main portion T4C1 along the first direction X, and a second electrode second branch T4C3; the orthographic projection of the second electrode first branch T4C2 on the substrate 1 overlaps with the orthographic projection of the gate line 3 on the substrate 1; the second electrode second branch T4C3 is reused as the first electrode T6B of the sixth transistor; the orthographic projection of the second electrode first main portion T4C1 on the substrate 1 overlaps with the orthographic projection of the second pixel electrode portion P2 on the substrate 1, so as to achieve electrical connection by punching in the overlapping area between the two. Specifically, the second electrode first main portion T4C1 and the second pixel electrode portion P2 can be electrically connected through the fifth via K5;

[0174] The second electrode T8C of the eighth transistor includes: a second electrode second main portion T8C1 extending along the second direction Y, a second electrode third branch portion T8C2 extending from the second electrode second main portion T8C1 along the first direction X, and a second electrode fourth branch T8C3; the orthographic projection of the second electrode third branch T8C2 on the substrate 1 has an overlapping area with the orthographic projection of the gate line 3 on the substrate 1; the second electrode fourth branch T8C3 is reused as the first electrode T9B of the ninth transistor, and the orthographic projection of the second electrode second main portion T8C1 on the substrate 1 has an overlapping area with the orthographic projection of the second pixel electrode portion P2 on the substrate 1. In this way, electrical connection is achieved by punching a hole in the overlapping area between the two, and electrical connection can be achieved through the ninth via K9.

[0175] In a possible implementation, referring to Figures 4A, 4B, and 4D, the second electrode T6C of the sixth transistor is located on a side of the second electrode second branch T4C3 away from the data line 4, and the data line 4 may specifically be the data line 4 connected to the sixth transistor T6; the second electrode T9C of the ninth transistor is located on a side of the second electrode fourth branch T8C3 away from the data line 4, and the data line 4 may specifically be the data line 4 connected to the ninth transistor T9.

[0176] In one possible embodiment, referring to FIG. 4A , FIG. 4B , and FIG. 4G , the second routing line 8 includes: a second routing line main portion 81 extending along a first direction X, and a second routing line lap portion 82 extending from the second routing line main portion 81 along a second direction Y toward a side of the first sub-pixel electrode 21 ; an orthographic projection of the second routing line lap portion 82 on the substrate 1 overlaps with an orthographic projection of the second electrode T6C of the sixth transistor on the substrate 1 , and the second routing line 8 is electrically connected to the second electrode T6C of the sixth transistor via the second routing line lap portion 82 ;

[0177] The third routing line 9 includes: a third routing main portion 91 extending along the first direction X, and a third routing overlap portion 92 extending from the third routing main portion 91 along the second direction Y toward the side of the second sub-pixel electrode 22; the orthographic projection of the third routing overlap portion 92 on the substrate 1 has an overlapping area with the orthographic projection of the second electrode T9C of the ninth transistor on the substrate 1, and the third routing line 9 is electrically connected to the second electrode T9C of the ninth transistor through the third routing overlap portion 92.

[0178] In one possible embodiment, referring to FIG. 4A , FIG. 4B , and FIG. 4G , the orthographic projection of the second wiring main portion 81 on the substrate 1 overlaps with the orthographic projection of the gap between the first sub-pixel electrode 21 and the second sub-pixel electrode 22 in the same pixel electrode group P on the substrate 1 .

[0179] The orthographic projection of the third wiring main portion 91 on the substrate 1 has an overlapping area with the orthographic projection of the gap between two adjacent pixel electrode groups P on the substrate 1 .

[0180] In a possible embodiment, referring to FIG. 4A , FIG. 4B and FIG. 4G , the second routing 8 and the third routing 9 may be formed in the same layer and material as the sub-pixel electrode 2 . In this way, the second routing 8 and the third routing 9 are formed at the same time as the sub-pixel electrode 2 is formed, thereby simplifying the manufacturing process of the array substrate.

[0181] In one possible embodiment, as shown in Figures 4A, 4B, and 4C, the array substrate further includes: a plurality of first common routing groups 7 extending along a second direction Y; the common routing group 7 includes: a first sub-common routing 71 located on one side of the gate line 3, and a second sub-common routing 72 located on the other side of the gate line 3; a second routing overlap portion 82, as projected onto the substrate 1, is located on the side of the gate line 3 facing the first sub-common routing 71; and a third routing overlap portion 92, as projected onto the substrate 1, is located on the side of the gate line 3 facing the second sub-common routing 72. In this way, second pixel electrode portions P2 are formed at different locations to match different sub-pixel electrodes 2.

[0182] In one possible embodiment, in combination with Figure 6, the multiple sub-pixel electrodes 2 include: a first color sub-pixel electrode 201, a second color sub-pixel electrode 202, and a third color sub-pixel electrode 203; wherein, the light emission wavelength range of the area where the first color sub-pixel electrode 201 is located is greater than the light emission wavelength range of the area where the second color sub-pixel electrode 202 is located, and the light emission wavelength range of the area where the second color sub-pixel 202 is located is greater than the light emission wavelength range of the area where the third color sub-pixel electrode 203 is located; among the first color sub-pixel electrode 201, the second color sub-pixel electrode 202, and the third color sub-pixel electrode 203, the area of ​​the planar electrode M of at least two is different.

[0183] In the embodiment of the present disclosure, the areas of the planar electrodes M of at least two of the first color sub-pixel electrode 201, the second color sub-pixel electrode 202, and the third color sub-pixel electrode 203 are different, so as to improve the color deviation problem of the display panel in a specific color by the difference in the planar electrodes M in different sub-pixel electrodes 2.

[0184] In a possible implementation, the region where the first color sub-pixel electrode 201 is located emits red light, the region where the second color sub-pixel electrode 202 is located emits green light, and the region where the third color sub-pixel electrode 203 is located emits blue light.

[0185] In one possible embodiment, the area of ​​the planar electrode M of the first color sub-pixel electrode 201 is larger than the area of ​​the planar electrode M of the second color sub-pixel electrode 202; and the area of ​​the planar electrode M of the second color sub-pixel electrode 202 is larger than the area of ​​the planar electrode M of the third color sub-pixel electrode 203. This can improve the problem of subjective greenish or whitish skin tones (bright overexposure) in the display panel. Specifically, the area of ​​the second color sub-pixel electrode 202 (i.e., the G sub-pixel) can be kept unchanged to maintain transmittance; the area of ​​the planar electrode M of the first color sub-pixel electrode 201 (i.e., the R sub-pixel) can be increased to increase the brightness of the first color sub-pixel electrode 201 (i.e., the R sub-pixel); and the area of ​​the planar electrode M of the third color sub-pixel electrode 203 (i.e., the B sub-pixel) can be reduced (in extreme cases, the planar electrode M can be removed) to improve the white overexposure problem.

[0186] Optionally, the planar electrodes M of the first color sub-pixel electrode 201, the second color sub-pixel electrode 202, and the third color sub-pixel electrode 203 all adopt a triangular pattern. In order to improve the problem of subjective skin color appearing green or white (bright and overexposed), the planar electrode M of the second color sub-pixel electrode 202 (that is, the G sub-pixel) can be kept in a triangular pattern shape and size unchanged, and the shape of the planar electrode M of the first color sub-pixel electrode 201 (that is, the R sub-pixel) can be changed to a rectangle to increase the area of ​​the planar electrode M of the first color sub-pixel electrode 201 (that is, the R sub-pixel), thereby increasing the brightness of the planar electrode M of the first color sub-pixel electrode 201 (that is, the R sub-pixel); at the same time, the triangular pattern shape of the planar electrode M of the third color sub-pixel electrode 203 (that is, the B sub-pixel) is kept unchanged, and the area of ​​the planar electrode M of the third color sub-pixel electrode 203 (that is, the B sub-pixel) is reduced, thereby improving the problem of white overexposure of the display panel.

[0187] In one possible implementation, the area of ​​the planar electrode of the second color sub-pixel electrode 202 is larger than the area of ​​the planar electrode M of the first color sub-pixel electrode 201. This can improve the reddening problem of the display panel. Specifically, the area of ​​the planar electrode M of the first color sub-pixel electrode 201 (i.e., the R sub-pixel) can be reduced, thereby reducing the brightness of the planar electrode M of the first color sub-pixel electrode 201 (i.e., the R sub-pixel), and / or the area of ​​the planar electrode M of the second color sub-pixel electrode 202 (i.e., the G sub-pixel) can be increased.

[0188] In one possible embodiment, as shown in FIG3A or FIG4A , at least one pixel electrode portion PXY includes two sub-pixel electrode portions PXY0 arranged along a first direction X; the slits F of the two sub-pixel electrode portions PXY0 within the same pixel electrode portion PXY extend in different directions; and a planar electrode M covers at least a portion of the interface between the two sub-pixel electrode portions PXY0. This can alleviate the dark streak problem at the interface between the two sub-pixel electrode portions PXY0 and improve the color shift problem of the display panel in the second direction Y (left-right viewing angle).

[0189] In one possible embodiment, as shown in FIG3I , the pixel electrode portion PXY includes a first axis k1 extending along the second direction Y. The two sub-pixel electrode portions PXY0 in the same pixel electrode portion PXY are symmetrical about the first axis k1. The planar electrodes M in the same pixel electrode portion PXY are symmetrical about the first axis k1. This avoids uneven distribution of the planar electrodes M in the pixel electrode portion PXY.

[0190] In one possible embodiment, as shown in FIG. 3A or FIG. 4A , the pixel electrode group P includes two planar electrodes M, and the two planar electrodes M are located in different pixel electrode sub-groups PX. This ensures that the planar electrodes M are distributed as evenly as possible in the first direction X, thereby avoiding significant brightness differences in the first direction X.

[0191] In one possible implementation, as shown in FIG3A or FIG15 , in the same pixel electrode group P, two planar electrodes M are arranged along the first direction X. That is, in the same pixel electrode group P, the two planar electrodes M are located on different sides of the gate line 3 and in the same column direction.

[0192] In one possible embodiment, as shown in FIG4A , FIG7 and FIG14 , two planar electrodes M are cross-distributed in the same pixel electrode group P. That is, in the same pixel electrode group P, the two planar electrodes M are located on different sides of the gate line 3 and in different columns.

[0193] In one possible embodiment, as shown in FIG3A and FIG4A , at least one edge of the planar electrode M is parallel to the extension direction of the slit F. This can improve the edge consistency of the planar electrode M and avoid dark lines caused by liquid crystal disorder on the edge of the planar electrode M.

[0194] In a possible implementation manner, as shown in combination with FIG. 8 and FIG. 16 , at least one edge of the area electrode M may also be perpendicular to the extension direction of the slit F.

[0195] In a possible implementation manner, as shown in conjunction with FIG. 3A and FIG. 4A , in the same pixel electrode group P, the planar electrodes M in different pixel electrode portions PXY have the same shape.

[0196] In a possible implementation manner, as shown in combination with FIG. 13 and FIG. 21 , in the same pixel electrode group P, the shapes of the planar electrodes M in different pixel electrode portions PXY are different.

[0197] In one possible embodiment, the shape of the planar electrode M includes: a triangle, a rectangle, a rhombus, a trapezoid, a circle, or an ellipse. Optionally, for example, as shown in Figures 3A, 9, 4A, and 17, the shape of the planar electrode M is a triangle; optionally, for example, as shown in Figures 10 and 18, the shape of the planar electrode M is a trapezoid; optionally, for example, as shown in Figures 11 and 19, the shape of the planar electrode M is a rectangle; optionally, for example, as shown in Figures 12 and 20, the shape of the planar electrode M is a rhombus.

[0198] In a possible implementation, as shown in FIG. 3A or FIG. 4A , in the same pixel electrode group P, the planar electrodes M in different pixel electrode portions PXY have the same area.

[0199] In a possible implementation, as shown in FIG. 13 or FIG. 21 , in the same pixel electrode group P, the areas of the planar electrodes M in different pixel electrode portions PXY are different.

[0200] In one possible embodiment, the area of ​​the planar electrode M is one tenth to nine tenths of the area of ​​the pixel electrode portion PXY. In another possible embodiment, the area of ​​the planar electrode M is one quarter, one third, or one half of the area of ​​the pixel electrode portion PXY.

[0201] In a possible embodiment, with reference to FIG. 3A to FIG. 3I , the array substrate may be provided with, in sequence, a gate line layer as shown in FIG. 3C , a data line layer as shown in FIG. 3D , an active layer as shown in FIG. 3E , a first insulating layer as shown in FIG. 3F , a first electrode layer as shown in FIG. 3G , a second insulating layer as shown in FIG. 3H , and a pixel electrode layer as shown in FIG. 3I on one side of the substrate 1;

[0202] The active layer may include an active pattern 6 corresponding to the transistor;

[0203] The first insulating layer may have a first via hole K1 and a second via hole K2; the first insulating layer may be a first passivation layer or an organic layer;

[0204] The first electrode layer may include a first hollow L1, a second hollow L2, a third hollow L3 and a fourth hollow L4, wherein the first hollow L1 may correspond to the pixel electrode subgroup PX; the orthographic projection of the second hollow L2 on the substrate 1 and the orthographic projection of the first via K1 on the substrate 1, so that the first pixel electrode portion P1 is conductively connected to the second electrode T1C of the first transistor through the second hollow portion L2; the orthographic projection of the third hollow L3 on the substrate 1 and the orthographic projection of the second via K2 on the substrate 1, so that the second pixel electrode portion P2 is conductively connected to the second electrode T2C of the second transistor through the third hollow L3; the orthographic projection of the fourth hollow L4 on the substrate 1 may have an overlapping area with the orthographic projection of the gate line 2 on the substrate 1 to reduce the overlapping capacitance with the gate line 2; specifically, the first electrode layer may be a transparent electrode layer, and the material of the first electrode layer may be the same as that of the pixel electrode layer;

[0205] The second insulating layer may have a third via hole K3 and a fourth via hole K4; the second insulating layer may be a second passivation layer;

[0206] In the embodiment of the present disclosure, the array substrate is further provided with a first electrode layer having a first hollow L1. The orthographic projection of the first electrode layer on the substrate 1 can cover at least a portion of the orthographic projection of the data line 4 on the substrate 1, and can cover at least a portion of the orthographic projection of the gate line 3 on the substrate 1, thereby shielding the coupling capacitance between the sub-pixel electrode 2 and the data line 4, and the coupling capacitance between the sub-pixel electrode 2 and the gate line 3, thereby improving the transmittance of the display panel.

[0207] Based on the same inventive concept, embodiments of the present disclosure further provide a display panel, comprising an array substrate as provided in embodiments of the present disclosure, and further comprising an opposing substrate disposed opposite the array substrate, the opposing substrate having a common electrode layer disposed on a side facing the array substrate. Specifically, as shown in FIG. 5A or FIG. 5B , the opposing substrate may include an opposing substrate 10 and a common electrode layer 101 located on a side of the opposing substrate 10 facing the array substrate.

[0208] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0209] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0210] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein, comprising: a substrate; a plurality of pixel electrode groups located on one side of the substrate, the plurality of pixel electrode groups comprising: two pixel electrode subgroups arranged along a first direction; at least one of the two pixel electrode subgroups comprising: two pixel electrode portions arranged along a second direction; the luminance of some of the pixel electrode portions in the pixel electrode group being greater than the luminance of the remaining pixel electrode portions being driven; wherein, the pixel electrode portion comprises: a slit; at least some of the pixel electrode portions in the same pixel electrode group further comprise: a planar electrode.

2. The array substrate according to claim 1, wherein, the plurality of pixel electrode portions in the pixel electrode group comprise: two first pixel electrode portions, and two second pixel electrode portions; the luminance of the first pixel electrode portion being greater than the luminance of the second pixel electrode portion; at least one of the first pixel electrode portions comprises the planar electrode.

3. The array substrate according to claim 2, wherein, both of the two first pixel electrode portions comprise the planar electrode; both of the two second pixel electrode portions only comprise the slit.

4. The array substrate according to claim 2, wherein, only one of the two first pixel electrode portions comprises the planar electrode; only one of the two second pixel electrode portions comprises the planar electrode.

5. The array substrate according to any one of claims 2-4, wherein, the array substrate comprises: a plurality of sub-pixel electrodes; at least one of the plurality of pixel electrode groups comprises one of the sub-pixel electrodes.

6. The array substrate according to claim 5, wherein, the array substrate further comprises: a gate line extending along the second direction, a first pixel connection portion extending along the first direction, and a second pixel connection portion; the two pixel electrode subgroups are respectively located on different sides of the gate line; the two first pixel electrode portions are arranged along the first direction and are electrically connected through the first pixel connection portion; the two second pixel electrode portions are arranged along the first direction and are electrically connected through the second pixel connection portion.

7. The array substrate according to claim 6, wherein, the array substrate further comprises: a data line extending along the first direction, a plurality of first pixel driving circuits, and a first trace; wherein, the first pixel driving circuit is configured to drive the pixel electrode group, and the first pixel driving circuit comprises: a first transistor, a second transistor, and a third transistor; the gate of the first transistor is electrically connected to the gate line, the first pole of the first transistor is electrically connected to the data line, and the second pole of the first transistor is electrically connected to the first pixel electrode portion; the gate of the second transistor is electrically connected to the gate line, the first pole of the second transistor multiplexes the first pole of the first transistor, and the second pole of the second transistor is electrically connected to the second pixel electrode portion; the gate of the third transistor is electrically connected to the gate line, the first pole of the third transistor multiplexes the second pole of the second transistor, and the second pole of the third transistor is electrically connected to the first trace.

8. The array substrate according to claim 7, wherein, The array substrate further includes: a first overlapping portion electrically connected to one of the first pixel electrode portions, and a second overlapping portion electrically connected to one of the second pixel electrode portions; The orthographic projection of the first pixel electrode portion on the substrate has an overlapping area with the orthographic projection of the second pole of the first transistor on the substrate, and the first pixel electrode portion is electrically connected to the second pole of the first transistor through the first pixel overlapping portion; The orthographic projection of the second pixel electrode portion on the substrate has an overlapping area with the orthographic projection of the second pole of the second transistor on the substrate, and the second pixel electrode portion is electrically connected to the second pole of the second transistor through the second pixel overlapping portion.

9. The array substrate according to claim 8, wherein, Both the first pixel overlapping portion and the second pixel overlapping portion are located between the first pixel connecting portion and the second pixel connecting portion.

10. The array substrate according to claim 8 or 9, wherein, Both the first pixel overlapping portion and the second pixel overlapping portion are located on different sides of the gate line.

11. The array substrate according to any one of claims 8-10, wherein, The first pixel overlapping portion has a first side extending along the first direction; the second pixel overlapping portion has a second side extending along the first direction; The orthographic projection of the extension line of the first side on the substrate overlaps with the orthographic projection of the second pixel overlapping portion on the substrate; The orthographic projection of the extension line of the second side on the substrate overlaps with the orthographic projection of the first pixel overlapping portion on the substrate.

12. The array substrate according to any one of claims 8-11, wherein, The second pole of the first transistor includes: a first main portion extending along the second direction, and a first branch portion extending from one end of the first main portion along the first direction; The orthographic projection of the first branch portion on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate; the orthographic projection of the first main portion on the substrate has an overlapping area with the orthographic projection of the first pixel overlapping portion on the substrate.

13. The array substrate according to any one of claims 8-12, wherein, The second pole of the second transistor includes: a second main portion extending along the second direction, and a second branch portion extending from one end of the first main portion along the first direction; The orthographic projection of the second branch portion on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate; the orthographic projection of the second main portion on the substrate has an overlapping area with the orthographic projection of the second pixel overlapping portion on the substrate.

14. The array substrate according to any one of claims 7-13, wherein, The first trace extends along the first direction, and the orthographic projection of the first trace on the substrate has an overlapping area with the gap between two adjacent pixel electrode portions on the substrate.

15. The array substrate according to claim 14, wherein, The first trace includes: a first bending portion located between adjacent pixel electrode sub-groups and bending towards the first pixel electrode portion side; The first pixel connection part has a second bending part that bends toward the first pixel electrode part side; At least a part of the orthographic projection of the first bending part on the substrate does not overlap with at least a part of the orthographic projection of the second bending part on the substrate.

16. The array substrate according to any one of claims 8-15, wherein, The array substrate further includes: a plurality of first common wiring groups extending along the second direction; each common wiring group includes: a first sub-common wiring located on one side of the gate line, and a second sub-common wiring located on the other side of the gate line; The first sub-common wiring includes: a first sub-common wiring main part, and a first sub-common wiring convex part extending from the first sub-common wiring main part toward the gate line side; the second sub-common wiring includes: a second sub-common wiring main part, and a second sub-common wiring convex part extending from the second sub-common wiring main part toward the gate line side; The orthographic projection of the first sub-common wiring convex part on the substrate has an overlapping area with the orthographic projection of the first pixel overlapping part on the substrate; the orthographic projection of the second sub-common wiring convex part on the substrate has an overlapping area with the orthographic projection of the second pixel overlapping part on the substrate.

17. The array substrate according to any one of claims 2-4, wherein, The array substrate includes: a plurality of sub-pixel electrodes; at least one pixel electrode group in the plurality of pixel electrode groups includes two sub-pixel electrodes.

18. The array substrate according to claim 17, wherein, The array substrate further includes: a gate line extending along the second direction; the pixel electrode group includes: a first sub-pixel electrode and a second sub-pixel electrode arranged along the second direction; The first sub-pixel electrode includes: the first pixel electrode part located on one side of the gate line, and the second pixel electrode part located on the other side of the gate line; the second sub-pixel electrode includes: the first pixel electrode part located on one side of the gate line, and the second pixel electrode part located on the other side of the gate line; The first pixel electrode part of the first sub-pixel electrode and the first pixel electrode part of the second sub-pixel electrode are located on different sides of the gate line.

19. The array substrate according to claim 18, wherein, The array substrate further includes: a data line extending along the first direction, a plurality of second pixel driving circuits, and a plurality of second wirings; wherein, the second pixel driving circuit is configured to drive the first sub-pixel electrode to emit light; the second pixel driving circuit includes: a fourth transistor, a fifth transistor, and a sixth transistor; The gate of the fourth transistor is electrically connected to the gate line, the first pole of the fourth transistor is electrically connected to the data line, and the second pole of the fourth transistor is electrically connected to the second pixel electrode part in the first sub-pixel electrode; The gate of the fifth transistor is electrically connected to the gate line, the first pole of the fifth transistor multiplexes the first pole of the fourth transistor and the second pole of the fifth transistor is electrically connected to the first pixel electrode part in the first sub-pixel electrode; The gate of the sixth transistor is electrically connected to the gate line. The first pole of the sixth transistor multiplexes the second pole of the fourth transistor. The second pole of the sixth transistor is electrically connected to the second trace.

20. The array substrate according to claim 19, wherein, the array substrate further includes: a plurality of third pixel driving circuits and a plurality of third traces; wherein, the third pixel driving circuit is configured to drive the second sub-pixel electrode to emit light; the third pixel driving circuit includes: a seventh transistor, an eighth transistor, and a ninth transistor; The gate of the seventh transistor is electrically connected to the gate line. The first pole of the seventh transistor is electrically connected to the data line. The second pole of the seventh transistor is electrically connected to the first pixel electrode portion of the second sub-pixel electrode. The gate of the eighth transistor is electrically connected to the gate line. The first pole of the eighth transistor multiplexes the first pole of the seventh transistor. The second pole of the eighth transistor is electrically connected to the second pixel electrode portion of the second sub-pixel electrode. The gate of the ninth transistor is electrically connected to the gate line. The first pole of the ninth transistor multiplexes the second pole of the eighth transistor. The second pole of the ninth transistor is electrically connected to the third trace.

21. The array substrate according to claim 19 or 20, wherein, the second pole of the fourth transistor includes: a first main portion of the second pole extending along the second direction, a first branch portion of the second pole extending from the first main portion of the second pole along the first direction, and a second branch portion of the second pole; the orthographic projection of the first branch portion of the second pole on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate; the second branch portion of the second pole multiplexes as the first pole of the sixth transistor; the second pole of the eighth transistor includes: a second main portion of the second pole extending along the second direction, a third branch portion of the second pole extending from the second main portion of the second pole along the first direction, and a fourth branch portion of the second pole; the orthographic projection of the third branch portion of the second pole on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate; the fourth branch portion of the second pole multiplexes as the first pole of the ninth transistor.

22. The array substrate according to claim 21, wherein, the second pole of the sixth transistor is located on a side of the second branch portion of the second pole away from the data line; the second pole of the ninth transistor is located on a side of the fourth branch portion of the second pole away from the data line.

23. The array substrate according to claim 21 or 22, wherein, the second trace includes: a main portion of the second trace extending along the first direction, and a second trace overlapping portion extending from the main portion of the second main trace along the second direction toward the first sub-pixel electrode; the orthographic projection of the second trace overlapping portion on the substrate has an overlapping area with the orthographic projection of the second pole of the sixth transistor on the substrate, and the second trace is electrically connected to the second pole of the sixth transistor through the second trace overlapping portion. The third routing includes: a third routing main portion extending along the first direction, and a third routing overlap portion extending from the second main portion along the second direction toward the second sub-pixel electrode; the orthographic projection of the third routing overlap portion on the substrate has an overlapping area with the orthographic projection of the second electrode of the ninth transistor on the substrate, and the third routing is electrically connected to the second electrode of the ninth transistor through the third routing overlap portion.

24. The array substrate according to claim 23, in, The orthographic projection of the main portion of the second wiring on the substrate has an overlapping area with the orthographic projection of the gap between the first sub-pixel electrode and the second sub-pixel electrode in the same pixel electrode group on the substrate; The orthographic projection of the third wiring main portion on the substrate has an overlapping area with the orthographic projection of the gap between two adjacent pixel electrode groups on the substrate.

25. The array substrate according to claim 23 or 24, in, The array substrate further comprises: a plurality of first common routing groups extending along the second direction; the common routing groups comprise: a first sub-common routing located on one side of the gate line, and a second sub-common routing located on the other side of the gate line; The orthographic projection of the second wiring overlap portion on the substrate is located on a side of the gate line facing the first sub-common wiring; The orthographic projection of the third routing overlap portion on the substrate is located on a side of the gate line facing the second sub-common routing line.

26. The array substrate according to any one of claims 5 to 25, in, The multiple sub-pixel electrodes include: a first color sub-pixel electrode, a second color sub-pixel electrode, and a third color sub-pixel electrode; wherein the light emission wavelength range of the region where the first color sub-pixel electrode is located is greater than the light emission wavelength range of the region where the second color sub-pixel electrode is located, and the light emission wavelength range of the region where the second color sub-pixel is located is greater than the light emission wavelength range of the region where the third color sub-pixel electrode is located; At least two of the first color sub-pixel electrode, the second color sub-pixel electrode, and the third color sub-pixel electrode have different areas of the planar electrode.

27. The array substrate according to claim 26, in, The area of ​​the planar electrode of the first color sub-pixel electrode is greater than the area of ​​the planar electrode of the second color sub-pixel electrode; the area of ​​the planar electrode of the second color sub-pixel electrode is greater than the area of ​​the planar electrode of the third color sub-pixel electrode.

28. The array substrate according to claim 26, in, An area of ​​the planar electrode of the second color sub-pixel electrode is greater than an area of ​​the planar electrode of the first color sub-pixel electrode.

29. The array substrate according to any one of claims 1 to 28, in, At least one of the pixel electrode portions comprises: two sub-pixel electrode portions arranged along the first direction; the slits of the two sub-pixel electrode portions in the same pixel electrode portion extend in different directions; The planar electrode covers at least a portion of a boundary region between two sub-pixel electrode portions.

30. The array substrate according to claim 29, wherein, the pixel electrode portion includes a first axis extending in the second direction, and two sub-pixel electrode portions of the same pixel electrode portion are symmetric about the first axis; the planar electrodes in the same pixel electrode portion are symmetric about the first axis.

31. The array substrate according to any one of claims 1-30, wherein, the pixel electrode group includes two planar electrodes, and the two planar electrodes are located in different pixel electrode subgroups.

32. The array substrate according to claim 31, wherein, in the same pixel electrode group, the two planar electrodes are arranged along the first direction.

33. The array substrate according to claim 31, wherein, in the same pixel electrode group, the two planar electrodes are cross-distributed.

34. The array substrate according to any one of claims 1-33, wherein, at least one edge of the planar electrode is parallel to the extending direction of the slit.

35. The array substrate according to any one of claims 1-33, wherein, at least one edge of the area electrode is perpendicular to the extending direction of the slit.

36. The array substrate according to any one of claims 1-35, wherein, in the same pixel electrode group, the planar electrodes in different pixel electrode portions have the same shape.

37. The array substrate according to any one of claims 1-35, wherein, in the same pixel electrode group, the planar electrodes in different pixel electrode portions have different shapes.

38. The array substrate according to claim 36 or 37, wherein, the shape of the planar electrode includes: triangle, rectangle, rhombus, trapezoid, circle, or ellipse.

39. The array substrate according to any one of claims 1-38, wherein, in the same pixel electrode group, the planar electrodes in different pixel electrode portions have the same area.

40. The array substrate according to any one of claims 1-39, wherein, in the same pixel electrode group, the planar electrodes in different pixel electrode portions have different areas.

41. The array substrate according to claim 39 or 40, wherein, the area of the planar electrode is one-tenth to nine-tenths of the area of the pixel electrode portion where it is located.

42. A display panel, wherein, it includes the array substrate according to any one of claims 1-41, and further includes an opposing substrate disposed opposite to the array substrate, and a common electrode layer is provided on the side of the opposing substrate facing the array substrate.

43. A display device, wherein, it includes the display panel according to claim 42.

Images