Thin film transistor, manufacturing method therefor, and array substrate

Abstract

A thin film transistor comprises a substrate and an active layer, the active layer being located on one side of the substrate; the active layer comprises: a first active part, a second active part and a channel connected to the first active part and the second active part; at least one of the first active part and the second active part is a selected active part, and the channel and the selected active part are arranged at different layers; the selected active part comprises silicon atoms and dopant atoms, and the silicon atoms and the dopant atoms in the selected active part are bonded by means of chemical bonds; the channel comprises a pure silicon layer.

Description

Thin film transistor, manufacturing method thereof, and array substrate CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to Chinese patent application No. 202311634457.3 filed on November 29, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a thin film transistor, a preparation method thereof, and an array substrate. Background Art

[0003] Thin-film transistors (TFTs), as pixel switching elements, are widely used in display technology. The active layer of a TFT consists of a connected channel region and source / drain electrode regions. During the fabrication process of the source / drain electrode regions, dopant atoms are typically implanted. During this implantation process, the dopant atoms often diffuse into the channel region, reducing the effective channel length and affecting the switching performance of the TFT. SUMMARY OF THE INVENTION

[0004] The embodiments of the present application provide a thin film transistor, a method for manufacturing the same, and an array substrate, aiming to solve the problem in the related art that the effective length of the channel region is reduced due to the presence of doped atoms in the channel region.

[0005] On the one hand, an embodiment of the present application provides a thin film transistor, comprising: a substrate and an active layer, wherein the active layer is located on one side of the substrate, and the active layer comprises: a first active portion, a second active portion, and a channel connected to the first active portion and the second active portion; wherein at least one of the first active portion and the second active portion is a selected active portion, and the channel is arranged in a different layer from the selected active portion; the selected active portion comprises silicon atoms and dopant atoms, the silicon atoms and the dopant atoms in the selected active portion are connected by chemical bonds, and the channel comprises a pure silicon layer.

[0006] On the other hand, an embodiment of the present application also provides a method for preparing a thin film transistor, which comprises: providing a substrate; and producing an active layer on one side of the substrate, the active layer comprising: a first active portion, a second active portion, and a channel connected to the first active portion and the second active portion; wherein at least one of the first active portion and the second active portion is a selected active portion, and the channel is arranged in a different layer from the selected active portion; the selected active portion comprises silicon atoms and dopant atoms, the silicon atoms and the dopant atoms in the selected active portion are connected by chemical bonds, and the channel comprises a pure silicon layer.

[0007] On the other hand, an embodiment of the present application further provides an array substrate, which includes a thin film transistor, wherein the thin film transistor includes: a substrate and an active layer, wherein the active layer is located on one side of the substrate, and the active layer includes: a first active portion, a second active portion, and a channel connected to the first active portion and the second active portion; wherein at least one of the first active portion and the second active portion is a selected active portion, and the channel is arranged in a different layer from the selected active portion; the selected active portion includes silicon atoms and doping atoms, the silicon atoms and the doping atoms in the selected active portion are connected by chemical bonds, and the channel includes a pure silicon layer. Beneficial effects

[0008] For the thin film transistor provided in the embodiment of the present application, since the silicon atoms and dopant atoms in the selected active portion are connected by chemical bonds, the connection stability of the dopant atoms is good, thereby preventing the dopant atoms from being free in the gaps between silicon atoms, and thus preventing them from diffusing into the channel. The channel includes a pure silicon layer, that is, there are no dopant atoms in the channel, and it will not be affected by the dopant atoms and cause the effective length to be shortened, thereby avoiding the increase of leakage current and affecting the device stability of the thin film transistor. In addition, the effective length of the channel is its own length, which is conducive to accurately controlling the effective length of the channel according to actual needs, thereby improving the performance of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG1 is a cross-sectional view of a thin film transistor provided in some embodiments of the present application;

[0010] FIG2 is a cross-sectional view of a thin film transistor provided in some other embodiments of the present application;

[0011] FIG3 is a cross-sectional view of a thin film transistor provided in some other embodiments of the present application;

[0012] FIG4A is a schematic diagram of a current-voltage characteristic curve of a thin film transistor in the related art;

[0013] FIG4B is a schematic diagram of a current-voltage characteristic curve of a thin film transistor provided in some embodiments of the present application;

[0014] FIG5 is a cross-sectional view of a thin film transistor provided in some other embodiments of the present application;

[0015] FIG6 is a cross-sectional view of a thin film transistor provided in some other embodiments of the present application;

[0016] FIG7 is a flow chart of a method for manufacturing a thin film transistor according to some embodiments of the present application;

[0017] 8 to 12 are schematic diagrams of a method for preparing a thin film transistor provided in some embodiments of the present application. Modes for Carrying Out the Invention

[0018] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The described technical solutions are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0019] In the description of this application, it should be understood that the terms "first," "second," and similar words do not indicate any order, quantity, or importance, but are simply used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise expressly limited.

[0020] The use of "configured to" in this application is intended to be open and inclusive language, and does not exclude devices that are adapted or configured to perform additional tasks or steps. In addition, the use of "based on" is intended to be open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0021] In this application, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any embodiment described in this application as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is provided to enable any person skilled in the art to make and use the present application.

[0022] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0023] The various embodiments of the present application are similar, and features in different embodiments and / or different examples may be combined with each other.

[0024] In related technologies, the active layer of a thin-film transistor includes a channel region and a source-drain electrode region that are interconnected. During the fabrication of the source-drain electrode region, an ion implantation (IMP) process is usually used to implant dopant atoms therein. However, the dopant atoms tend to diffuse into the channel region during this process, causing the effective channel length of the channel region to decrease. This can easily lead to an increase in leakage current, affect the switching performance of the thin-film transistor, and be detrimental to the device stability of the thin-film transistor.

[0025] Based on this, some embodiments of the present application provide a thin film transistor. As shown in Figures 1-3, the thin film transistor 100 includes a substrate 10 and an active layer 20. The active layer 20 is located on one side of the substrate 10 and includes a first active portion 22, a second active portion 23, and a channel 21. The first active portion 22 and the second active portion 23 are respectively connected to the channel 21, so that the first active portion 22 and the second active portion 23 can transmit carriers through the channel 21, thereby achieving current conduction.

[0026] At least one of the first active portion 22 and the second active portion 23 is a selected active portion, the channel 21 and the selected active portion are arranged in a different layer, the selected active portion includes silicon atoms and dopant atoms, and the silicon atoms and dopant atoms in the selected active portion are connected by chemical bonds; the channel 21 includes a pure silicon layer.

[0027] This arrangement ensures that the silicon atoms and dopant atoms in the active portion are chemically bonded, resulting in a stable connection between the dopant atoms. This prevents the dopant atoms from being free and residing in the gaps between silicon atoms, thereby preventing them from diffusing into the channel 21. The channel 21 comprises a pure silicon layer, meaning that there are no dopant atoms in the channel 21 and the channel 21 is not affected by the dopant atoms, resulting in a shortened effective length. This prevents increased leakage current from affecting the stability of the thin film transistor 100. Furthermore, the effective length of the channel 21 is its own length, which facilitates accurate control of the effective length of the channel 21 according to actual needs, thereby improving the performance of the thin film transistor 100.

[0028] The thin film transistors in the related art use the IMP process to implant dopant atoms. Most of the dopant atoms exist in the gaps between silicon atoms in the channel in a free state, resulting in an increase in leakage current. As shown in Figure 4A, the horizontal axis in the figure represents the voltage applied to the gate of the thin film transistor, and the vertical axis represents the current in the thin film transistor. As can be seen from Figure 4A, in the process of applying different voltages to the gate of the thin film transistor in the related art, the thin film transistor has a large current under most voltage conditions, that is, the thin film transistor remains in the on state under most voltage conditions, which makes it difficult for the voltage at the gate to effectively control the switching of the thin film transistor.

[0029] As shown in FIG4B (the horizontal and vertical axes in FIG4B have the same meanings as those in FIG4A ), when a positive voltage is applied to the gate of the thin film transistor 100, the thin film transistor 100 remains almost closed and cannot conduct current. However, when a negative voltage is applied, such as -5V or -10V, the thin film transistor 100 is in the open state and can conduct current. This ensures good switching performance of the thin film transistor 100.

[0030] In some embodiments, as shown in FIGS. 1-3 , the selected active portion has a projection area P on the channel 21 .

[0031] In some examples, the first active portion 22 is a selected active portion, the projected area P includes a first sub-projected area P1, the orthographic projection of the first active portion 22 on the channel 21 is located within the first sub-projected area P1, and the concentration of dopant atoms in the first sub-projected area P1 of the channel 21 is 0. That is, the dopant atoms in the first active portion 22 do not diffuse into the first sub-projected area P1 of the channel 21. Thus, the dopant atoms in the first active portion 22 do not diffuse into other areas of the channel 21, thereby preventing the channel 21 from being affected by the dopant atoms in the first active portion 22, thereby facilitating ensuring the effective length of the channel 21.

[0032] Exemplarily, the first active portion 22 is formed by chemical vapor deposition. By chemical vapor deposition, the dopant atoms in the first active portion 22 are directly connected to the silicon atoms therein through stable chemical bonds. Thus, the dopant atoms do not diffuse into the channel 21, thereby effectively ensuring the effective length of the channel 21.

[0033] The specific implementation of chemical vapor deposition growth is described in detail below.

[0034] In other examples, the second active portion 23 is a selected active portion, the projected area P includes a second sub-projected area P2, the orthographic projection of the second active portion 23 on the channel 21 is located within the second sub-projected area P2, and the concentration of dopant atoms in the second sub-projected area P2 of the channel 21 is zero. In other words, the dopant atoms in the second active portion 23 will not diffuse into the channel 21. Thus, the dopant atoms in the second active portion 23 will not diffuse into other areas of the channel 21, thereby preventing the channel 21 from being affected by the dopant atoms in the second active portion 23, thereby facilitating ensuring the effective length of the channel 21.

[0035] For example, the second active portion 23 is formed by chemical vapor deposition, so that the doping atoms in the second active portion 23 are directly connected to the silicon atoms through stable chemical bonds, thereby effectively preventing the diffusion of the doping atoms.

[0036] In some other examples, both the first active portion 22 and the second active portion 23 are selected active portions, and the projected area P includes a first sub-projected area P1 and a second sub-projected area P2. The orthographic projection of the first active portion 22 on the channel 21 is located within the first sub-projected area P1, and the orthographic projection of the second active portion 23 on the channel 21 is located within the second sub-projected area P2. The concentration of dopant atoms in the first sub-projected area P1 and the second sub-projected area P2 of the channel 21 is both 0. In other words, the dopant atoms in the first active portion 22 and the second active portion 23 will not diffuse into the first sub-projected area P1 and the second sub-projected area P2 of the channel 21. Thus, the dopant atoms will not diffuse into other areas of the channel 21, thereby ensuring the effective length of the channel 21.

[0037] Exemplarily, the selected active portions (i.e., the first active portion 22 and the second active portion 23) are formed by chemical vapor deposition. Thus, in the first active portion 22 or the second active portion 23, the dopant atoms are directly connected to the silicon atoms through stable chemical bonds, thereby effectively preventing diffusion of the dopant atoms.

[0038] In some examples, the doping atoms may be phosphorus, arsenic, boron fluoride, boron, etc., which is not limited in the embodiments of the present application.

[0039] In some embodiments, the crystal grain sizes of the active portion and the channel 21 are selected to be consistent. Exemplarily, the crystal grain sizes of the active portion and the channel 21 are selected to be equal or substantially equal.

[0040] For example, the crystal grain sizes of the active portion and the channel 21 are both selected to be 400 nm.

[0041] For another example, the size deviation of the two grains is within 5%, that is, the size difference of the two grains is less than or equal to 5% of the larger grain size.

[0042] This arrangement helps ensure good performance of the thin film transistor 100. During the fabrication of the selected active portion, an amorphous silicon layer corresponding to the channel can be first formed using a chemical vapor deposition process, and then an amorphous silicon layer corresponding to the selected active portion can be formed using a chemical vapor deposition growth process. The two amorphous silicon layers are then laser annealed to form two polycrystalline silicon layers, and the channel and the selected active portion are then formed using an etching process.

[0043] Since the thickness of each part of the two amorphous silicon layers is equal during the laser annealing step, it is beneficial to ensure that the grain sizes of the crystals in the selected active portion and the channel 21 are consistent.

[0044] It should be noted that the crystals selected for the active portion and the crystals for the channel 21 refer to the silicon atomic crystals contained in both.

[0045] In some embodiments, as shown in FIG6 , the pure silicon layer has an ohmic contact region Q1 and a non-ohmic contact region Q2, and the selected active portion is connected to the portion of the pure silicon layer located in the ohmic contact region Q1; the orthographic projections of the first active portion 22 and the second active portion 23 on the pure silicon layer are located outside the non-ohmic contact region Q2; the pure silicon layer includes a first silicon atom located in the ohmic contact region Q1 and a second silicon atom located in the non-ohmic contact region Q2.

[0046] In some examples, when the grain sizes of the crystals of the active portion and the channel 21 are selected to be consistent, in the channel 21 , the grain size of the first silicon atoms is equal to the grain size of the second silicon atoms.

[0047] In other examples, the grain size of the first silicon atoms is larger than the grain size of the second silicon atoms.

[0048] Exemplarily, the grain size of the first silicon atoms is 400 nm, and the grain size of the second silicon atoms is 350 nm.

[0049] With this arrangement, the thin film transistor 100 can have better operating performance. During the process of fabricating the selected active portion, an amorphous silicon layer corresponding to the channel can be first formed through a chemical vapor deposition process, and then an amorphous silicon layer corresponding to the selected active portion can be formed through a chemical vapor deposition growth process. The amorphous silicon layer corresponding to the selected active portion is then etched through an etching process, and then the two amorphous silicon layers are simultaneously formed into two polycrystalline silicon layers through a laser annealing step, thereby forming the corresponding channel and the selected active portion.

[0050] The ohmic contact region Q1 may overlap with the projection region P of the selected active portion on the channel 21. For example, when both the first active portion 22 and the second active portion 23 are selected active portions, both the first sub-projection region P1 and the second sub-projection region P2 are ohmic contact regions Q1.

[0051] It should be noted that the above-mentioned grain size is the average grain size of silicon atoms in the corresponding region, not the size of all or a single silicon atom.

[0052] In some embodiments, the thickness of the first active portion 22 is greater than or equal to 50 Å and less than or equal to 200 Å.

[0053] During the fabrication of the first active portion 22, an amorphous silicon layer corresponding to the first active portion 22 can be fabricated first. Dopant atoms are grown in the amorphous silicon layer. Laser annealing is then performed to transform the amorphous silicon layer into a polycrystalline silicon layer. The polycrystalline silicon layer is then etched to ultimately serve as the first active portion 22. Due to the energy limitations of the laser annealing process, the thickness of the first active portion 22 is set within the aforementioned range, which facilitates fabrication of the first active portion 22.

[0054] For example, the thickness of the first active portion 22 may be 50 Å, 80 Å, 100 Å, 120 Å, 150 Å, 180 Å, or 200 Å.

[0055] In some embodiments, the thickness of the second active portion 23 is greater than or equal to 50 Å and less than or equal to 200 Å.

[0056] During the fabrication of the second active portion 23, an amorphous silicon layer corresponding to the second active portion 23 can be first fabricated, doped atoms grown in the amorphous silicon layer, and then laser annealing is performed to transform the amorphous silicon layer into a polycrystalline silicon layer. This polycrystalline silicon layer is then etched to ultimately serve as the second active portion 23. Due to the energy limitations of the laser annealing process, the thickness of the second active portion 23 is set within the aforementioned range, which facilitates fabrication of the second active portion 23.

[0057] For example, the thickness of the second active portion 23 may be 50 Å, 80 Å, 100 Å, 120 Å, 150 Å, 180 Å, or 200 Å.

[0058] When the first active portion 22 and the second active portion 23 are manufactured in the same layer, they may have the same thickness.

[0059] In some embodiments, the first active portion 22 can be provided in the same layer as the channel 21, so that the two can have a contact surface in the horizontal direction (the horizontal direction is perpendicular to the thickness direction of the substrate 10). This arrangement is conducive to reducing the overall thickness of the thin film transistor 100.

[0060] In other embodiments, as shown in Figures 1-3, the first active portion 22 and the channel 21 can be located in different layers, so that the two can have a contact surface in the vertical direction (i.e., the thickness direction of the substrate 10). This configuration helps reduce the orthographic projection area of ​​the thin film transistor 100 on the substrate 10, thereby reducing the horizontal size of the thin film transistor 100, and further improving the pixel density (pixels per inch, PPI) of the display panel manufactured therefrom.

[0061] The second active portion 23 may be provided in the same layer as the channel 21 or in a different layer from the channel 21 , and this embodiment of the present application does not impose any limitation thereto.

[0062] In some examples, the first active portion 22 and the second active portion 23 are respectively located at two ends of the channel 21 , so that the channel 21 has a longer length, thereby facilitating the transmission of carriers in the channel 21 .

[0063] In some embodiments, as shown in FIG. 1 , the first active portion 22 and the second active portion 23 are both located on a side of the channel 21 away from the substrate 10 , and the first active portion 22 and the second active portion 23 are disposed in the same layer.

[0064] Since the first active portion 22 and the second active portion 23 both contain the same doping atoms, the first active portion 22 and the second active portion 23 can be simultaneously manufactured through the same process step, thereby helping to reduce the manufacturing steps of the thin film transistor 100 and saving its manufacturing cost.

[0065] In other embodiments, as shown in Figure 2, the first active portion 22 and the second active portion 23 are both located between the channel 21 and the substrate 10, and the thin film transistor 100 also includes a first insulating layer 31, which is located between the channel 21 and the substrate 10 and is arranged around the first active portion 22 and the second active portion 23, respectively. The plane of the first insulating layer 31 away from the side of the substrate 10, the plane of the first active portion 22 away from the side of the substrate 10, and the plane of the second active portion 23 away from the side of the substrate 10 are coplanar.

[0066] With this arrangement, the first active portion 22 and the second active portion 23 can be manufactured in the same layer, which is beneficial for reducing the manufacturing steps of the thin film transistor 100 .

[0067] In this embodiment, the orthographic projection of the first active portion 22 on the substrate 10 partially overlaps with the orthographic projection of the channel 21 on the substrate 10, enabling contact between the first active portion 22 and the channel 21. The orthographic projection of the second active portion 23 on the substrate 10 partially overlaps with the orthographic projection of the channel 21 on the substrate 10, enabling contact between the second active portion 23 and the channel 21. Furthermore, a portion of the first active portion 22 does not overlap with the channel 21, facilitating connection between the first active portion 22 and a corresponding electrode (e.g., a drain electrode). Furthermore, a portion of the second active portion 23 does not overlap with the channel 21, facilitating connection between the second active portion 23 and a corresponding electrode (e.g., a source electrode).

[0068] In some other embodiments, as shown in Figure 3, the first active portion 22 is located between the channel 21 and the substrate 10, and the thin film transistor 100 also includes a second insulating layer 32, which is located between the channel 21 and the substrate 10 and is arranged around the first active portion 22. The plane of the second insulating layer 32 away from the substrate 10 is coplanar with the plane of the first active portion 22 away from the substrate 10, and the second active portion 23 is located on the side of the channel 21 away from the substrate 10.

[0069] This arrangement is beneficial to the flexibility of arranging the first active portion 22 and the second insulating layer 32 , and they can be arranged according to adaptability requirements.

[0070] In this embodiment, the orthographic projection of the first active portion 22 on the substrate 10 partially overlaps with the orthographic projection of the channel 21 on the substrate 10, enabling contact between the first active portion 22 and the channel 21. The orthographic projection of the second active portion 23 on the substrate 10 partially overlaps with the orthographic projection of the channel 21 on the substrate 10, enabling contact between the second active portion 23 and the channel 21. In addition, a portion of the first active portion 22 does not overlap with the channel 21, which facilitates connection between the first active portion 22 and a corresponding electrode (e.g., a drain electrode).

[0071] For the sake of simplicity, the following embodiments of this application are described by assuming that both the first active portion 22 and the second active portion 23 are located on the side of the channel 21 away from the substrate 10, and that the first active portion 22 and the second active portion 23 are arranged on the same layer. Of course, the following embodiments and related examples are for illustrative purposes only and do not limit the combination of the various embodiments.

[0072] In some embodiments, as shown in FIG. 5 and FIG. 6 , the thin film transistor 100 further includes a gate layer 30 and a gate insulating layer 40 .

[0073] 5 , the gate layer 30 is located on a side of the active layer 20 away from the substrate 10, and the gate insulating layer 40 is located between the gate layer 30 and the active layer 20. In this case, the thin film transistor 100 has a top-gate structure.

[0074] In other examples, as shown in FIG6 , the gate layer 30 and the gate insulating layer 40 are stacked sequentially in a direction away from the substrate 10 and are located between the substrate 10 and the channel 21. That is, the gate layer 30 is located between the substrate 10 and the channel 21, and the gate insulating layer 40 is located between the gate layer 30 and the channel 21. This arrangement can increase the distance between the gate layer 30 and the corresponding electrode (e.g., the drain electrode) to which the first active portion 22 is connected, thereby reducing the coupling capacitance between the two and avoiding the potential instability of the corresponding electrode to which the first active portion 22 is connected due to the large coupling capacitance. In addition, when the first active portion 22 is connected to the corresponding electrode, a via hole needs to be opened. The gate layer 30 is located below the first active portion 22. This can also prevent the gate layer 30 from interfering with the opening of the via hole, thereby avoiding increasing the difficulty of producing the thin film transistor 100 in order to ensure the spacing accuracy between the via hole and the gate layer 30.

[0075] In some examples, as shown in FIG6 , the gate layer 30 includes a connection surface and a top surface and a bottom surface disposed opposite each other along the thickness direction of the substrate 10. The connection surface is located between the top and bottom surfaces and connects them. A gate layer angle α is formed between the connection surface and the bottom surface. The gate layer angle α is greater than or equal to 20° and less than or equal to 40°. This gives the connection surface of the gate layer 30 a slope, which facilitates the fabrication of the gate layer 30.

[0076] The gate insulating layer 40 covers the top surface and the connection surface of the gate layer 30 , thereby cooperating with the substrate 10 to completely surround the gate layer 30 , thereby preventing the gate layer 30 from contacting other conductive materials and affecting the device stability of the thin film transistor 100 .

[0077] In some examples, the substrate 10 may be a rigid substrate, such as a silicon wafer, glass, etc., or a flexible substrate, such as polyethylene naphthalate, polyethylene terephthalate, or polyimide.

[0078] In some examples, the thin film transistor 100 further includes a buffer layer 11 located between the substrate 10 and the gate layer 30 . The material of the buffer layer 11 may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0079] In some embodiments, as shown in Figure 6, the gate insulation layer 40 includes: a transition surface 43 and a first surface 41 (in Figure 6, the first surface 41 is located on the side of the gate insulation layer 40 away from the substrate 10) and a second surface 42 (in Figure 6, the second surface 42 is located on the side of the gate insulation layer 40 close to the substrate 10) that are relatively arranged along the thickness direction of the substrate 10. The transition surface 43 is connected to the first surface 41 and the second surface 42, and the transition surface 43 includes an inclined surface; the channel 21 includes a main body 212, and the main body 212 is located on the inclined surface.

[0080] Due to the presence of the inclined surface, and the fact that the main portion 212 of the channel 21 is disposed on this inclined surface, the actual length of the main portion 212 can be greater than the length of its orthographic projection on the substrate 10. This allows the horizontal size of the thin-film transistor 100 to be reduced while maintaining a certain length for the channel 21. On the one hand, the longer channel 21 can prevent an increase in leakage current. On the other hand, the reduced horizontal size of the thin-film transistor 100 can help improve the PPI of the display panel fabricated therefrom.

[0081] In some embodiments, an angle β is formed between the inclined surface and the second surface 42, and the angle β is greater than or equal to 20° and less than or equal to 40°. This configuration is conducive to ensuring that the gate insulating layer 40 can be well manufactured. On the other hand, it can also ensure that the channel 21 has a relatively large length within a certain range, while ensuring that the orthographic projection of the channel 21 on the substrate 10 has a small size in the horizontal direction.

[0082] In some examples, the angle β may be 20°, 25°, 30°, 35°, or 40°.

[0083] For example, the angle β may be 30°, so that the device stability of the thin film transistor manufactured is relatively good.

[0084] For example, the included angle β between the inclined surface and the second surface 42 may be the same as the included angle α of the gate layer, which can improve the uniformity and stability of the fabrication of each film layer.

[0085] In some examples, each sub-transition surface of the transition surface 43 in each direction on a horizontal plane (the horizontal plane is perpendicular to the thickness direction of the substrate 10 ) is an inclined surface, which is beneficial for manufacturing the gate insulation layer 40 .

[0086] Exemplarily, each sub-transition surface has an included angle β of the same size with the second surface, so that the device stability of the thin film transistor manufactured thereby is better.

[0087] In some embodiments, as shown in FIG6 , the channel 21 further includes a first connecting portion 211 and a second connecting portion 213 connected to both sides of the main portion 212. The first connecting portion 211 is disposed in contact with the first active portion 22, and the second connecting portion 213 is disposed in contact with the second active portion 23. In this way, carriers in the first active portion 22 and the second active portion 23 can be transmitted through the first connecting portion 211, the main portion 212, and the second connecting portion 213, thereby achieving current conduction.

[0088] In some examples, the contact surface between the first connection portion 211 and the first active portion 22 is perpendicular to the thickness direction of the substrate 10. That is, the first active portion 22 is disposed on a plane of the first connection portion 211 away from the substrate 10, which facilitates the fabrication of the first connection portion 211.

[0089] Illustratively, the first connection portion 211 is located on the first surface 41 of the gate insulation layer 40 , and the first connection portion 211 has a contact plane on the side away from the substrate 10 , and the first active portion 22 is arranged on the contact plane, thereby ensuring good and stable contact between the first connection portion 211 and the first active portion 22 .

[0090] In some examples, the contact surface between the second connection portion 213 and the second active portion 23 is perpendicular to the thickness direction of the substrate 10. That is, the second active portion 23 is disposed on a plane of the second connection portion 213 away from the substrate 10, which facilitates the fabrication of the second connection portion 213.

[0091] Illustratively, the second connection portion 213 is located on the buffer layer 11 , and the second connection portion 213 has a contact plane on the side away from the substrate 10 , and the second active portion 23 is arranged on the contact plane, thereby ensuring good and stable contact between the second connection portion 213 and the second active portion 23 .

[0092] In some embodiments, as shown in Figure 6, the first active portion 22 and the second active portion 23 can be used as a sub-active layer as a whole, and the thin film transistor 100 also includes a third insulating layer 50, a metal conductive layer 60, a fourth insulating layer 70 and a source-drain electrode layer located on the side of the sub-active layer away from the substrate 10 and stacked in sequence.

[0093] In some examples, the source-drain electrode layer includes a drain electrode 81, which is located on a side of the first active portion 22 away from the substrate 10 and connected to the first active portion 22. Exemplarily, a first via is defined in the third insulating layer and the fourth insulating layer, and the drain electrode 81 is connected to the first active portion 22 through the first via.

[0094] In some examples, the source-drain electrode layer further includes a source electrode 82, which is located on a side of the second active portion 23 away from the substrate 10 and is connected to the second active portion 23. Exemplarily, a second via is further defined in the third insulating layer and the fourth insulating layer, and the source electrode 82 is connected to the second active portion 23 through the second via.

[0095] In some examples, the orthographic projection of the drain electrode 81 on the substrate 10 overlaps with the orthographic projection of the gate layer 30 on the substrate 10. Thus, a coupling capacitor exists between the drain electrode 81 and the gate layer 30. Connecting the second active portion 23 to the source electrode 82 effectively prevents the coupling capacitor from affecting the source electrode 82 and, in turn, the current input of the thin film transistor 100.

[0096] In some embodiments, as shown in FIG6 , the thin film transistor 100 further includes a gate signal line 33 , which can be used as a scan line of the array substrate to selectively turn on the thin film transistor according to a scan signal of a driver, thereby driving the pixel electrode to operate.

[0097] In some examples, the first gate signal line 33 may be provided in the same layer as the gate layer 30. The conductor arranged in the gate layer 30 may be used as a gate of a thin film transistor.

[0098] In some examples, additional gate signal lines may be arranged in the metal conductive layer 60 to flexibly control a circuit composed of multiple thin film transistors.

[0099] Some embodiments of the present application further provide a method for manufacturing a thin film transistor. As shown in FIG. 7 , the method includes steps S201 - S202 .

[0100] S201: providing a substrate 10.

[0101] S202: An active layer 20 is fabricated on one side of the substrate 10, wherein the active layer includes: a channel 21, and a first active portion 22 and a second active portion 23 connected to the channel 21; at least one of the first active portion 22 and the second active portion 23 is a selected active portion, the channel 21 and the selected active portion are located in different layers, the selected active portion includes silicon atoms and dopant atoms, and the silicon atoms and dopant atoms in the selected active portion are connected by chemical bonds; the channel 21 includes a pure silicon layer.

[0102] This arrangement ensures that the silicon atoms and dopant atoms in the selected active portion are connected by chemical bonds, resulting in a stable connection between the dopant atoms. This prevents the dopant atoms from being free and existing in the gaps between silicon atoms, thereby preventing them from diffusing into the channel 21. The channel 21 comprises a pure silicon layer, meaning that there are no dopant atoms in the channel 21 and the channel 21 is not affected by the dopant atoms, resulting in a shortened effective length. This prevents increased leakage current from affecting the device stability of the thin film transistor 100. Furthermore, the effective length of the channel 21 is the same as its own length, which facilitates accurate control of the effective length of the channel 21 according to actual needs, thereby improving the performance of the thin film transistor 100.

[0103] In some examples, substrate 10 may be a rigid substrate, such as glass.

[0104] In some embodiments, as shown in FIG8 , between steps S201 and S202 , the preparation method may further include steps S2011 - S2013 .

[0105] S2011 : a buffer layer 11 is provided on one side of the substrate 10 .

[0106] For example, the material of the buffer layer 11 may be silicon nitride, which may be deposited on the substrate 10 by a plasma enhanced chemical vapor deposition process.

[0107] S2012 : Disposing a gate layer 30 on a side of the buffer layer 11 away from the substrate 10 .

[0108] For example, a metal layer may be deposited on the buffer layer 11 and patterned to form the gate layer.

[0109] S2013 : Disposing a gate insulating layer 40 on a side of the gate layer 30 away from the substrate 10 .

[0110] For example, an insulating layer may be formed on the buffer layer 11 and the gate layer 30 , and then patterned to retain only the region covering the gate layer 30 , thereby forming the gate insulating layer 40 .

[0111] In some embodiments, as shown in Figures 8-12, step S202 includes steps S2021-S2024.

[0112] S2021 : Disposing a first amorphous silicon layer 51 on one side of the substrate 10 .

[0113] When the preparation method includes steps S2011 - S2013 , the first amorphous silicon layer 51 is disposed on a side of the gate insulating layer 40 away from the substrate 10 .

[0114] As shown in FIG8 , the first amorphous silicon layer 51 can be deposited on the gate insulating layer 40 by a chemical vapor deposition process. The thickness of the first amorphous silicon layer 51 can be greater than or equal to 400 Å and less than or equal to 500 Å. For example, the thickness of the first amorphous silicon layer 51 is 450 Å.

[0115] S2022: depositing a second amorphous silicon layer 52 on a side of the first amorphous silicon layer 51 away from the substrate 10 by a chemical vapor deposition growth process, wherein doping atoms are grown in the second amorphous silicon layer 52 , and the doping atoms are connected to the silicon atoms in the first amorphous silicon layer 51 by chemical bonds.

[0116] For example, the raw materials used in the chemical vapor deposition growth process include phosphine, so that phosphorus atoms can be grown in the second amorphous silicon layer 52 .

[0117] As another example, the raw materials used in the chemical vapor deposition growth process include boron fluoride, so that boron atoms can be grown in the second amorphous silicon layer 52 .

[0118] Since the doping atoms are doped into the second amorphous silicon layer 52 by chemical vapor deposition, this can prevent the doping atoms from being injected into the second amorphous silicon layer 52 through the IMP process, thereby preventing the doping atoms from diffusing into the channel 21 and causing the device stability of the thin film transistor 100 to be reduced.

[0119] S2023 : forming the second polysilicon layer 521 and the first polysilicon layer 511 from the second amorphous silicon layer 52 and the first amorphous silicon layer 51 through a laser annealing step.

[0120] As shown in FIG9 and FIG10 , the second amorphous silicon layer 52 and the first amorphous silicon layer 51 can be synchronously transformed through the laser annealing step to form a second polysilicon layer 521 and a first polysilicon layer 511 , respectively, thereby improving manufacturing efficiency.

[0121] S2024 : patterning the second polysilicon layer 521 and the first polysilicon layer 511 so that the second polysilicon layer 521 forms the first active portion 22 and the second active portion 23 , and the first polysilicon layer 511 forms a pure silicon layer of the channel 21 .

[0122] Exemplarily, a halftone mask process can be used to pattern the second polysilicon layer 521 and the first polysilicon layer 511. The areas to be removed (portions of the second polysilicon layer 521 and the first polysilicon layer 511 not covered by the channel 21 and the sub-active layer (including the first active portion 22 and the second active portion 23)) are fully exposed, the area corresponding to the sub-active layer is not exposed, and the area between the first active portion 22 and the second active portion 23 in the second polysilicon layer 521 is partially exposed. This allows the area between the first active portion 22 and the second active portion 23 in the second polysilicon layer 521 to be etched away, ultimately retaining the area corresponding to the channel 21 in the first polysilicon layer 511, the area corresponding to the first active portion 22 in the second polysilicon layer 521, and the area corresponding to the second active portion 23 in the second polysilicon layer 521. Therefore, a Halftone mask process is used to expose different areas to different degrees, so that the desired structure can be obtained in one step.

[0123] For example, as shown in Figures 10-12, a photoresist layer is first applied to one side of the second polysilicon layer 521. After exposure and development steps, the structure shown in Figure 8 is formed. Reference numeral 53 in the figure represents the photoresist. Due to the use of a halftone masking process, the photoresist thickness corresponding to the first active portion 22 and the second active portion 23 is greater than the photoresist thickness in the region between the first active portion 22 and the second active portion 23. Subsequently, etching and other steps are used to remove the areas not covered by the photoresist. Subsequently, exposure and development steps are performed to form the structure shown in Figure 9. Subsequently, etching and other steps are used to remove the areas of the second polysilicon layer 521 not covered by the photoresist. Finally, the remaining photoresist is removed, forming the structure shown in Figure 12.

[0124] In the above embodiment, the first active portion 22 and the second active portion 23 are formed by first performing a laser annealing step on the second amorphous silicon layer 52 and then performing a patterning (etching) step. In other embodiments, the first active portion 22 and the second active portion 23 may be formed by first performing a patterning (etching) step on the second amorphous silicon layer 52 and then performing a laser annealing step.

[0125] Some embodiments of the present application further provide an array substrate, which includes the thin film transistor 100 described in any of the above embodiments.

[0126] Since the array substrate includes the thin film transistor 100 , the array substrate has all the technical effects possessed by the thin film transistor 100 , which will not be described in detail here.

[0127] Some embodiments of the present application further provide a display panel, which includes the above-mentioned array substrate.

[0128] Since the display panel includes the thin film transistor 100 , the display panel has all the technical effects possessed by the thin film transistor 100 , which will not be described in detail here.

[0129] In addition, since the thin film transistor 100 has a small size and occupies a small area, and its device stability is high, it is also beneficial for the display panel to achieve narrow frame, high aperture ratio, high brightness and high resolution.

[0130] In summary, although the present application is disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application is based on the scope defined by the claims.

Claims

1. A thin film transistor, comprising: substrate; as well as, An active layer, located on one side of the substrate, the active layer comprising: a first active portion, a second active portion, and a channel connected to the first active portion and the second active portion; At least one of the first active portion and the second active portion is a selected active portion, the channel and the selected active portion are arranged in different layers, the selected active portion includes silicon atoms and doped atoms, the silicon atoms and the doped atoms in the selected active portion are connected by chemical bonds, and the channel includes a pure silicon layer.

2. The thin film transistor according to claim 1, wherein: The first active portion and the second active portion are both the selected active portions; The selected active portion is formed by chemical vapor deposition growth.

3. The thin film transistor according to claim 2, wherein: The selected active portion and the channel have crystal grain sizes that are consistent.

4. The thin film transistor according to claim 3, wherein: The first active portion and the second active portion are respectively located at two ends of the channel, the first active portion and the second active portion are both located at a side of the channel away from the substrate, and the first active portion and the second active portion are arranged in the same layer.

5. The thin film transistor according to any one of claims 1 to 4, wherein: Also includes: A gate layer and a gate insulating layer, wherein the gate layer is located between the substrate and the channel, and the gate insulating layer is located between the gate layer and the channel.

6. The thin film transistor according to claim 5, wherein: The gate insulating layer includes: a transition surface and a first surface and a second surface arranged opposite to each other along the thickness direction of the substrate, the transition surface is connected to the first surface and the second surface, and the transition surface includes an inclined surface; the channel includes a main body, and the main body is located on the inclined surface.

7. The thin film transistor according to claim 6, wherein: The channel further includes a first connection portion and a second connection portion connected to both sides of the main body portion, the first connection portion is arranged in contact with the first active portion, and the second connection portion is arranged in contact with the second active portion; wherein, A contact surface between the first connecting portion and the first active portion is perpendicular to a thickness direction of the substrate; and / or A contact surface between the second connection portion and the second active portion is perpendicular to a thickness direction of the substrate.

8. The thin film transistor according to claim 6, wherein: An included angle is formed between the inclined surface and the second surface, and the included angle is greater than or equal to 20° and less than or equal to 40°.

9. The thin film transistor according to claim 5, wherein: It also includes: a drain electrode, which is located on a side of the first active portion away from the substrate and connected to the first active portion, and an orthographic projection of the drain electrode on the substrate overlaps with an orthographic projection of the gate layer on the substrate.

10. The thin film transistor according to any one of claims 1 to 4, wherein: Also includes: A gate layer and a gate insulating layer, wherein the gate layer is located on a side of the active layer away from the substrate, and the gate insulating layer is located between the gate layer and the active layer.

11. The thin film transistor according to any one of claims 1 to 4, wherein: The thickness of the first active portion is greater than or equal to 50Å and less than or equal to 200Å; and / or The thickness of the second active portion is greater than or equal to 50Å and less than or equal to 200Å.

12. The thin film transistor according to claim 2, wherein: The pure silicon layer has an ohmic contact region and a non-ohmic contact region, the selected active portion is connected to a portion of the pure silicon layer located in the ohmic contact region, and the orthographic projections of the first active portion and the second active portion on the pure silicon layer are located outside the non-ohmic contact region; the pure silicon layer includes a first silicon atom located in the ohmic contact region and a second silicon atom located in the non-ohmic contact region; wherein The grain size of the first silicon atoms is greater than the grain size of the second silicon atoms.

13. The thin film transistor according to claim 3, wherein: The first active portion and the second active portion are both located between the channel and the substrate, the thin film transistor further comprises a first insulating layer, the first insulating layer is located between the channel and the substrate and is disposed around the first active portion and the second active portion respectively, a plane of the first insulating layer away from the substrate, a plane of the first active portion away from the substrate, and a plane of the second active portion away from the substrate are coplanar; or The first active portion is located between the channel and the substrate. The thin film transistor also includes a second insulating layer, which is located between the channel and the substrate and is arranged around the first active portion. The plane of the second insulating layer away from the substrate is coplanar with the plane of the first active portion away from the substrate. The second active portion is located on the side of the channel away from the substrate.

14. A method for preparing a thin film transistor, comprising: providing a substrate; as well as An active layer is fabricated on one side of the substrate, the active layer comprising: a first active portion, a second active portion, and a channel connected to the first active portion and the second active portion; wherein at least one of the first active portion and the second active portion is a selected active portion, the channel and the selected active portion are arranged in different layers, the selected active portion comprises silicon atoms and doped atoms, the silicon atoms and the doped atoms in the selected active portion are connected by chemical bonds, and the channel comprises a pure silicon layer.

15. The preparation method according to claim 14, wherein: The step of manufacturing an active layer on one side of the substrate comprises: Disposing a first amorphous silicon layer on one side of the substrate; Depositing a second amorphous silicon layer on a side of the first amorphous silicon layer away from the substrate by a chemical vapor deposition growth process, wherein the doping atoms are grown in the second amorphous silicon layer, and the doping atoms are connected to the silicon atoms in the first amorphous silicon layer by the chemical bonds; Through a laser annealing step, the second amorphous silicon layer and the first amorphous silicon layer are respectively formed into a second polycrystalline silicon layer and a first polycrystalline silicon layer; The second polysilicon layer and the first polysilicon layer are patterned so that the second polysilicon layer forms the first active portion and the second active portion, and the first polysilicon layer forms a pure silicon layer of the channel.

16. An array substrate, comprising a thin film transistor, wherein the thin film transistor comprises: substrate; as well as, An active layer, located on one side of the substrate, the active layer comprising: a first active portion, a second active portion, and a channel connected to the first active portion and the second active portion; At least one of the first active portion and the second active portion is a selected active portion, the channel and the selected active portion are arranged in different layers, the selected active portion includes silicon atoms and doped atoms, the silicon atoms and the doped atoms in the selected active portion are connected by chemical bonds, and the channel includes a pure silicon layer.

17. The array substrate according to claim 16, wherein: The first active portion and the second active portion are both the selected active portions; The selected active portion is formed by chemical vapor deposition growth.

18. The array substrate according to claim 17, wherein: The selected active portion and the channel have crystal grain sizes that are consistent.

19. The array substrate according to claim 18, wherein: The first active portion and the second active portion are respectively located at two ends of the channel, the first active portion and the second active portion are both located at a side of the channel away from the substrate, and the first active portion and the second active portion are arranged in the same layer.

20. The array substrate according to any one of claims 16 to 19, wherein: Also includes: A gate layer and a gate insulating layer, wherein the gate layer is located between the substrate and the channel, and the gate insulating layer is located between the gate layer and the channel.

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