Light-emitting assembly and preparation method therefor, and display panel

Abstract

The present application relates to the technical field of display. Disclosed are a light-emitting assembly and a preparation method therefor, and a display panel. The light-emitting assembly comprises a light-emitting unit, a driving unit and a plurality of connecting electrodes, wherein the plurality of connecting electrodes can be used for receiving a driving signal provided by a driving backboard in a display panel, so that the plurality of connecting electrodes can provide driving signals for the driving unit, and thus the driving unit drives the light-emitting unit to emit light. Since light-emitting assemblies are independently arranged, a certain light-emitting assembly can be directly replaced with a new one in case of light emission failure. Since the structure of the driving backboard in the display panel is relatively simple, even if the driving backboard is damaged when a light-emitting assembly is replaced, a relatively simple process can be used to directly prepare a new driving backboard, so that the abnormal waste of cost can be avoided on the basis of ensuring the yield of the display panel.

Description

Light-emitting component and preparation method thereof, and display panel

[0001] This disclosure claims priority to Chinese patent application No. 202311629987.9 filed on November 30, 2023, entitled “Display substrate, preparation method thereof, display panel and display device”. The entire contents of the above case are incorporated into this disclosure by reference. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a light-emitting component and a preparation method thereof, and a display panel. Background Art

[0003] The display panel includes a driving backplane and a plurality of light-emitting units connected to the driving backplane. The driving backplane can provide driving signals to the light-emitting units so that the light-emitting units emit light, thereby realizing display.

[0004] Summary of the Invention

[0005] This application provides a light-emitting component and a method for manufacturing the same, and a display panel. The technical solutions are as follows:

[0006] In one aspect, a light emitting assembly is provided, comprising:

[0007] a light-emitting unit, the light-emitting unit comprising a light-emitting unit electrode and a light-emitting portion electrically connected to the light-emitting unit electrode;

[0008] A driving unit, comprising a driving electrode and a driving circuit electrically connected to the driving electrode, wherein the driving electrode is located on a side of the driving circuit facing the light-emitting unit; the driving electrode is electrically connected to the light-emitting unit electrode;

[0009] Also, a plurality of connecting electrodes are located on a side of the driving unit away from the light-emitting unit, the connecting electrodes are electrically connected to the driving circuit, the connecting electrodes are configured to be electrically connected to a driving backplane included in the display panel, and the driving backplane is configured to provide a driving signal to the driving circuit through the connecting electrodes.

[0010] Optionally, the light-emitting unit electrode includes a first light-emitting unit electrode and a second light-emitting unit electrode, the driving electrode includes a first driving electrode and a second driving electrode, and the driving circuit includes a pixel driving circuit;

[0011] The first light-emitting unit electrode is electrically connected to the first driving electrode, and the second light-emitting unit electrode is electrically connected to the second driving electrode; the first driving electrode is also electrically connected to the pixel driving circuit.

[0012] Optionally, the light-emitting component includes a plurality of light-emitting units, and the plurality of light-emitting units include a light-emitting unit of a first color, a light-emitting unit of a second color, and a light-emitting unit of a third color; wherein the first color, the second color, and the third color are different from each other;

[0013] The driving circuit includes a plurality of pixel driving circuits corresponding to the plurality of light-emitting units, the driving electrode includes a plurality of first driving electrodes, the plurality of pixel driving circuits and the plurality of first driving electrodes are also arranged correspondingly, each of the first driving electrodes is electrically connected to the first light-emitting unit electrode of the corresponding light-emitting unit, and each of the pixel driving circuits is electrically connected to the corresponding first driving electrode.

[0014] Optionally, the plurality of light-emitting units include a common second light-emitting unit electrode, and the driving unit further includes a common second driving electrode;

[0015] Wherein, the second light emitting unit electrode is electrically connected to the second driving electrode.

[0016] Optionally, the driving circuit includes a first type of thin film transistor, the first type of thin film transistor is a dual-gate transistor, the first type of thin film transistor includes a first active pattern, a first bottom gate, a first top gate, a first source and a first drain; the driving unit includes: a substrate, a barrier layer, a first metal layer, a first buffer layer, a first active layer, a first insulating layer, a second metal layer, a second insulating layer and a third metal layer stacked in sequence.

[0017] Optionally, the first metal layer includes the first bottom gate, the second metal layer includes the first top gate, the first active layer includes a first active pattern, the first active pattern is located between the first bottom gate and the first top gate, and the first top gate is electrically connected to the first bottom gate through a via hole passing through the first insulating layer and the first buffer layer;

[0018] The second metal layer includes a first transfer pattern, and the first transfer pattern is electrically connected to the connection electrode through a via hole passing through the first insulating layer, the first buffer layer, and the barrier layer;

[0019] The third metal layer includes the first source and the first drain, and a first interconnection pattern, the first source is electrically connected to the source region of the first active pattern through a via passing through the second insulating layer and the first insulating layer, the first drain is electrically connected to the drain region of the first active pattern through a via passing through the second insulating layer and the first insulating layer, the first interconnection pattern is electrically connected to the first transfer pattern through a via passing through the second insulating layer, and the first interconnection pattern is electrically connected to the first active pattern through a via passing through the second insulating layer and the first insulating layer.

[0020] Optionally, the driving unit includes: a connection pattern located between the substrate and the barrier layer, at least a portion of the connection electrode being located inside the substrate, the substrate having a connection via hole exposing the connection electrode, a portion of the connection pattern being located within the connection via hole and electrically connected to the connection electrode, and another portion of the connection pattern being located on a side of the substrate close to the driving circuit;

[0021] The first transfer pattern is electrically connected to the connection pattern through a via hole passing through the first insulating layer, the first buffer layer, and the barrier layer.

[0022] Optionally, the driving circuit includes a plurality of thin film transistors; the plurality of thin film transistors include at least one low-temperature polysilicon thin film transistor and at least one oxide thin film transistor;

[0023] Among them, at least one of the low-temperature polysilicon thin film transistors included in the plurality of thin film transistors is the first type of thin film transistor.

[0024] Optionally, the oxide thin film transistor is a single-gate transistor, comprising a gate, a second active pattern, a second source electrode, and a second drain electrode; the driving unit further comprises: a fourth metal layer located between the second insulating layer and the third metal layer, a third insulating layer, a second active layer, and a fourth insulating layer;

[0025] The fourth metal layer includes the gate, the second active layer includes a second active pattern, and an orthographic projection of the second active pattern on the substrate partially overlaps with an orthographic projection of the gate on the substrate;

[0026] The third metal layer further includes the second source and the second drain, the second source being electrically connected to the source region of the second active pattern through a via passing through the fourth insulating layer, and the second drain being electrically connected to the drain region of the second active pattern through a via passing through the fourth insulating layer.

[0027] Optionally, the oxide thin film transistor is a single-gate transistor, comprising a gate, a second active pattern, a second source electrode, and a second drain electrode; the driving unit further comprises: a fourth metal layer located between the second insulating layer and the third metal layer, a third insulating layer, a second active layer, a fourth insulating layer, a fifth metal layer, and a fifth insulating layer;

[0028] The fourth metal layer or the fifth metal layer includes the gate, the second active layer includes a second active pattern, and an orthographic projection of the second active pattern on the substrate partially overlaps with an orthographic projection of the gate on the substrate;

[0029] The third metal layer also includes the second source and the second drain, the second source is electrically connected to the source region of the second active pattern through a via passing through the fifth insulating layer and the fourth insulating layer, and the second drain is electrically connected to the drain region of the second active pattern through a via passing through the fifth insulating layer and the fourth insulating layer.

[0030] Optionally, the oxide thin film transistor is a dual-gate transistor, comprising a second active pattern, a second bottom gate, a second top gate, a second source electrode, and a second drain electrode; the driving unit further comprises: a fourth metal layer located between the second insulating layer and the third metal layer, a third insulating layer, a second active layer, a fourth insulating layer, a fifth metal layer, and a fifth insulating layer;

[0031] The fourth metal layer includes the second bottom gate, the fifth metal layer includes the second top gate, the second active layer includes a second active pattern, and the second active pattern is located between the second bottom gate and the second top gate;

[0032] The third metal layer further includes a third interconnect pattern, the third interconnect pattern being electrically connected to the second top gate via a via passing through the fifth insulating layer and the fourth insulating layer, and the third interconnect pattern being electrically connected to the second bottom gate via a via passing through the fifth insulating layer, the fourth insulating layer, and the third insulating layer;

[0033] The third metal layer also includes the second source and the second drain, the second source is electrically connected to the source region of the second active pattern through a via passing through the fifth insulating layer and the fourth insulating layer, and the second drain is electrically connected to the drain region of the second active pattern through a via passing through the fifth insulating layer and the fourth insulating layer.

[0034] Optionally, the driving circuit includes a first type of thin film transistor, the first type of thin film transistor is a dual-gate transistor, and the first type of thin film transistor includes a first active pattern, a first bottom gate, a first top gate, a first source and a first drain; the driving unit includes: a substrate, a blocking layer, a first metal layer, a first buffer layer, a first active layer, a first insulating layer, a second metal layer, a second insulating layer, a fourth metal layer, a third insulating layer and a third metal layer stacked in sequence.

[0035] Optionally, the first metal layer includes the first bottom gate, the second metal layer includes the first top gate, the first active layer includes a first active pattern, the first active pattern is located between the first bottom gate and the first top gate, the fourth metal layer includes a second interconnection pattern, the second interconnection pattern is electrically connected to the first top gate through a via hole passing through the second insulating layer, and the second interconnection pattern is electrically connected to the first bottom gate through a via hole passing through the first insulating layer, the second insulating layer, and the first buffer layer;

[0036] The fourth metal layer further includes a second transfer pattern, and the second transfer pattern is electrically connected to the connection electrode through a via hole passing through the first insulating layer, the second insulating layer, the first buffer layer and the barrier layer;

[0037] The third metal layer includes the first source, the first drain, and a third interconnection pattern. The first source is electrically connected to the source region of the first active pattern through a via passing through the third insulating layer, the second insulating layer, and the first insulating layer. The first drain is electrically connected to the drain region of the first active pattern through a via passing through the third insulating layer, the second insulating layer, and the first insulating layer. The third interconnection pattern is electrically connected to the third-type transfer pattern through a via passing through the third insulating layer, and the first interconnection pattern is electrically connected to the first active pattern through a via passing through the third insulating layer, the second insulating layer, and the first insulating layer.

[0038] Optionally, the driving unit includes: a connection pattern located between the substrate and the barrier layer, at least a portion of the connection electrode being located inside the substrate, the substrate having a connection via hole exposing the connection electrode, a portion of the connection pattern being located within the connection via hole and electrically connected to the connection electrode, and another portion of the connection pattern being located on a side of the substrate close to the driving circuit;

[0039] The second transfer pattern is electrically connected to the connection pattern through a via hole passing through the second insulating layer, the first insulating layer, the first buffer layer, and the barrier layer.

[0040] Optionally, the driving circuit includes a plurality of thin film transistors; the plurality of thin film transistors include at least one low-temperature polysilicon thin film transistor and at least one oxide thin film transistor;

[0041] Among them, at least one of the low-temperature polysilicon thin film transistors included in the plurality of thin film transistors is the first type of thin film transistor.

[0042] Optionally, the oxide thin film transistor is a single-gate transistor, comprising a gate, a second active pattern, a second source electrode, and a second drain electrode; the driving unit further comprises: a second active layer and a fourth insulating layer located between the third insulating layer and the third metal layer;

[0043] The fourth metal layer includes the gate, the second active layer includes a second active pattern, and an orthographic projection of the second active pattern on the substrate partially overlaps with an orthographic projection of the gate on the substrate;

[0044] The third metal layer further includes the second source and the second drain, the second source being electrically connected to the source region of the second active pattern through a via passing through the fourth insulating layer, and the second drain being electrically connected to the drain region of the second active pattern through a via passing through the fourth insulating layer.

[0045] Optionally, the oxide thin film transistor is a single-gate transistor, comprising a gate, a second active layer, a second source electrode, and a second drain electrode; the driving unit further comprises: a second active layer, a fourth insulating layer, a fifth metal layer, and a fifth insulating layer located between the third insulating layer and the third metal layer;

[0046] The fourth metal layer or the fifth metal layer includes the gate, the second active layer includes a second active pattern, and an orthographic projection of the second active pattern on the substrate partially overlaps with an orthographic projection of the gate on the substrate;

[0047] The third metal layer also includes the second source and the second drain, the second source is electrically connected to the source region of the second active pattern through a via passing through the fifth insulating layer and the fourth insulating layer, and the second drain is electrically connected to the drain region of the second active pattern through a via passing through the fifth insulating layer and the fourth insulating layer.

[0048] Optionally, the oxide thin film transistor is a dual-gate transistor, comprising a second active layer, a second bottom gate, a second top gate, a second source electrode, and a second drain electrode; the driving unit further comprises: a second active layer, a fourth insulating layer, a fifth metal layer, and a fifth insulating layer located between the third insulating layer and the third metal layer;

[0049] The fourth metal layer includes the second bottom gate, the fifth metal layer includes the second top gate, the second active layer includes a second active pattern, and the second active pattern is located between the second bottom gate and the second top gate;

[0050] The third metal layer further includes a third interconnect pattern, the third interconnect pattern being electrically connected to the second top gate via a via passing through the fifth insulating layer and the fourth insulating layer, and the third interconnect pattern being electrically connected to the second bottom gate via a via passing through the fifth insulating layer, the fourth insulating layer, and the third insulating layer;

[0051] The third metal layer also includes the second source and the second drain, the second source is electrically connected to the source region of the second active pattern through a via passing through the fifth insulating layer and the fourth insulating layer, and the second drain is electrically connected to the drain region of the second active pattern through a via passing through the fifth insulating layer and the fourth insulating layer.

[0052] Optionally, the thickness of the first metal layer ranges from 20 nanometers to 200 nanometers.

[0053] Optionally, the barrier layer has a thickness ranging from 50 nm to 600 nm;

[0054] The thickness of the first buffer layer is greater than or equal to 170 nanometers.

[0055] Optionally, the light-emitting unit electrode includes a first light-emitting unit electrode and a second light-emitting unit electrode, and the driving electrode includes the first driving electrode and the second driving electrode;

[0056] The first driving electrode is electrically connected to one of the thin film transistors in the driving circuit, and the first driving electrode is used to transmit a first signal to the first light-emitting unit electrode of the light-emitting unit;

[0057] The second driving electrode is used to transmit a second signal to the second light-emitting unit electrode, and the potential of the second signal is different from the potential of the first signal.

[0058] Optionally, the driving unit further includes: an organic film layer, a first inorganic film layer, and a second inorganic film layer located on a side of the third metal layer away from the substrate;

[0059] The organic film layer has a first electrode connection hole, the first electrode connection hole has a hole sidewall and a hole bottom, and the first electrode connection hole is used to expose at least a portion of the pattern in the source and drain electrode layer;

[0060] The first inorganic film layer has a second electrode connection hole, the orthographic projection of the second electrode connection hole on the substrate is located within the orthographic projection of the first electrode connection hole on the substrate, the first inorganic film layer covers the sidewalls of the hole and exposes the bottom of the hole to expose at least a portion of the pattern in the source and drain layer exposed at the bottom of the hole, and the drive electrode is connected to the pattern in the source and drain layer through the second electrode connection hole and the first electrode connection hole;

[0061] The second inorganic film layer has a via hole exposing the driving electrode, and the light-emitting unit electrode is electrically connected to the driving electrode through the via hole of the second inorganic film layer.

[0062] Optionally, the orthographic projection of the via in the second inorganic film layer on the substrate is located within the orthographic projection of the driving electrode on the substrate, and the second inorganic film layer wraps the edge of the driving electrode.

[0063] Optionally, the driving unit further includes: an organic film layer located on a side of the third metal layer away from the substrate, a first inorganic film layer, and a second inorganic film layer; the organic film layer has a first electrode connection hole, the first electrode connection hole being used to expose at least a portion of the pattern in the source and drain layer; the first inorganic film layer has a second electrode connection hole to expose at least a portion of the pattern in the source and drain layer, the driving electrode is connected to at least a portion of the pattern in the source and drain layer through the second electrode connection hole and the first electrode connection hole; the second inorganic film layer has a via hole exposing the driving electrode, and the light-emitting unit electrode is electrically connected to the driving electrode through the via hole in the second inorganic film layer;

[0064] The first metal layer is a light-shielding layer, the first active layer is a low-temperature polycrystalline silicon semiconductor layer, the first insulating layer is a first gate insulating layer, the second metal layer is a first gate layer, the second insulating layer is a second gate insulating layer, the fourth metal layer is a second gate layer, the third insulating layer includes a first interlayer dielectric layer and a second buffer layer, the second active layer is an oxide semiconductor layer, the fourth insulating layer is a third gate insulating layer, the fifth metal layer is a third gate layer, the fifth insulating layer is a second interlayer dielectric layer, the organic film layer is a planarizing layer, the first inorganic film layer is a first passivation layer, and the second inorganic film layer is a second passivation layer.

[0065] Optionally, the thickness of the substrate ranges from 3 microns to 10 microns.

[0066] Optionally, the thickness of the first interlayer dielectric layer is in a range of 50 nanometers to 500 nanometers.

[0067] Optionally, the thickness of the first inorganic film layer ranges from 50 nanometers to 300 nanometers.

[0068] Optionally, the thickness of the second inorganic film layer ranges from 50 nanometers to 300 nanometers.

[0069] Optionally, the orthographic projection of the driving electrode on the substrate in the driving unit and the orthographic projection of the connecting electrode on the substrate in the driving unit do not overlap.

[0070] Optionally, the light emitting assembly further comprises: a dam structure located between the light emitting portion and the driving circuit;

[0071] The dam structure is ring-shaped and surrounds the light-emitting unit electrode and the driving electrode.

[0072] Optionally, the width of the dam structure is greater than or equal to 0.9 micrometers and less than or equal to 11 micrometers.

[0073] Optionally, an orthographic projection of the dam structure on the substrate in the driving unit does not overlap with a connection via in the substrate.

[0074] Optionally, an orthographic projection of the dam structure on the substrate in the driving unit partially overlaps with an orthographic projection of a connection pattern in the driving unit on the substrate, and the overlapping position is located on a side of the connection via close to the light-emitting component.

[0075] Optionally, the driving circuit includes a plurality of thin film transistors; the plurality of thin film transistors include at least one low-temperature polysilicon thin film transistor and at least one oxide thin film transistor;

[0076] The active layer of the at least one low-temperature polysilicon thin film transistor is located on a side of the active layer of the at least one oxide thin film transistor away from the driving electrode.

[0077] Optionally, the light-emitting unit electrode includes a first light-emitting unit electrode and a second light-emitting unit electrode, and the driving electrode includes the first driving electrode and the second driving electrode;

[0078] The first driving electrode is electrically connected to one of the thin film transistors in the driving circuit, and the first driving electrode is used to transmit a first signal to the first light-emitting unit electrode of the light-emitting unit;

[0079] The second driving electrode is used to transmit a second signal to the second light-emitting unit electrode, and the potential of the second signal is different from the potential of the first signal.

[0080] Optionally, the driving circuit includes a gate driving circuit and a light-emitting driving circuit, and the light-emitting unit is electrically connected to the gate driving circuit and the light-emitting driving circuit.

[0081] Optionally, the driving circuit further includes a multiplexing circuit, and the driving signal of the driving backplane is transmitted to the light-emitting component after passing through the multiplexing circuit.

[0082] In another aspect, a method for preparing a light-emitting component is provided. The method is used to prepare the light-emitting component according to the above aspect, and the method comprises:

[0083] Obtain a first substrate and a light-emitting unit located on one side of the first substrate, the light-emitting unit comprising: a light-emitting unit electrode and a light-emitting portion electrically connected to the light-emitting unit electrode, the light-emitting unit electrode being located on a side of the light-emitting portion away from the first substrate;

[0084] Obtain a second substrate and a driving unit located on one side of the second substrate, the driving unit comprising a driving electrode and a driving circuit electrically connected to the driving electrode, the driving electrode being located on a side of the driving circuit away from the second substrate;

[0085] Bonding the light emitting unit and the driving unit together through a bonding process, so that the driving electrode and the light emitting unit electrode are electrically connected;

[0086] peeling the second substrate from one side of the driving unit;

[0087] A plurality of connecting electrodes are formed on a side of the driving unit away from the light-emitting unit, the plurality of connecting electrodes are electrically connected to the driving circuit, the connecting electrodes are configured to be electrically connected to a driving backplane included in the display panel, and the driving backplane is configured to provide a driving signal to the driving power supply through the connecting electrodes.

[0088] In another aspect, a display panel is provided, comprising: a driving backplane, and a plurality of light-emitting components as described in the above aspects arranged in an array and located on one side of the driving backplane;

[0089] The driving backplane is used to provide a driving signal for the light-emitting component to make the light-emitting component emit light. BRIEF DESCRIPTION OF THE DRAWINGS

[0090] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0091] FIG1 is a schematic structural diagram of a light-emitting component provided in an embodiment of the present application;

[0092] FIG2 is a top view of a first driving electrode and a second driving electrode provided in an embodiment of the present application;

[0093] FIG3 is a schematic structural diagram of a driving unit and connecting electrodes provided in an embodiment of the present application;

[0094] FIG4 is a schematic structural diagram of another driving unit and connecting electrodes provided in an embodiment of the present application;

[0095] FIG5 is a schematic structural diagram of another driving unit and connecting electrodes provided in an embodiment of the present application;

[0096] FIG6 is a schematic structural diagram of another driving unit and connecting electrodes provided in an embodiment of the present application;

[0097] FIG7 is a schematic structural diagram of another driving unit and connecting electrodes provided in an embodiment of the present application;

[0098] FIG8 is a schematic structural diagram of another driving unit and connecting electrodes provided in an embodiment of the present application;

[0099] FIG9 is a schematic structural diagram of another driving unit and connecting electrodes provided in an embodiment of the present application;

[0100] FIG10 is a schematic structural diagram of another driving unit and connecting electrodes provided in an embodiment of the present application;

[0101] FIG11 is a schematic structural diagram of another driving unit and connecting electrodes provided in an embodiment of the present application;

[0102] FIG12 is a schematic structural diagram of another driving unit and connecting electrodes provided in an embodiment of the present application;

[0103] FIG13 is a schematic diagram of forming a substrate, a first passivation layer, and a connection pattern according to an embodiment of the present application;

[0104] FIG14 is a schematic diagram of another method for forming a substrate, a first passivation layer, and a connection pattern provided by an embodiment of the present application;

[0105] FIG15 is a top view of a driving electrode and a connecting electrode provided in an embodiment of the present application;

[0106] FIG16 is a top view of a driving electrode, a connection pattern, and a second dam portion provided in an embodiment of the present application;

[0107] FIG17 is a schematic structural diagram of another light-emitting assembly provided in an embodiment of the present application;

[0108] FIG18 is a top view of another driving electrode, a connection pattern, and a second dam portion provided in an embodiment of the present application;

[0109] FIG19 is a schematic diagram of an equivalent circuit of a pixel driving circuit provided in an embodiment of the present application;

[0110] FIG20 is a schematic diagram of an equivalent circuit of a gate drive circuit provided in an embodiment of the present application;

[0111] FIG21 is a schematic diagram of an equivalent circuit of a light-emitting driving circuit provided in an embodiment of the present application;

[0112] FIG22 is a flow chart of a method for preparing a light-emitting component provided in an embodiment of the present application;

[0113] FIG23 is a schematic diagram of a bonding connection between a light emitting unit and a driving unit provided in an embodiment of the present application;

[0114] FIG24 is a schematic diagram of peeling off a second substrate provided in an embodiment of the present application;

[0115] FIG25 is a schematic diagram of forming a connecting electrode according to an embodiment of the present application;

[0116] FIG26 is a schematic diagram of forming a release layer on one side of a second substrate according to an embodiment of the present application;

[0117] FIG27 is a schematic diagram of forming a connection pad film according to an embodiment of the present application;

[0118] FIG28 is a schematic diagram of forming a connection pad according to an embodiment of the present application;

[0119] FIG29 is a schematic diagram of forming a substrate film according to an embodiment of the present application;

[0120] FIG30 is a schematic diagram of forming a substrate provided in an embodiment of the present application;

[0121] FIG31 is a schematic diagram of forming a third passivation layer according to an embodiment of the present application;

[0122] FIG32 is a schematic diagram of forming a connection pattern provided by an embodiment of the present application;

[0123] FIG33 is a schematic diagram of forming a barrier film according to an embodiment of the present application;

[0124] FIG34 is a schematic diagram of forming a light shielding layer according to an embodiment of the present application;

[0125] 35 is a schematic diagram of forming a first buffer film and a low-temperature polysilicon semiconductor layer according to an embodiment of the present application;

[0126] FIG36 is a schematic diagram of forming a first gate insulating layer according to an embodiment of the present application;

[0127] FIG37 is a schematic diagram of forming a first gate layer according to an embodiment of the present application;

[0128] FIG38 is a schematic diagram of forming a second gate insulating film and a second gate layer according to an embodiment of the present application;

[0129] FIG39 is a schematic diagram of forming a first interlayer dielectric film, a second buffer film, and an oxide semiconductor layer according to an embodiment of the present application;

[0130] FIG40 is a schematic diagram of forming a third gate insulating film and a third gate layer according to an embodiment of the present application;

[0131] 41 is a schematic diagram of forming a via hole exposing a first transfer pattern, a via hole exposing a low-temperature polysilicon semiconductor layer, a via hole exposing a first gate layer, and a via hole exposing a second gate layer, provided by an embodiment of the present application;

[0132] FIG42 is a schematic diagram of forming a via hole exposing an oxide semiconductor layer and a via hole exposing a third gate layer according to an embodiment of the present application;

[0133] FIG43 is a schematic diagram of forming a source and drain layer according to an embodiment of the present application;

[0134] FIG44 is a schematic diagram of forming a flat layer according to an embodiment of the present application;

[0135] FIG45 is a schematic diagram of forming a first passivation layer according to an embodiment of the present application;

[0136] FIG46 is a schematic diagram of forming a first driving electrode, a second driving electrode, and a second dam portion provided in an embodiment of the present application;

[0137] FIG47 is a schematic diagram of forming a second passivation film according to an embodiment of the present application;

[0138] FIG48 is a schematic diagram of forming multiple independent drive units according to an embodiment of the present application;

[0139] FIG49 is a schematic diagram of an inorganic film layer and a substrate provided in an embodiment of the present application;

[0140] FIG50 is a schematic diagram of forming a second passivation layer according to an embodiment of the present application;

[0141] Figure 51 is a structural schematic diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0142] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0143] In some embodiments, a driving backplane includes a substrate and a driving circuit located on the substrate. The driving circuit includes a plurality of pixel circuits corresponding to a plurality of light-emitting units. Each pixel circuit is connected to a corresponding light-emitting unit to drive the light-emitting unit to emit light. The plurality of light-emitting units can be connected to the driving backplane via transfer printing.

[0144] However, during the process of transferring the plurality of light-emitting units to the driving backplane, some of the light-emitting units may fail to emit light, thereby resulting in a poor yield of the entire display panel.

[0145] The present disclosure describes a plurality of embodiments, but this description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0146] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features, and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive solution defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any appropriate combination. Therefore, the embodiments are not subject to other limitations except for the limitations set forth in the appended claims and their equivalents. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0147] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation on the claims. In addition, the claims to the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can be changed and still remain within the spirit and scope of the disclosed embodiments.

[0148] In the drawings, the size of one or more components, thickness of layers, or regions may be exaggerated for clarity. In addition, the drawings schematically illustrate ideal examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0149] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0150] The thickness range of the film layer in this specification is A to B, which is used to indicate that the thickness is between A and B, and includes the two endpoint values ​​of A and B.

[0151] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0152] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0153] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0154] In this specification, the first electrode of a transistor can be a drain electrode, and the second electrode of a transistor can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0155] In this specification, "connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0156] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0157] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0158] In the present disclosure, “thickness” and “height” refer to the vertical distance between the surface of the film layer away from the substrate and the surface of the film layer close to the substrate.

[0159] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0160] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0161] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0162] FIG1 is a schematic diagram of the structure of a light emitting assembly provided in an embodiment of the present application. Referring to FIG1 , it can be seen that the light emitting assembly 100 includes: a light emitting unit 101 , a driving unit 102 , and a plurality of connecting electrodes 103 located on a side of the driving unit 102 away from the light emitting unit 101 .

[0163] The light emitting unit 101 includes a light emitting unit electrode 1011 and a light emitting portion 1012 electrically connected to the light emitting unit electrode 1011. The light emitting unit electrode 1011 is located on one side of the light emitting portion 1012.

[0164] The driving unit 102 includes a driving electrode 1021 and a driving circuit 1022 electrically connected to the driving electrode 1021. The driving electrode 1021 is located on a side of the driving circuit 1022 facing the light emitting unit 101. The driving electrode 1021 is electrically connected to the light emitting unit electrode 1011.

[0165] The plurality of connection electrodes 103 are electrically connected to the driving circuit 1022. The connection electrodes 103 are configured to be electrically connected to the driving backplane included in the display panel. The driving backplane is configured to provide a driving signal to the driving circuit 1022 through the connection electrodes 103. That is, in the embodiment of the present application, the plurality of connection electrodes 103 included in the light-emitting component 100 can be used to receive the driving signal provided by the driving backplane, and then the plurality of connection electrodes 103 can provide the driving signal to the driving unit 102, so that the driving unit 102 drives the light-emitting unit 101 to emit light.

[0166] In the embodiment of the present application, the light-emitting assembly 100 can be an independently provided light-emitting assembly. This allows for direct replacement of a light-emitting assembly if it fails. Because the driver backplane in the display panel has a relatively simple structure, even if the driver backplane is damaged during replacement of the light-emitting assembly, a new driver backplane can be directly produced using a relatively simple process. This avoids significant cost waste while maintaining the yield of the display panel.

[0167] In summary, an embodiment of the present application provides a light-emitting component, which includes a light-emitting unit, a driving unit, and a plurality of connecting electrodes. Among them, the plurality of connecting electrodes can be used to receive a driving signal provided by a driving backplane in a display panel, and then the plurality of connecting electrodes can provide a driving signal to the driving unit, so that the driving unit drives the light-emitting unit to emit light. Since the light-emitting components are independently arranged, in the event that some light-emitting components fail to emit light, a new light-emitting component can be directly replaced. Since the structure of the driving backplane in the display panel is relatively simple, even if the driving backplane is damaged when the light-emitting component is replaced, a new driving backplane can be directly prepared using a simpler process, which can avoid abnormal waste of costs while ensuring the yield of the display panel.

[0168] In an embodiment of the present application, referring to FIG1 , the connection electrode 103 may include a pin 1031 protruding from the drive unit. Alternatively, in addition to the pin 1031, the connection electrode 103 may also include a connection pad 1032 located within the drive unit 102 and having a surface exposed to the drive unit (the surface being the side of the drive unit facing away from the light-emitting unit). The drawings of the embodiment of the present application illustrate an example in which the connection electrode 103 includes the pin 1031 and the connection pad 1032.

[0169] In the embodiment of the present application, since the light-emitting component 100 is independently provided, when preparing different display panels, after designing the driving backplane, the connecting electrode 103 of the light-emitting component 100 can be connected to the driving backplane to obtain the required display panel. In this way, a display panel of any shape can be formed, such as a rectangle, a circle, an ellipse, a cross, a trapezoid, other polygonal shapes and irregular shapes. Since the driving backplane does not contain logic devices such as transistors, but only has simple wiring and binding pads and other structures, the design of the driving backplane is simpler, which can greatly save the cost of manpower design. By preparing multiple light-emitting components 100 in advance, they can be directly connected to the driving backplane, which greatly simplifies the preparation process of the display panel. By setting the driving unit 102 in the light-emitting component 100, a single light-emitting component 100 can directly receive the input signal from the driving backplane, which can effectively reduce the voltage drop, reduce the power consumption of the display panel, and improve the display effect of the display panel.

[0170] As can be seen from FIG1 , the light-emitting unit electrode 1011 includes a first light-emitting unit electrode 10111 and a second light-emitting unit electrode 10112. The driving electrode 1021 includes a first driving electrode 10211 and a second driving electrode 10212. The driving circuit 1022 includes a pixel driving circuit. The first light-emitting unit electrode 10111 is electrically connected to the first driving electrode 10211, the second light-emitting unit electrode 10112 is electrically connected to the second driving electrode 10212, and the first driving electrode 10211 is also electrically connected to the pixel driving circuit.

[0171] Optionally, the light emitting assembly 100 includes a plurality of light emitting units 101. The plurality of light emitting units 101 include a light emitting unit of a first color, a light emitting unit of a second color, and a light emitting unit of a third color. The first color, the second color, and the third color are different from each other.

[0172] For example, if the first color is red (red, R), the light-emitting unit of the first color can be called a red light-emitting unit. If the second color is green (green, G), the light-emitting unit of the second color can be called a green light-emitting unit. If the third color is blue (blue, B), the light-emitting unit of the third color can be called a blue light-emitting unit.

[0173] Optionally, the driving circuit 1022 includes multiple pixel driving circuits corresponding to the multiple light-emitting units 101. The driving electrodes include multiple first driving electrodes 10211 corresponding to the multiple light-emitting units 101. The multiple pixel driving circuits and the multiple first driving electrodes 10211 are also provided correspondingly. Each first driving electrode 10211 is electrically connected to the first light-emitting unit electrode 10111 of the corresponding light-emitting unit 101, and each pixel driving circuit is electrically connected to the corresponding first driving electrode 10211.

[0174] Furthermore, the plurality of light emitting units 101 include a common second light emitting unit electrode 10112, and the driving unit 102 further includes a common second driving electrode 10212. The second light emitting unit electrode 10112 and the second driving electrode 10212 are electrically connected.

[0175] In an embodiment of the present application, the pixel driving circuit may include a plurality of thin film transistors (TFTs). The plurality of TFTs include at least one low temperature poly-silicon (LTPS) TFT and at least one oxide (LTPO) TFT. The active layer of the at least one LTPS TFT is located on a side of the active layer of the at least one oxide TFT away from the driving electrode 1021.

[0176] Optionally, the first drive electrode 10211 is electrically connected to a thin film transistor in the pixel drive circuit. The first drive electrode 10211 is used to transmit a first signal to the first light-emitting unit electrode 10111 of the corresponding light-emitting unit 101. The second drive electrode 10212 is used to transmit a second signal to the second light-emitting unit electrode 10112, and the second signal has a different potential than the first signal.

[0177] Optionally, when the common electrode formed by the electrical connection between the second light-emitting unit electrode 10112 and the second driving electrode 10212 is a cathode, the multiple light-emitting units 101 (such as three light-emitting units 101) included in the light-emitting component 100 can adopt a common cathode design.

[0178] For example, referring to FIG2 , the first first drive electrode 10211a, the second first drive electrode 10211b, the third first drive electrode 10211c, and the second drive electrode 10212 can be arranged in an array. For example, the first first drive electrode 10211a and the second first drive electrode 10211b can be arranged along a first direction X, and the second first drive electrode 10211b can be located on one side of the first first drive electrode 10211a along the first direction X. The third first drive electrode 10211c and the second drive electrode 10212 can be arranged along the first direction X, and the third first drive electrode 10211c can be located on one side of the second drive electrode 10212 along the first direction X. The first direction X and the second direction Y intersect.

[0179] Furthermore, the first first driving electrode 10211a and the second driving electrode 10212 may be arranged along the second direction Y, and the second driving electrode 10212 may be located on a side of the first first driving electrode 10211a opposite to the second direction Y. The second first driving electrode 10211b and the third first driving electrode 10211c may be arranged along the second direction Y, and the third first driving electrode 10211c may be located on a side of the second first driving electrode 10211b opposite to the second direction Y.

[0180] For example, the first first driving electrode 10211a can be connected to the first light-emitting unit electrode 10111 of the red light-emitting unit, the second first driving electrode 10211b can be connected to the first light-emitting unit electrode 10111 of the green light-emitting unit, and the third first driving electrode 10211c can be connected to the first light-emitting unit electrode 10111 of the blue light-emitting unit.

[0181] In other embodiments, the three light-emitting units 101 may not adopt a common cathode design. For example, the second drive electrode 10212 may be arranged around the first drive electrode 10211, and the three light-emitting units 101 may be arranged as needed. The embodiment of the present application does not limit the arrangement of the second drive electrode 10212 and the arrangement of the light-emitting units 101. Figure 2 illustrates a single light-emitting component 100 including three light-emitting units 101 of different colors (i.e., three sub-pixels). In other embodiments, a single light-emitting component may include four light-emitting units 101 of different colors. The number, color, and distribution of the light-emitting units 101 included in a single light-emitting component may be set as needed, and the embodiment of the present application does not limit this.

[0182] In an embodiment of the present application, the plurality of thin film transistors include at least one low temperature poly-silicon (LTPS) thin film transistor and at least one low temperature polycrystalline oxide (LTPO) thin film transistor.

[0183] Optionally, during the preparation of the driving unit 102, a low-temperature polysilicon thin-film transistor can be prepared first, and then an oxide thin-film transistor can be prepared. The reason is that there are process limitations (for example, high-temperature process) when preparing the low-temperature polysilicon thin-film transistor. If the oxide thin-film transistor is prepared first, the process limitations when preparing the low-temperature polysilicon thin-film transistor will affect the oxide thin-film transistor. For example, the low-temperature polysilicon thin-film transistor is arranged farther away from the light-emitting unit 101 than the oxide thin-film transistor.

[0184] Optionally, the pixel driving circuit of the driving circuit 1022 includes a first type of thin film transistor. The first type of thin film transistor may be a dual-gate transistor, comprising a first bottom gate n31, a first top gate n71, a first source n91, and a first drain n92. Among the plurality of thin film transistors, at least one low-temperature polysilicon thin film transistor is a first type of thin film transistor, that is, at least one low-temperature polysilicon thin film transistor is a dual-gate transistor.

[0185] Since dual-gate transistors can achieve higher mobility and larger drive current than single-gate transistors, at least one of the low-temperature polysilicon thin-film transistors can be configured as a dual-gate transistor. For example, the driving transistor in the pixel driving circuit can be configured as a dual-gate transistor.

[0186] As an optional implementation, referring to Figure 3, the driving unit 102 includes: a substrate n1, a barrier layer n2, a first metal layer n3, a first buffer layer n4, a first active layer n5, a first insulating layer n6, a second metal layer n7, a second insulating layer n8 and a third metal layer n9 stacked in sequence.

[0187] Optionally, referring to Figure 3 , the first metal layer n3 includes a first bottom gate n31, and the second metal layer n7 includes a first top gate n71. The first active layer n5 includes a first active pattern n51, which is located between the first bottom gate n31 and the first top gate n71. The first top gate n71 is electrically connected to the first bottom gate n31 via a via passing through the first insulating layer n6 and the first buffer layer n4. The second metal layer n7 includes a first switching pattern n72. The first switching pattern n72 is electrically connected to the connection electrode via a via passing through the first insulating layer n6, the first buffer layer n4, and the barrier layer n2.

[0188] Referring to Figure 3, the third metal layer n9 includes a first source n91 and a first drain n92, and a first interconnect pattern n93 (the first interconnect pattern n93 and the first source n91 in Figure 3 are the same pattern). The first source n91 is electrically connected to the source region of the first active pattern n51 through a via passing through the second insulating layer n8 and the first insulating layer n6. The first drain n92 is electrically connected to the drain region of the first active pattern n51 through a via passing through the second insulating layer n8 and the first insulating layer n6. The first interconnect pattern n93 is electrically connected to the first transfer pattern n72 through a via passing through the second insulating layer n8, and the first interconnect pattern n93 is electrically connected to the first active pattern n51 through a via passing through the second insulating layer n8 and the first insulating layer n6.

[0189] In the embodiment of the present application, referring to FIG3 , the driving unit 102 further includes a connection pattern 1023 located between the substrate n1 and the barrier layer n2. At least a portion of the connection electrode 103 is located within the substrate n1. A connection via 1032 is exposed on the side of the substrate n1 near the driving circuit 1022. A portion of the connection pattern 1023 is located within the connection via and electrically connected to the connection electrode 103. Another portion of the connection pattern 1023 is located on the side of the substrate n1 near the driving circuit 102.

[0190] The first transfer pattern n72 is electrically connected to the connection pattern 1023 via a via hole that passes through the first insulating layer n6, the first buffer layer n4, and the barrier layer n2. That is, the first interconnection pattern n93 can be connected to the connection pattern 1023 via the first transfer pattern n72, and the connection pattern 1023 is in turn connected to the connection electrode 103. Thus, the driving backplane included in the display panel can sequentially provide driving signals to the first interconnection pattern n93 via the connection electrode 103, the connection pattern 1023, and the first transfer pattern n72.

[0191] Optionally, the first transfer pattern n72 and the first top gate n71 can be formed using the same mask process. Before forming the first transfer pattern n72 and the first top gate n71, a single mask process can be used to simultaneously form vias that expose the connection pattern 1023 and the first bottom gate n31, and then the first transfer pattern n72 and the first top gate n71 are formed.

[0192] As can be seen in Figure 3, the first transfer pattern n72 located on the second metal layer n7 requires vias passing through more film layers than the first top gate n71 located on the second metal layer n7 to connect to the connection pattern 1023. Therefore, during the etching process to form the vias exposing the connection pattern 1023 and the first bottom gate n31, even after the first bottom gate n31 has been exposed, the connection pattern 1023 is still not exposed. In this case, further etching is required until the connection pattern 1023 is exposed. During this stage, the first bottom gate n31 will suffer some etching damage.

[0193] Therefore, the thickness of the first metal layer n3 where the first bottom gate n31 is located can be set to be thicker to reduce the impact of etching damage. For example, the thickness of the first metal layer n3 ranges from 20nm (nanometers) to 200nm. Optionally, the thickness of the first metal layer n3 can be greater than or equal to 50nm, for example, the thickness of the first metal layer n3 can be 100nm. In addition, the material of the first metal layer n3 can be molybdenum (Mo).

[0194] It should be noted that the thickness of the first metal layer n3 should not be set too large, because too large a thickness of the first metal layer n3 will affect the flatness of the first active layer n5, which may further lead to a poor crystallization effect of excimer laser annealing.

[0195] In a first possible scenario, the oxide thin film transistor is a single-gate transistor. The oxide thin film transistor includes a gate, a second source electrode n94, and a second drain electrode n95. Referring to FIG4 , the driving unit 102 further includes: a fourth metal layer n10 located between the second insulating layer n8 and the third metal layer n9, a third insulating layer n11, a second active layer n12, and a fourth insulating layer n13.

[0196] Optionally, the fourth metal layer n10 includes a gate n101, the second active layer n12 includes a second active pattern n121, and an orthographic projection of the second active pattern n121 on the substrate n1 partially overlaps with an orthographic projection of the gate n121 on the substrate n1.

[0197] Optionally, the third metal layer n9 further includes a second source n94 and a second drain n95, the second source n94 is electrically connected to the source region of the second active pattern n121 through a via passing through the fourth insulating layer n13, and the second drain n95 is electrically connected to the drain region of the second active pattern n121 through a via passing through the fourth insulating layer n13.

[0198] As a second possible scenario, the oxide thin film transistor is a single-gate transistor. The oxide thin film transistor includes a gate, a second source electrode n94, and a second drain electrode n95. Referring to Figure 5, the driving unit 102 also includes: a fourth metal layer n10 located between the second insulating layer n8 and the third metal layer n9, a third insulating layer n11, a second active layer n12, a fourth insulating layer n13, a fifth metal layer n14, and a fifth insulating layer n15.

[0199] Optionally, the fourth metal layer n10 or the fifth metal layer n14 includes a gate ( FIG5 takes the fifth metal layer n14 including the gate n141 as an example), the second active layer n12 includes a second active pattern n121, and the orthographic projection of the second active pattern n121 on the substrate n1 partially overlaps with the orthographic projection of the gate on the substrate n1. In other words, the gate can be located in either the fourth metal layer n10 or the fifth metal layer n14.

[0200] Optionally, the third metal layer n9 further includes a second source electrode n94 and a second drain electrode n95. The second source electrode n94 is electrically connected to the source region of the second active pattern n121 via a via passing through the fifth insulating layer n15 and the fourth insulating layer n13. The second drain electrode n95 is electrically connected to the drain region of the second active pattern n121 via a via passing through the fifth insulating layer n15 and the fourth insulating layer n13.

[0201] As a third possible scenario, the oxide thin film transistor is a dual-gate transistor. The oxide thin film transistor includes a second bottom gate n102, a second top gate n142, a second source n94, and a second drain n95. Referring to Figure 6, the driving unit 102 also includes: a fourth metal layer n10 located between the second insulating layer n8 and the third metal layer n9, a third insulating layer n11, a second active layer n12, a fourth insulating layer n13, a fifth metal layer n14, and a fifth insulating layer n15.

[0202] Optionally, the fourth metal layer n10 includes a second bottom gate n102, and the fifth metal layer n14 includes a second top gate n142. The second active layer n12 includes a second active pattern n121, and the second active pattern n121 is located between the second bottom gate n102 and the second top gate n142.

[0203] Optionally, the third metal layer n9 further includes a third interconnection pattern n96. The third interconnection pattern n96 is electrically connected to the second top gate n142 through a via hole passing through the fifth insulating layer n15 and the fourth insulating layer n13, and the third interconnection pattern n96 is electrically connected to the second bottom gate n102 through a via hole passing through the fifth insulating layer n15, the fourth insulating layer n13, and the third insulating layer n11.

[0204] Optionally, the third metal layer n9 further includes a second source electrode n94 and a second drain electrode n95. The second source electrode n94 is electrically connected to the source region of the second active pattern n121 through a via hole passing through the second insulating layer n8 and the fourth insulating layer n13, and the second drain electrode n95 is electrically connected to the drain region of the second active pattern n121 through a via hole passing through the second insulating layer n8 and the fourth insulating layer n13.

[0205] In the embodiment of the present application, the first metal layer n3 is a light shielding layer (LS), the first active layer n5 is a low-temperature polycrystalline silicon semiconductor layer (poly), the first insulating layer n6 is a first gate insulator (GI1), the second metal layer n7 is a first gate layer (gate1), the second insulating layer n8 is a second gate insulating layer (GI2), and the fourth metal layer n10 is a second gate layer (gate2). The third insulating layer n11 includes a first inter-level dielectric layer (ILD) and a second buffer layer (buffer2). The second active layer n12 is an oxide semiconductor layer (IGZO), the fourth insulating layer n13 is a third gate insulating layer (GI3), the fifth metal layer n14 is a third gate layer (gate3), the fifth insulating layer n15 is a second inter-level dielectric layer (ILD2), and the third metal layer n9 is a source and drain layer (SD).

[0206] Optionally, in the schemes shown in Figures 3 to 6, the light shielding layer can be used for light shielding, or it can be reused as the first bottom gate n31 of the low-temperature polysilicon thin-film transistor. The first transfer pattern n72 and the first top gate n71 of the low-temperature polysilicon thin-film transistor are located in the first gate layer. The first transfer pattern n72 is electrically connected to the connection pattern 1023 through a via passing through the first gate insulating layer, the first buffer layer n4, and the barrier layer n2. The first top gate n71 is electrically connected to the first bottom gate n31 located in the light shielding layer through a via passing through the first gate insulating layer and the first buffer layer n4.

[0207] Optionally, the pixel driving circuit of the driving circuit 1022 includes a first type of thin film transistor. The first type of thin film transistor may be a dual-gate transistor, comprising a first bottom gate n31, a first top gate n71, a first source n91, and a first drain n92. Among the plurality of thin film transistors, at least one low-temperature polysilicon thin film transistor is a first type of thin film transistor, that is, at least one low-temperature polysilicon thin film transistor is a dual-gate transistor.

[0208] As another optional implementation, referring to Figure 7, the driving unit 102 includes: a substrate n1, a barrier layer n2, a first metal layer n3, a first buffer layer n4, a first active layer n5, a first insulating layer n6, a second metal layer n7, a second insulating layer n8, a fourth metal layer n10, a third insulating layer n11 and a third metal layer n9 stacked in sequence.

[0209] Optionally, the first metal layer n3 includes a first bottom gate n31, and the second metal layer n7 includes a first top gate n71. The first active layer n5 includes a first active pattern n51, which is located between the first bottom gate n31 and the first top gate n71. The fourth metal layer n10 includes a second interconnect pattern n103. The second interconnect pattern n103 is electrically connected to the first top gate n71 via a via passing through the second insulating layer n8. The second interconnect pattern n103 is also electrically connected to the first bottom gate n31 via a via passing through the first insulating layer n6, the second insulating layer n8, and the first buffer layer n4. In other words, the first bottom gate n31 and the first top gate n71 are indirectly connected via the second interconnect pattern n103.

[0210] Optionally, the fourth metal layer n10 further includes a second switching pattern n104. The second switching pattern n104 is electrically connected to the connection electrode through a via hole passing through the first insulating layer n6, the second insulating layer n8, the first buffer layer n4, and the barrier layer n2.

[0211] Optionally, the third metal layer n9 includes a first source electrode n91 and a first drain electrode n92. The first source electrode n91 is electrically connected to the source region of the first active pattern n51 via a via that passes through the third insulating layer n11, the second insulating layer n8, and the first insulating layer n6. The first drain electrode n92 is electrically connected to the drain region of the first active pattern n51 via a via that passes through the third insulating layer n11, the second insulating layer n8, and the first insulating layer n6.

[0212] In the embodiment of the present application, referring to FIG7 , the driving unit 102 further includes a connection pattern 1023 located between the substrate n1 and the barrier layer n2. The connection electrode 103 is located within the substrate n1. The side of the substrate n1 closest to the driving circuit has a connection via that exposes a connection pad 1032. A portion of the connection pattern 1023 is located within the connection via and is electrically connected to the connection electrode 103. Another portion of the connection pattern 1023 is located on the side of the substrate n1 closest to the driving circuit.

[0213] The second transfer pattern n104 is electrically connected to the connection pattern 1023 via a via that passes through the second insulating layer n8, the first insulating layer n6, the first buffer layer n4, and the barrier layer n2. In other words, the first interconnection pattern n93 can be connected to the connection pattern 1023 via the second transfer pattern n104, and the connection pattern 1023 is in turn connected to the connection electrode. Thus, the drive backplane included in the display panel can sequentially provide drive signals to the first interconnection pattern n93 via the connection electrode 103, the connection pattern 1023, and the second transfer pattern n104.

[0214] Optionally, the second transfer pattern n104 can be formed using a different masking process than the first top gate n71 of the low-temperature polysilicon thin-film transistor. To avoid the need for an additional masking process during the formation of the first insulating layer n6 to form a via in the first insulating layer n6 and the first buffer layer n4 to expose the first bottom gate n31, the first bottom gate n31 and the second top gate n142 can be indirectly connected via the second interconnection pattern n103 located on the fourth metal layer n10.

[0215] Optionally, when the second interconnect pattern n103 located on the fourth metal layer n10 is used to connect the first top gate n71 and the first bottom gate n31, a masking process can be used to form a via hole exposing the connection pattern 1023, a via hole exposing the first top gate n71, and a via hole exposing the first bottom gate n31 after the second insulating layer n8. The second interconnect pattern n103 and the second transfer pattern n104 are then formed when the fourth metal layer n10 is prepared.

[0216] As shown in Figure 7, the second transfer pattern n104 located on the fourth metal layer n10 requires vias passing through more film layers to connect to the connection pattern 1023, compared to the vias located on the second interconnect pattern n103. Therefore, when etching the vias that expose the connection pattern 1023 and the first bottom gate n31, even after the first bottom gate n31 has been exposed, the connection pattern 1023 is still not exposed. Further etching is required until the connection pattern 1023 is exposed, and at this stage, the first bottom gate n31 will suffer some etching damage.

[0217] Therefore, the thickness of the first metal layer n3 where the first bottom gate n31 is located can be set to be thicker to reduce the impact of etching damage. For example, the thickness of the first metal layer n3 ranges from 20nm (nanometers) to 200nm. Optionally, the thickness of the first metal layer n3 can be greater than or equal to 50nm, for example, the thickness of the first metal layer n3 can be 100nm. In addition, the material of the first metal layer n3 can be molybdenum (Mo).

[0218] It should be noted that the thickness of the first metal layer n3 should not be set too large, because too large a thickness of the first metal layer n3 will affect the flatness of the first active layer n5, which may further lead to a poor crystallization effect of excimer laser annealing.

[0219] As a first possible scenario, the oxide thin film transistor is a single-gate transistor. The oxide thin film transistor includes a gate, a second source electrode n94, and a second drain electrode n95. Referring to FIG8 , the driving unit 102 further includes a second active layer n12 and a fourth insulating layer n13 located between the third insulating layer n11 and the third metal layer n9.

[0220] Optionally, the fourth metal layer n10 includes a gate electrode, the second active layer n12 includes a second active pattern n121 , and an orthographic projection of the second active pattern n121 on the substrate n1 partially overlaps with a second orthographic projection of the gate electrode on the substrate n1 .

[0221] Optionally, the third metal layer n9 further includes a second source electrode n94 and a second drain electrode n95. The second source electrode n94 is electrically connected to the source region of the second active pattern n121 through a via hole passing through the fourth insulating layer n13, and the second drain electrode n95 is electrically connected to the drain region of the second active pattern n121 through a via hole passing through the fourth insulating layer n13.

[0222] Optionally, the fourth metal layer n10 includes a gate electrode, the second active layer n12 includes a second active pattern n121 , and an orthographic projection of the second active pattern n121 on the substrate n1 partially overlaps with an orthographic projection of the gate electrode on the substrate n1 .

[0223] Optionally, the third metal layer n9 further includes a second source electrode n94 and a second drain electrode n95. The second source electrode n94 is electrically connected to the source region of the second active pattern n121 through a via hole passing through the second insulating layer n8, and the second drain electrode n95 is electrically connected to the drain region of the second active pattern n121 through a via hole passing through the second insulating layer n8.

[0224] As a second possible scenario, the oxide thin film transistor is a single-gate transistor. The oxide thin film transistor includes a gate, a second source electrode n94, and a second drain electrode n95. Referring to Figure 9, the driving unit also includes: a second active layer n12 located between the third insulating layer n11 and the third metal layer n9, a fourth insulating layer n13, a fifth metal layer n14, and a fifth insulating layer n15.

[0225] Optionally, the fourth metal layer n10 or the fifth metal layer n14 includes a gate ( FIG9 takes the fifth metal layer n14 including the gate n141 as an example), and the second active layer n12 includes a second active pattern n121. The orthographic projection of the second active pattern n121 on the substrate n1 partially overlaps with the orthographic projection of the gate on the substrate n1. In other words, the gate can be located in either the fourth metal layer n10 or the fifth metal layer n14.

[0226] Optionally, the third metal layer n9 further includes a second source electrode n94 and a second drain electrode n95. The second source electrode n94 is electrically connected to the source region of the second active pattern n121 through a via hole passing through the fifth insulating layer n15 and the fourth insulating layer n13, and the second drain electrode n95 is electrically connected to the drain region of the second active pattern n121 through a via hole passing through the fifth insulating layer n15 and the fourth insulating layer n13.

[0227] As a third possible scenario, the oxide thin film transistor is a dual-gate transistor. The oxide thin film transistor includes a second bottom gate n102, a second top gate n142, a second source n94, and a second drain n95. Referring to FIG10 , the driving unit 102 further includes: a second active layer n12, a fourth insulating layer n13, a fifth metal layer n14, and a fifth insulating layer n15, located between the third insulating layer n11 and the third metal layer n9.

[0228] Optionally, the fourth metal layer n10 includes a second bottom gate n102, and the fifth metal layer n14 includes a second top gate n142. The second active layer n12 includes a second active pattern n121, and the second active pattern n121 is located between the second bottom gate n102 and the second top gate n142.

[0229] Optionally, the third metal layer n9 further includes a third interconnection pattern n96. The third interconnection pattern n96 is electrically connected to the second top gate n142 through a via hole passing through the fifth insulating layer n15 and the fourth insulating layer n13, and the third interconnection pattern n96 is electrically connected to the second bottom gate n102 through a via hole passing through the fifth insulating layer n15, the fourth insulating layer n13, and the third insulating layer n11.

[0230] Optionally, the third metal layer n9 further includes a second source electrode n94 and a second drain electrode n95. The second source electrode n94 is electrically connected to the source region of the second active pattern n121 through a via hole passing through the second insulating layer n8 and the fourth insulating layer n13, and the second drain electrode n95 is electrically connected to the drain region of the second active pattern n121 through a via hole passing through the second insulating layer n8 and the fourth insulating layer n13.

[0231] In the embodiment of the present application, the first metal layer n3 is a light shielding layer, the first active layer n5 is a low-temperature polycrystalline silicon semiconductor layer, the first insulating layer n6 is a first gate insulating layer, the second metal layer n7 is a first gate layer, the second insulating layer n8 is a second gate insulating layer, and the fourth metal layer n10 is a second gate layer. The third insulating layer n11 includes a first interlayer dielectric layer and a second buffer layer, the second active layer n12 is an oxide semiconductor layer, the fourth insulating layer n13 is a third gate insulating layer, the fifth metal layer n14 is a third gate layer, the fifth insulating layer n15 is a second interlayer dielectric layer, and the third metal layer n9 is a source and drain layer.

[0232] Optionally, in the schemes shown in Figures 7 to 10, the light-shielding layer can be used for light shielding, or it can be reused as the first bottom gate n31 of the low-temperature polycrystalline silicon thin-film transistor. The second transfer pattern n104 and the second interconnection pattern n103 are located in the second gate layer. The second transfer pattern n104 is electrically connected to the connection pattern 1023 through a via passing through the second gate insulating layer, the first gate insulating layer, the first buffer layer n4, and the barrier layer n2. The second interconnection pattern n103 is electrically connected to the first top gate n71 located in the first gate layer through a via passing through the second gate insulating layer, and is electrically connected to the first bottom gate n31 located in the light-shielding layer through a via passing through the second gate insulating layer, the first gate insulating layer, and the first buffer layer n4.

[0233] In the embodiment of the present application, referring to FIG. 11 and FIG. 12 , the driving unit 102 further includes: an organic film layer n16 located on a side of the third metal layer n9 away from the substrate n1 , a first inorganic film layer n17 , and a second inorganic film layer n18 .

[0234] The organic film layer n16 has a first electrode connection hole K1 having a hole sidewall and a hole bottom. The first electrode connection hole K1 is used to expose at least part of the pattern in the source and drain electrode layer.

[0235] The first inorganic film layer n17 has a second electrode connection hole K2. The orthographic projection of the second electrode connection hole K2 on the substrate n1 is located within the orthographic projection of the first electrode connection hole K1 on the substrate n1. The first inorganic film layer n17 covers the sidewalls of the hole and exposes the bottom of the hole, thereby exposing at least a portion of the pattern in the source and drain layer exposed at the bottom of the hole.

[0236] The driving electrodes of the driving unit 102 (such as the first driving electrode 10211 and the second driving electrode 10212) are located between the first inorganic film layer n17 and the second inorganic film layer n18, and the driving electrode 1021 is connected to the pattern in the source and drain layer through the second connection hole K2 and the first electrode connection hole K1.

[0237] 11 and 12 , the second inorganic film layer n18 has a via hole exposing the driving electrode 1021 , and the light emitting unit electrode 1011 is electrically connected to the driving electrode 1021 through the via hole of the second inorganic film layer n18 .

[0238] Referring to Figures 11 and 12 , the first drive electrode 10211 is connected to the thin film transistor via the second electrode connection hole K2 and the first electrode connection hole K1. The source and drain layer further includes a target pattern n97 for transmitting a second signal. The second drive electrode is connected to the target pattern n97 via the second electrode connection hole K2 and the first electrode connection hole K1. The target pattern n97 may also be connected to a connection electrode (not shown).

[0239] Optionally, the orthographic projection of the via hole in the second inorganic film layer n18 on the substrate n1 is located within the orthographic projection of the driving electrode 1021 on the substrate n1 , and the second inorganic film layer n18 wraps the edge of the driving electrode 1021 .

[0240] Since the sidewalls of the driving electrode 1021 are easily oxidized, the oxidized driving electrode 1021 may fall off, which may affect the yield of the light-emitting component 100. Therefore, wrapping the edge of the driving electrode 1021 with the second inorganic film layer n18 can prevent the sidewalls of the driving electrode 1021 from being oxidized.

[0241] In the embodiment of the present application, the organic film layer n16 can be a planarization layer (PLN), the first inorganic film layer n17 can be a first passivation layer (PVX1), and the second inorganic film layer n18 can be a second passivation layer (PVX2). Referring to Figures 3 to 12 , it can be seen that the drive unit 102 also includes a third passivation layer n19 (PVX3) located between the substrate n1 and the connection pattern 1023. The third passivation layer n19 has a via that exposes the connection pad 1032. The connection pattern 1023 is electrically connected to the connection pad 1032 through the via in the third passivation layer n19.

[0242] In the embodiments of the present application, Figures 3 to 12 are not intended to represent actual schematic diagrams of a cross section of a light-emitting assembly, but are only intended to illustrate the stacking and connection relationships of the film layers. For example, the pattern on the right side of Figures 3 to 12 is used to indicate the electrical connection between the first bottom gate and the first top gate, and the first bottom gate and first top gate shown on the right side may be the first bottom gate and first top gate of the low-temperature polycrystalline silicon thin-film transistor shown on the left side.

[0243] In the embodiment of the present application, for the thin film transistors (which may be low-temperature polysilicon thin film transistors or oxide thin film transistors) included in the pixel driving circuit and which need to be directly electrically connected to the connection pattern 1023, the source electrode of the thin film transistor can be integrally formed with the first interconnection pattern n93. In other words, the source electrode of the thin film transistor can directly obtain the driving signal through the connection pattern 1023.

[0244] In the embodiment of the present application, the thickness of substrate n1 can range from 3 μm (micrometers) to 10 μm, for example, 5 μm. If the thickness of substrate n1 is set to be thin (for example, less than 3 μm), the film uniformity of substrate n1 will be poor, and the support capacity for other film layers formed subsequently will be insufficient. If the thickness of substrate n1 is set to be thick (for example, greater than 10 μm), the etching time when forming the via hole exposing the connection pad 1032 will be too long, and the etching deviation will be large, which is not conducive to the layout.

[0245] For example, the substrate n1 is a flexible substrate.

[0246] For example, the material of the substrate n1 is polyimide.

[0247] Optionally, there are generally two schemes for etching the substrate n1 to form a via hole exposing the connection pad 1032. In the first scheme, referring to FIG13 , a via hole is etched before forming the third passivation layer n19. Then, the third passivation layer n19 is formed (the third passivation layer has a via hole exposing the connection pad 1032). Then, the connection pattern 1023 is formed to electrically connect the connection pattern 1023 and the connection pad 1032.

[0248] In this case, the bottom dimension h1 of the via formed in substrate n1, which exposes the connection pad 1032, is smaller than the top dimension h2 of the via, which may cause the via to occupy a larger space. Furthermore, to ensure the reliability of the placement of the transistor above, the via needs to be avoided (i.e., the projections of the transistor and the via do not overlap), which may affect the layout of the board.

[0249] The second solution, referring to FIG14 , after forming the via hole of the third passivation layer n19 , the third passivation layer n19 is used as a hard mask to etch the via hole of the underlying substrate n1 , and then a connection pattern 1023 is formed to electrically connect the connection pattern 1023 and the connection pad 1032 .

[0250] In this case, the bottom size of the via formed in substrate n1, exposing the connection pad 1032, can be roughly equal to the top size of the via. However, this may create a sharp corner at the via in the third passivation layer n19, potentially causing a risk of overlap fracture in the subsequent connection pattern 1023. However, this solution can reduce the space occupied by the via, facilitating layout.

[0251] In the embodiments of the present application, one of the above two solutions can be selected based on the specific size design of the product. For example, if the focus is on reducing the size of the light-emitting component, the second solution can be selected, or if the focus is on ensuring the reliability of the connection pattern 1023, the first solution can be selected.

[0252] In the embodiment of the present application, the material of the planar layer (organic film layer n16) can be an organic material, and the materials of the third passivation layer (PVX3), the barrier layer (barrier) n2, the first buffer layer (buffer1) n4, the first gate insulating layer (GI1), the second gate insulating layer (GI2), the first interlayer dielectric layer (ILD1), the second buffer layer (buffer2), the third gate insulating layer (GI3), the second interlayer dielectric layer (ILD2), the first passivation layer (PVX1), and the second passivation layer (PVX2) can all be inorganic materials. Accordingly, the planar layer can be referred to as the organic film layer n16, the first passivation layer, the barrier layer n2, the first buffer layer n4, the first gate insulating layer, the second gate insulating layer, the first interlayer dielectric layer, the second buffer layer, the third gate insulating layer, the second interlayer dielectric layer, the first passivation layer, and the second passivation layer can all be referred to as inorganic film layers.

[0253] In the embodiment of the present application, it is necessary to control the thickness of each inorganic film layer in the driving circuit 1022 to avoid excessive stress caused by the total thickness of the inorganic film layers being too large. Optionally, the third passivation layer can be a single layer or a stack of silicon oxide (SiO2) and silicon nitride (SiNx). The thickness of the third passivation layer can range from 100nm to 300nm. For example, the material of the third passivation layer can be silicon oxide, and its thickness can be 100nm.

[0254] If the third passivation layer is too thin, the uniformity of its formation may be affected (for example, leakage may occur). If the third passivation layer is too thick, the stress in the third passivation layer may be too high, and subsequent film preparation processes may gradually accumulate stress, which may easily cause deformation of the substrate n1.

[0255] Optionally, the material of the connection pattern 1023 can be molybdenum (Mo), titanium (Ti), aluminum (Al) or other metals or a combination thereof. For example, the material of the connection pattern 1023 can be Mo, and its thickness can be 220 nm.

[0256] Alternatively, the connection pattern 1023 can be fabricated using either a dry or wet etching process. Wet etching can avoid damage to the underlying film layer, but the control of deviation and uniformity are slightly worse than with dry etching. This embodiment of the present application only requires ensuring good contact and overlap between the connection pattern 1023 and the connection pad 1032, with no broken wires.

[0257] Optionally, the barrier layer n2 can be a single layer or a stack of silicon oxide (SiO2) and silicon nitride (SiNx). The thickness of the barrier layer n2 can range from 50nm to 600nm. The barrier layer n2 serves as a boundary layer between the via in the substrate n1 and the film layer of the upper drive circuit 1022. Its function is to block impurities in the substrate n1 and ensure the characteristics of the devices in the upper drive circuit 1022. For example, the material of the barrier layer n2 can be silicon oxide, and its thickness can be 400nm. The thickness of the barrier layer n2 is selected to be 400nm mainly because this thickness can fully isolate the impurities in the substrate n1.

[0258] Optionally, the first buffer layer n4 typically employs a stacked structure of SiNx and SiO2. The SiNx serves to block impurities in the underlying film layer, while the SiO2 serves as a buffer and thermal insulation layer during ELA crystallization of the low-temperature polycrystalline silicon semiconductor layer n5. The thickness of the SiNx layer ranges from 50 nm to 100 nm, and the thickness of the SiO2 layer is greater than or equal to 120 nm. For example, the thickness of the SiNx layer can be 50 nm, and the thickness of the SiO2 layer can be 300 nm.

[0259] In the embodiment of the present application, due to the presence of the barrier layer n2 and the first buffer layer n4, when etching to form via holes exposing the first bottom gate and via holes exposing the connection pattern, the first bottom gate may be damaged by dry etching.

[0260] Optionally, the thickness of the low-temperature polysilicon semiconductor layer ranges from 40 nm to 55 nm, for example, may be 47 nm.

[0261] Optionally, the first gate insulating layer may be a stacked structure of SiO2 and SiNx, wherein the thickness of SiO2 may be 80 nm and the thickness of SiNx may be 40 nm.

[0262] Optionally, the material of the first gate layer can be molybdenum (Mo), and its thickness can range from 100nm to 600nm, for example, 330nm. Among them, the appropriate thickness can be selected according to the resistivity requirements of the product. If the resistance is required to be reduced, the thickness of the first gate layer can be appropriately thickened. If the resistance requirement is relatively small, the thickness of the first gate layer can be designed to be thinner, as long as the first transfer pattern n72 located on the first gate layer n7 can be overlapped to the connection pattern 1023 without disconnection.

[0263] Optionally, the material of the second gate insulating layer may be SiNx, and the thickness thereof may be 140 nm.

[0264] Optionally, the material of the second gate layer may be molybdenum (Mo), and the thickness thereof may be 330 nm.

[0265] Optionally, the first interlayer dielectric layer may be a single layer or a stack of silicon oxide (SiO2) and silicon nitride (SiNx). If a single layer is used, the thickness of the single layer may range from 50 nm to 500 nm. If a double layer is used, the thickness of each double layer may range from 50 nm to 500 nm. For example, the first interlayer dielectric layer may be a single layer of SiNx, and its thickness may be 100 nm.

[0266] If the thickness of the first interlayer dielectric layer is set too thick, it will cause very high stress in the entire light-emitting component. If the thickness of the first interlayer dielectric layer is set too thin, it will affect the effect of the first interlayer dielectric layer on hydrogen replenishment of the low-temperature polycrystalline silicon semiconductor layer, resulting in insufficient hydrogen content in the low-temperature polycrystalline silicon semiconductor layer, affecting device characteristics.

[0267] Optionally, the second buffer layer may be made of SiO2 and may be 300 nm thick. If the second buffer layer is too thin, the oxide semiconductor layer may be more sensitive to the second gate layer. If the second buffer layer is too thick, stress problems may occur.

[0268] Optionally, the thickness of the oxide semiconductor layer ranges from 20 nm to 70 nm, for example, may be 25 nm.

[0269] Optionally, the material of the third gate insulating layer may be SiO 2 , and the thickness thereof may be 140 nm.

[0270] Optionally, the material of the third gate layer may be molybdenum (Mo), or the third gate layer may be a stacked structure of titanium nitride (TiN) and molybdenum (Mo). For example, the third gate layer may be a stacked structure of titanium nitride (TiN) and molybdenum (Mo), with the thickness of TiN being 30 nm and the thickness of Mo being 250 nm.

[0271] Optionally, the second interlayer dielectric layer may be a single layer or a stack of silicon oxide (SiO2) and silicon nitride (SiNx). For example, the second interlayer dielectric layer may be a stack of SiO2 and SiNx (SiO2 being closer to the oxide semiconductor layer n12), and the thickness of the second interlayer dielectric layer may be in a range of 100 nm to 600 nm.

[0272] When forming the second interlayer dielectric layer, a mask process is required to form multiple vias, including vias for overlapping interconnect patterns and vias for overlapping source and drain electrodes. The deepest vias are etched into the low-temperature polysilicon semiconductor layer.

[0273] Optionally, the source and drain electrode layers may be made of a triple-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), wherein the thickness of the titanium layer may be 50 nm, and the thickness of the aluminum layer may be 650 nm.

[0274] Optionally, the function of the planarization layer is planarization, and the thickness of the planarization layer may be greater than or equal to 2 μm, for example, 2 μm.

[0275] Optionally, the first passivation layer may be a single layer or a stacked layer of silicon oxide (SiO2) and silicon nitride (SiNx). For example, the material of the first passivation layer is SiNx, and its thickness may be 100 nm.

[0276] Optionally, the vias in the third passivation layer and the vias in the planar layer can be formed in stages. That is, after forming the vias in the planar layer, the first passivation film is formed and then etched to form the vias in the first passivation layer. This allows the first passivation layer to wrap around the sidewalls of the vias in the planar layer, preventing the planar layer from absorbing the level and affecting product reliability. The size of the vias in the first passivation layer is smaller than that of the vias in the planar layer.

[0277] Optionally, the material of the first drive electrode 10211 and the second drive electrode 10212 may include copper (Cu). Since copper has a certain diffusivity, a molybdenum nickel titanium (MTD) layer may be provided below the Cu layer to prevent copper from diffusing downward. The thickness of the molybdenum nickel titanium layer may be 30 nm, and the thickness of the Cu layer may be 1800 nm.

[0278] Alternatively, the sidewalls of the Cu layer may oxidize, and the Cu layer may easily fall off after corrosion. Therefore, a second passivation layer may be provided to protect the Cu layer in the drive electrode. The thickness of the second passivation layer ranges from 50 nm to 300 nm. The second passivation layer may be a single layer of SiO2 and SiNx. For example, the second passivation layer may be a single layer of SiNx, and its thickness may be 200 nm.

[0279] In the embodiment of the present application, referring to FIG. 1 , the light emitting assembly 100 further includes a first substrate 104 located on a side of the light emitting unit 101 away from the driving unit 102 .

[0280] 15 , the orthographic projection of the driving electrode 1021 on the first substrate 104 and the orthographic projection of the connection electrode 103 on the first substrate 104 do not overlap.

[0281] Optionally, the light-emitting component 100 may include nine connecting electrodes 103, which may be evenly arranged in an array of three rows and three columns. Each connecting electrode 103 may be configured to receive a drive signal from the driver backplane and transmit it to the pixel driving circuit in the driving circuit 1022 to control the light-emitting unit 101 to emit light. In other embodiments, the light-emitting component 100 may include a greater or fewer number of connecting electrodes 103, which is not limited in this embodiment of the present application.

[0282] In the embodiment of the present application, referring to FIG16 , the light-emitting assembly 1400 further includes a dam structure 105 located between the light-emitting portion 1012 and the driving circuit 1022. Referring to FIG16 and FIG17 , the dam structure 105 is annular and surrounds the light-emitting unit electrode 1011 and the driving electrode 1021. The provision of the dam structure 105 is used to prevent liquid from invading the light-emitting unit electrode 1011 or the driving electrode 1021 during the subsequent formation of the connecting electrode 103, thereby ensuring the yield of the light-emitting unit electrode 1011 and the driving electrode 1021.

[0283] Optionally, the material of the dam structure 105 can be metal. The dam structure 105 can also play an anti-static role to ensure the reliability of the light-emitting component 100. The dam structure 105 can also prevent the expansion of cracks in the light-emitting component, which helps to improve the yield and reliability of the light-emitting component and help to extend the service life of the light-emitting component 100.

[0284] In an embodiment of the present application, referring to Figure 16, the orthographic projection of the dam structure 105 on the substrate n1 may not overlap with the orthographic projection of the connection via on the substrate n1, and the orthographic projection of the dam structure 105 on the substrate n1 may overlap with the orthographic projection of the connection pattern 1023 on the substrate n1.

[0285] Continuing with FIG16 , the substrate n1 of the driving unit has nine connection vias corresponding to the nine connection electrodes 103. The driving unit also includes nine connection patterns 1023 corresponding to the nine connection vias. The orthographic projection of each connection pattern 1023 on substrate n1 overlaps the orthographic projection of a corresponding connection via on substrate n1, and the orthographic projection of the connection pattern 1023 on substrate n1 extends beyond the connection via.

[0286] To simplify the design of the dam structure, referring to FIG16 , the orthographic projection of the dam structure 105 on substrate n1 can partially overlap with the orthographic projection of the connection pattern 1023 on substrate n1. Furthermore, the overlapping position can be located on the side of the connection via corresponding to the connection pattern 1023 near the center of the light-emitting component 100.

[0287] Optionally, the nine connection patterns 1023 may be arranged in three rows and three columns, and the orthographic projections of the other eight connection patterns 1023 except the connection pattern 1023 in the second row and second column on the substrate n1 may partially overlap with the orthographic projection of the dam structure on the substrate n1.

[0288] Of course, referring to FIG. 18 , to ensure a flat surface for the dam structure 105, the orthographic projection of the dam structure 105 on substrate n1 can be designed to not overlap with the orthographic projections of the plurality of connection patterns 1023 on substrate n1. For example, the orthographic projection of the dam structure 105 on substrate n1 can have a relief structure at the positions of eight of the nine connection patterns 1023, except for the one in the second row and second column. This allows the dam structure 105 to be formed into an annular shape as a whole.

[0289] Optionally, the width d of the dam structure 105 is greater than or equal to 0.9 μm and less than or equal to 11 μm. For example, the width of the dam structure 105 can be set to be greater than or equal to 1 μm and less than or equal to 10 μm. The embodiment of the present application does not specifically limit the width of the dam structure 105.

[0290] Referring to Figure 17, the dam structure 105 includes a first dam portion 1051 and a second dam portion 1052, both of which are ring-shaped. The first dam portion 1051 is located on the side of the light-emitting portion 1012 away from the first substrate 104, and is in contact with the light-emitting portion 1012. The second dam portion 1052 is located on the side of the drive circuit 1022 facing the light-emitting unit 101, and is in contact with the drive circuit 1022. The first dam portion 1051 and the second dam portion 1052 cooperate with each other and are bonded to form a closed space surrounding each electrode. The light-emitting unit electrode 1011 and the drive electrode 1021 are both located in the closed space. Therefore, the dam structure 105 not only encapsulates the light-emitting unit electrode 1011 and the drive electrode 1021, but also increases the support area between the light-emitting unit 101 and the drive unit 102.

[0291] Optionally, the first dam portion 1051 and the light emitting unit electrode 1011 can be made of the same material and manufactured through the same patterning process. The second dam portion 1052 and the driving electrode 1021 can be made of the same material and manufactured through the same patterning process.

[0292] In the embodiment of the present application, since organic materials are more likely to absorb water and oxygen than inorganic materials, with reference to Figures 11 and 12, the organic film layer n16 (flat layer) can be designed as an island with the light-emitting component 100 as a unit, to ensure that the organic film layer n16 in the light-emitting component 100 is covered by the inorganic film layer. That is, the orthographic projection of the organic film layer n16 on the substrate n1 is located within the orthographic projection of the inorganic film layer on the substrate n1, and the sidewalls of the organic film layer n16 are wrapped by the inorganic film layer, preventing the organic film layer n16 from being exposed to the outside, thereby preventing external water and oxygen from invading the interior of the light-emitting component 100 along the organic film layer n16, preventing the light-emitting component 100 from failing due to the intrusion of water and oxygen, and ensuring the yield of the light-emitting component 100.

[0293] Since the planarization layer is the organic film layer n16, the location where the organic film layer n16 is disposed in the light-emitting component 100 has a better planarization effect. To ensure the reliability of the dam structure 105, the orthographic projection of the dam structure 105 on the substrate n1 can be positioned within the orthographic projection of the planarization layer on the substrate n1.

[0294] Among them, the orthographic projection of the dam structure 105 on the substrate n1 is located within the orthographic projection of the flat layer on the substrate n1, which may mean that: the orthographic projection of the first dam portion 1051 on the substrate n1 is located within the orthographic projection of the organic film layer n16 on the substrate n1, and the orthographic projection of the second dam portion 1052 on the substrate n1 is located within the orthographic projection of the organic film layer n16 on the substrate n1.

[0295] In the embodiment of the present application, referring to Figures 16 and 18 , each pixel driving circuit PX of the multiple pixel driving circuits included in the driving circuit 1022 is provided corresponding to a first driving electrode 10211. Figures 16 and 18 illustrate the pixel driving circuit PX for the first first driving electrode 10211a, and omit the pixel driving circuits PX corresponding to the second first driving electrode 10211b and the third first driving electrode 10211c. By providing the pixel driving circuit PX in the light-emitting component 100, the structure of the light-emitting component 100 is simplified, reducing the manufacturing complexity of the light-emitting component 100.

[0296] Optionally, the light emitting assembly 100 further includes a multiplexing circuit, and the data signal from the driving backplane can be transmitted to the corresponding data signal line in the light emitting assembly after passing through the multiplexing circuit. By providing the multiplexing circuit, the number of connection electrodes 103 provided in the light emitting assembly 100 can be reduced.

[0297] Referring to Figures 16 and 18 , the light-emitting component 100 also includes a gate drive circuit GOA and a light-emitting drive circuit EOA. Each first drive electrode 10211 can be provided with a corresponding gate drive circuit GOA and a corresponding light-emitting drive circuit EOA. Figures 16 and 18 illustrate the gate drive circuit GOA and light-emitting drive circuit EOA corresponding to the first first drive electrode 10211a, omitting the gate drive circuits GOA and light-emitting drive circuits EOA corresponding to the second first drive electrode 10211b and the third first drive electrode 10211c. By integrating the pixel drive circuit PX, the gate drive circuit GOA, and the light-emitting drive circuit EOA within the light-emitting component 100, the light-emitting component achieves a higher level of integration and simplifies the structural design of the corresponding driver backplane. This reduces the complexity of the design and manufacturing process of the light-emitting component 100, helping to lower production costs and improve production efficiency. Furthermore, the light-emitting component 100 can directly receive input signals from the driver backplane via the connection electrode 103, which helps reduce voltage drop and enhance the display quality of the light-emitting component 100.

[0298] Figure 19 is a schematic diagram of an equivalent circuit of a pixel driving circuit provided in an embodiment of the present application. Optionally, the pixel driving circuit 1022 can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure or other pixel driving circuit, not limited to the pixel driving circuit shown in Figure 10. As shown in Figure 19, the pixel driving circuit may include 10 transistors (first transistor T1 to tenth transistor T10) and 2 capacitors (first capacitor C1 and second capacitor Cst). The pixel driving circuit is connected to 9 signal lines (data signal line Data, first scan signal line Gate_P, second scan signal line Gate_N, luminous signal line EM, initial signal line Vini, reset signal line Rst_N, high frequency signal line HF, first power line VDD and second power line VSS).

[0299] Referring to FIG19 , the pixel driving circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, a fifth node N5, and a sixth node N6. The first node N1 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively. The second node N2 is connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the second capacitor Cst, respectively. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 is connected to the control electrode of the sixth transistor, the second electrode of the eighth transistor T8, and the second electrode of the ninth transistor T9, respectively. The fifth node N5 is connected to the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7, and the first electrode of the light-emitting device, respectively. The sixth node N6 is connected to the second end of the first capacitor C1, the control electrode of the eighth transistor T8, the control electrode of the ninth transistor T9, and the second electrode of the tenth transistor T10, respectively.

[0300] In the embodiment of the present application, a first end of the first capacitor C1 is connected to the initial signal line Vinit. A first end of the second capacitor Cst is connected to the first power line VDD, and a second end of the second capacitor Cst is connected to the second node N2. That is, the second end of the second capacitor Cst is connected to the control electrode of the third transistor T3. The control electrode of the first transistor T1 is connected to the reset signal line Rst_N, the first electrode of the first transistor T1 is connected to the initial signal line Vinit, and the second electrode of the first transistor is connected to the second node N2. The control electrode of the second transistor T2 is connected to the second scan signal line Gate_N, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. The control electrode of the third transistor T3 is connected to the second node N2, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The control electrode of the fourth transistor T4 is connected to the first scan signal line Gate_P, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the first node N1. A control electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, a first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and a second electrode of the fifth transistor T5 is connected to the first node N1. A control electrode of the sixth transistor T6 is connected to the fourth node N4, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fifth node N5, that is, connected to the first electrode of the light-emitting device. A control electrode of the seventh transistor T7 is connected to the reset signal line Rst_N, a first electrode of the seventh transistor T7 is connected to the initial signal line Vinit, and a second electrode of the seventh transistor T7 is connected to the fifth node N5, that is, connected to the first electrode of the light-emitting device. A control electrode of the eighth transistor T8 is connected to the sixth node N6, that is, connected to the second end of the first capacitor C1, a first electrode of the eighth transistor T8 is connected to the high-frequency signal line HF, and a second electrode of the eighth transistor T8 is connected to the fourth node N4. The control electrode of the ninth transistor T9 is connected to the sixth node N6, that is, to the second end of the first capacitor C1. The first electrode of the ninth transistor T9 is connected to the light emitting signal line EM, and the second electrode of the ninth transistor T9 is connected to the fourth node N4. The eighth transistor T8 and the ninth transistor T9 can form an inverter for switching between the high-frequency signal and the light emitting signal. The control electrode of the tenth transistor T10 is connected to the reset signal line Rst_N, the first electrode of the tenth transistor T10 is connected to the data signal line Data, and the second electrode of the tenth transistor T10 is connected to the sixth node N6.

[0301] Optionally, the light-emitting unit 101 may be a light-emitting diode (LED). The second electrode of the light-emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously high level signal.

[0302] The first transistor T1 to the tenth transistor T10 can be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the tenth transistor T10 can include P-type transistors and N-type transistors.

[0303] In the embodiment of the present application, the first transistor T1 to the tenth transistor T10 can adopt low-temperature polycrystalline silicon thin film transistors, or can adopt oxide thin film transistors, or can adopt low-temperature polycrystalline silicon thin film transistors and oxide thin film transistors. The active layer of the low-temperature polycrystalline silicon thin film transistor adopts low-temperature polycrystalline silicon (LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). Low-temperature polycrystalline silicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. The low-temperature polycrystalline silicon thin film transistor and the oxide thin film transistor are integrated into a light-emitting component to form a low-temperature polycrystalline oxide (LTPO) light-emitting component. In this way, the advantages of both can be utilized, not only to achieve low-frequency driving, but also to reduce power consumption and improve display quality. For example, the first transistor T1, the second transistor T2, the seventh transistor T7, the ninth transistor T9 and the tenth transistor T10 can be oxide thin film transistors, which can effectively reduce leakage current, achieve low frequency and thus reduce power consumption. The remaining transistors can be low-temperature polycrystalline silicon thin film transistors, which can achieve high mobility and reduce circuit power consumption during the light-emitting process.

[0304] In an embodiment of the present application, the input ends of the signal lines in the pixel driving circuit can all be provided with input signals by the driver backplane. The pixel driving circuit can be a circuit in the light-emitting assembly that directly drives the light-emitting unit to emit light. Specifically, the light-emitting assembly can be used to form a display panel, and each light-emitting assembly can constitute a pixel of the display panel. For example, for a solution in which the light-emitting assembly includes a red light-emitting unit, a green light-emitting unit, and a blue light-emitting unit, each light-emitting assembly can be referred to as a pixel, and each light-emitting unit can be referred to as a sub-pixel.

[0305] Figure 20 is a schematic diagram of an equivalent circuit of a gate drive circuit provided in an embodiment of the present application. In an exemplary embodiment, the gate drive circuit GOA is not limited to the structure shown in Figure 20, and other structures can be adopted as needed, which is not limited by the embodiment of the present application. The gate drive circuit GOA may include 8 transistors (the eleventh transistor T11 to the eighteenth transistor T18) and 2 capacitors (a third capacitor C3 and a fourth capacitor C4). The gate drive circuit GOA is connected to four signal lines (a first clock signal line CK, a second clock signal line CB, a third power line VH, and a fourth power line VL).

[0306] In an embodiment of the present application, the gate drive circuit GOA may include an eleventh node N11, a twelfth node N12, a thirteenth node N13, and a fourteenth node N14. The eleventh node N11 is connected to the second electrode of the eleventh transistor T11, the control electrode of the twelfth transistor T12, the first electrode of the seventeenth transistor T17, and the first electrode of the eighteenth transistor T18, respectively. The twelfth node N12 is connected to the second electrode of the twelfth transistor T12, the second electrode of the thirteenth transistor T13, the control electrode of the fourteenth transistor T14, the control electrode of the sixteenth transistor T16, and the first end of the fourth capacitor C4, respectively. The thirteenth node N13 is connected to the first electrode of the sixteenth transistor T16 and the second electrode of the seventeenth transistor T17, respectively. The fourteenth node N14 is connected to the control electrode of the fifteenth transistor T15, the second electrode of the eighteenth transistor T18, and the first end of the third capacitor C3, respectively.

[0307] In the embodiment of the present application, the second end of the third capacitor C3 is respectively connected to the second electrode of the fourteenth transistor T14, the second electrode of the fifteenth transistor T15, and the output terminal OUTPUT. The second end of the fourth capacitor C4 is connected to the first electrode of the fourteenth transistor T14 and the third power line VH. The control electrode of the eleventh transistor T11 is connected to the first clock signal line CK, and the first electrode of the eleventh transistor T11 is connected to the input terminal INPUT. The first electrode of the twelfth transistor T12 is connected to the first clock signal line CK, the control electrode of the thirteenth transistor T13 is connected to the fourth power line VL, and the first electrode of the thirteenth transistor T13 is connected to the fourth power line VL. The first electrode of the fifteenth transistor T15 is connected to the second clock signal line CB. The first electrode of the sixteenth transistor T16 is connected to the third power line VH. The control electrode of the seventeenth transistor T17 is connected to the second clock signal line CB. The control electrode of the eighteenth transistor T18 is connected to the fourth power line VL.

[0308] In the embodiment of the present application, different first clock signal lines CK can transmit different clock signals, different second clock signal lines CB can transmit different clock signals, the third power line VH can transmit a high level signal, and the fourth power line VL can transmit a low level signal.

[0309] Figure 21 is a schematic diagram of an equivalent circuit of a light-emitting drive circuit provided in an embodiment of the present application. In an exemplary embodiment, the light-emitting drive circuit EOA is not limited to the structure shown in Figure 21, and other structures can be adopted as needed, and the present disclosure is not limited to this. The light-emitting drive circuit EOA may include 12 transistors (the eleventh transistor T11 to the twenty-second transistor T22) and three capacitors (a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5). The light-emitting drive circuit EOA is connected to four signal lines (a first clock signal line CK, a second clock signal line CB, a third power line VH, and a fourth power line VL). The dotted area S1 in Figure 21 is the input subcircuit of the light-emitting drive circuit EOA. This circuit has the same structure as the gate drive circuit GOA shown in Figure 20 and will not be repeated here.

[0310] In an exemplary embodiment, the light emitting driving circuit EOA may further include a fifteenth node N15 connected to the second electrode of the nineteenth transistor T19, the second electrode of the twentieth transistor T20, the first end of the fifth capacitor C5, and the control electrode of the twenty-second transistor T22, respectively.

[0311] In an exemplary embodiment, a second end of the fifth capacitor C5 is connected to the second clock signal line CB. The control electrode of the nineteenth transistor T19 is respectively connected to the control electrode of the twenty-first transistor T21 and the output terminal OUTPUT of the gate drive circuit GOA, and a first electrode of the nineteenth transistor T19 is connected to the third power line VH. The control electrode of the twentieth transistor T20 is connected to the fourth power line VL, and a first electrode of the twentieth transistor T20 is connected to the fourth power line VL. The first electrode of the twenty-first transistor T21 is connected to the third power line VH, and the second electrode of the twenty-first transistor T21 is respectively connected to the second electrode of the twenty-second transistor T22 and the signal output terminal Eout. The first electrode of the twenty-second transistor T22 is connected to the fourth power line VL.

[0312] In the embodiments of the present application, the light-emitting unit 101 may be referred to as a light-emitting diode (LED) chip. The driver unit 102 may be referred to as a driver chip. The light-emitting assembly is formed by bonding an LED chip and a driver chip (chip by chip). The light-emitting assembly 100 may be an active-matrix light-emitting diode (AMLED) chip.

[0313] In the embodiments of the present application, the light-emitting component 100 may also be referred to as a pixel island, the light-emitting unit 101 may also be referred to as a light-emitting device, the driving electrode included in the driving unit 102 may also be referred to as an upper electrode, and the driving circuit included in the driving unit 102 may also be referred to as a circuit structure layer. The connecting electrode 103 may also be referred to as a lower electrode. The dam structure 105 may also be referred to as an anti-static ring.

[0314] In summary, an embodiment of the present application provides a light-emitting component, which includes a light-emitting unit, a driving unit, and a plurality of connecting electrodes. Among them, the plurality of connecting electrodes can be used to receive a driving signal provided by a driving backplane in a display panel, and then the plurality of connecting electrodes can provide a driving signal to the driving unit, so that the driving unit drives the light-emitting unit to emit light. Since the light-emitting components are independently arranged, in the event that some light-emitting components fail to emit light, a new light-emitting component can be directly replaced. Since the structure of the driving backplane in the display panel is relatively simple, even if the driving backplane is damaged when the light-emitting component is replaced, a new driving backplane can be directly prepared using a simpler process, which can avoid abnormal waste of costs while ensuring the yield of the display panel.

[0315] FIG22 is a flow chart of a method for preparing a light-emitting component according to an embodiment of the present application. Referring to FIG22 , the method includes:

[0316] Step S101: obtain a first substrate and a light-emitting unit located on one side of the first substrate.

[0317] In the embodiment of the present application, the light emitting unit 101 includes a light emitting unit electrode 1011 and a light emitting portion 1012 electrically connected to the light emitting unit electrode 1011. The light emitting unit electrode 1011 is located on a side of the light emitting portion 1012 away from the first substrate 104.

[0318] Step S102 : obtaining a second substrate and a driving unit located on one side of the second substrate.

[0319] In the embodiment of the present application, the driving unit 102 includes a driving electrode 1021 and a driving circuit 1022 electrically connected to the driving electrode 1021 . The driving electrode 1021 is located on a side of the driving circuit 1022 away from the second substrate.

[0320] Step S103 : bonding the light emitting unit and the driving unit together through a bonding process, so that the driving electrode and the light emitting unit electrode are electrically connected.

[0321] Optionally, referring to Figure 23, the first light-emitting unit electrode 10111 included in the light-emitting unit electrode 1011 can be electrically connected to the first driving electrode 10211 included in the driving electrode 1021, and the second light-emitting unit electrode 10112 included in the light-emitting unit electrode 1011 can be electrically connected to the second driving electrode 10212 included in the driving electrode 1021.

[0322] Step S104: peeling the second substrate from one side of the driving unit.

[0323] In the embodiment of the present application, referring to FIG24 , a laser liftoff (LLO) process can be used to remove the second substrate. Furthermore, after the second substrate is removed, the plurality of drive units 102 are island-shaped, i.e., there is a gap between any two adjacent drive units 102.

[0324] Optionally, after peeling the second substrate from one side of the driving unit 102, the first substrate 104 can also be thinned (the thickness of the first substrate 104 after thinning is less than the thickness of the first substrate 104 before thinning) so that the total thickness of the light-emitting component finally formed is thinner, which facilitates the realization of a thinner display panel.

[0325] Step S105 : forming a plurality of connecting electrodes on a side of the driving unit away from the light-emitting unit.

[0326] In an embodiment of the present application, referring to FIG. 25 , the entire assembly formed by steps S101 to S104 above can be placed in a specific solution, and a plurality of connection electrodes 103 can be formed on the side of the driving unit 102 away from the light-emitting unit 101 using an electroplating process or a chemical plating process. The plurality of connection electrodes 103 can be connected to the driving unit 102, so that the driving backplane included in the display panel can provide a driving signal to the driving unit 102 through the connection electrodes 103, so that the driving unit 102 can drive the light-emitting unit 101 to emit light. The connection electrodes 103 are connected to the driving circuit 1022 via connection pads 1032 located in the connection vias of the substrate n1 in the driving unit 102.

[0327] In summary, an embodiment of the present application provides a method for preparing a light-emitting component, and the light-emitting component prepared by the method includes a light-emitting unit, a driving unit and a plurality of connecting electrodes. Among them, the plurality of connecting electrodes can be used to receive a driving signal provided by a driving backplane in a display panel, and then the plurality of connecting electrodes can provide a driving signal to the driving unit, so that the driving unit drives the light-emitting unit to emit light. Since the light-emitting components are independently arranged, in the event that some light-emitting components fail to emit light, a new light-emitting component can be directly replaced. Since the structure of the driving backplane in the display panel is relatively simple, even if the driving backplane is damaged when the light-emitting component is replaced, a new driving backplane can be directly prepared using a simpler process, which can avoid abnormal waste of costs while ensuring the yield of the display panel.

[0328] In the embodiment of the present application, a plurality of light-emitting components can be prepared by a single preparation process. The specific content of the above-mentioned step S102 is exemplified by the preparation process of a plurality of light-emitting components. The "patterning process" mentioned in the present disclosure includes, for metal materials, inorganic materials or transparent conductive materials, processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist. For organic materials, it includes processes such as coating organic materials, mask exposure and development. Deposition can be carried out by any one or more of sputtering, evaporation and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in the embodiment of the present application. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process (the patterning process can also be called a masking process) during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the embodiment of the present application means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the substrate. In the embodiment of the present application, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0329] In the embodiment of the present application, the preparation process of multiple light-emitting components is described by taking the first gate layer including the first transfer pattern as an example.

[0330] (1) Referring to FIG. 26 , a de-bonding layer (DBL) material is coated on the entire surface of the second substrate to serve as a sacrificial layer for the dissociation device.

[0331] The release layer (DBL) is a heat-resistant organic polymer introduced externally. Its denaturation under UV light allows for laser dissociation of the device above the DBL from the secondary substrate. The release layer thickness ranges from 30nm to 100nm, ensuring continuous film formation without breakage or leakage.

[0332] (2) Referring to FIG27 , a connection pad film is formed on the side of the release layer away from the second substrate. Then, referring to FIG28 , the connection pad film is patterned to obtain a connection pad 1032 .

[0333] In the embodiment of the present application, the connection pad film can be a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a two-layer structure of aluminum (Al) and titanium (Ti), or a three-layer structure of molybdenum (Mo), aluminum (Al), and molybdenum (Mo), or a two-layer structure of aluminum (Al) and molybdenum (Mo). The thickness of the connection pad film can be determined according to design requirements. It is required that the connection pad 1032 obtained after patterning will not peel on the release layer so that the second substrate can be successfully separated later. The connection pad 1032 is the overlapping metal connecting the upper (connection pattern 1023) and the lower (connection electrode 103).

[0334] For example, the connection pad film may be a double-layer structure of aluminum (Al) and titanium (Ti), the thickness of the Al layer may be 50 nm, and the thickness of the Ti layer may be 650 nm.

[0335] Alternatively, the connection pad film can be a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), wherein the thickness of the titanium layer can be 50 nm, the thickness of the aluminum layer can be 650 nm, and the square resistance of the connection pad 1032 is 0.045 ohms (Ω). The aluminum layer mainly reduces the resistance, and the thickness of the aluminum layer is generally less than or equal to 700 nm.

[0336] Optionally, dry etching is preferred during patterning of the connection pad 1032 to simultaneously remove any excess release layer. This is because the release layer is very thin and the etching gas will etch it away. Of course, even if some release layer material remains, it will not affect subsequent processing.

[0337] (3) Referring to FIG29 , a substrate film is formed by coating. Then, referring to FIG30 , the substrate film is patterned to obtain substrate n1.

[0338] The thickness of the substrate n1 can range from 3 μm (micrometers) to 10 μm, for example, 5 μm. If the thickness of the substrate n1 is set to be thin (for example, less than 3 μm), the film uniformity of the substrate n1 will be poor, and the support capacity for the other film layers of the subsequent formation of the drive circuit 1022 will be insufficient. If the thickness of the substrate n1 is set to be thicker (for example, greater than 10 μm), the etching time will be too long when forming the via g1 exposing the connection pad 1032, and the etching deviation will be large, which is not conducive to the layout. Optionally, the method of etching the via g1 of the substrate n1 to expose the connection pad 1032 can be one of the two methods described in the above embodiment.

[0339] (4) Referring to FIG. 31 , a third passivation film is deposited and patterned to obtain a third passivation layer n19.

[0340] The third passivation layer n19 can be a single layer or a stack of silicon oxide (SiO2) and silicon nitride (SiNx). The thickness of the third passivation layer n19 can range from 100nm to 300nm. For example, the material of the third passivation layer n19 can be silicon oxide, and its thickness can be 100nm.

[0341] If the thickness of the third passivation layer n19 is too thin, the uniformity of the film formation of the third passivation layer n19 may be affected (for example, there may be film leakage). If the thickness of the third passivation layer n19 is too thick, the stress of the third passivation layer n19 will be too high, and the subsequent film preparation process will gradually accumulate stress, which may easily cause deformation of the substrate n1.

[0342] (5) Referring to FIG. 32 , a connection pattern film is formed and patterned to obtain a connection pattern 1023 .

[0343] Optionally, the material of the connection pattern 1023 can be molybdenum (Mo), titanium (Ti), aluminum (Al) or other metals or a combination thereof. For example, the material of the connection pattern 1023 can be Mo, and its thickness can be 220 nm.

[0344] Alternatively, the connection pattern 1023 can be fabricated using either a dry or wet etching process. Wet etching can avoid damage to the underlying film layer, but the deviation control and uniformity are slightly worse than with dry etching. In this embodiment, it is sufficient to ensure that the connection pattern 1023 and the connection pad 1032 are in good contact and overlap, with no breakage.

[0345] (6) Referring to FIG. 33 , a barrier film is formed.

[0346] Optionally, the barrier layer n2 can be a single layer or a stack of silicon oxide (SiO2) and silicon nitride (SiNx). The thickness of the barrier layer n2 can range from 50nm to 600nm. The barrier layer n2 serves as a boundary layer between the via in the substrate n1 and the film layer of the upper drive circuit 1022. Its function is to block impurities in the substrate n1 and ensure the characteristics of the devices in the upper drive circuit 1022. For example, the material of the barrier layer n2 can be silicon oxide, and its thickness can be 400nm. The thickness of the barrier layer n2 is selected to be 400nm mainly because this thickness can fully isolate the impurities in the substrate n1.

[0347] In the embodiments of the present application, experimental verification has shown that when the connection pad 1032 has a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a two-layer structure of aluminum (Al) and titanium (Ti), perfect separation between the connection pad 1032 and the second substrate can be ensured. When the connection pad 1032 has a three-layer structure of molybdenum (Mo), aluminum (Al), and molybdenum (Mo), a small amount of pad material may remain on the second substrate.

[0348] (7) Referring to FIG. 34 , a light-shielding film is formed and patterned to obtain a light-shielding layer n3 .

[0349] Because the light shielding layer n3 will withstand some etching damage in subsequent processes, the thickness of the light shielding layer n3 can be set to be relatively thick, for example, the thickness of the light shielding layer n3 ranges from 30 nm (nanometers) to 100 nm. Optionally, the thickness of the light shielding layer n3 is greater than 50 nm (nanometers), for example, the thickness of the light shielding layer n3 can be 100 nm. In addition, the material of the light shielding layer n3 can be molybdenum (Mo).

[0350] The thickness of the light shielding layer n3 should not be too large. If the thickness of the light shielding layer n3 is too large, the planarity of the low-temperature polysilicon semiconductor layer n5 will be affected, and the crystallization effect of excimer laser annealing may be deteriorated.

[0351] (8) Referring to FIG. 35 , a first buffer film and an amorphous silicon (a-Si) film are formed, and the amorphous silicon film is crystallized and doped. The amorphous silicon film is then patterned to obtain a low-temperature polycrystalline silicon semiconductor layer n5.

[0352] Optionally, the first buffer layer n4 typically employs a stacked structure of SiNx and SiO2. The SiNx serves to block impurities in the underlying film layer, while the SiO2 serves as a buffer and thermal insulation layer during ELA crystallization of the low-temperature polycrystalline silicon semiconductor layer n5. The thickness of the SiNx layer ranges from 50 nm to 100 nm, and the thickness of the SiO2 layer is greater than or equal to 120 nm. For example, the thickness of the SiNx layer can be 50 nm, and the thickness of the SiO2 layer can be 300 nm.

[0353] Optionally, the thickness of the low-temperature polysilicon semiconductor layer n5 ranges from 40 nm to 55 nm, for example, may be 47 nm.

[0354] (9) Referring to FIG. 36 , a first gate insulating layer is formed.

[0355] In the embodiment of the present application, a first gate insulating film can be formed first, and then a masking process can be used to form the via. Optionally, the first gate insulating layer n6 can be a stacked structure of SiO2 and SiNx. The thickness of SiO2 can be 80nm, and the thickness of SiNx can be 40nm.

[0356] Optionally, the vias formed using the masking process can be of two types: one type of via g2 needs to expose the connection pattern 1023, and the other type of via g3 needs to expose the light-shielding pattern of the light-shielding layer n3 (the first bottom gate n31 of the low-temperature polysilicon thin-film transistor). The depth of the via exposing the connection pattern 1023 is greater than the depth of the via exposing the light-shielding pattern, meaning that the light-shielding pattern needs to withstand some over-etching damage.

[0357] (10) Referring to FIG. 37 , a first gate layer n7 is formed.

[0358] Optionally, the material of the first gate layer n7 can be molybdenum (Mo), and its thickness can range from 100 nm to 600 nm, for example, 330 nm. The appropriate thickness can be selected based on the product's resistivity requirements. If lower resistance is required, the thickness of the first gate layer n7 can be appropriately increased. If the resistance requirement is relatively low, the thickness of the first gate layer n7 can be designed to be thinner, as long as the first connection pattern 1023n103 on the first gate layer n7 can overlap the connection pattern 1023 without disconnection.

[0359] Optionally, the first gate layer n7 may include: a first top gate n71 of a low-temperature polysilicon thin film transistor, a transmission pattern n73 for transmitting signals, and a first switching pattern n72.

[0360] The first top gate n71 can be connected to the first bottom gate n31n61 through the via g3 formed in step (9) to expose the first bottom gate n31. The first transfer pattern n72 can be connected to the connection pattern 1023 through the via hole formed in step (9) to expose the connection pattern 1023.

[0361] (11) Referring to FIG. 38 , a second gate insulating film and a second gate layer are deposited and formed.

[0362] Optionally, the material of the second gate insulating film may be SiNx, and the thickness thereof may be 140 nm. The material of the second gate layer may be molybdenum (Mo), and the thickness thereof may be 330 nm.

[0363] When preparing the second gate layer n10 , a second gate thin film may be first deposited and then the second gate thin film may be patterned to obtain the second gate layer n10 .

[0364] (12) Referring to FIG. 39 , a first interlayer dielectric film, a second buffer film, and an oxide semiconductor layer are deposited and formed.

[0365] Optionally, the first interlayer dielectric film may be a single layer or a stack of silicon oxide (SiO2) and silicon nitride (SiNx). If it is a single layer, the thickness of the single layer may range from 100 nm to 500 nm. If it is a double layer, the thickness of each double layer may range from 100 nm to 500 nm. For example, the first interlayer dielectric film may be a single layer of SiNx, and its thickness may be 100 nm.

[0366] If the thickness of the first interlayer dielectric film is set too thick, it will cause very high stress in the entire light-emitting component. If the thickness of the first interlayer dielectric film is set too thin, it will affect the effect of the first interlayer dielectric layer on hydrogen replenishment of the low-temperature polycrystalline silicon semiconductor layer n5, resulting in insufficient hydrogen content in the low-temperature polycrystalline silicon semiconductor layer n5, affecting device characteristics.

[0367] Optionally, the second buffer film may be made of SiO2 and have a thickness of 300 nm. If the second buffer film is too thin, the oxide semiconductor layer n12 may be more sensitive to the second gate layer n10. If the second buffer layer n14 is too thick, stress problems may occur.

[0368] Optionally, the thickness of the oxide semiconductor layer n12 ranges from 20 nm to 70 nm, for example, may be 25 nm.

[0369] When preparing the oxide semiconductor layer n12, an oxide semiconductor thin film may be first deposited and then the oxide semiconductor thin film may be patterned to obtain the oxide semiconductor layer n12.

[0370] (13) Referring to FIG. 40 , a third gate insulating film and a third gate layer n14 are deposited and formed.

[0371] Optionally, the material of the third gate insulating film may be SiO 2 , and the thickness thereof may be 140 nm.

[0372] Optionally, the material of the third gate layer n14 may be molybdenum (Mo), or the third gate layer n14 may be a stacked structure of titanium nitride (TiN) and molybdenum (Mo). For example, the third gate layer n14 may be a stacked structure of titanium nitride (TiN) and molybdenum (Mo), with the thickness of TiN being 30 nm and the thickness of Mo being 250 nm.

[0373] When preparing the third gate layer n14 , a third gate film may be first deposited and then the third gate film may be patterned to obtain the third gate layer n14 .

[0374] (14) A second interlayer dielectric layer n15 is formed.

[0375] In an embodiment of the present application, a second interlayer dielectric film can be formed first, and then a via hole can be formed by two mask processes to obtain a second interlayer dielectric layer n15. The second interlayer dielectric layer n15 can be a single layer or a stack of silicon oxide (SiO2) and silicon nitride (SiNx). For example, the second interlayer dielectric layer n15 adopts a stacked structure of SiO2 and SiNx (SiO2 is closer to the oxide semiconductor layer n12), and the thickness of the second interlayer dielectric layer n15 ranges from 100nm to 600nm.

[0376] Optionally, referring to FIG41 , the first masking process can form a via hole g4 exposing the first connection pattern 1023n103, a via hole g5 exposing the low-temperature polysilicon semiconductor layer n5, a via hole g6 exposing the first gate layer n7, and a via hole g7 exposing the second gate layer n10. That is, the via holes formed in the first masking process are formed so that the deepest possible via hole is exposed at the low-temperature polysilicon semiconductor layer n5.

[0377] 42 , the second masking process can form a via hole g8 exposing the oxide semiconductor layer n12 and a via hole g9 exposing the third gate layer n14. That is, the via holes formed by the second masking process are as deep as to expose the oxide semiconductor layer n12.

[0378] The reason for using two masking processes is that the oxide semiconductor layer n12 cannot withstand long etching times. If the two masking processes are combined into one masking process, the deepest etching will expose the low-temperature polysilicon semiconductor layer n5, which will cause the oxide semiconductor layer n12 to be damaged by the etching.

[0379] (15) Referring to FIG. 43 , a source-drain layer n9 is formed.

[0380] Optionally, the material of the source / drain electrode layer n9 may be a triple-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), wherein the thickness of the titanium layer may be 50 nm, and the thickness of the aluminum layer may be 650 nm.

[0381] When preparing the source-drain electrode layer n9, a source-drain electrode thin film may be first deposited and then the source-drain electrode thin film may be patterned to obtain the source-drain electrode layer n9.

[0382] Optionally, the source-drain layer n9 includes a first source n91 and a first drain n92 of a low-temperature polysilicon thin film transistor, a second source n94 and a second drain n95 of an oxide thin film transistor, and the like.

[0383] (16) Referring to FIG. 44 , a flat layer n16 is formed.

[0384] In the embodiment of the present application, the flat layer n16 can be prepared by first forming a flat film, and then patterning the flat film to obtain the flat layer n16. The flat layer n16 is used for planarization, and the thickness of the flat layer n16 can be greater than or equal to 2 μm, for example, 2 μm.

[0385] The planar layer n16 may have a plurality of first electrode connection holes K1, wherein the first electrode connection holes K1 expose patterns located in the source / drain layer n9. For example, a portion of the first electrode connection holes K1 exposes the first drain electrode n92 or the second drain electrode n95, while another portion of the first electrode connection holes K1 exposes a target pattern located in the source / drain layer n9 for transmitting the second signal.

[0386] (17) Referring to FIG. 45 , a first passivation layer n17 is formed.

[0387] In the embodiment of the present application, the first passivation layer n17 can be prepared by first forming a second passivation film, and then patterning the second passivation film to obtain the first passivation layer n17. The first passivation layer n17 can be a single layer or a stack of silicon oxide (SiO2) and silicon nitride (SiNx). For example, the material of the first passivation layer n17 is SiNx, and its thickness can be 100nm.

[0388] The first passivation layer n17 has multiple second electrode connection holes K2, where the orthographic projections of the second electrode connection holes K2 on the substrate n1 are located within the orthographic projections of the first electrode connection holes K1 on the substrate n1. The first passivation layer n17 wraps around the sidewalls of the vias in the planarization layer n16, preventing the planarization layer n16 from absorbing water and affecting product reliability.

[0389] (18) Referring to FIG. 46 , the first drive electrode 10211 , the second drive electrode 10212 , and the second dam portion 1052 are formed.

[0390] In the embodiment of the present application, the first drive electrode 10211, the second drive electrode 10212, and the second dam portion 1052 can be made of the same material and fabricated using the same patterning process. Alternatively, during fabrication, a metal film can be formed first, and then patterned to form the first drive electrode 10211, the second drive electrode 10212, and the second dam portion 1052.

[0391] Optionally, the metal film may include copper (Cu). Since copper has a certain degree of diffusion, a molybdenum nickel titanium (MTD) layer may be provided below the Cu layer of the electrode layer to prevent the copper layer from diffusing downward. The thickness of the MTD layer may be 30 nm, and the thickness of the Cu layer may be 1800 nm.

[0392] (19) Referring to FIG. 47 , a third passivation film is formed.

[0393] Optionally, the thickness of the third passivation film ranges from 50 nm to 300 nm. The third passivation film may be a single layer of SiO2 and SiNx. For example, the third passivation film may be a single layer of SiNx with a thickness of 200 nm.

[0394] (20) Etching away the inorganic film layers and substrate n1 between adjacent light-emitting components.

[0395] Referring to Figure 48, as of the process of step (19), all inorganic film layers of the multiple light-emitting components prepared on the entire second substrate are continuous. In order to prepare independent light-emitting components, the inorganic film layers between adjacent light-emitting components and the substrate n1 can be etched away.

[0396] Optionally, all inorganic film layers of the multiple light-emitting components prepared on the second substrate can be etched in one step or in multiple steps (e.g., two to three steps). Substrate n1 can then be etched using a single etching process. For example, all inorganic film layers are etched using a single etching process, and substrate n1 is etched using a single etching process, i.e., two etching processes are used in total, saving costs. The etched inorganic film layer can be used as a mask when etching substrate n1.

[0397] Optionally, the total thickness of all inorganic film layers is approximately 2.7 μm.

[0398] 49 , it can be seen that the edge of the inorganic film layer formed by etching can be a stepped edge. Furthermore, the edge of the substrate n1 obtained by etching using the inorganic film layer as a mask is almost a steep edge, that is, the side edge of the substrate n1 can be perpendicular to the surface of the substrate n1.

[0399] (21) Referring to FIG. 48 and FIG. 50 , a plurality of via holes are formed on the third passivation film using a single mask process to obtain a second passivation layer n18.

[0400] The plurality of via holes include a first via hole g10 exposing the first driving electrode 10211 , a second via hole g11 exposing the second driving electrode 10212 , and a third via hole g12 exposing the second dam portion 1052 .

[0401] Since the sidewalls of the first drive electrode 10211 and the second drive electrode 10212 are easily oxidized, the oxidized first drive electrode 10211 and the second drive electrode 10212 may fall off, which may affect the yield of the light-emitting component. Therefore, by having the second passivation layer n18 include the edges of the first drive electrode 10211 and the second drive electrode 10212, the sidewalls of the first drive electrode 10211 and the second drive electrode 10212 can be prevented from being oxidized.

[0402] Optionally, the orthographic projection of the first via g10 on the substrate n1 is located within the orthographic projection of the first drive electrode 10211 on the substrate n1, and the second passivation layer n18 wraps around the edge of the first drive electrode 10211. The orthographic projection of the second via g11 on the substrate n1 is located within the orthographic projection of the second drive electrode 10212 on the substrate n1, and the second passivation layer n18 wraps around the edge of the second drive electrode 10212.

[0403] In the embodiment of the present application, when the driving units 102 of multiple light-emitting components 100 are prepared at the same time, the mask plates included in the preparation process include: 1. a mask plate for forming the connection pad 1032, which is used to pattern the connection pad film and the release layer; 2. a mask plate for forming the substrate n1, which is used to open holes (holes need to be opened on the substrate n1 for connecting the connection pattern 1023 and the connection pad 1032); 3. a mask plate for forming the first passivation layer, which is used to open holes (holes need to be opened on the first passivation layer for connecting the connection pattern 1023 and the connection pad 1032 connection); 4. a mask for the connection pattern 1023, which is used to pattern the connection pattern film; 5. a mask for forming a light shielding layer, which is used to pattern the light shielding film; 6. a mask for doping the active layer of the low-temperature polycrystalline silicon thin film transistor; 7. a mask for forming a first gate insulating layer, which is used to form a via hole exposing the connection pattern 1023 and a via hole exposing the light shielding pattern of the light shielding layer n3 (the first bottom gate n31 of the low-temperature polycrystalline silicon thin film transistor); 8. a mask for forming the first gate layer 9. A mask for patterning the first gate film; 10. A mask for forming the oxide semiconductor layer; 11. A mask for forming the third gate layer; 12. A mask for the first mask process when forming the second interlayer dielectric layer; 13. A mask for the second mask process when forming the second interlayer dielectric layer; 14. A mask for forming the source and drain layer; The following are the mask plates used to pattern the source and drain thin films: 15. A mask plate for forming the planar layer, used to form the first electrode connection hole; 16. A mask plate for forming the second passivation layer, used to form the second electrode connection hole; 17. A mask plate for forming the drive electrode and the second dam, used to pattern the metal film; 18. A mask plate used for etching the inorganic film layer and substrate n1, used to form the independent drive unit; 19. A mask plate for forming the third passivation layer, used to form the first via hole, the second via hole, and the third via hole. In other words, a total of 19 masks can be used in the process of manufacturing the drive unit 102.

[0404] In this embodiment, TPV (Through PI VIA) signal line (connection pattern 1023) vias are first prepared on the second substrate, and then the pixel drive circuit and necessary device structures are completed. The completed light-emitting component is used for direct display. Compared with traditional direct display, it is easier to produce special-shaped screens, with lower power consumption and low maintenance costs.

[0405] Figure 51 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. Referring to Figure 51 , the display panel includes a driver backplane 200 and multiple light-emitting assemblies 100 as provided in the above-described embodiments. The multiple light-emitting assemblies 100 can be connected to the driver backplane via die bonding. The driver backplane 200 can be a passive matrix (PM) driver backplane, also known as a PM backplane.

[0406] Referring to Figure 51 , multiple light-emitting components are located in the display area a of the display panel, and the multiple light-emitting components 100 are arranged in an array. The driving backplane 200 is used to provide driving signals to the driving units 102 103 via the multiple connecting electrodes 103 in the light-emitting components 100, so that the driving units 102 drive the light-emitting units 101 to emit light.

[0407] Optionally, the display panel may be a display screen in a mobile phone, a laptop computer, or a flat-panel computer, or may be an outdoor advertising screen.

[0408] Since the display panel can have substantially the same technical effects as the light-emitting assembly described in the previous embodiment, the technical effects of the display panel will not be repeatedly described here for the purpose of brevity.

[0409] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A light emitting component, characterized in that: The light emitting component comprises: A light-emitting unit, the light-emitting unit comprising a light-emitting unit electrode and a light-emitting portion electrically connected to the light-emitting unit electrode; A driving unit, the driving unit comprising a driving electrode and a driving circuit electrically connected to the driving electrode, the driving electrode being located on a side of the driving circuit facing the light-emitting unit; the driving electrode is electrically connected to an electrode of the light-emitting unit; And, a plurality of connecting electrodes are located on a side of the driving unit away from the light-emitting unit, the connecting electrodes are electrically connected to the driving circuit, the connecting electrodes are configured to be electrically connected to a driving backplane included in the display panel, and the driving backplane is configured to provide a driving signal to the driving circuit through the connecting electrodes.

2. The light emitting assembly according to claim 1, characterized in that: The light emitting unit electrode comprises a first light emitting unit electrode and a second light emitting unit electrode, the driving electrode comprises a first driving electrode and a second driving electrode, and the driving circuit comprises a pixel driving circuit; The first light-emitting unit electrode is electrically connected to the first driving electrode, the second light-emitting unit electrode is electrically connected to the second driving electrode; and the first driving electrode is also electrically connected to the pixel driving circuit.

3. The light emitting assembly according to claim 2, characterized in that: The light-emitting component includes a plurality of light-emitting units, and the plurality of light-emitting units include a light-emitting unit of a first color, a light-emitting unit of a second color, and a light-emitting unit of a third color; wherein the first color, the second color, and the third color are different from each other; The driving circuit includes a plurality of pixel driving circuits corresponding to the plurality of light-emitting units, the driving electrode includes a plurality of the first driving electrodes, the plurality of pixel driving circuits and the plurality of the first driving electrodes are also arranged correspondingly, each of the first driving electrodes is electrically connected to the first light-emitting unit electrode of the corresponding light-emitting unit, and each of the pixel driving circuits is electrically connected to the corresponding first driving electrode.

4. The light emitting assembly according to claim 3, characterized in that: The plurality of light emitting units include a common second light emitting unit electrode, and the driving unit further includes a common second driving electrode; Wherein, the second light emitting unit electrode is electrically connected to the second driving electrode.

5. The light emitting assembly according to claim 1, characterized in that: The driving circuit includes a first type of thin film transistor, which is a dual-gate transistor, and includes a first active pattern, a first bottom gate, a first top gate, a first source and a first drain; the driving unit includes: a substrate, a barrier layer, a first metal layer, a first buffer layer, a first active layer, a first insulating layer, a second metal layer, a second insulating layer and a third metal layer stacked in sequence.

6. The light emitting assembly according to claim 5, characterized in that: The first metal layer includes the first bottom gate, the second metal layer includes the first top gate, the first active layer includes a first active pattern, the first active pattern is located between the first bottom gate and the first top gate, and the first top gate is electrically connected to the first bottom gate through a via hole passing through the first insulating layer and the first buffer layer; The second metal layer includes a first transfer pattern, and the first transfer pattern is electrically connected to the connection electrode through a via hole passing through the first insulating layer, the first buffer layer and the barrier layer; The third metal layer includes the first source and the first drain, and a first interconnection pattern, the first source is electrically connected to the source region of the first active pattern through a via passing through the second insulating layer and the first insulating layer, the first drain is electrically connected to the drain region of the first active pattern through a via passing through the second insulating layer and the first insulating layer, the first interconnection pattern is electrically connected to the first transfer pattern through a via passing through the second insulating layer, and the first interconnection pattern is electrically connected to the first active pattern through a via passing through the second insulating layer and the first insulating layer.

7. The light emitting assembly according to claim 5 or 6, characterized in that: The driving unit comprises: a connection pattern located between the substrate and the barrier layer, at least a portion of the connection electrode is located inside the substrate, the substrate has a connection via hole exposing the connection electrode, a portion of the connection pattern is located in the connection via hole and is electrically connected to the connection electrode, and another portion of the connection pattern is located on a side of the substrate close to the driving circuit; The first transfer pattern is electrically connected to the connection pattern through a via hole that passes through the first insulating layer, the first buffer layer, and the barrier layer.

8. The light emitting assembly according to claim 5 or 6, characterized in that: The driving circuit includes a plurality of thin film transistors; the plurality of thin film transistors include at least one low temperature polysilicon thin film transistor and at least one oxide thin film transistor; Among them, at least one of the low-temperature polysilicon thin film transistors included in the plurality of thin film transistors is the first type of thin film transistor.

9. The light emitting assembly according to claim 8, characterized in that: The oxide thin film transistor is a single-gate transistor, and the oxide thin film transistor includes a gate, a second active pattern, a second source and a second drain; the driving unit further includes: a fourth metal layer located between the second insulating layer and the third metal layer, a third insulating layer, a second active layer and a fourth insulating layer; The fourth metal layer includes the gate, the second active layer includes a second active pattern, and an orthographic projection of the second active pattern on the substrate partially overlaps with an orthographic projection of the gate on the substrate; The third metal layer further includes the second source and the second drain, the second source being electrically connected to the source region of the second active pattern through a via hole passing through the fourth insulating layer, and the second drain being electrically connected to the drain region of the second active pattern through a via hole passing through the fourth insulating layer.

10. The light emitting assembly according to claim 8, characterized in that: The oxide thin film transistor is a single-gate transistor, and the oxide thin film transistor includes a gate, a second active pattern, a second source and a second drain; the driving unit further includes: a fourth metal layer located between the second insulating layer and the third metal layer, a third insulating layer, a second active layer, a fourth insulating layer, a fifth metal layer and a fifth insulating layer; The fourth metal layer or the fifth metal layer includes the gate, the second active layer includes a second active pattern, and an orthographic projection of the second active pattern on the substrate partially overlaps with an orthographic projection of the gate on the substrate; The third metal layer further includes the second source electrode and the second drain electrode, and the second source electrode is electrically connected to the source region of the second active pattern through a via hole passing through the fifth insulating layer and the fourth insulating layer. The second drain electrode is electrically connected to the drain region of the second active pattern through a via hole passing through the fifth insulating layer and the fourth insulating layer.

11. The light emitting assembly according to claim 8, characterized in that: The oxide thin film transistor is a dual-gate transistor, and the oxide thin film transistor includes a second active pattern, a second bottom gate, a second top gate, a second source electrode and a second drain electrode; the driving unit further includes: a fourth metal layer located between the second insulating layer and the third metal layer, a third insulating layer, a second active layer, a fourth insulating layer, a fifth metal layer and a fifth insulating layer; The fourth metal layer includes the second bottom gate, the fifth metal layer includes the second top gate, the second active layer includes a second active pattern, and the second active pattern is located between the second bottom gate and the second top gate; The third metal layer further includes a third interconnection pattern, the third interconnection pattern is electrically connected to the second top gate through a via hole passing through the fifth insulating layer and the fourth insulating layer, and the third interconnection pattern is electrically connected to the second bottom gate through a via hole passing through the fifth insulating layer, the fourth insulating layer and the third insulating layer; The third metal layer also includes the second source and the second drain, the second source is electrically connected to the source region of the second active pattern through a via passing through the fifth insulating layer and the fourth insulating layer, and the second drain is electrically connected to the drain region of the second active pattern through a via passing through the fifth insulating layer and the fourth insulating layer.

12. The light emitting assembly according to claim 1, characterized in that: The driving circuit includes a first type of thin film transistor, which is a dual-gate transistor, and includes a first active pattern, a first bottom gate, a first top gate, a first source and a first drain; the driving unit includes: a substrate, a barrier layer, a first metal layer, a first buffer layer, a first active layer, a first insulating layer, a second metal layer, a second insulating layer, a fourth metal layer, a third insulating layer and a third metal layer stacked in sequence.

13. The light emitting assembly according to claim 12, characterized in that: The first metal layer includes the first bottom gate, the second metal layer includes the first top gate, the first active layer includes a first active pattern, and the first active pattern is located between the first bottom gate and the first top gate. The fourth metal layer includes a second interconnection pattern between the first top gate and the second top gate, the second interconnection pattern is electrically connected to the first top gate through a via hole passing through the second insulating layer, and the second interconnection pattern is electrically connected to the first bottom gate through a via hole passing through the first insulating layer, the second insulating layer and the first buffer layer; The fourth metal layer further includes a second transfer pattern, and the second transfer pattern is electrically connected to the connection electrode through a via hole passing through the first insulating layer, the second insulating layer, the first buffer layer and the barrier layer; The third metal layer includes the first source, the first drain, and a third interconnection pattern, the first source is electrically connected to the source region of the first active pattern through a via passing through the third insulating layer, the second insulating layer, and the first insulating layer, the first drain is electrically connected to the drain region of the first active pattern through a via passing through the third insulating layer, the second insulating layer, and the first insulating layer, the third interconnection pattern is electrically connected to the third-type transfer pattern through a via passing through the third insulating layer, and the first interconnection pattern is electrically connected to the first active pattern through a via passing through the third insulating layer, the second insulating layer, and the first insulating layer.

14. The light emitting assembly according to claim 12 or 13, characterized in that: The driving unit comprises: a connection pattern located between the substrate and the barrier layer, at least a portion of the connection electrode is located inside the substrate, the substrate has a connection via hole exposing the connection electrode, a portion of the connection pattern is located in the connection via hole and is electrically connected to the connection electrode, and another portion of the connection pattern is located on a side of the substrate close to the driving circuit; The second transfer pattern is electrically connected to the connection pattern through a via hole that passes through the second insulating layer, the first insulating layer, the first buffer layer, and the barrier layer.

15. The light emitting assembly according to claim 12 or 13, characterized in that: The driving circuit includes a plurality of thin film transistors; the plurality of thin film transistors include at least one low temperature polysilicon thin film transistor and at least one oxide thin film transistor; Among them, at least one of the low-temperature polysilicon thin film transistors included in the plurality of thin film transistors is the first type of thin film transistor.

16. The light emitting assembly according to claim 15, characterized in that: The oxide thin film transistor is a single-gate transistor, and the oxide thin film transistor includes a gate, a second active pattern, a second source and a second drain; the driving unit further includes: a second active layer and a fourth insulating layer located between the third insulating layer and the third metal layer; The fourth metal layer includes the gate, the second active layer includes a second active pattern, and an orthographic projection of the second active pattern on the substrate partially overlaps with an orthographic projection of the gate on the substrate; The third metal layer further includes the second source and the second drain, the second source being electrically connected to the source region of the second active pattern through a via hole passing through the fourth insulating layer, and the second drain being electrically connected to the drain region of the second active pattern through a via hole passing through the fourth insulating layer.

17. The light emitting assembly according to claim 15, characterized in that: The oxide thin film transistor is a single-gate transistor, and the oxide thin film transistor includes a gate, a second active layer, a second source electrode and a second drain electrode; The driving unit further includes: a second active layer, a fourth insulating layer, a fifth metal layer and a fifth insulating layer located between the third insulating layer and the third metal layer; The fourth metal layer or the fifth metal layer includes the gate, the second active layer includes a second active pattern, and an orthographic projection of the second active pattern on the substrate partially overlaps with an orthographic projection of the gate on the substrate; The third metal layer also includes the second source and the second drain, the second source is electrically connected to the source region of the second active pattern through a via passing through the fifth insulating layer and the fourth insulating layer, and the second drain is electrically connected to the drain region of the second active pattern through a via passing through the fifth insulating layer and the fourth insulating layer.

18. The light emitting assembly according to claim 15, characterized in that: The oxide thin film transistor is a dual-gate transistor, and the oxide thin film transistor includes a second active layer, a second bottom gate, a second top gate, a second source electrode and a second drain electrode; the driving unit further includes: a second active layer, a fourth insulating layer, a fifth metal layer and a fifth insulating layer located between the third insulating layer and the third metal layer; The fourth metal layer includes the second bottom gate, the fifth metal layer includes the second top gate, the second active layer includes a second active pattern, and the second active pattern is located between the second bottom gate and the second top gate; The third metal layer further includes a third interconnection pattern, the third interconnection pattern is electrically connected to the second top gate through a via hole passing through the fifth insulating layer and the fourth insulating layer, and the third interconnection pattern is electrically connected to the second bottom gate through a via hole passing through the fifth insulating layer, the fourth insulating layer and the third insulating layer; The third metal layer also includes the second source and the second drain, the second source is electrically connected to the source region of the second active pattern through a via passing through the fifth insulating layer and the fourth insulating layer, and the second drain is electrically connected to the drain region of the second active pattern through a via passing through the fifth insulating layer and the fourth insulating layer.

19. The light emitting assembly according to any one of claims 5 to 18, characterized in that: The thickness of the first metal layer ranges from 20 nanometers to 200 nanometers.

20. The light emitting assembly according to claim 19, characterized in that: The thickness of the barrier layer ranges from 50 nanometers to 600 nanometers; The thickness of the first buffer layer is greater than or equal to 170 nanometers.

21. The light emitting assembly according to claim 8 or 15, characterized in that: The light emitting unit electrode includes a first light emitting unit electrode and a second light emitting unit electrode, and the driving electrode includes the first driving electrode and the second driving electrode; The first driving electrode is electrically connected to one of the thin film transistors in the driving circuit, and the first driving electrode is used to transmit a first signal to a first light emitting unit electrode of the light emitting unit; The second driving electrode is used to transmit a second signal to the second light emitting unit electrode, and a potential of the second signal is different from a potential of the first signal.

22. The light emitting assembly according to any one of claims 5 to 18, characterized in that: The driving unit further includes: an organic film layer, a first inorganic film layer and a second inorganic film layer located on a side of the third metal layer away from the substrate; The organic film layer has a first electrode connection hole, the first electrode connection hole has a hole sidewall and a hole bottom, and the first electrode connection hole is used to expose at least part of the pattern in the source and drain electrode layer; The first inorganic film layer has a second electrode connection hole, the orthographic projection of the second electrode connection hole on the substrate is located within the orthographic projection of the first electrode connection hole on the substrate, the first inorganic film layer covers the sidewall of the hole and exposes the bottom of the hole to expose at least a portion of the pattern in the source and drain electrode layer exposed at the bottom of the hole, and the driving electrode is connected to the pattern in the source and drain electrode layer through the second electrode connection hole and the first electrode connection hole; The second inorganic film layer has a via hole exposing the driving electrode, and the light-emitting unit electrode is electrically connected to the driving electrode through the via hole of the second inorganic film layer.

23. The light emitting assembly according to claim 22, characterized in that: The orthographic projection of the via hole in the second inorganic film layer on the substrate is located within the orthographic projection of the driving electrode on the substrate, and the second inorganic film layer wraps the edge of the driving electrode.

24. The light emitting assembly according to any one of claims 5 to 18, characterized in that: The driving unit further comprises: an organic film layer located on a side of the third metal layer away from the substrate, a first inorganic film layer and a second inorganic film layer; the organic film layer has a first electrode connection hole, the first electrode connection hole is used to expose at least part of the pattern in the source and drain layer; the first inorganic film layer has a second electrode connection hole to expose at least part of the pattern in the source and drain layer, the driving electrode is connected through the second electrode connection hole and the first electrode connection hole and at least part of the pattern in the source and drain layer; the second inorganic film layer has a via hole exposing the driving electrode, the light-emitting unit electrode is electrically connected to the driving electrode through the via hole of the second inorganic film layer; The first metal layer is a light-shielding layer, the first active layer is a low-temperature polycrystalline silicon semiconductor layer, the first insulating layer is a first gate insulating layer, the second metal layer is a first gate layer, the second insulating layer is a second gate insulating layer, the fourth metal layer is a second gate layer, the third insulating layer includes a first interlayer dielectric layer and a second buffer layer, the second active layer is an oxide semiconductor layer, the fourth insulating layer is a third gate insulating layer, the fifth metal layer is a third gate layer, the fifth insulating layer is a second interlayer dielectric layer, the organic film layer is a planarizing layer, the first inorganic film layer is a first passivation layer, and the second inorganic film layer is a second passivation layer.

25. The light emitting assembly according to any one of claims 5 to 18, characterized in that: The thickness of the substrate ranges from 3 micrometers to 10 micrometers.

26. The light emitting assembly according to claim 11 or 18, characterized in that: The thickness of the first interlayer dielectric layer is in a range of 50 nanometers to 500 nanometers.

27. The light emitting assembly according to claim 22, characterized in that: The thickness of the first inorganic film layer ranges from 50 nanometers to 300 nanometers.

28. The light emitting assembly according to claim 22, characterized in that: The thickness of the second inorganic film layer ranges from 50 nanometers to 300 nanometers.

29. The light emitting assembly according to any one of claims 1 to 18, 20 and 23 to 28, characterized in that: The orthographic projection of the driving electrode on the substrate in the driving unit and the orthographic projection of the connecting electrode on the substrate in the driving unit do not overlap.

30. The light emitting assembly according to any one of claims 1 to 18, 20 and 23 to 28, characterized in that: The light emitting assembly further comprises: a dam structure located between the light emitting portion and the driving circuit; The dam structure is ring-shaped and surrounds the light-emitting unit electrode and the driving electrode.

31. The light emitting assembly according to claim 30, characterized in that: The width of the dam structure is greater than or equal to 0.9 micrometers and less than or equal to 11 micrometers.

32. The light emitting assembly according to claim 31, characterized in that: The orthographic projection of the dam structure on the substrate in the driving unit does not overlap with the connecting via in the substrate.

33. The light emitting assembly according to claim 32, characterized in that: The orthographic projection of the dam structure on the substrate in the driving unit partially overlaps with the orthographic projection of the connection pattern in the driving unit on the substrate, and the overlapping position is located on a side of the connection via hole close to the light-emitting component.

34. The light emitting assembly according to any one of claims 1 to 4, characterized in that: The driving circuit includes a plurality of thin film transistors; the plurality of thin film transistors include at least one low temperature polysilicon thin film transistor and at least one oxide thin film transistor; The active layer of the at least one low-temperature polysilicon thin film transistor is located on a side of the active layer of the at least one oxide thin film transistor away from the driving electrode.

35. The light emitting assembly according to claim 34, characterized in that: The light emitting unit electrode includes a first light emitting unit electrode and a second light emitting unit electrode, and the driving electrode includes the first driving electrode and the second driving electrode; The first driving electrode is electrically connected to one of the thin film transistors in the driving circuit, and the first driving electrode is used to transmit a first signal to a first light emitting unit electrode of the light emitting unit; The second driving electrode is used to transmit a second signal to the second light emitting unit electrode, and a potential of the second signal is different from a potential of the first signal.

36. The light emitting assembly according to any one of claims 1 to 18, 20 and 23 to 28, characterized in that: The driving circuit includes a gate driving circuit and a light-emitting driving circuit, and the light-emitting unit is electrically connected to the gate driving circuit and the light-emitting driving circuit.

37. The light emitting assembly according to claim 36, characterized in that: The driving circuit also includes a multiplexing circuit, and the driving signal of the driving backplane is transmitted to the light-emitting component after passing through the multiplexing circuit.

38. A method for preparing a light-emitting component, characterized in that: The preparation method is used to prepare the light-emitting component according to any one of claims 1 to 37, and the method comprises: Obtain a first substrate and a light-emitting unit located on one side of the first substrate, wherein the light-emitting unit comprises: a light-emitting unit electrode and a light-emitting portion electrically connected to the light-emitting unit electrode, wherein the light-emitting unit electrode is located on a side of the light-emitting portion away from the first substrate; Obtain a second substrate and a driving unit located on one side of the second substrate, the driving unit comprising a driving electrode and a driving circuit electrically connected to the driving electrode, the driving electrode being located on a side of the driving circuit away from the second substrate; Bonding the light emitting unit and the driving unit through a bonding process so that the driving electrode and the light emitting unit electrode are electrically connected; peeling the second substrate from one side of the driving unit; A plurality of connecting electrodes are formed on a side of the driving unit away from the light-emitting unit, the plurality of connecting electrodes are electrically connected to the driving circuit, the connecting electrodes are configured to be electrically connected to a driving backplane included in the display panel, and the driving backplane is configured to provide a driving signal to the driving power supply through the connecting electrodes.

39. A display panel, characterized in that: The display panel comprises: a driving backplane, and a plurality of light-emitting components according to any one of claims 1 to 37 arranged in an array and located on one side of the driving backplane; The driving backplane is used to provide a driving signal for the light-emitting component to make the light-emitting component emit light.

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