Pixel circuit, driving method therefor, display panel and display apparatus

Abstract

Provided are a pixel circuit, a driving method therefor, a display panel and a display apparatus, belonging to the technical field of display. In the pixel circuit, in response to receiving reset signals, a reset circuit can control a connection / disconnection between a first initial power line and an intermediate node, a connection / disconnection between the intermediate node and a driving node, a connection / disconnection between a second initial power line and the intermediate node and a connection / disconnection between the second initial power line and a light-emitting element; and, on the basis of the potential of the driving node, a driving circuit can drive the light-emitting element to emit light. In addition, the absolute value of the potential of a first initial power signal provided by the first initial power line is less than the absolute value of the potential of a second initial power signal provided by the second initial power line. Thus, each signal can be flexibly set, such that after the first initial power signal is transmitted to the driving node, the same second initial power signal is transmitted to the light-emitting element and the intermediate node so as to reduce the leakage current of a transistor coupled to the driving node, thereby ensuring that the driving circuit reliably drives the light-emitting element to emit light and achieving a good display effect.

Description

Pixel circuit and driving method thereof, display panel, and display device

[0001] This disclosure claims priority to Chinese patent application number 202311596846.1 filed on November 27, 2023, entitled “Pixel circuit and driving method thereof, display panel, and display device,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display panel, and a display device. Background Art

[0003] A display panel generally includes a substrate and a plurality of pixels located on the substrate. Each pixel includes a pixel circuit and a light-emitting element. The pixel circuit is coupled to the light-emitting element and is used to drive the light-emitting element to emit light.

[0004] In related art, a pixel circuit generally includes a reset circuit and a driver circuit. The reset circuit is coupled to two initial power lines, the driver circuit, and the light-emitting element, respectively, and is used to transmit the initial power signals provided by the two initial power lines to the driver circuit and the light-emitting element, respectively, to reset the driver circuit and the light-emitting element. The driver circuit is also coupled to the light-emitting element to drive the light-emitting element to emit light.

[0005] However, because the potentials of the initial power signals provided by the two initial power lines are generally different, the driving circuit cannot reliably drive the light-emitting element to emit light, thereby causing poor display effect of the display panel.

[0006] Summary of the Invention

[0007] The present disclosure provides a pixel circuit and a driving method thereof, a display panel, and a display device. The technical solution is as follows:

[0008] In one aspect, a pixel circuit is provided for coupling with a light-emitting element; the pixel circuit comprises:

[0009] a reset circuit, coupled to a first reset line, a second reset line, a third reset line, a first initial power line, a second initial power line, an intermediate node, a driving node, and the light-emitting element, respectively, and configured to control the connection and disconnection between the first initial power line and the intermediate node, and between the intermediate node and the driving node, in response to a first reset signal provided by the first reset line, control the connection and disconnection between the second initial power line and the intermediate node, and control the connection and disconnection between the second initial power line and the light-emitting element, in response to a second reset signal provided by the second reset line;

[0010] a driving circuit, coupled to the plurality of driving signal lines, the driving node, and the light-emitting element, respectively, and configured to transmit a light-emitting driving signal to the light-emitting element based on the driving signals provided by the plurality of driving signal lines and the potential of the driving node, so as to drive the light-emitting element to emit light;

[0011] The absolute value of the potential of the first initial power signal provided by the first initial power line is smaller than the absolute value of the potential of the second initial power signal provided by the second initial power line.

[0012] Optionally, the reset circuit includes:

[0013] a first reset sub-circuit, coupled to the first reset line, the first initial power line, the intermediate node, and the driving node, respectively, and configured to control the connection and disconnection between the first initial power line and the intermediate node, and control the connection and disconnection between the intermediate node and the driving node in response to the first reset signal;

[0014] The second reset subcircuit is coupled to the second reset line, the third reset line, the second initial power line, the intermediate node and the light-emitting element, respectively, and is used to control the connection and disconnection of the second initial power line and the intermediate node in response to the second reset signal, and to control the connection and disconnection of the second initial power line and the light-emitting element in response to the third reset signal.

[0015] Optionally, the second reset sub-circuit includes:

[0016] a first reset unit, coupled to the second reset line, the second initial power line and the intermediate node respectively, and configured to control the connection and disconnection between the second initial power line and the intermediate node in response to the second reset signal;

[0017] The second reset unit is coupled to the third reset line, the second initial power line and the light emitting element respectively, and is used to control the connection and disconnection of the second initial power line and the light emitting element in response to the third reset signal.

[0018] Optionally, the first reset unit includes: a first transistor;

[0019] A gate of the first transistor is coupled to the second reset line, a first electrode of the first transistor is coupled to the second initial power line, and a second electrode of the first transistor is coupled to the intermediate node.

[0020] Optionally, the second reset unit includes: a second transistor;

[0021] A gate of the second transistor is coupled to the third reset line, a first electrode of the second transistor is coupled to the second initial power line, and a second electrode of the second transistor is coupled to the light emitting element.

[0022] Optionally, the first reset sub-circuit includes: two third transistors with a common gate;

[0023] The gates of the two third transistors are both coupled to the first reset line, and, among the two third transistors, the first electrode and the second electrode of one third transistor are respectively coupled to the first initial power line and the intermediate node, and the first electrode and the second electrode of the other third transistor are respectively coupled to the intermediate node and the driving node.

[0024] Optionally, the plurality of driving signal lines include: gate lines, data lines, light emitting control lines and driving power lines; the driving circuit includes:

[0025] a first light-emitting control subcircuit, coupled to the light-emitting control line, the driving power line, and the first node, respectively, and configured to control the connection and disconnection between the driving power line and the first node in response to a light-emitting control signal provided by the light-emitting control line;

[0026] a second light-emitting control subcircuit, coupled to the light-emitting control line, the second node, and the light-emitting element, respectively, and configured to control the on / off connection between the second node and the light-emitting element in response to the light-emitting control signal;

[0027] a data writing sub-circuit, coupled to the gate line, the data line and the first node respectively, and configured to control the connection and disconnection between the data line and the first node in response to a gate driving signal provided by the gate line;

[0028] a compensation sub-circuit, coupled to the gate line, the second node and the driving node respectively, and configured to control the connection and disconnection between the second node and the driving node in response to the gate driving signal;

[0029] a driving subcircuit, coupled to the driving node, the first node, and the second node, respectively, and configured to transmit a light-emitting driving signal to the second node based on a potential of the driving node and a potential of the first node;

[0030] The storage sub-circuit is coupled to the driving power line and the driving node respectively, and is used to store the potential of the driving node based on the driving power signal provided by the driving power line.

[0031] Optionally, the first light-emitting control subcircuit includes a fourth transistor; the second light-emitting control subcircuit includes a fifth transistor; the data writing subcircuit includes a sixth transistor; the compensation subcircuit includes a seventh transistor; the driving subcircuit includes an eighth transistor; and the storage subcircuit includes a storage capacitor.

[0032] The gate of the fourth transistor and the gate of the fifth transistor are both coupled to the light emitting control line, the first electrode of the fourth transistor is coupled to the driving power line, the second electrode of the fourth transistor is coupled to the first node, the first electrode of the fifth transistor is coupled to the second node, and the second electrode of the fifth transistor is coupled to the light emitting element;

[0033] The gate of the sixth transistor and the gate of the seventh transistor are both coupled to the gate line, the first electrode of the sixth transistor is coupled to the data line, the second electrode of the sixth transistor is coupled to the first node, the first electrode of the seventh transistor is coupled to the second node, and the second electrode of the seventh transistor is coupled to the driving node;

[0034] The gate of the eighth transistor is coupled to the driving node, the first electrode of the eighth transistor is coupled to the first node, and the second electrode of the eighth transistor is coupled to the second node;

[0035] A first end of the storage capacitor is coupled to the driving power line, and a second end of the storage capacitor is coupled to the driving node.

[0036] Optionally, the plurality of rows of pixel circuits drive the coupled light-emitting elements to emit light row by row;

[0037] The second reset line is shared with the light emitting control line coupled to the light emitting control subcircuit in the previous row of pixel circuits; the third reset line is shared with the first reset line coupled to the reset circuit in the previous row of pixel circuits.

[0038] Optionally, the pixel circuit includes: an active layer, a first conductive layer, a second conductive layer, and a third conductive layer stacked in sequence, and an insulating layer located between any two film layers;

[0039] The active layer and the first conductive layer are configured to form transistors in the pixel circuit; and the first conductive layer is further configured to form the first reset line, the second reset line, the third reset line, the gate line, and the light emitting control line;

[0040] The second conductive layer is configured to form the first initial power line and the second initial power line;

[0041] The third conductive layer is configured to overlap the active layer and the second conductive layer respectively through via holes penetrating the insulating layer, so as to transfer the active layer and the second conductive layer.

[0042] Optionally, the transistor in the pixel circuit includes a P-type transistor; the active layer includes: a P-type conductive layer; the first conductive layer and the second conductive layer both include: a gate metal layer; and the third conductive layer includes: a source-drain metal layer.

[0043] In another aspect, a method for driving a pixel circuit is provided, which is applied to the pixel circuit described in the first aspect above; the method comprises:

[0044] In the first stage, the reset circuit controls the first initial power line to be conductively connected to the intermediate node, and controls the intermediate node to be conductively connected to the driving node in response to the first reset signal provided by the first reset line, so that the first initial power signal provided by the first initial power line is transmitted to the driving node;

[0045] In the second stage, the reset circuit controls the second initial power line to be connected to the intermediate node in response to the second reset signal, and controls the second initial power line to be connected to the light-emitting element in response to the third reset signal, so that the second initial power signal provided by the second initial power line is transmitted to the intermediate node and the light-emitting element respectively;

[0046] In a third stage, the reset circuit controls the second initial power line to be conductive with the intermediate node in response to the second reset signal, so that the second initial power signal is transmitted to the intermediate node; and the driving circuit transmits a light-emitting driving signal to the light-emitting element based on the driving signals provided by the plurality of driving signal lines and the potential of the driving node, so as to drive the light-emitting element to emit light;

[0047] The absolute value of the potential of the first initial power signal is smaller than the absolute value of the potential of the second initial power signal.

[0048] In yet another aspect, a display panel is provided, comprising: a substrate, and a plurality of pixels located on the substrate;

[0049] The pixel includes: a light-emitting element, and the pixel circuit as described in the above aspect; the pixel circuit is coupled to the light-emitting element and is used to drive the light-emitting element to emit light.

[0050] Optionally, the plurality of pixels are arranged in an array;

[0051] The first reset line, gate line, light emitting control line, second initial power line and first initial power line coupled to the pixel circuit in each pixel are sequentially arranged in an interval manner along the pixel column direction;

[0052] Furthermore, the first initial power line is coupled to a power supply terminal providing a first initial power signal through a first initial power lead, and the second initial power line is coupled to a power supply terminal providing a second initial power signal through a second initial power lead; the first initial power lead and the second initial power lead are arranged around the multiple pixels and are spaced apart from each other.

[0053] In another aspect, a display device is provided, comprising: a display driving circuit, and the display panel according to the above aspect;

[0054] The display driving circuit is coupled to the signal line in the display panel and is used to provide a signal to the signal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0056] FIG1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0057] FIG2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0058] FIG3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0059] FIG4 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0060] FIG5 is a schematic diagram of a circuit structure of a pixel circuit provided by an embodiment of the present disclosure;

[0061] FIG6 is a film layer structure diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0062] FIG7 is a film layer structure diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0063] FIG8 is a cross-sectional view of a film layer of a pixel circuit provided by an embodiment of the present disclosure;

[0064] FIG9 is a diagram of a film structure including a substrate and an active layer provided by an embodiment of the present disclosure;

[0065] FIG10 is a diagram of a film structure including a substrate, an active layer, a first insulating layer, a first gate metal layer, a second insulating layer, and a second gate metal layer provided by an embodiment of the present disclosure;

[0066] 11 is a diagram of a film structure including a substrate, an active layer, a first insulating layer, a first gate metal layer, a second insulating layer, a second gate metal layer and a third insulating layer provided by an embodiment of the present disclosure;

[0067] 12 is a diagram of a film structure including a substrate, an active layer, a first insulating layer, a first gate metal layer, a second insulating layer, a second gate metal layer, a third insulating layer, a source / drain metal layer, and a planarization layer, provided by an embodiment of the present disclosure;

[0068] FIG13 is a flow chart of a driving method for a pixel circuit provided in an embodiment of the present disclosure;

[0069] FIG14 is a schematic diagram of a source-drain voltage difference of a third transistor provided by an embodiment of the present disclosure;

[0070] FIG15 is a schematic diagram of a source-drain voltage difference of a third transistor in the related art;

[0071] FIG16 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0072] FIG17 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0073] FIG18 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0074] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0075] It should be noted that the transistors used in all embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of the present disclosure are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. The source is referred to as the first electrode and the drain as the second electrode, or the drain is referred to as the first electrode and the source as the second electrode. According to the configuration in the accompanying drawings, the middle end of the transistor is defined as the gate, the signal input end as the source, and the signal output end as the drain. Furthermore, the switching transistors used in the embodiments of the present disclosure may include either a P-type transistor or an N-type transistor, or a combination thereof. A P-type transistor is turned on when the gate voltage is low and turned off when the gate voltage is high, while an N-type transistor is turned on when the gate voltage is high and turned off when the gate voltage is low. Furthermore, multiple signals in each embodiment correspond to a first potential and a second potential. The first potential and the second potential merely represent that the potential of the signal has two different states and do not represent that the first potential or the second potential has a specific value.

[0076] FIG1 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure, which is coupled to a light emitting element L1 . As shown in FIG1 , the pixel circuit 00 includes a reset circuit 01 and a drive circuit 02 .

[0077] The reset circuit 01 is coupled to the first reset line R1, the second reset line R2, the third reset line R3, the first initial power line Vinit1, the second initial power line Vinit2, the intermediate node N0, the driving node N1 and the light-emitting element L1, respectively, and is used to control the connection and disconnection of the first initial power line Vinit1 and the intermediate node N0 in response to a first reset signal provided by the first reset line R1, and control the connection and disconnection of the intermediate node N0 and the driving node N1, control the connection and disconnection of the second initial power line Vinit2 and the intermediate node N0 in response to a second reset signal provided by the second reset line R2, and control the connection and disconnection of the second initial power line Vinit2 and the light-emitting element L1 in response to a third reset signal provided by the third reset line R3.

[0078] For example, when the potential of the first reset signal provided by the first reset line R1 is a first potential, the reset circuit 01 can control the first initial power line Vinit1 to be conductive with the intermediate node N0, and also control the intermediate node N0 to be conductive with the driving node N1, so that the first initial power signal provided by the first initial power line Vinit1 can be transmitted to the intermediate node N0 and the driving node N1 in sequence. Furthermore, when the potential of the first reset signal provided by the first reset line R1 is a second potential, the reset circuit 01 can control the first initial power line Vinit1 to be decoupled from the intermediate node N0, and also control the intermediate node N0 to be decoupled from the driving node N1. This also shows that in the disclosed embodiment, the first initial power line Vinit1 and the driving node N1 can be indirectly coupled via the intermediate node N0.

[0079] Similarly, the reset circuit 01 can control the second initial power line Vinit2 to be conductive with the intermediate node N0 when the potential of the second reset signal provided by the second reset line R2 is the first potential, so that the second initial power signal provided by the second initial power line Vinit2 is transmitted to the intermediate node N0; and the reset circuit 01 can control the second initial power line Vinit2 to be disconnected from the intermediate node N0 when the potential of the second reset signal provided by the second reset line R2 is the second potential.

[0080] In addition, the reset circuit 01 can control the second initial power line Vinit2 to be turned on with the light-emitting element L1 when the potential of the third reset signal provided by the third reset line R3 is the first potential, so that the second initial power signal provided by the second initial power line Vinit2 is transmitted to the light-emitting element L1; and the reset circuit 01 can control the second initial power line Vinit2 to be disconnected from the light-emitting element L1 when the potential of the third reset signal provided by the third reset line R3 is the second potential.

[0081] Optionally, the light-emitting element L1 may be an organic light-emitting diode (OLED). The reset circuit O1 may be coupled to the anode of the light-emitting element L1 so that the second initial power signal provided by the second initial power line Vinit2 is transmitted to the anode of the light-emitting element L1. The cathode of the light-emitting element L1 may be coupled to the pull-down power line Vss. Of course, the anode and cathode of the light-emitting element L1 may be interchangeable.

[0082] Optionally, in the embodiment of the present disclosure, the first potential may be an effective potential, the second potential may be an ineffective potential, and the first potential may be a low potential relative to the second potential. It can also be seen from this that the transistor in the pixel circuit provided in the embodiment of the present disclosure may be a P-type transistor with a low effective potential. Of course, in some other embodiments, the first potential may be a high potential relative to the second potential, and the corresponding transistor may be an N-type transistor with a high effective potential.

[0083] Optionally, in the embodiment of the present disclosure, the potential of the driving power signal provided by the driving power line Vdd may be a high potential, and the potential of the pull-down power signal provided by the pull-down power line Vss may be a low potential. Here, high potential and low potential are relative.

[0084] In addition, in the embodiment of the present disclosure, the potential V of the first initial power signal provided by the first initial power line Vinit1 is Vinit1 The absolute value of V Vinit1 | can be less than the potential V of the second initial power signal provided by the second initial power line Vinit2 Vinit2 The absolute value of V Vinit2 That is, for the pixel circuit including the P-type transistor, the potential V of the first initial power supply signal for resetting the driving node N1 is Vinit1 The potential V of the second initial power supply signal for resetting the light emitting element L1 is Vinit2 More negative, satisfying: |V Vinit2 |<|V Vinit1 This can avoid problems such as afterimages and uneven brightness.

[0085] In the related art, the first initial power line Vinit1 is generally directly coupled to the driving node N1. When the reset circuit 01 controls the first initial power line Vinit1 to be disconnected from the driving node N1, the voltage across the transistor directly coupled to the driving node N1 in the reset circuit 01 is: the potential V of the first initial power signal provided by the first initial power line Vinit1 Vinit1 and the potential V of the driving node N1 N1 The difference "|V Vinit1 -V N1 |". Because |V Vinit2 |<|V Vinit1 Therefore, it can be seen that in the related art, the transistor directly coupled to the driving node N1 has a large voltage drop, resulting in a large leakage current, making it difficult to maintain the potential of the driving node N1, causing the display panel to have display abnormalities such as defective dots, affecting the image quality and yield of the display product.

[0086] In the embodiment of the present disclosure, since the first initial power line Vinit1 is indirectly coupled to the driving node N1 via the intermediate node N0, that is, transistors are provided between the first initial power line Vinit1 and the intermediate node N0, and between the intermediate node N0 and the driving node N1, respectively. Therefore, when the reset circuit O1 controls the first initial power line Vinit1 to be disconnected from the intermediate node N0 and simultaneously controls the intermediate node N0 to be disconnected from the driving node N1, the second initial power line Vinit2 can be controlled to be conductive with the intermediate node N0 in response to the second reset signal provided by the second reset line R2, so that the second initial power signal provided by the second initial power line Vinit2 is transmitted to the intermediate node N0. In this way, the voltage across the transistor directly coupled to the driving node N1 can be changed from "|V Vinit1 -V N1 |" becomes "|V Vinit2 -V N1 |". Because |V Vinit2 |<|V Vinit1 |, it can be seen that compared with the related art, the solution described in the embodiment of the present disclosure can reliably reduce the voltage across the transistor directly coupled to the driving node N1 in the reset circuit O1, thereby reducing the leakage current of the transistor, preventing leakage in the display panel and causing display abnormalities such as defective dots, thereby improving the image quality and yield of the display product.

[0087] Continuing to refer to Figure 1, it can be seen that the driving circuit 02 is coupled to multiple driving signal lines V1, the driving node N1 and the light-emitting element L1 respectively, and is used to transmit a light-emitting driving signal to the light-emitting element L1 based on the driving signals provided by the multiple driving signal lines V1 and the potential of the driving node N1, so as to drive the light-emitting element L1 to emit light.

[0088] For example, the driving circuit 02 may also be coupled to the anode of the light emitting element L1. The light emitting element L1 may emit light under the voltage difference between the light emitting driving signal transmitted by the driving circuit 02 and the pull-down power signal provided by the pull-down power line Vss.

[0089] In summary, an embodiment of the present disclosure provides a pixel circuit. The pixel circuit includes a reset circuit and a drive circuit. The reset circuit can control the on-off connection between the first initial power line and the intermediate node, the on-off connection between the intermediate node and the drive node, and the on-off connection between the second initial power line and the intermediate node and the light-emitting element in response to the received reset signal; the drive circuit can drive the light-emitting element to emit light based on the potential of the drive node. Moreover, the absolute value of the potential of the first initial power signal provided by the first initial power line is less than the absolute value of the potential of the second initial power signal provided by the second initial power line. In this way, by flexibly setting each signal, after controlling the first initial power line to transmit the first initial power signal to the drive node, the second initial power line is controlled to transmit the same second initial power signal to the light-emitting element and the intermediate node, thereby reducing the leakage current of the transistor directly coupled to the drive node in the drive circuit. Furthermore, it is ensured that the drive circuit reliably drives the light-emitting element to emit light, so that the display effect of the display panel is better.

[0090] Optionally, FIG2 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present disclosure. As shown in FIG2 , in the pixel circuit provided by an embodiment of the present disclosure, the reset circuit 01 may include: a first reset sub-circuit 011 and a second reset sub-circuit 012 .

[0091] The first reset sub-circuit 011 can be coupled to the first reset line R1, the first initial power line Vinit1, the intermediate node N0 and the driving node N1 respectively, and can be used to control the connection and disconnection of the first initial power line Vinit1 and the intermediate node N0, and control the connection and disconnection of the intermediate node N0 and the driving node N1 in response to the first reset signal.

[0092] For example, when the potential of the first reset signal is a first potential, the first reset sub-circuit 011 can control the first initial power line Vinit1 to be electrically connected to the intermediate node N0, and also control the intermediate node N0 to be electrically connected to the driving node N1, so that the first initial power signal provided by the first initial power line Vinit1 can be sequentially transmitted to the intermediate node N0 and the driving node N1. Furthermore, when the potential of the first reset signal is a second potential, the first reset sub-circuit 011 can control the first initial power line Vinit1 to be decoupled from the intermediate node N0, and also control the intermediate node N0 to be decoupled from the driving node N1.

[0093] The second reset sub-circuit 012 can be coupled to the second reset line R2, the third reset line R3, the second initial power line Vinit2, the intermediate node N0 and the light-emitting element L1 (here referring to the anode of the light-emitting element L1), respectively, and can be used to control the connection and disconnection of the second initial power line Vinit2 and the intermediate node N0 in response to the second reset signal, and can control the connection and disconnection of the second initial power line Vinit2 and the light-emitting element L1 in response to the third reset signal.

[0094] For example, the second reset sub-circuit 012 can control the second initial power line Vinit2 to be conductive with the intermediate node N0 when the potential of the second reset signal is the first potential, so that the second initial power signal provided by the second initial power line Vinit2 is transmitted to the intermediate node N0; and the second reset sub-circuit 012 can control the second initial power line Vinit2 to be decoupled from the intermediate node N0 when the potential of the second reset signal is the second potential.

[0095] Similarly, the second reset sub-circuit 012 can control the second initial power line Vinit2 to be turned on with the light-emitting element L1 when the potential of the third reset signal is the first potential, so that the second initial power signal provided by the second initial power line Vinit2 is transmitted to the light-emitting element L1; and the second reset sub-circuit 012 can control the second initial power line Vinit2 to be disconnected from the light-emitting element L1 when the potential of the third reset signal is the second potential.

[0096] Optionally, FIG3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure. As shown in FIG3 , in the pixel circuit provided by an embodiment of the present disclosure, the second reset subcircuit 012 may include: a first reset unit 0121 and a second reset unit 0122 .

[0097] The first reset unit 0121 may be coupled to the second reset line R2 , the second initial power line Vinit2 and the middle node N0 respectively, and may be used to control the connection and disconnection between the second initial power line Vinit2 and the middle node N0 in response to a second reset signal.

[0098] For example, the first reset unit 0121 can control the second initial power line Vinit2 to be connected to the intermediate node N0 when the potential of the second reset signal is the first potential, so that the second initial power signal provided by the second initial power line Vinit2 is transmitted to the intermediate node N0; and the first reset unit 0121 can control the second initial power line Vinit2 to be disconnected from the intermediate node N0 when the potential of the second reset signal is the second potential.

[0099] The second reset unit 0122 can be coupled to the third reset line R3, the second initial power line Vinit2 and the light emitting element L1 respectively, and can be used to control the connection and disconnection of the second initial power line Vinit2 and the light emitting element L1 in response to the third reset signal.

[0100] For example, the second reset unit 0122 can control the second initial power line Vinit2 to be connected to the light-emitting element L1 when the potential of the third reset signal is the first potential, so that the second initial power signal provided by the second initial power line Vinit2 is transmitted to the light-emitting element L1; and the second reset unit 0122 can control the second initial power line Vinit2 to be disconnected from the light-emitting element L1 when the potential of the third reset signal is the second potential.

[0101] Optionally, Figure 4 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present disclosure. As shown in Figure 4, in the pixel circuit described in the embodiment of the present disclosure, the multiple drive signal lines V1 coupled to the driver circuit 02 may include: a gate line G1, a data line D1, an emission control line EM, and a drive power line Vdd. Accordingly, the driver circuit 02 may include: a first emission control sub-circuit 021, a second emission control sub-circuit 022, a data writing sub-circuit 023, a compensation sub-circuit 024, a driver sub-circuit 025, and a storage sub-circuit 026.

[0102] The first light-emitting control subcircuit 021 can be coupled to the light-emitting control line EM, the driving power line Vdd and the first node N01 respectively, and can be used to control the connection and disconnection of the driving power line Vdd and the first node N01 in response to the light-emitting control signal provided by the light-emitting control line EM.

[0103] For example, the first light-emitting control sub-circuit 021 can control the driving power line Vdd to be connected to the first node N01 when the potential of the light-emitting control signal provided by the light-emitting control line EM is a first potential, so that the driving power signal provided by the driving power line Vdd is transmitted to the first node N01; and the first light-emitting control sub-circuit 021 can control the driving power line Vdd to be disconnected from the first node N01 when the potential of the light-emitting control signal provided by the light-emitting control line EM is a second potential.

[0104] The second light-emitting control subcircuit 022 can be coupled to the light-emitting control line EM, the second node N02 and the light-emitting element L1 (here referring to the anode of the light-emitting element L1) respectively, and can be used to control the on and off of the second node N02 and the light-emitting element L1 in response to the light-emitting control signal.

[0105] For example, the second light-emitting control sub-circuit 022 can control the second node N02 and the light-emitting element L1 to be turned on when the potential of the light-emitting control signal is the first potential, so that the signal transmitted to the second node N02 is further transmitted to the first node N01; and the second light-emitting control sub-circuit 022 can control the second node N02 to be disconnected from the light-emitting element L1 when the potential of the light-emitting control signal is the second potential.

[0106] The data writing sub-circuit 023 may be coupled to the gate line G1 , the data line D1 and the first node N01 respectively, and may be used to control the connection and disconnection between the data line D1 and the first node N01 in response to a gate driving signal provided by the gate line G1 .

[0107] For example, the data writing sub-circuit 023 can control the data line D1 to be conductive with the first node N01 when the potential of the gate driving signal provided by the gate line G1 is a first potential, so that the data signal provided by the data line D1 is transmitted to the first node N01; and the data writing sub-circuit 023 can control the data line D1 to be decoupled from the first node N01 when the potential of the gate driving signal provided by the gate line G1 is a second potential.

[0108] The compensation sub-circuit 024 may be coupled to the gate line G1 , the second node N02 and the driving node N1 , respectively, and may be configured to control the connection and disconnection between the second node N02 and the driving node N1 in response to a gate driving signal.

[0109] For example, the compensation sub-circuit 024 can control the second node N02 and the driving node N1 to be conductive when the potential of the gate driving signal is the first potential, so that the signal transmitted to the second node N02 is further transmitted to the first node N1; and the compensation sub-circuit 024 can control the second node N02 to be decoupled from the driving node N1 when the potential of the gate driving signal is the second potential.

[0110] The driving sub-circuit 025 may be coupled to the driving node N1, the first node N01 and the second node N02 respectively, and may be used to transmit a light-emitting driving signal to the second node N02 based on the potential of the driving node N1 and the potential of the first node N01.

[0111] The storage sub-circuit 026 may be coupled to the driving power line Vdd and the driving node N1 respectively, and may be configured to store the potential of the driving node N1 based on a driving power signal provided by the driving power line Vdd.

[0112] Optionally, based on Figure 4, Figure 5 shows a circuit structure diagram of a pixel circuit. As shown in Figure 5, in the pixel circuit described in the embodiment of the present disclosure, the first reset unit 0121 may include: a first transistor T1.

[0113] A gate of the first transistor T1 may be coupled to the second reset line R2 , a first electrode of the first transistor T1 may be coupled to the second initial power line Vinit2 , and a second electrode of the first transistor T1 may be coupled to the intermediate node N0 .

[0114] Optionally, with continued reference to FIG. 5 , it can be seen that the second reset unit 0122 may include: a second transistor T2 .

[0115] The gate of the second transistor T2 can be coupled to the third reset line R3, the first electrode of the second transistor T2 can be coupled to the second initial power line Vinit2, and the second electrode of the second transistor T2 can be coupled to the light emitting element L1 (here can refer to the anode of the light emitting element L1).

[0116] Optionally, referring to FIG5 , it can be seen that the first reset sub-circuit 011 may include two third transistors T3 with a common gate, respectively labeled as T3 - 1 and T3 - 2 , which may also be called dual-gate transistors.

[0117] The gates of the two third transistors T3-1 and T3-2 may both be coupled to the first reset line R1. Furthermore, of the two third transistors T3-1 and T3-2, the first electrode and the second electrode of one third transistor T3-1 may be coupled to the first initial power line Vinit1 and the intermediate node N0, respectively, and the first electrode and the second electrode of the other third transistor T3-2 may be coupled to the intermediate node N0 and the driving node N1, respectively.

[0118] Of course, this is only an illustrative description. In some other embodiments, the first reset sub-circuit 011 may also include two independent transistors respectively coupled to different reset lines, provided that the potentials of the reset signals provided by the different reset lines are the same.

[0119] Continuing with reference to FIG. 5 , it can be seen that the first light-emission control subcircuit 021 may include a fourth transistor T4. The second light-emission control subcircuit 022 may include a fifth transistor T5. The data writing subcircuit 023 may include a sixth transistor T6. The compensation subcircuit 024 may include a seventh transistor T7. The driving subcircuit 025 may include an eighth transistor T8. The storage subcircuit 026 may include a storage capacitor Cst.

[0120] Among them, the gate of the fourth transistor T4 and the gate of the fifth transistor T5 can both be coupled to the light-emitting control line EM, the first electrode of the fourth transistor T4 can be coupled to the driving power line Vdd, the second electrode of the fourth transistor T4 can be coupled to the first node N01, the first electrode of the fifth transistor T5 can be coupled to the second node N02, and the second electrode of the fifth transistor T5 can be coupled to the light-emitting element L1.

[0121] The gate of the sixth transistor T6 and the gate of the seventh transistor T7 can both be coupled to the gate line G1, the first electrode of the sixth transistor T6 can be coupled to the data line D1, the second electrode of the sixth transistor T6 can be coupled to the first node N01, the first electrode of the seventh transistor T7 can be coupled to the second node N02, and the second electrode of the seventh transistor T7 can be coupled to the driving node N1.

[0122] A gate of the eighth transistor T8 may be coupled to the driving node N1 , a first electrode of the eighth transistor T8 may be coupled to the first node N01 , and a second electrode of the eighth transistor T8 may be coupled to the second node N02 .

[0123] A first terminal of the storage capacitor Cst may be coupled to the driving power line Vdd, and a second terminal of the storage capacitor Cst may be coupled to the driving node N1 .

[0124] That is, the pixel circuit provided in the embodiment of the present disclosure may be an 8T1C (i.e., 8 transistors and 1 capacitor) structure. Of course, in some embodiments, the pixel circuit may also be of other structures, such as 6T2C, provided that it includes the first transistor T1, the second transistor T2, and the third transistor T3 described in the embodiment of the present disclosure. Among them, the third transistor T3 is divided into two transistors T3-1 and T3-2, and the two transistors T3-1 and T3-2 form an electrically connected structure, and also form an electrically connected structure with the first transistor T1, and the first transistor T1 and the second transistor T2 also form an electrically connected structure.

[0125] Based on the above embodiment, combined with the pixel circuit structure shown in Figure 5, it can be seen that first, in the reset phase, a first reset signal of a first potential can be provided to the first reset line R1, so that the two third transistors T3-1 and T3-2 are both turned on, thereby causing the first initial power signal provided by the first initial power line Vinit1 to be transmitted to the intermediate node N0 and the driving node N1 in sequence. Then, after the reset phase, a first reset signal of a second potential can be provided to the first reset line R1, so that the two third transistors T3-1 and T3-2 are both turned off; at the same time, a second reset signal of a first potential can be provided to the second reset line R2, so that the first transistor T1 is turned on, thereby causing the second initial power signal provided by the second initial power line Vinit2 to be transmitted to the intermediate node N0. As a result, the voltage across the third transistor T3-2 directly coupled to the driving node N1 can satisfy: |V Vinit2 -V N1 In the related art, since there is no first transistor T1, after the reset phase, that is, after both third transistors T3-1 and T3-2 are turned off, the voltage across the third transistor T3-2 directly coupled to the driving node N1 is: |V Vinit1 -V N1 |. Because |V Vinit2|<|V Vinit1 Therefore, it can be seen that compared with the related art, the embodiment of the present disclosure can reliably reduce the cross-voltage of the third transistor T3-2, thereby reducing the leakage current of the third transistor T3-2 and preventing the display panel from having display abnormalities such as defective dots.

[0126] The coupled pixel circuit 00 and light-emitting element L1 can be referred to as a pixel. A display panel typically includes multiple pixels arranged in an array, and multiple rows of pixel circuits can sequentially drive the coupled light-emitting elements L1 to emit light. Furthermore, as can be seen in conjunction with FIG5 , the second reset line R2 can be shared with the emission control line EM coupled to the emission control subcircuit 021 in the previous row of pixel circuits. The third reset line R3 can be shared with the first reset line R1 coupled to the reset circuit 01 in the previous row of pixel circuits.

[0127] That is, for the current row of pixel circuits, the first reset signal provided by the coupled first reset line R1 can not only serve as the gate signal of the third transistors T3-1 and T3-2 included therein, but also serve as the gate signal of the second transistor T2 in the previous row of pixel circuits, that is, serve as the third reset signal of the previous row of pixel circuits. The light-emitting control signal provided by the coupled light-emitting control line EM can not only serve as the gate signal of the fourth transistor T4 and the fifth transistor T5 included therein, but also serve as the gate signal of the first transistor T1 in the previous row of pixel circuits, that is, serve as the second reset signal of the previous row of pixel circuits. Therefore, it can also be seen that the second initial power signal provided by the second initial power line Vinit2 can serve as both the initialization signal of the third transistor T3 in the current row of pixel circuits and the initialization signal of the second transistor T2 in the next row of pixel circuits. In addition, in some embodiments, for the current row of pixel circuits, the gate drive signal provided by the coupled gate line G1 and the first reset signal provided by the coupled first reset line R1 of the next row of pixel circuits can be the same signal.

[0128] It should be noted that the gate of each transistor in the pixel circuit can be coupled to a gate driver on array (GOA) circuit to receive a gate signal provided by the GOA circuit. The GOA circuit includes multiple GOA units corresponding to multiple rows of pixel circuits. The gate signal of any of the above-mentioned pixel circuit rows can refer to the signal transmitted to the pixel circuit in that row by the coupled GOA unit.

[0129] Optionally, Figure 6 is a film layer structure diagram of a pixel circuit provided in an embodiment of the present disclosure, which includes two adjacent pixel circuits. Figure 7 is a film layer structure diagram of one of the pixel circuits shown in Figure 6. Figure 8 is a film layer cross-sectional view of the pixel circuit shown in the AA' direction based on Figure 7. In addition, Figure 6 also schematically identifies the position of each transistor in the pixel circuit on the layout.

[0130] As can be seen from Figures 6 to 8 , the pixel circuit provided in the embodiments of the present disclosure may include: an active (ACT) layer, a first conductive layer E1, a second conductive layer E2, and a third conductive layer E3 stacked in sequence, and an insulating layer JX located between any two film layers. For example, the first insulating layer J1 is located between the active layer ACT and the first conductive layer E1, the second insulating layer J2 is located between the first conductive layer E1 and the second conductive layer E2, and the third insulating layer J3 is located between the second conductive layer E2 and the third conductive layer E3.

[0131] As can be seen in Figures 6 and 7 , the active layer ACT and the first conductive layer E1 can be configured to form transistors in the pixel circuit. Furthermore, the first conductive layer E1 can also be configured to form a first reset line R1, a second reset line R2, a third reset line R3, a gate line G1, and an emission control line EM. In other words, the first conductive layer E1 primarily connects reset signals, gate drive signals, and emission control signals. The second reset line R2 and the third reset line R3 are not shown in Figures 6 and 7 .

[0132] That is, as shown in Figure 8, the active layer ACT can be located at the bottom layer, close to one side of the substrate 10 in the display panel, to conduct drive signals. The orthographic projection of the first conductive layer E1 on the substrate 10 can be located within the orthographic projection of the active layer ACT on the substrate 10, but the two are not connected. In this way, the flow of carriers in the active layer ACT can be controlled by the voltage on the first conductive layer E1.

[0133] Optionally, as described in the above embodiment, the transistors in the pixel circuit provided by the embodiment of the present disclosure may include P-type transistors. Accordingly, the active layer ACT may include: a P-type conductive layer.

[0134] Optionally, the first conductive layer E1 may include a gate metal layer GATE. That is, the first conductive layer E1 here may refer to the gate metal layer GATE.

[0135] 6 and 7 , it can be seen that the second conductive layer E2 can be configured to form a first initial power line Vinit1 and a second initial power line Vinit2 . That is, the second conductive layer E2 can mainly connect the first initial power signal and the second initial power signal.

[0136] Optionally, the second conductive layer E2 may also include a gate metal layer GATE. That is, the second conductive layer E2 may also be referred to as the gate metal layer GATE. For purposes of distinction, the first conductive layer E1 is generally referred to as the first gate metal layer GATE1, and the second conductive layer E2 is generally referred to as the second gate metal layer GATE2.

[0137] 6 and 7 , it can be seen that the third conductive layer E3 can be configured to overlap the active layer ACT and the second conductive layer E2 respectively through vias penetrating the insulating layer to transfer the active layer ACT and the second conductive layer E2 to form an electrical connection structure.

[0138] Optionally, as can be seen in conjunction with FIG8 , the third conductive layer E3 can overlap with the active layer ACT through a via H1 penetrating the third insulating layer J3, the second insulating layer J2, and the first insulating layer J1, and can overlap with the second conductive layer E2 through a via H2 penetrating the third insulating layer J3. Accordingly, it can be seen that the orthographic projection of the third conductive layer E3 on the substrate 10 can overlap with the orthographic projection of the active layer ACT on the substrate 10, and can overlap with the orthographic projection of the second conductive layer E2 on the substrate 10. The orthographic projection of the second conductive layer E2 on the substrate 10 may not overlap with the orthographic projection of the active layer ACT on the substrate 10, and may not overlap with the orthographic projection of the first conductive layer E1 on the substrate 10.

[0139] Optionally, the third conductive layer E3 may include a source and drain (SD) metal layer. That is, the third conductive layer E3 here may refer to a source and drain metal layer SD.

[0140] Optionally, based on FIG8 , the following embodiment illustrates the preparation process of the pixel circuit:

[0141] (1) Step 1: Provide a substrate 10 and provide an active layer ACT on one side of the substrate 10 .

[0142] Optionally, the active layer ACT may include the P-type conductive layer described in the above embodiment. In addition, the material of the active layer ACT may include semiconductor materials such as amorphous silicon (A-Si) or gallium arsenide (GaAs).

[0143] For example, FIG9 shows a film structure diagram including a substrate 10 and an active layer ACT.

[0144] (2) Step 2: A first insulating layer J1, a first gate metal layer GATE1 (i.e., a first conductive layer E1), a second insulating layer J2, and a second gate metal layer GATE2 (i.e., a second conductive layer E2) are stacked in sequence on the side of the active layer ACT away from the substrate 10.

[0145] Optionally, the material of the first insulating layer J1 and the second insulating layer J2 may include silicon nitride (SiN) or silicon oxide (SiO); the material of the first gate metal layer GATE1 and the second gate metal layer GATE2 may include metal molybdenum (Mo) or metal copper (Cu).

[0146] For example, FIG10 shows a film structure diagram including a substrate 10, an active layer ACT, a first insulating layer J1, a first gate metal layer GATE1, a second insulating layer J2 and a second gate metal layer GATE2.

[0147] (3) Step 3: A third insulating layer J3 is provided on a side of the second gate metal layer GATE away from the substrate 10, and holes are punched at positions corresponding to the active layer ACT and the second gate metal layer GATE, that is, via holes H1 penetrating the third insulating layer J3, the second insulating layer J2, and the first insulating layer J1, as well as via holes H2 penetrating the third insulating layer J3, as described in the above embodiment, are provided to facilitate the subsequent formation of an electrical connection structure.

[0148] Optionally, the material of the third insulating layer J3 may also include silicon nitride SiN or silicon oxide SiO.

[0149] For example, FIG11 shows a film structure diagram including a substrate 10, an active layer ACT, a first insulating layer J1, a first gate metal layer GATE1, a second insulating layer J2, a second gate metal layer GATE2 and a third insulating layer J3.

[0150] (4) Step 4: A source / drain metal layer SD (i.e., the third conductive layer E3) is provided on the side of the third insulating layer J3 away from the substrate 10. The source / drain metal layer SD is connected to the active layer ACT and the second gate metal layer GATE2 through the vias H1 and H2 opened in Step 3, respectively, to form an electrical connection structure. Subsequently, a planarization layer (PLN) may be further provided on the side of the source / drain metal layer SD away from the substrate 10 to planarize the prepared film layer and facilitate the provision of subsequent process film layers. The subsequent process film layers may include the anode, light-emitting layer, and cathode of the light-emitting element L1.

[0151] Optionally, the material of the source / drain metal layer SD may include metal aluminum (Al) and / or metal titanium (Ti).

[0152] For example, FIG12 shows a film structure diagram including a substrate 10, an active layer ACT, a first insulating layer J1, a first gate metal layer GATE1, a second insulating layer J2, a second gate metal layer GATE2, a third insulating layer J3, a source / drain metal layer SD and a planar layer PLN.

[0153] It should be noted that the above film structure, film materials, and preparation steps are merely illustrative. Furthermore, during the preparation process, a mask can be used to form the desired film layer through a patterning process. A single patterning process may include multiple exposure, development, or etching processes.

[0154] In summary, an embodiment of the present disclosure provides a pixel circuit. The pixel circuit includes a reset circuit and a drive circuit. The reset circuit can control the on-off connection between the first initial power line and the intermediate node, the on-off connection between the intermediate node and the drive node, and the on-off connection between the second initial power line, the intermediate node and the light-emitting element in response to the received reset signal; the drive circuit can drive the light-emitting element to emit light based on the potential of the drive node. Moreover, the absolute value of the potential of the first initial power signal provided by the first initial power line is less than the absolute value of the potential of the second initial power signal provided by the second initial power line. In this way, by flexibly setting each signal, after controlling the first initial power line to transmit the first initial power signal to the drive node, the second initial power line is controlled to transmit the same second initial power signal to the light-emitting element and the intermediate node, thereby reducing the leakage current of the transistor directly coupled to the drive node in the drive circuit. Furthermore, it is ensured that the drive circuit reliably drives the light-emitting element to emit light, so that the display effect of the display panel is better.

[0155] FIG13 is a flow chart of a method for driving a pixel circuit according to an embodiment of the present disclosure, which can be applied to the pixel circuit described in the above embodiment. As shown in FIG13 , the method includes:

[0156] Step 1301, in the first stage, the reset circuit controls the first initial power line to be conductive with the intermediate node in response to the first reset signal provided by the first reset line, and controls the intermediate node to be conductive with the driving node, so that the first initial power signal provided by the first initial power line is transmitted to the driving node.

[0157] Step 1302, in the second stage, the reset circuit controls the second initial power line and the intermediate node to be connected in response to the second reset signal, and controls the second initial power line and the light-emitting element to be connected in response to the third reset signal, so that the second initial power signal provided by the second initial power line is transmitted to the intermediate node and the light-emitting element respectively.

[0158] Step 1303, the third stage: In response to the second reset signal, the reset circuit controls the second initial power line to be conductively connected to the intermediate node, so that the second initial power signal is transmitted to the intermediate node. Furthermore, based on the drive signals provided by the multiple drive signal lines and the potential of the drive node, the drive circuit transmits a light-emitting drive signal to the light-emitting element to drive the light-emitting element to emit light.

[0159] The absolute value of the potential of the first initial power signal is smaller than the absolute value of the potential of the second initial power signal.

[0160] Alternatively, taking the structure shown in FIG5 , where the transistor is a P-type transistor, the effective potential is a low potential, and the ineffective potential is a high potential, as an example, FIG14 shows a timing diagram of the source-drain voltage difference Vds of the third transistor T3-2 directly coupled to the driving node N1. The abscissa represents time, and the ordinate represents the absolute value of the source-drain voltage difference Vds, |T3-2 Vds|. The operating principle of the pixel circuit is described below in conjunction with the accompanying drawings:

[0161] (1) In the first phase t01, the potential of the first reset signal provided by the first reset line R1 can be a low potential. Accordingly, the two third transistors T3-1 and T3-2 are both turned on, so that the first initial power line Vinit1 is conductive with the intermediate node N0, and the intermediate node N0 is conductive with the driving node N1. Furthermore, the first initial power signal provided by the first initial power line Vinit1 can be transmitted to the intermediate node N0 through the turned-on third transistor T3-1, and then transmitted to the driving node N1 through the turned-on third transistor T3-2 to reset the driving node N1. At this time, it can be seen from Figure 14 that in the first phase t01, the absolute value of the source-drain voltage difference of the third transistor T3-2 |T3-2 Vds|=0. The first phase t01 can also be called a reset phase.

[0162] In addition, in the first stage t01, the potential of the second reset signal provided by the second reset line R2, the potential of the third reset signal provided by the third reset line R3, the potential of the gate drive signal provided by the gate line G1, and the potential of the light-emitting control signal provided by the light-emitting control line EM can all be high potentials, so that all transistors in the pixel circuit except the two third transistors T3-1 and T3-2 are turned off.

[0163] (2) In the second phase t02, the potential of the gate drive signal provided by the gate line G1 can be low. Accordingly, the sixth transistor T6 and the seventh transistor T7 are both turned on. Moreover, since the first initial power signal with a low potential is transmitted to the driving node N1 in the first phase t01, the potential of the driving node N1 can be maintained at the first initial power signal with a low potential under the storage effect of the storage capacitor Cst, so that the eighth transistor T8 is turned on. Furthermore, the data signal provided by the data line D1 can be transmitted to the driving node N1 through the turned-on sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. The second phase t02 can also be called the data writing phase.

[0164] Furthermore, in the second phase t02, the potential of the first reset signal provided by the first reset line R1 can be a high potential, and the potential of the second reset signal provided by the second reset line R2 can be a low potential. Accordingly, the two third transistors T3-1 and T3-2 can both be turned off, and the first transistor T1 can be turned on, so that the second initial power signal provided by the second initial power line Vinit2 can be transmitted to the intermediate node N0. At this time, combined with Figure 14, it can be seen that in the second phase t02, the absolute value of the source-drain voltage difference of the third transistor T3-2 |T3-2Vds|=|V Vinit2 -V N1 As described in the above embodiment, V Vinit2 Refers to the potential of the second initial power supply signal; V N1 It refers to the potential of the driving node N1.

[0165] In addition, in the second phase t02 , the potentials of the light emitting control signals provided by the light emitting control line EM may all be high, so that the fourth transistor T4 and the fifth transistor T5 are both turned off.

[0166] (3) In the third stage t03, under the storage effect of the storage capacitor Cst, the potential of the driving node N1 can be maintained at a low potential, so that the eighth transistor T8 remains on. In addition, the potential of the light-emitting control signal provided by the light-emitting control line EM can be a low potential. Accordingly, the fourth transistor T4 and the fifth transistor T5 can both be turned on, so that a path is formed between the driving power line Vdd and the light-emitting element L1 through the fourth transistor T4, the eighth transistor T8, and the fifth transistor T5. The eighth transistor T8 can transmit a light-emitting drive signal to the anode of the light-emitting element L1 based on the potential of the driving node N1 and the driving power signal provided by the driving power line Vdd, thereby driving the light-emitting element L1 to emit light. The third stage t03 can also be called a light-emitting stage.

[0167] Furthermore, in the third phase t03, the potential of the first reset signal provided by the first reset line R1 can be a high potential, and the potential of the second reset signal provided by the second reset line R2 can be a low potential. Accordingly, both third transistors T3-1 and T3-2 can be turned off, and the first transistor T1 can be turned on, so that the second initial power signal provided by the second initial power line Vinit2 can be transmitted to the intermediate node N0. At this time, combined with Figure 14, it can be seen that in the third phase t03, the absolute value of the source-drain voltage difference of the third transistor T3-2 |T3-2Vds|=|V Vinit2 -V N1 |.

[0168] Furthermore, in the third phase t03 , the potential of the third reset signal provided by the third reset line R3 and the potential of the gate drive signal provided by the gate line G1 may both be high, so that the second transistor T2 , the sixth transistor T6 and the seventh transistor T7 are all turned off.

[0169] It should be noted that in a stage before the third stage t03, the potential of the third reset signal provided by the third reset line R3 can be a low potential, so that the second transistor T2 is turned on, and the second initial power signal provided by the second initial power line Vinit2 can be transmitted to the anode of the light-emitting element L1 to reset the anode of the light-emitting element L1, ensuring that different light-emitting elements L1 emit light based on the same second initial power signal, thereby ensuring that the display uniformity of the display panel can be better.

[0170] Optionally, in combination with the above-mentioned embodiment, the pixel circuit in the related art is generally a 7T1C structure, that is, the first transistor T1 shown in Figure 5 is not included, and the two third transistors T3-1 and T3-2 can be regarded as one transistor. On this basis, Figure 15 shows the absolute value of the source-drain voltage difference of the third transistor T3 in the first stage t01 to the third stage t03 in the related art |T3 Vds|. It can be seen from Figure 15 that since the first transistor T1 is not included in writing the second initial power supply signal to the intermediate node N0, the absolute value of the source-drain voltage difference of the third transistor T3 |T3 Vds|=|V Vinit1 -V N1 As described in the above embodiment, V Vini1 Refers to the potential of the first initial power supply signal.

[0171] Since the absolute value of the potential of the first initial power signal is smaller than the absolute value of the potential of the second initial power signal, that is, |V Vinit1 |>|V Vinit2 |, so we know |V Vinit2 -V N1 |<|V Vinit1 -V N1 That is, compared to pixel circuits in related arts, the pixel circuit provided by the embodiment of the present disclosure can effectively reduce the voltage across the transistor directly coupled to the drive node N1 in the reset circuit O1, thereby reducing the leakage current of the transistor, preventing display anomalies such as pixel defects on the display panel, and thereby improving the image quality and yield of the display panel.

[0172] That is, in the disclosed embodiment, the second initial power signal provided by the second initial power line Vinit2 can be used as the initialization signal for the third transistor T3, converting the initialization signal of the third transistor T3 from a DC signal to a square wave signal. In the first phase t01, the first initial power signal provided by the first initial power line Vinit1 serves as the input signal for the third transistor T3, ensuring a sufficiently low initialization voltage to reliably reset the driving node N1. In the second phase t02 and the third phase t03, the second initial power signal provided by the second initial power line Vinit2 serves as the input signal for the third transistor T3, ensuring a low voltage across the transistor T3-2 in the third transistor T3 that is directly coupled to the driving node N1.

[0173] Since the driving method can have substantially the same technical effects as the pixel circuit described in the previous embodiment, the technical effects of the driving method will not be repeatedly described here for the purpose of brevity.

[0174] FIG16 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure. As shown in FIG16 , the display panel includes: a substrate 10 and a plurality of pixels P1 located on the substrate 10 .

[0175] 1 , the pixel P1 may include: a light emitting element L1 and a pixel circuit 00 as described in the above embodiment. The pixel circuit 00 is coupled to the light emitting element L1 and is used to drive the light emitting element L1 to emit light.

[0176] Alternatively, Figure 17 shows a schematic structural diagram of another display panel. As shown in Figure 17, multiple pixels P1 can be arranged in an array. That is, the display surface can include multiple rows and columns of pixels P1.

[0177] On this basis, combined with Figure 6, it can be seen that the first reset line R1, gate line G1, light-emitting control line EM, second initial power line Vinit2 and first initial power line Vinit1 coupled to the pixel circuit in each pixel P1 can be arranged in sequence along the pixel column direction Y, and the pixel column direction Y intersects with the pixel row direction X, and are perpendicular to each other as shown in Figure 6.

[0178] In addition, it can be seen from Figure 17 that the first initial power line Vinit1 can be coupled to the power supply terminal providing the first initial power signal through the first initial power lead Vinit10, and the second initial power line Vinit2 can be coupled to the power supply terminal providing the second initial power signal through the second initial power lead Vinit20. The first initial power lead Vinit10 and the second initial power lead Vinit20 can be arranged around multiple pixels P1 and can be spaced apart from each other. The surrounding here can refer to partial surrounding as shown in Figure 17. The power supply terminal can be integrated into the integrated circuit (IC) shown in Figure 17. In this way, wiring can be facilitated, which is beneficial to the narrow frame design of the display panel. Of course, the arrangement shown in Figure 17 is only a schematic illustration.

[0179] Optionally, referring to FIG17 , in some embodiments, the display panel may further include a camera hole, in which a camera assembly may be provided for capturing images. Of course, other components such as a speaker and a microphone may also be included, which is not limited in the present disclosure.

[0180] Since the display panel can have substantially the same technical effects as the pixel circuit described in the previous embodiment, the technical effects of the display panel will not be repeatedly described here for the purpose of brevity.

[0181] FIG18 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG18 , the display device includes: a display driving circuit 100 and a display panel 000 as described in the above embodiment.

[0182] The display driver circuit 100 can be coupled to a signal line (eg, gate line G1) in the display panel 000 and used to provide signals to the signal line. The display driver circuit 100 can include the IC shown in FIG17 and can also include the GOA circuit described in the above embodiment.

[0183] Optionally, the display device may be an OLED display device or an active-matrix organic light-emitting diode (AMOLED) display device, etc. OLED display technology has been widely recognized by the market due to its advantages such as high resolution and high contrast.

[0184] Optionally, the display device may also include: any product or component with a display function, such as a mobile phone, a tablet computer, a flexible display device, a television, and a monitor.

[0185] Since the display device can have substantially the same technical effects as the display panel described in the previous embodiment, the technical effects of the display device will not be repeatedly described here for the purpose of brevity.

[0186] It should be noted that the terms used in the examples of this disclosure are only used to explain the examples and are not intended to limit the present disclosure. Unless otherwise defined, technical terms or scientific terms used in the embodiments of this disclosure should have the common meanings understood by people with ordinary skills in the field to which this disclosure belongs.

[0187] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0188] When we say an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intermediate elements may be present. In addition, "connected" or "coupled" as used herein may include wireless connection or wireless coupling.

[0189] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0190] Words such as “include” or “comprising” mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0191] “Up,” “down,” “left,” or “right” are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0192] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A pixel circuit for coupling with a light emitting element; The pixel circuit comprises: a reset circuit, coupled to the first reset line, the second reset line, the third reset line, the first initial power line, the second initial power line, the intermediate node, the driving node and the light-emitting element, respectively, and used to control the connection and disconnection between the first initial power line and the intermediate node in response to a first reset signal provided by the first reset line, and control the connection and disconnection between the intermediate node and the driving node, control the connection and disconnection between the second initial power line and the intermediate node in response to a second reset signal provided by the second reset line, and control the connection and disconnection between the second initial power line and the light-emitting element in response to a third reset signal provided by the third reset line; A driving circuit, coupled to the plurality of driving signal lines, the driving node and the light-emitting element, respectively, and configured to transmit a light-emitting driving signal to the light-emitting element based on the driving signals provided by the plurality of driving signal lines and the potential of the driving node, so as to drive the light-emitting element to emit light; The absolute value of the potential of the first initial power signal provided by the first initial power line is smaller than the absolute value of the potential of the second initial power signal provided by the second initial power line.

2. The pixel circuit according to claim 1, wherein: The reset circuit comprises: a first reset subcircuit, coupled to the first reset line, the first initial power line, the intermediate node and the driving node respectively, and used to control the connection and disconnection between the first initial power line and the intermediate node, and control the connection and disconnection between the intermediate node and the driving node in response to the first reset signal; The second reset subcircuit is coupled to the second reset line, the third reset line, the second initial power line, the intermediate node and the light-emitting element, respectively, and is used to control the connection and disconnection of the second initial power line and the intermediate node in response to the second reset signal, and to control the connection and disconnection of the second initial power line and the light-emitting element in response to the third reset signal.

3. The pixel circuit according to claim 2, wherein: The second reset sub-circuit comprises: a first reset unit, coupled to the second reset line, the second initial power line and the intermediate node respectively, and used to control the connection and disconnection of the second initial power line and the intermediate node in response to the second reset signal; The second reset unit is coupled to the third reset line, the second initial power line and the light emitting element respectively, and is used to control the connection and disconnection of the second initial power line and the light emitting element in response to the third reset signal.

4. The pixel circuit according to claim 3, wherein: The first reset unit includes: a first transistor; A gate of the first transistor is coupled to the second reset line, a first electrode of the first transistor is coupled to the second initial power line, and a second electrode of the first transistor is coupled to the intermediate node.

5. The pixel circuit according to claim 3 or 4, wherein: The second reset unit includes: a second transistor; A gate of the second transistor is coupled to the third reset line, a first electrode of the second transistor is coupled to the second initial power line, and a second electrode of the second transistor is coupled to the light emitting element.

6. The pixel circuit according to any one of claims 2 to 5, wherein: The first reset subcircuit comprises: two third transistors with a common gate; The gates of the two third transistors are both coupled to the first reset line, and, among the two third transistors, the first pole and the second pole of one third transistor are respectively coupled to the first initial power line and the intermediate node, and the first pole and the second pole of the other third transistor are respectively coupled to the intermediate node and the driving node.

7. The pixel circuit according to any one of claims 1 to 6, wherein: The plurality of driving signal lines include: a gate line, a data line, a light emitting control line and a driving power line; the driving circuit includes: A first light-emitting control subcircuit is coupled to the light-emitting control line, the driving power line and the first node respectively, and is used to control the connection and disconnection of the driving power line and the first node in response to a light-emitting control signal provided by the light-emitting control line; A second light-emitting control subcircuit is coupled to the light-emitting control line, the second node and the light-emitting element respectively, and is used to control the on-off of the second node and the light-emitting element in response to the light-emitting control signal; A data writing subcircuit is coupled to the gate line, the data line and the first node respectively, and is used to control the data line and the first node in response to a gate driving signal provided by the gate line. On / off; A compensation subcircuit, coupled to the gate line, the second node and the driving node respectively, and used to control the connection and disconnection of the second node and the driving node in response to the gate driving signal; a driving subcircuit, coupled to the driving node, the first node and the second node respectively, and configured to transmit a light-emitting driving signal to the second node based on a potential of the driving node and a potential of the first node; The storage sub-circuit is coupled to the driving power line and the driving node respectively, and is used to store the potential of the driving node based on the driving power signal provided by the driving power line.

8. The pixel circuit according to claim 7, wherein: The first light-emitting control subcircuit includes: a fourth transistor; the second light-emitting control subcircuit includes: a fifth transistor; the data writing subcircuit includes: a sixth transistor; the compensation subcircuit includes: a seventh transistor; the driving subcircuit includes: an eighth transistor; the storage subcircuit includes: a storage capacitor; The gate of the fourth transistor and the gate of the fifth transistor are both coupled to the light emitting control line, the first electrode of the fourth transistor is coupled to the driving power line, the second electrode of the fourth transistor is coupled to the first node, the first electrode of the fifth transistor is coupled to the second node, and the second electrode of the fifth transistor is coupled to the light emitting element; The gate of the sixth transistor and the gate of the seventh transistor are both coupled to the gate line, the first electrode of the sixth transistor is coupled to the data line, the second electrode of the sixth transistor is coupled to the first node, the first electrode of the seventh transistor is coupled to the second node, and the second electrode of the seventh transistor is coupled to the driving node; The gate of the eighth transistor is coupled to the driving node, the first electrode of the eighth transistor is coupled to the first node, and the second electrode of the eighth transistor is coupled to the second node; A first end of the storage capacitor is coupled to the driving power line, and a second end of the storage capacitor is coupled to the driving node.

9. The pixel circuit according to claim 7 or 8, wherein: The plurality of rows of pixel circuits drive the coupled light-emitting elements to emit light row by row; The second reset line is shared with a light emitting control line coupled to a light emitting control subcircuit in a previous row of pixel circuits; the third reset line is shared with a first reset line coupled to a reset circuit in a previous row of pixel circuits.

10. The pixel circuit according to any one of claims 7 to 9, wherein: The pixel circuit comprises: an active layer, a first conductive layer, a second conductive layer and a third conductive layer stacked in sequence, and an insulating layer located between any two film layers; Wherein, the active layer and the first conductive layer are configured to form a transistor in the pixel circuit; and the first conductive layer is further configured to form the first reset line, the second reset line, the third reset line, the gate line and the light emitting control line; The second conductive layer is configured to form the first initial power line and the second initial power line; The third conductive layer is configured to overlap the active layer and the second conductive layer respectively through via holes penetrating the insulating layer, so as to transfer the active layer to the second conductive layer.

11. The pixel circuit according to claim 10, wherein: The transistor in the pixel circuit includes a P-type transistor; The active layer includes: a P-type conductive layer; the first conductive layer and the second conductive layer both include: a gate metal layer; the third conductive layer includes: a source-drain metal layer.

12. A method for driving a pixel circuit, applied to the pixel circuit according to any one of claims 1 to 11; the method comprising: In the first stage, the reset circuit controls the first initial power line to be connected to the intermediate node in response to the first reset signal provided by the first reset line, and controls the intermediate node to be connected to the driving node, so that the first initial power signal provided by the first initial power line is transmitted to the driving node; In the second stage, the reset circuit controls the second initial power line to be connected to the intermediate node in response to the second reset signal, and controls the second initial power line to be connected to the light-emitting element in response to the third reset signal, so that the second initial power signal provided by the second initial power line is transmitted to the intermediate node and the light-emitting element respectively; In the third stage, the reset circuit controls the second initial power line to be connected to the intermediate node in response to the second reset signal, so that the second initial power signal is transmitted to the intermediate node; The driving circuit transmits a light-emitting driving signal to the light-emitting element based on the driving signals provided by the plurality of driving signal lines and the potential of the driving node, so as to drive the light-emitting element to emit light; The absolute value of the potential of the first initial power signal is smaller than that of the second initial power signal. The absolute value of the potential.

13. A display panel, comprising: a substrate, and a plurality of pixels located on the substrate; Wherein, the pixel comprises: a light-emitting element, and a pixel circuit as described in any one of claims 1 to 11; the pixel circuit is coupled to the light-emitting element and is used to drive the light-emitting element to emit light.

14. The display panel according to claim 13, wherein: The plurality of pixels are arranged in an array; Wherein, the first reset line, the gate line, the light emitting control line, the second initial power line and the first initial power line coupled to the pixel circuit in each pixel are sequentially arranged in intervals along the pixel column direction; Furthermore, the first initial power line is coupled to a power terminal providing a first initial power signal through a first initial power lead, and the second initial power line is coupled to a power terminal providing a second initial power signal through a second initial power lead; the first initial power lead and the second initial power lead are arranged around the multiple pixels and are spaced apart from each other.

15. A display device, comprising: A display driving circuit, and a display panel as claimed in claim 13 or 14; Wherein, the display driving circuit is coupled to the signal line in the display panel and is used to provide a signal to the signal line.

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