Power-on auto-start‌ circuit and computing power board

Abstract

Disclosed in the present application are a power-on auto-start circuit and a computing power board. The circuit provided by the present application comprises: a power supply, a control module, a current control device, and a power management chip. A first power supply end of the power supply is electrically connected to a first end of the power management chip, and a second power supply end of the power supply is electrically connected to a first end of the control module. A first end of the current control device is electrically connected to a second end of the power management chip, and a second end of the current control device is grounded. A second end of the control module is electrically connected to the second end and a control end of the current control device. The control module is used for controlling, by means of the control end, the first end and the second end of the current control device to be turned on after power-on for a first duration, and to be turned off after power-on for a second duration, the second duration being greater than the first duration.

Description

A power-on circuit and computing power board

[0001] Cross-references

[0002] This application claims priority to a Chinese patent application filed with the Patent Office of China on December 1, 2023, with application number 202311648233.8 and invention name “A power-on circuit and computing power board”. The entire contents of that application are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of electronic circuits, and in particular to a power-on circuit and a computing power board. Background Art

[0004] In the field of electronic circuits, traditional electronic devices are often provided with a power button. When the user presses the power button, a specific power-on signal is generated to trigger the power management chip to turn on and start the entire electronic device.

[0005] With the diversification of electronic devices, some electronic devices no longer have a power button, and directly powering on cannot generate the power-on signal required for the power management chip to start up.

[0006] How to realize the automatic power-on function of the circuit is the technical problem to be solved by this application.

[0007] Summary of the Invention

[0008] The purpose of the embodiments of the present application is to provide a circuit and a computing power board that can be powered on.

[0009] In a first aspect, a power-on circuit is provided, comprising: a power supply, a control module, a current control device and a power management chip; the first power supply end of the power supply is electrically connected to the first end of the power management chip, and the second power supply end of the power supply is electrically connected to the first end of the control module; the first end of the current control device is electrically connected to the second end of the power management chip, and the second end of the current control device is grounded; the second end of the control module is electrically connected to the second end of the current control device and the control end, and the control module is used to control the first end and the second end of the current control device to be turned on after a first time period after power-on, and to be turned off after a second time period after power-on, and the second time period is greater than the first time period.

[0010] In a second aspect, a power-on computing board is provided, wherein the power-on computing board includes the power-on circuit described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0012] FIG1a is a schematic diagram of a circuit structure of a power-on circuit according to an embodiment of the present application;

[0013] FIG1 b is a schematic diagram showing a voltage variation trend of a power management chip after power-on of a power-on circuit according to an embodiment of the present application;

[0014] FIG2 is a second circuit structure diagram of a power-on circuit according to an embodiment of the present application;

[0015] FIG3 is a third circuit structure diagram of a power-on circuit according to an embodiment of the present application;

[0016] FIG4 is a fourth circuit structure diagram of a power-on circuit according to an embodiment of the present application;

[0017] FIG5 a is a fifth circuit structure diagram of a power-on circuit according to an embodiment of the present application;

[0018] FIG5 b is a voltage diagram of a power-on circuit based on FIG5 a . DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. The figure numbers in this application are only used to distinguish the various steps in the scheme and are not used to limit the execution order of the various steps. The specific execution order is subject to the description in the specification.

[0020] With the development of technology, terminal products have various ways to start up, such as using a power button or plugging in a USB (Universal Serial Bus) to start up.

[0021] Traditional end products often include a power button (Flexible Printed Circuit), a battery, and a charging management circuit. Pressing the power button generates a voltage-changing power-on signal, which triggers the power chip to power on, ultimately powering up the entire product. This button-powered approach is limited by the FPC, making it difficult to implement in some newer, less-advanced projects without a power button.

[0022] The USB-powered boot method is limited by battery and charge management circuitry. This requires the end product to have a battery, making it unusable for some products with reduced charging capabilities. After detecting the USB voltage, the chip platform must detect the relevant power source within a very short period of time. However, in products with reduced charging capabilities, the USB cannot directly provide power and requires a separate power supply, which fails to meet the timing requirements for USB booting. Alternatively, the product would need to add an additional USB port and complicate the boot process.

[0023] In practical applications, power management chips are often used to power on devices that don't require power, or to automatically power on computing servers. Specifically, computing server applications may involve unusual power outages followed by power restoration. In these power restoration scenarios, the computing server needs to automatically boot up as soon as possible after powering up to minimize losses caused by the power outage. Manual button startup methods often make it difficult to immediately power up the computing server. Furthermore, the startup signals for computing server power management chips are complex; simple high-level signals are insufficient to trigger the chip's automatic startup.

[0024] For terminal products without a power button, how to generate a power-on signal with voltage changes after power-on to trigger the power chip to start up is a technical problem that needs to be solved urgently.

[0025] The present invention provides a circuit for powering on a device, which can be applied to electronic devices such as terminals and computing servers that require self-starting upon powering on. As shown in Figure 1a, the circuit provided by this solution includes:

[0026] A power supply 11, a control module 12, a current control device 13 and a power management chip 14; the first power supply end 11a of the power supply is electrically connected to the first end 14a of the power management chip, and the second power supply end 11b of the power supply is electrically connected to the first end 12a of the control module; the first end 13a of the current control device is electrically connected to the second end 14b of the power management chip, and the second end 13b of the current control device is grounded; the second end 12b of the control module is electrically connected to the second end 13b of the current control device and the control end 13c; the control module 12 is used to control the first end 13a and the second end 13b of the current control device through the control end 13c to be turned on after a first time period after power-on, and to be turned off after a second time period after power-on, and the second time period is greater than the first time period.

[0027] This application discloses an automatic power-on circuit for terminal projects and computing server projects that do not require a power-on button FPC. When the product is connected to an external power source, the automatic power-on circuit generates a signal that triggers the power management chip to automatically power on the product. This application achieves the purpose of automatic power-on of the product by building a purely hardware circuit, meeting the power-on detection requirements of the chip platform, thereby achieving automatic power-on, with the advantages of low cost and high reliability.

[0028] This solution can be applied to special scenarios where power is restored after an abnormal power outage. Traditional button products often require manual operation to start up, while this application can achieve timely power-on and automatic startup, reducing or avoiding the losses caused by the inability to automatically start up after power is restored.

[0029] FIG1 b is a schematic diagram showing the voltage variation trend of the power management chip after power-on, wherein the abscissa represents time T and the ordinate represents voltage V. In this example, it is assumed that power is turned on at the origin time.

[0030] Within a first period of time after power-on, since the first terminal and the second terminal of the current control device are in an off state, the power management chip is in a high level state.

[0031] After a first period of time after power-on, the current control device is turned on under the control of the control module, thereby causing the voltage of the power management chip to drop, as indicated by the voltage drop arrow in FIG. 1 b .

[0032] After a second period of time after power-on, the current control device is turned off again, causing the power management chip to return to a high level state again, as indicated by the voltage rising arrow in FIG1 b .

[0033] In this example, the second duration is greater than the first duration, so that after power-on, the voltage first decreases and then increases. The first duration is greater than or equal to 0 and less than the second duration. The first and second durations can be pre-set based on the startup timing requirements of the electronic device in actual application.

[0034] In an embodiment of the present application, the circuit for powering on includes a power supply, a control module, a current control device and a power management chip. The power supply supplies power to the control module and the power management chip respectively, and the control module controls the control end of the current control device based on a preset duration. Within the first duration after power-on, since the first end and the second end of the current control device are in an off state, the power management chip is in a high level state. After the first duration after power-on, the current control device is turned on under the control of the control module, thereby causing the voltage of the power management chip to drop. After the second duration after power-on, the current control device is turned off again, causing the power management chip to return to a high level state again. In the circuit for powering on provided by this solution, the voltage of the power management chip after power-on has a change from high level to low level to high level, thereby simulating the voltage change formed by the user pressing the power button, forming a start signal to control the start of the power management chip, thereby realizing power-on of the circuit.

[0035] Based on the circuit provided in the above embodiment, in one embodiment, as shown in Figure 2, the control module includes a first resistor R1, a first capacitor C1 and a second capacitor C2; the first end R1a of the first resistor is electrically connected to the first power supply end 11b of the power supply, and the second end R1b of the first resistor is electrically connected to the first end C1a of the first capacitor and the first end C2a of the second capacitor; the second end C1b of the first capacitor is grounded; and the second end C2b of the second capacitor is electrically connected to the control end 13c of the current control device.

[0036] In actual applications, if the automatic power-on circuit only outputs a simple rising edge or falling edge waveform, it cannot effectively trigger the power management chip to start. The power-on waveform required by electronic equipment platforms such as mobile phones is relatively complex, including both rising and falling edges, as well as timing requirements.

[0037] In the circuit provided in the embodiment of the present application, the control module includes a resistor and a capacitor. After the circuit is powered on, the power supply quickly charges the first capacitor and the second capacitor through the first resistor. Subsequently, the current through the second capacitor rises rapidly from 0. When the voltage of the control terminal connected to the second capacitor reaches a certain value, the first terminal and the second terminal of the current control device are connected, so that after power is turned on, the power management chip forms a voltage change based on the high level after power-on, which first drops and then rises, thereby effectively starting the power management chip.

[0038] Based on the circuit provided in the above embodiment, in one embodiment, as shown in Figure 3, the circuit further includes: a second resistor R2 connected between the second end 13b and the control end 13c of the current control device; and a third resistor R3 connected between the second end 14b of the power management chip and the first end 13a of the current control device.

[0039] For terminals equipped with a power button, the corresponding GPIO (General-Purpose Input / Output) port is initially pulled high after the terminal is powered on. After the user presses the power button, the GPIO port voltage level is pulled low for a period of time. When the user releases the button, the GPIO port is pulled high again. Therefore, the trigger waveforms of some power management chips are relatively complex, including both rising and falling edges, and may also have timing requirements.

[0040] The circuit provided in an embodiment of the present application includes a second resistor and a third resistor. After the circuit is powered on, the power management chip pulls up the startup signal, which is at a high level. The power supply rapidly charges the first and second capacitors through the current of the first resistor. The current through the second capacitor then rapidly increases from zero, and the current through the second resistor also rapidly increases. When the voltage at the control terminal connected to the second capacitor reaches a certain value, the first and second terminals of the current control device are connected, and the startup signal, which was previously at a high level, is pulled down to a low level. Subsequently, the current through the second capacitor reaches a maximum value and then slowly decreases. The current through the second resistor remains almost constant, and the voltage divided by the third resistor remains almost constant. As the current through the second capacitor gradually decreases, the voltage at the control terminal connected to the second capacitor also gradually decreases. After decreasing to a certain value, the first and second terminals of the current control device are disconnected, and the startup signal, which was previously at a low level, is pulled up to a high level again. Through this solution, the power management chip undergoes a "high → low → high" transition after power-on, effectively triggering the power management chip to self-start, thereby enabling the entire circuit to achieve power-on startup.

[0041] The solution provided by the embodiments of this application can be applied to devices without power buttons or batteries. This provides a purely hardware circuit. When a product equipped with this circuit is powered on, the circuit can output a high-level waveform that first falls and then rises, meeting the power-on detection requirements of the chip platform, thereby enabling the entire device to power on. Furthermore, in the special scenario of abnormal power outages and subsequent power restoration, this circuit can achieve timely and automatic power-on, improving reliability.

[0042] Based on the circuit provided in the above embodiment, in one embodiment, as shown in FIG4 , the current control device is a triode;

[0043] The first end 13a of the current control device is a collector, the second end 13b of the current control device is an emitter, and the control end 13c of the current control device is a base.

[0044] In this application example, the current control device is a transistor. After the circuit is powered on, the power management chip pulls up the start signal, which is at a high level. The power supply rapidly charges the first and second capacitors through the current of the first resistor. Because the voltage across the capacitors cannot change suddenly, the transistor base voltage is initially zero, and the transistor is in a non-conducting state.

[0045] Then, the current through the second capacitor rapidly increases from zero. Because the transistor is not conducting, the current through the second resistor rapidly increases, causing the transistor base voltage to rise rapidly. When the base voltage exceeds the threshold voltage, the transistor collector and emitter become conductive, effectively turning the transistor on. After the transistor turns on, the current through the second capacitor continues to rise to its maximum value. The transistor base current and collector current simultaneously rise rapidly from zero to their maximum values. The voltage divided by the third resistor rapidly increases, and the previously high-level start signal is pulled down to a low level.

[0046] Subsequently, the current through the second capacitor reaches its maximum value and begins to slowly decrease, with the rate of decrease being lower than the rate of increase. The transistor base current simultaneously and slowly decreases, while the current through the second resistor remains almost unchanged, so the transistor base voltage remains essentially unchanged. At this point, the transistor base voltage is higher than both the collector voltage and the emitter voltage, and the transistor enters a saturated state. In a saturated state, even if the base current of a transistor slowly decreases, the emitter current remains essentially unchanged, and the voltage divider of the third resistor remains essentially unchanged. Therefore, the low-level start signal remains continuously at a low level, and the transistor remains in a saturated state.

[0047] Then, after the start signal remains at a low level for a period of time, that is, after the transistor base current decreases for a period of time, the transistor emitter current decreases at a faster rate, the third resistor voltage is significantly reduced, and the start signal voltage begins to rise. At the same time, the current through the second resistor begins to decrease, and the transistor base voltage begins to decrease until it falls below the threshold voltage. The transistor is then turned off, and the start signal level reaches the initial voltage, returning to the pull-up state.

[0048] Based on the circuit provided in the above embodiment, in one embodiment, the transistor is an NPN transistor. With this solution, the power management chip undergoes a "high → low → high" transition after power-on, effectively triggering the power management chip to self-start, thereby enabling the entire circuit to power on.

[0049] Based on the circuit provided by the above embodiment, in one embodiment, the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor.

[0050] Based on the circuit provided by the above embodiment, in one embodiment, the resistance value of the second resistor is equal to the resistance value of the third resistor.

[0051] The control module, consisting of a first resistor, a first capacitor, and a second capacitor, ensures that the transistor turns on and turns off after both circuits are powered on. One circuit is the startup signal pull-up power supply. After the startup signal is pulled high, the NPN turns on, pulling the startup signal low and ensuring the first falling edge. Furthermore, according to the chip platform power-on timing requirements, the startup signal's falling edge must be triggered after a certain preceding circuit is powered on, meaning that the NPN turns on after that preceding circuit is powered on.

[0052] Figure 5a shows a schematic diagram of a power-on circuit. VBAT is the system's main power supply. NPN1 is an NPN transistor, a current control device. PM is the power management chip, a crucial component of the terminal chip platform. It receives a power-on signal, also called a startup signal in this example, represented by KEY_ON.

[0053] Based on the circuit provided by the above embodiment, in one embodiment, the capacitance value of the first capacitor and the second capacitor is 22 microfarads.

[0054] Based on the circuit provided in the above embodiment, in one embodiment, the resistance value of the second resistor and the third resistor is 10 kilo-ohms.

[0055] The following example illustrates the circuit. Assuming the VBAT voltage is 4V and the circuit delay is 3T = 300ms, then in this example, R1 is a 10K resistor, C1 is a 22uf capacitor, C2 is a 22uf capacitor, and R2 is a 10K resistor.

[0056] Through simulation, Figure 5b, corresponding to the circuit structure shown in Figure 5a, is obtained. Figure 5b is a voltage schematic diagram, where the abscissa represents time T and the ordinate represents voltage V. In the figure, V1 represents the voltage of node A connected to R1, C2, and C1, shown as a dotted line. V2 represents the voltage of node B connected to C2, R2, and NPN1, shown as a continuous line. KEY_ON represents the start signal, shown as a wire-like dotted line. Nodes A and B are indicated by arrows in Figure 5a.

[0057] In Figure 5a, the VBAT power supply is used as the main power supply of the product. After power-on, the KEY_ON pull-up power supply is configured through the power chip to pull the KEY_ON signal high.

[0058] After VBAT is powered on, the current flowing through resistor R1 quickly charges capacitors C1 and C2. Since the voltage across the capacitors cannot change suddenly, the initial base voltage of transistor NPN1 is 0, and the transistor is not conducting.

[0059] The current through capacitor C2 rises rapidly from 0. Since the transistor is not conducting, the current through R2 rises rapidly, and the base voltage of NPN1 rises rapidly. When the base voltage exceeds the threshold voltage, the collector and emitter of the transistor are turned on, and the transistor is turned on.

[0060] After the transistor is turned on, the current through C2 continues to rise to the maximum value. The base current and collector current of the transistor rise rapidly from 0 to the maximum value synchronously. The voltage divider of R3 increases rapidly, and the KEY_ON signal is quickly pulled down to a low level.

[0061] After the current through capacitor C2 reaches its maximum, it begins to slowly decrease. The rate of decrease is slower than the rate of increase. The transistor base current decreases simultaneously, while the current through R2 remains nearly constant. Therefore, the transistor base voltage remains essentially unchanged. At this point, the transistor base voltage is higher than both the collector and emitter voltages, and the transistor enters saturation. In a saturated transistor, even if the base current slowly decreases, the emitter current remains essentially unchanged, and the voltage divider across R3 remains essentially unchanged. Therefore, the KEY_ON low level remains essentially unchanged, and the transistor remains in saturation.

[0062] After KEY_ON is low for about 300ms, that is, the base current of the transistor decreases for 300ms, the rate of decrease of the transistor emitter current increases, the voltage divider of R3 decreases significantly, and the KEY_ON voltage begins to rise significantly. At the same time, the current through R2 begins to decrease, and the base voltage of the transistor begins to decrease until it falls below the threshold voltage. The transistor is cut off, and the KEY_ON level reaches the initial voltage, returning to the pull-up state.

[0063] The delay circuit, consisting of resistor R1, capacitor C1, and capacitor C2, ensures that the transistor is turned on, that is, the KEY_ON signal is pulled low, after both circuits are powered on. One circuit is the KEY_ON pull-up power supply. After the KEY_ON signal is pulled high, the NPN turns on, pulling the KEY_ON signal low to ensure the formation of the first falling edge. At the same time, according to the chip platform power-on timing requirements, the KEY_ON falling edge trigger must be triggered after a certain previous circuit is powered on, that is, the NPN turns on after a certain previous circuit is powered on. However, designing a delay time that is too long will increase the overall startup time. The delay time set according to the figure meets the requirements of the power-on signal falling edge and the chip power-on timing requirements.

[0064] The circuit composed of capacitor C2, resistor R2 and resistor R3 ensures that the transistor is turned off again after being turned on for a fixed time, and the KEY_ON signal is pulled high again.

[0065] Through the above process, the circuit of the present application finally outputs a waveform that is first pulled high, then pulled low, and then pulled high again, meeting the timing requirements and power-on requirements of the chip platform. The circuit has the advantages of low cost, strong reliability and high stability.

[0066] The solution provided in this application example can be widely applied to new product projects, such as terminal projects without power button FPC requirements and computing power server projects using this product. This solution uses a pure hardware circuit to automatically output relevant waveforms when the product is powered on, meeting the power-on detection requirements of the chip platform, thereby automatically starting the product.

[0067] In addition, for the special scenario of abnormal power outage and power restoration faced in actual use of the product, this circuit can realize timely automatic startup and reduce or avoid the losses caused by power outage.

[0068] In order to solve the problems existing in the prior art, an embodiment of the present application provides a computing power board card that is powered on and turned on, and the computing power board card includes the power-on and turned on circuit described in any of the above embodiments.

[0069] A computing server is a server that can be used for high-performance computing and data processing tasks. It has powerful computing power and high-speed data processing capabilities, and can be used for complex scientific computing, data analysis, artificial intelligence training and reasoning, and other tasks.

[0070] Computing servers are typically equipped with efficient multi-core CPUs (Central Processing Units), large amounts of memory, fast storage, and specialized graphics processing units (GPUs) or coprocessors. This hardware combination provides powerful parallel computing capabilities and high-speed data transfer, accelerating the execution of various compute-intensive tasks. By using computing servers, users can efficiently complete complex computing tasks, improving work efficiency and scientific research innovation. The computing boards on the servers must be reliable and timely.

[0071] If the chip platform of the terminal product is used for a computing board project on a computing server, then due to the special nature of the computing project, the original platform peripherals are completely reduced, and the button FPC and battery are no longer provided. In this application scenario, the device needs to be able to automatically start up after power is applied.

[0072] For this application scenario, the embodiment of the present application can meet the automatic power-on requirements of computing power projects. In addition, after an abnormal power outage is restored, the device can automatically start up, and the server can resume processing data in a timely manner, avoiding various adverse effects caused by no one starting up the machine after the power outage is restored.

[0073] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0074] The present application is described with reference to the flow chart and / or block diagram of the method, device (system), and computer program product according to the embodiment of the present application. It should be understood that each flow process and / or box in the flow chart and / or block diagram and the combination of the flow process and / or box in the flow chart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processing machine or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for realizing the function specified in one flow chart flow or multiple flows and / or one box or multiple boxes of the block diagram.

[0075] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0076] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0077] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0078] Memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0079] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0080] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0081] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0082] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A power-on circuit, wherein: include: Power supply, control module, current control device and power management chip; The first power supply end of the power supply is electrically connected to the first end of the power management chip, and the second power supply end of the power supply is electrically connected to the first end of the control module; The first end of the current control device is electrically connected to the second end of the power management chip, and the second end of the current control device is grounded; The second end of the control module is electrically connected to the second end and the control end of the current control device, and the control module is used to control the first end and the second end of the current control device to be turned on after a first time period after power-on, and to be turned off after a second time period after power-on, and the second time period is greater than the first time period.

2. The circuit of claim 1, wherein: The control module includes a first resistor, a first capacitor and a second capacitor; A first end of the first resistor is electrically connected to a first power supply end of the power supply, and a second end of the first resistor is electrically connected to a first end of the first capacitor and a first end of the second capacitor; The second end of the first capacitor is grounded; The second end of the second capacitor is electrically connected to the control end of the current control device.

3. The circuit of claim 2, wherein: The capacitance value of the first capacitor is equal to the capacitance value of the second capacitor.

4. The circuit of claim 3, wherein: The capacitance value of the first capacitor and the second capacitor is 22 microfarads.

5. The circuit according to any one of claims 1 to 4, wherein: The circuit further comprises: a second resistor connected between the second terminal and the control terminal of the current control device; A third resistor is connected between the second terminal of the power management chip and the first terminal of the current control device.

6. The circuit of claim 5, wherein: The resistance value of the second resistor is equal to the resistance value of the third resistor.

7. The circuit of claim 6, wherein: The resistance values ​​of the second resistor and the third resistor are 10 kilo-ohms.

8. The circuit of claim 1, wherein: The current control device is a triode; The first end of the current control device is a collector, the second end of the current control device is an emitter, and the control end of the current control device is a base.

9. The circuit of claim 8, wherein: The transistor is an NPN transistor.

10. A power board card that is powered on, wherein: The computing power board includes a power-on circuit as described in any one of claims 1 to 9.

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